Display board and method for manufacturing the same, display device

Abstract

The present invention relates to a display board, a method for manufacturing the same, and a display device. The display board comprises a plurality of repeating units (100), each repeating unit (100) including at least one first power line (51), at least one compensation signal line (53), at least two data signal line groups, and a plurality of subpixels, the plurality of subpixels forming at least two pixel rows and at least two pixel columns, the data signal line group including at least two data signal lines (52), the subpixels including memory capacitors (60), the first power line (51) and the compensation signal line (53) being installed between two adjacent pixel columns in the repeating unit (100), the at least two data signal line groups being installed on both sides of the pixel row direction in the repeating unit (100), and the memory capacitor (60) being installed between the data signal line (52) and the first power line (51), or between the data signal line (52) and the compensation signal line (53).

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, but is not limited thereto, and particularly relates to a display substrate, a method for manufacturing the same, and a display device. [Background Art]

[0002] Organic Light Emitting Diodes (abbreviated as OLED) and Quantum-dot Light Emitting Diodes (abbreviated as QLED) are active light-emitting display devices, and have advantages such as self-luminescence, wide viewing angles, high contrast ratio, low power consumption, extremely high response speed, light weight and thin thickness, bendability, and low cost. With the continuous development of display technology, flexible displays, which use OLED or QLED as light-emitting devices and perform signal control through thin film transistors (abbreviated as TFT), have become mainstream products in the current display field. [Summary of the Invention] [Means for Solving the Problem]

[0003] The following is a summary of the subject matter detailed herein. This summary is not intended to limit the scope of protection of the claims.

[0004] In one embodiment, the present disclosure provides a display board comprising a plurality of repeating units, at least one repeating unit comprising at least one first power line, at least one compensation signal line, at least two data signal line groups and a plurality of subpixels, the plurality of subpixels forming at least two pixel rows and at least two pixel columns, the data signal line group comprising at least two data signal lines, at least one subpixel comprising a pixel driving circuit, the pixel driving circuit comprising at least a storage capacitor, the first power line and the compensation signal line being installed between two adjacent pixel columns in the repeating unit, the at least two data signal line groups being installed on both sides of the pixel row direction of the repeating unit, the storage capacitor being installed between the data signal line and the first power line, or the storage capacitor being installed between the data signal line and the compensation signal line.

[0005] In an exemplary embodiment, the repeating unit includes one compensation signal line and two first power lines, the two first power lines include a first first power line and a second first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the compensation signal line is located between the first pixel row and the second pixel row in the repeating unit, and the first data signal line group is located on the side of the first pixel row away from the compensation signal line. The second data signal line group is installed on the side of the second pixel row away from the compensation signal line, the first power supply line is installed on the side of the compensation signal line closer to the first data signal line group, the memory capacitor in the first pixel row is installed between the first data signal line group and the first power supply line, the second power supply line is installed on the side of the compensation signal line closer to the second data signal line group, and the memory capacitor in the second pixel row is installed between the second data signal line group and the second power supply line.

[0006] In an exemplary embodiment, at least one repeating unit further comprises two power connection electrodes, the shape of which the power connection electrodes are strip-shaped extending along the pixel row direction and positioned across the first and second pixel rows, one end of which is connected to the first power line and the other end of which is connected to the second power line, forming an annular structure for transmitting a first power signal within the repeating unit.

[0007] In an exemplary embodiment, at least one repeating unit further comprises a power connection electrode, the shape of which is a strip extending along the pixel row direction and positioned across the first and second pixel rows, wherein the orthographic projection of the power connection electrode on the display board plane does not overlap with the orthographic projection of the data signal lines on the display board plane, and the orthographic projection of the power connection electrode on the display board plane at least partially overlaps with the orthographic projection of the compensation signal lines on the display board plane.

[0008] In an exemplary embodiment, the repeating unit includes one compensation signal line and one first power line; the at least two data signal line groups include a first data signal line group and a second data signal line group; the at least two pixel rows include a first pixel row and a second pixel row; the compensation signal line is located between the first pixel row and the second pixel row in the repeating unit; the first data signal line group is located on the side of the first pixel row away from the compensation signal line; the second data signal line group is located on the side of the second pixel row away from the compensation signal line; the first power line is located on the side of the compensation signal line closer to the second data signal line group; a storage capacitor in the first pixel row is located between the first data signal line group and the compensation signal line; and a storage capacitor in the second pixel row is located between the second data signal line group and the first power line.

[0009] In an exemplary embodiment, the memory capacitor includes at least two capacitor plates, wherein in the first pixel row, the edge of at least one capacitor plate closest to the compensation signal line has a first distance from the edge of the compensation signal line closest to the capacitor plate, and in the second pixel row, the edge of at least one capacitor plate closest to the first power line has a second distance from the edge of the first power line closest to the capacitor plate, and the first distance is greater than or equal to the second distance.

[0010] In an exemplary embodiment, the repeating unit includes one compensation signal line and one first power line; the at least two data signal line groups include a first data signal line group and a second data signal line group; the at least two pixel rows include a first pixel row and a second pixel row; the compensation signal line is located between the first pixel row and the second pixel row in the repeating unit; the first data signal line group is located on the side of the first pixel row away from the compensation signal line; the second data signal line group is located on the side of the second pixel row away from the compensation signal line; the first power line is located on the side of the compensation signal line closer to the first data signal line group; a storage capacitor in the first pixel row is located between the first data signal line group and the first power line; and a storage capacitor in the second pixel row is located between the second data signal line group and the compensation signal line.

[0011] In an exemplary embodiment, the memory capacitor includes at least two capacitor plates, wherein in the first pixel row, the edge of at least one capacitor plate closest to the first power line has a second distance from the edge of the first power line closest to the capacitor plate, and in the second pixel row, the edge of at least one capacitor plate closest to the compensation signal line has a first distance from the edge of the compensation signal line closest to the capacitor plate, and both the first and second distances are greater than the distance between the edge of the compensation signal line closest to the first power line and the edge of the first power line closest to the compensation signal line.

[0012] In an exemplary embodiment, the repeating unit includes one first power line and two compensation signal lines, the two compensation signal lines include a first compensation signal line and a second compensation signal line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the first power line is located between the first pixel row and the second pixel row in the repeating unit, and the first data signal line group is located away from the first power line of the first pixel row. The second data signal line group is installed on the side of the second pixel row away from the first power line, the first compensation signal line is installed on the side of the first power line closer to the first data signal line group, the memory capacitor in the first pixel row is installed between the first data signal line group and the first compensation signal line, the second compensation signal line is installed on the side of the first power line closer to the second data signal line group, and the memory capacitor in the second pixel row is installed between the second data signal line group and the second compensation signal line.

[0013] In an exemplary embodiment, at least one repeating unit further comprises two compensating connection electrodes, the shape of which the compensating connection electrodes are strip-shaped extending along the pixel row direction and positioned across the first and second pixel rows, one end of which is connected to the first compensating signal line and the other end of which is connected to the second compensating signal line, forming an annular structure for transmitting a compensation signal within the repeating unit.

[0014] In an exemplary embodiment, at least one repeating unit further comprises two compensating connection electrodes, the shape of which the compensating connection electrodes are strip-like extending along the pixel row direction and positioned across the first and second pixel rows, wherein the orthographic projection of the compensating connection electrodes on the display board plane does not overlap with the orthographic projection of the data signal lines on the display board plane, and the orthographic projection of the compensating connection electrodes on the display board plane at least partially overlaps with the orthographic projection of the first power lines on the display board plane.

[0015] In an exemplary embodiment, the repeating unit includes one compensation signal line and one first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the first power line is located between the first pixel row and the second pixel row in the repeating unit, the first data signal line group is located on the side of the first pixel row away from the first power line, the second data signal line group is located on the side of the second pixel row away from the first power line, and the compensation signal line is The first power line is installed on the side closer to the second data signal line group, the memory capacitor in the first pixel row is installed between the first data signal line group and the first power line, the memory capacitor in the second pixel row is installed between the second data signal line group and the compensation signal line, or the compensation signal line is installed on the side closer to the first data signal line group of the first power line, the memory capacitor in the first pixel row is installed between the first data signal line group and the compensation signal line, and the memory capacitor in the second pixel row is installed between the second data signal line group and the first power line.

[0016] In an exemplary embodiment, the memory capacitor includes at least two capacitor plates, wherein in the first pixel row, the edge of at least one capacitor plate closest to the first power line has a third distance from the edge of the first power line closest to the capacitor plate, and in the second pixel row, the edge of at least one capacitor plate closest to the compensation signal line has a fourth distance from the edge of the compensation signal line closest to the capacitor plate, or, in the first pixel row, the edge of at least one capacitor plate closest to the compensation signal line has a fourth distance from the edge of the compensation signal line closest to the capacitor plate, and in the second pixel row, the edge of at least one capacitor plate closest to the first power line has a third distance from the edge of the first power line closest to the capacitor plate, and both the third and fourth distances are greater than the distance between the edge of the compensation signal line closest to the first power line and the edge of the first power line closest to the compensation signal line.

[0017] In an exemplary embodiment, the memory capacitor includes at least two capacitor plates, and in at least one pixel row, the distance between the edge of at least one capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate is 3 μm or more.

[0018] In an exemplary embodiment, the memory capacitor includes a first plate and a second plate, the pixel driving circuit further includes a first transistor, a second transistor and a third transistor, the first electrode of the first transistor being connected to the data signal line, the second electrode of the first transistor being connected to the first plate and the gate electrode of the second transistor, respectively, the first electrode of the third transistor being connected to the compensation signal line, the second electrode of the third transistor being connected to the second plate and the second electrode of the second transistor, and in at least one repeating unit, the gate electrodes of a plurality of the first transistors and the gate electrodes of a plurality of the third transistors are connected to the same scan signal line.

[0019] In an exemplary embodiment, the first transistor includes at least a first active layer, a first region of the first active layer connected to the data signal line via a connecting electrode, a second region of the first active layer connected to the second electrode plate, and in at least one subpixel, the orthogonal projection of the first active layer on the display substrate plane does not overlap with the orthogonal projection of the data signal line on the display substrate plane.

[0020] In an exemplary embodiment, the third transistor includes at least a third active layer, a first region of the third active layer connected to the compensation signal line via a connecting electrode, a second region of the third active layer connected to the first electrode plate, and in at least one subpixel, the orthogonal projection of the third active layer on the display substrate plane does not overlap with the orthogonal projection of the first power line on the display substrate plane.

[0021] In other embodiments, the present disclosure further provides a display device comprising the above-described display board.

[0022] In still another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate includes a plurality of repeating units, and the manufacturing method includes: forming, in at least one repeating unit, at least one first power supply line, at least one compensation signal line, at least two data signal line groups and a plurality of sub-pixels, the plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, the data signal line group including at least one data signal line, at least one sub-pixel including a pixel driving circuit, the pixel driving circuit including at least a storage capacitor, wherein the first power supply line and the compensation signal line are arranged between two adjacent pixel columns in the repeating unit, the at least two data signal line groups are respectively arranged on both sides of the repeating unit in the pixel row direction, and the storage capacitor is arranged between the data signal line and the first power supply line, or the storage capacitor is arranged between the data signal line and the compensation signal line.

[0023] Other aspects will be understood after reading and comprehending the drawings and detailed description.

[0024] The drawings are provided to further understand the technical solution of the present disclosure, constitute a part of the specification, are used to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, and are not intended to limit the technical solution of the present disclosure. The shape and size of each component in the drawings do not reflect the actual proportion, but are intended to schematically illustrate the content of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] [Figure 1] Fig. 1 is a schematic structural diagram of a display device. [Figure 2] Fig. 2 is a schematic planar structural diagram of a display substrate according to an exemplary embodiment of the present disclosure. [Figure 3] Fig. 3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an embodiment of the present disclosure. [Figure 4]It is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure. [Figure 5] It is a schematic diagram after a first conductive layer pattern is formed on the display substrate of the present disclosure. [Figure 6A] It is a schematic diagram after a second conductive layer pattern is formed on the display substrate of the present disclosure. [Figure 6B] It is a schematic diagram after a second conductive layer pattern is formed on the display substrate of the present disclosure. [Figure 7A] It is a schematic diagram after a semiconductor layer pattern is formed on the display substrate of the present disclosure. [Figure 7B] It is a schematic diagram after a semiconductor layer pattern is formed on the display substrate of the present disclosure. [Figure 8] It is a schematic diagram after a second insulating layer pattern is formed on the display substrate of the present disclosure. [Figure 9A] It is a schematic diagram after a third conductive layer pattern is formed on the display substrate of the present disclosure. [Figure 9B] It is a schematic diagram after a third conductive layer pattern is formed on the display substrate of the present disclosure. [Figure 10] It is a schematic diagram after a third insulating layer and a flat layer pattern are formed on the display substrate of the present disclosure. [Figure 11A] It is a schematic diagram after a fourth conductive layer pattern is formed on the display substrate of the present disclosure. [Figure 11B] It is a schematic diagram after a fourth conductive layer pattern is formed on the display substrate of the present disclosure. [Figure 12] It is a schematic diagram after a pixel definition layer pattern is formed on the display substrate of the present disclosure. [Figure 13] It is an equivalent circuit diagram of a pixel driving circuit in another repeating unit according to an embodiment of the present disclosure. [Figure 14] It is a schematic plan structural diagram of another display substrate according to an embodiment of the present disclosure. [Figure 15] It is an equivalent circuit diagram of a pixel driving circuit in still another repeating unit according to an embodiment of the present disclosure. [Figure 16] It is a schematic structural diagram of still another display substrate according to an embodiment of the present disclosure. [Figure 17A]This is a schematic diagram showing the display substrate of the present disclosure after a second conductive layer pattern has been formed on it. [Figure 17B] This is a schematic diagram showing the display substrate of the present disclosure after a second conductive layer pattern has been formed on it. [Figure 18A] This is a schematic diagram showing the state of another display substrate after a semiconductor layer pattern has been formed on it. [Figure 18B] This is a schematic diagram showing the state of another display substrate after a semiconductor layer pattern has been formed on it. [Figure 19] This is a schematic diagram showing the display substrate of the present disclosure after a second insulating layer pattern has been formed on it. [Figure 20A] This is a schematic diagram showing the display substrate of the present disclosure after a third conductive layer pattern has been formed on it. [Figure 20B] This is a schematic diagram showing the display substrate of the present disclosure after a third conductive layer pattern has been formed on it. [Figure 21] This is an equivalent circuit diagram of a pixel driving circuit in yet another repeating unit of an embodiment of the present disclosure. [Figure 22] This is a schematic diagram of yet another display board structure according to the embodiments of the present disclosure. [Figure 23] This is a schematic diagram of yet another display board structure according to the embodiments of the present disclosure. [Figure 24] This is a schematic diagram showing the display substrate of the present disclosure after a first conductive layer pattern has been formed on it. [Figure 25A] This is a schematic diagram showing the display substrate of the present disclosure after a second conductive layer pattern has been formed on it. [Figure 25B] This is a schematic diagram showing the display substrate of the present disclosure after a second conductive layer pattern has been formed on it. [Figure 26A] This is a schematic diagram showing the state of another display substrate after a semiconductor layer pattern has been formed on it. [Figure 26B] This is a schematic diagram showing the state of another display substrate after a semiconductor layer pattern has been formed on it. [Figure 27] This is a schematic diagram showing the display substrate of the present disclosure after a second insulating layer pattern has been formed on it. [Figure 28A]This is a schematic diagram showing the display substrate of the present disclosure after a third conductive layer pattern has been formed on it. [Figure 28B] This is a schematic diagram showing the display substrate of the present disclosure after a third conductive layer pattern has been formed on it. [Modes for carrying out the invention]

[0026] To further clarify the purpose, technical proposal, and advantages of this disclosure, embodiments of this disclosure will be described in detail below with reference to the drawings. Embodiments can be carried out in many different forms. It is a fact that will be readily apparent to those skilled in the art that the form and content can be transformed into various forms without departing from the gist and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the descriptions of the embodiments below. Where there is no conflict, embodiments and features of embodiments of this disclosure can be combined with each other.

[0027] The proportions in the drawings in this disclosure may, but are not limited to, those shown in the drawings for reference in actual processes. For example, the ratio of channel width to length, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual requirements. The number of pixels on the display substrate and the number of subpixels in each pixel are not limited to those shown in the drawings, and the drawings described in this disclosure are merely schematic diagrams of the structure. One aspect of this disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0028] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion regarding the constituent elements and do not limit them in terms of quantity.

[0029] In this specification, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationships such as "center," "top," "bottom," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside." This is for the purpose of describing and simplifying this specification, and is not intended to indicate or suggest that the described apparatus or element has a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit this disclosure. The positional relationships of the components may be appropriately changed depending on the direction in which each component is described. Therefore, the terms used may be appropriately changed in some cases, not limited to those described in the specification.

[0030] In this specification, unless explicitly stated or limited, the terms “attach,” “connect,” and “connect” should be understood broadly. For example, this could be a fixed connection, a removable connection, or an integrated connection; a mechanical connection, or an electrical connection; a direct connection, an indirect connection via a linker, or internal communication between two elements. Those skilled in the art will be able to understand the specific meaning of the above technical terms in this disclosure depending on the specific circumstances.

[0031] In this specification, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to the region through which current primarily flows.

[0032] In this specification, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. When using transistors with opposite polarity, or when the direction of current changes during operation in the circuit, the functions of the "source electrode" and the "drain electrode" may be converted to each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be converted to each other, and the "source terminal" and the "drain terminal" can be converted to each other.

[0033] In this specification, "electrically connected" includes cases where components are connected via an element having an electrical function. The "element having an electrical function" is not particularly limited and only needs to be capable of transmitting and receiving electrical signals between the connected components. Examples of "elements having an electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and elements with various other functions.

[0034] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and therefore also includes a state in which the angle is between -5° and 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and therefore also includes a state in which the angle is between 85° and 95°.

[0035] In this specification, "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0036] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have small deformations due to tolerances, as well as chamfers, arcs, and other deformations.

[0037] In this disclosure, "approximately" means that the boundary is not strictly defined and that numerical values ​​within the error range of the process and measurement are permitted.

[0038] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scanning driver, and a pixel array. The timing controller is connected to the data driver and the scanning driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), respectively. The scanning driver is connected to a plurality of scanning signal lines (S1 to Sm), respectively. The pixel array may include a plurality of sub-pixels Pxij, each sub-pixel Pxij being connected to a corresponding data signal line and a corresponding scanning signal line, where i and j are natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit, each pixel driving circuit being connected to a scanning signal line and a data signal line, respectively. The display unit may include at least a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the circuit unit. The sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scanning signal line and the j-th data signal line. In an exemplary embodiment, the timing controller provides the data driver with grayscale values ​​and control signals conforming to the data driver's specifications, and provides the scan driver with a clock signal, a scan start signal, etc., conforming to the scan driver's specifications. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages supplied to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can use the clock signal to sample grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel row basis, where n is a natural number. The scan driver can receive the clock signal, a scan start signal, etc., from the timing controller to generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm. For example, the scan driver can sequentially supply scan signals having turn-on level pulses to scan signal lines S1 to Sm.For example, the scan driver may be configured in the form of a shift register and generate a scan signal by sequentially transporting a scan start signal, provided in the form of a turn-on level pulse under the control of a clock signal, to the next level of circuitry, where m is a natural number. In an exemplary embodiment, the pixel array may be mounted on a display board.

[0039] An exemplary embodiment of the present disclosure provides a display board comprising a plurality of repeating units, at least one repeating unit comprising at least one first power line, at least one compensation signal line, at least two data signal line groups and a plurality of subpixels, the plurality of subpixels forming at least two pixel rows and at least two pixel columns, the data signal line group comprising at least one data signal line, at least one subpixel comprising a pixel driving circuit, the pixel driving circuit comprising at least a memory capacitor, the first power line and the compensation signal line being located between two adjacent pixel columns in the repeating unit, the at least two data signal line groups being located on either side of the pixel row direction of the repeating unit, the memory capacitor being located between the data signal line and the first power line, or the memory capacitor being located between the data signal line and the compensation signal line.

[0040] In an exemplary embodiment, the repeating unit includes one compensation signal line and two first power lines, the two first power lines include a first first power line and a second first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the compensation signal line is located between the first pixel row and the second pixel row in the repeating unit, and the first data signal line group is located on the side of the first pixel row away from the compensation signal line. The second data signal line group is installed on the side of the second pixel row away from the compensation signal line, the first power supply line is installed on the side of the compensation signal line closer to the first data signal line group, the memory capacitor in the first pixel row is installed between the first data signal line group and the first power supply line, the second power supply line is installed on the side of the compensation signal line closer to the second data signal line group, and the memory capacitor in the second pixel row is installed between the second data signal line group and the second power supply line.

[0041] In an exemplary embodiment, the repeating unit includes one compensation signal line and one first power line; the at least two data signal line groups include a first data signal line group and a second data signal line group; the at least two pixel rows include a first pixel row and a second pixel row; the compensation signal line is located between the first pixel row and the second pixel row in the repeating unit; the first data signal line group is located on the side of the first pixel row away from the compensation signal line; the second data signal line group is located on the side of the second pixel row away from the compensation signal line; the first power line is located on the side of the compensation signal line closer to the second data signal line group; a storage capacitor in the first pixel row is located between the first data signal line group and the compensation signal line; and a storage capacitor in the second pixel row is located between the second data signal line group and the first power line.

[0042] In an exemplary embodiment, the repeating unit includes one compensation signal line and one first power line; the at least two data signal line groups include a first data signal line group and a second data signal line group; the at least two pixel rows include a first pixel row and a second pixel row; the compensation signal line is located between the first pixel row and the second pixel row in the repeating unit; the first data signal line group is located on the side of the first pixel row away from the compensation signal line; the second data signal line group is located on the side of the second pixel row away from the compensation signal line; the first power line is located on the side of the compensation signal line closer to the first data signal line group; a storage capacitor in the first pixel row is located between the first data signal line group and the first power line; and a storage capacitor in the second pixel row is located between the second data signal line group and the compensation signal line.

[0043] In an exemplary embodiment, the repeating unit includes one first power line and two compensation signal lines, the two compensation signal lines include a first compensation signal line and a second compensation signal line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the first power line is located between the first pixel row and the second pixel row in the repeating unit, and the first data signal line group is located away from the first power line of the first pixel row. The second data signal line group is installed on the side of the second pixel row away from the first power line, the first compensation signal line is installed on the side of the first power line closer to the first data signal line group, the memory capacitor in the first pixel row is installed between the first data signal line group and the first compensation signal line, the second compensation signal line is installed on the side of the first power line closer to the second data signal line group, and the memory capacitor in the second pixel row is installed between the second data signal line group and the second compensation signal line.

[0044] In an exemplary embodiment, the repeating unit includes one compensation signal line and one first power line; the at least two data signal line groups include a first data signal line group and a second data signal line group; the at least two pixel rows include a first pixel row and a second pixel row; the first power line is located between the first pixel row and the second pixel row in the repeating unit; the first data signal line group is located on the side of the first pixel row away from the first power line; the second data signal line group is located on the side of the second pixel row away from the first power line; the compensation signal line is located on the side of the first power line closer to the second data signal line group; a storage capacitor in the first pixel row is located between the first data signal line group and the first power line; and a storage capacitor in the second pixel row is located between the second data signal line group and the compensation signal line.

[0045] In an exemplary embodiment, the repeating unit includes one compensation signal line and one first power line; the at least two data signal line groups include a first data signal line group and a second data signal line group; the at least two pixel rows include a first pixel row and a second pixel row; the first power line is located between the first pixel row and the second pixel row in the repeating unit; the first data signal line group is located on the side of the first pixel row away from the first power line; the second data signal line group is located on the side of the second pixel row away from the first power line; the compensation signal line is located on the side of the first power line closer to the first data signal line group; a storage capacitor in the first pixel row is located between the first data signal line group and the compensation signal line; and a storage capacitor in the second pixel row is located between the second data signal line group and the first power line.

[0046] The display substrates of this disclosure will be described below by illustrating several exemplary embodiments.

[0047] Figure 2 is a schematic diagram of the planar structure of a display substrate in an exemplary embodiment of the present disclosure. As shown in Figure 2, in the exemplary embodiment, the display substrate may include a plurality of repeating units 100 in a direction parallel to the display substrate, and at least one repeating unit 100 may include a plurality of subpixels. In the exemplary embodiment, the repeating units are the basic units constituting the display substrate, and the display substrate is constructed by being repeatedly and continuously installed along at least one direction, that is, the display substrate is constructed by joining a plurality of repeating units.

[0048] In an exemplary embodiment, at least one repeating unit 100 may include four subpixels, the four subpixels may include a first subpixel P1 emitting a first color ray, a second subpixel P2 emitting a second color ray, a third subpixel P3 emitting a third color ray, and a fourth subpixel P4 emitting a fourth color ray, and the four subpixels may be arranged in a square pattern, which can effectively increase the aperture ratio and the light transmission area.

[0049] In an exemplary embodiment, in at least one repeating unit 100, a second subpixel P2 may be located on the first direction X side of the first subpixel P1, a third subpixel P3 may be located on the second direction Y side of the first subpixel P1, and a fourth subpixel P4 may be located on the first direction X side of the third subpixel P3. Multiple subpixels sequentially located along the first direction X may be called pixel rows, and multiple subpixels sequentially located along the second direction Y may be called pixel columns. Multiple pixel rows and multiple pixel columns constitute a pixel array in an array arrangement, and the first direction X and the second direction Y intersect.

[0050] In exemplary embodiments, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, the third subpixel P3 may be a white subpixel (W) emitting white light, and the fourth subpixel P4 may be a green subpixel (G) emitting green light. In several possible embodiments, the arrangement of the RBWG can be adjusted according to actual needs and is not specifically limited herein.

[0051] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a drive circuit layer installed on the base and a light-emitting structure layer installed on the side of the drive circuit layer away from the base. In at least one repeating unit, the drive circuit layer may include a plurality of circuit units, each circuit unit may include at least a pixel drive circuit, each pixel drive circuit being connected to a scan signal line and a data signal line, respectively, and the pixel drive circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and to output a current corresponding to a light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, each light-emitting unit may include at least a light-emitting device, each light-emitting device being connected to a pixel drive circuit in the circuit unit of the sub-pixel, and the light-emitting device being configured to emit light of a corresponding brightness in response to the current output by the pixel drive circuit of the sub-pixel.

[0052] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a drive circuit layer mounted on the base, a color film structure layer mounted on the side of the drive circuit layer away from the base, and a light-emitting structure layer mounted on the side of the color film structure layer away from the base. In at least one repeating unit, the color film structure layer may include a plurality of color film units, each color film unit may include at least a color filter layer, the color filter layer configured to emit light rays of a desired color from the corresponding subpixels.

[0053] In exemplary embodiments, the circuit unit described herein means a region divided by a pixel driving circuit. The color film unit described herein means a region divided by a color filter layer. The display unit described herein means a region divided by a light-emitting device. The positions of the orthographic projections on the base of the circuit unit, the base of the color filter layer, and the base of the light-emitting unit may or may not correspond.

[0054] In exemplary embodiments of this disclosure, the positions of the orthographic projection on the base of the circuit unit, the orthographic projection on the base of the color filter layer, and the orthographic projection on the base of the light-emitting unit correspond one-to-one, and the circuit unit, color film unit, and light-emitting unit constitute subpixels. Therefore, in the following description, the circuit unit, color film unit, and light-emitting unit are consistently referred to as subpixels.

[0055] Figure 3 is an equivalent circuit diagram of a pixel driver circuit in a repeating unit of an exemplary embodiment of the present disclosure. As shown in Figure 3, at least one repeating unit may include four pixel driver circuits, the four pixel driver circuits may be arranged in a square configuration, and the pixel driver circuits may have a 3T1C structure.

[0056] In an exemplary embodiment, at least one pixel driving circuit may comprise three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and one memory capacitor C, and the pixel driving circuit is connected to the scan signal line 30, the first power line 51, the data signal line 52, and the compensation signal line 53, respectively.

[0057] In an exemplary embodiment, each pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first terminal of the memory capacitor C, respectively, while the second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second terminal of the memory capacitor C, respectively.

[0058] In an exemplary embodiment, the first end of the memory capacitor C is connected to the first node N1, the second end of the memory capacitor C is connected to the second node N2, and the memory capacitor C is used to store the potential of the gate electrode of the second transistor T2.

[0059] In the exemplary embodiment, the first transistor T1 is a switch transistor, the second transistor T2 is a drive transistor, and the third transistor T3 is a compensation transistor.

[0060] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the scan signal line 30, the first electrode of the first transistor T1 is connected to the data signal line 52, and the second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 30, the first transistor T1 inputs the data signal from the data signal line 52 to the gate electrode of the second transistor T2.

[0061] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first node N1, the first electrode of the second transistor T2 is connected to the first power line 51, and the second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received by its gate electrode.

[0062] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the scan signal line 30, the first electrode of the third transistor T3 is connected to the compensation signal line 53, and the second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing, thereby compensating for the threshold voltage Vth.

[0063] In an exemplary embodiment, in a pixel driving circuit for at least one subpixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30.

[0064] In an exemplary embodiment, in a plurality of pixel driving circuits for at least one pixel row, the gate electrodes of a plurality of first transistors T1 and the gate electrodes of a plurality of third transistors T3 are connected to the same scan signal line 30.

[0065] In an exemplary embodiment, in a plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of a plurality of first transistors T1 and the gate electrodes of a plurality of third transistors T3 are connected to the same scan signal line 30.

[0066] In exemplary embodiments, the light-emitting device EL may be an OLED comprising a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or a QLED comprising a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to a second node N2, and the second electrode of the light-emitting device EL is connected to a second power line 52. The light-emitting device EL emits light of a corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0067] In an exemplary embodiment, the signal on the first power line 51 is a continuously supplied high-level signal, and the signal on the second power line 52 is a continuously supplied low-level signal.

[0068] In exemplary embodiments, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. By employing the same type of transistors in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the yield rate of the product can be improved. In some possible implementations, the first to third transistors T1 to T3 may include both P-type and N-type transistors.

[0069] In an exemplary embodiment, the first to third transistors T1 to T3 may be low-temperature polysilicon thin-film transistors, oxide thin-film transistors, or a combination of low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor. Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. By integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized, enabling low-frequency driving, reducing power consumption, and improving display attributes.

[0070] Figure 4 is a schematic diagram of the structure of a display substrate in an exemplary embodiment of the present disclosure, showing the structure of a pixel driving circuit in one repeating unit (four subpixels) of a bottom emission display substrate. As shown in Figure 4, in the exemplary embodiment, at least one repeating unit may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square manner, each subpixel comprising a pixel driving circuit.

[0071] In an exemplary embodiment, at least one repeating unit may include one scan signal line 30, two first power lines 51, four data signal lines 52, and one compensation signal line 53, the signal lines being connected to pixel drive circuits in the corresponding subpixels, the scan signal line 30 being configured to supply scan signals to the pixel drive circuits, the first power lines 51 being configured to supply power signals to the pixel drive circuits, the data signal lines 52 being configured to supply data signals to the pixel drive circuits, and the compensation signal line 53 being configured to supply compensation signals to the pixel drive circuits.

[0072] In an exemplary embodiment, the shape of the scanning signal line 30 may be linear, with the main body extending along the first direction X (pixel row direction), and the shapes of the first power line 51, data signal line 52, and compensation signal line 53 may be linear, with the main body extending along the second direction Y (pixel column direction), and the first direction X and the second direction Y intersect.

[0073] In an exemplary embodiment, the scan signal line 30 may be located in the middle of the second direction Y of the repeating unit, and one compensation signal line 53 may be located in the middle of the first direction X of the repeating unit. Thus, one scan signal line 30 extending along the first direction X may form by limiting two pixel rows, and one compensation signal line 53 extending along the second direction Y may form by limiting two pixel columns, forming a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square configuration within one repeating unit.

[0074] In an exemplary embodiment, in at least one repeating unit, four subpixels may be mirror-symmetric with respect to the scan signal line 30, and four subpixels may be mirror-symmetric with respect to the compensation signal line 53.

[0075] In an exemplary embodiment, in at least one repeating unit, two pixel rows may include a first pixel row and a second pixel row, two first power lines 51 may include a first power line 51-1 and a second power line 51-2 that are sequentially installed along a first direction X, and four data signal lines 52 may include a first data signal line 52-1, a second data signal line 52-2, a third data signal line 52-3 and a fourth data signal line 52-4 that are sequentially installed along a first direction X, the first data signal line 52-1 and the second data signal line 52-2 may constitute a first data signal line group, and the third data signal line 52-3 and the fourth data signal line 52-4 may constitute a second data signal line group.

[0076] In exemplary embodiments, the compensation signal line 53, the first first power line 51-1, and the second first power line 51-2 may be located in the central region of the repeating unit in the first direction X, the first data signal line group (including the first data signal line 52-1 and the second data signal line 52-2) may be located on the opposite side of the repeating unit in the first direction X, the second data signal line group (including the third data signal line 52-3 and the fourth data signal line 52-4) may be located on the side of the repeating unit in the first direction X, the first first power line 51-1 may be installed on the side of the compensation signal line 53 closer to the first data signal line group, and the second first power line 51-2 may be installed on the side of the compensation signal line 53 closer to the first data signal line group.

[0077] In an exemplary embodiment, the pixel driving circuit for at least one subpixel may include at least a memory capacitor 60, a first transistor T1, a second transistor T2, and a third transistor T3, and the memory capacitor may include a first plate and a second plate as capacitor plates. The memory capacitor 60 of the first pixel row may be installed between a first power line 51-1 and a second data signal line 52-2 in the first data signal line group, and the memory capacitor 60 of the second pixel row may be installed between a second first power line 51-2 and a third data signal line 52-3 in the second data signal line group.

[0078] In an exemplary embodiment, the first electrode of the first transistor T1 is connected to the data signal line 52, the second electrode of the first transistor T1 is connected to the gate electrode of the second transistor T2 and the second plate of the memory capacitor 60, respectively, the first electrode of the second transistor T2 is connected to the first power line 51, the first electrode of the third transistor T3 is connected to the compensation signal line 53, and the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2 and the first plate of the memory capacitor 60, respectively.

[0079] In exemplary embodiments, at least one repeating unit further comprises two power supply connection electrodes 18, the two power supply connection electrodes 18 being located on the second direction Y side of the repeating unit, respectively. The shape of each power supply connection electrode 18 may be a strip extending along the first direction X, and each power supply connection electrode 18 is located across a first pixel row and a second pixel row. The first end of each power supply connection electrode 18 is connected to a first first power line 51-1 and the first electrode of a second transistor T2 in the first pixel row, and the second end of each power supply connection electrode 18 is connected to a second first power line 51-2 and the first electrode of a second transistor T2 in the second pixel row. In this way, the two first power lines 51 and the two power supply connection electrodes 18 in the repeating unit form an annular structure for transmitting the first power supply signal.

[0080] In an exemplary embodiment, the orthographic projection of the power connection electrode 18 on the display board plane does not overlap with the orthographic projection of the data signal line 52 on the display board plane.

[0081] In an exemplary embodiment, the orthographic projection of the power connection electrode 18 on the display board plane overlaps at least partially with the orthographic projection of the compensation signal line 53 on the display board plane.

[0082] The following is an illustrative explanation of the manufacturing process of a display substrate. The “patterning process” described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic materials, inorganic materials, or transparent conductive materials, and processes such as organic material coating, mask exposure, and development for organic materials. Deposition may be one or more of sputtering, vapor deposition coating, or chemical vapor deposition. Coating may be one or more of spray coating, spin coating, and inkjet printing. Etching may be one or more of dry etching and wet etching, but is not limited to these. A “thin film” refers to a single thin film produced on a base by deposition, coating, or other processes using a certain material. If the “thin film” does not require a patterning process throughout the entire manufacturing process, the “thin film” may also be referred to as a “layer.” If the “thin film” requires a patterning process throughout the entire manufacturing process, it is referred to as a “thin film” before the patterning process and as a “layer” after the patterning process. A “layer” after the patterning process contains at least one “pattern.” “A and B are placed in the same layer” as described in this disclosure means that A and B are formed simultaneously by the same patterning process. The “thickness” of a film layer is its size in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0083] In an exemplary embodiment, taking four subpixels (first subpixel P1, second subpixel P2, third subpixel P3, and fourth subpixel P4) of one repeating unit as an example, the manufacturing process of the display substrate in the embodiment of the present disclosure may include the following operations.

[0084] (11) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in Figure 5, forming a first conductive layer pattern includes depositing a first conductive thin film on a base and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern on the base.

[0085] In an exemplary embodiment, the first conductive layer of each subpixel on the display substrate may include at least a first connecting electrode 11, a second connecting electrode 12, and a first electrode plate 61 of a memory capacitor.

[0086] In an exemplary embodiment, the shape of the first electrode plate 61 may be rectangular, chamfers may be provided on the corners of the rectangle, the first electrode plate 61 may be one of the transparent electrodes of a transparent memory capacitor, and the first electrode plate 61 is configured to form a transparent memory capacitor together with a second electrode plate formed subsequently.

[0087] In an exemplary embodiment, the first connecting electrode 11 and the second connecting electrode 12 may be installed on both sides of the first electrode plate 61 in the second direction Y, respectively.

[0088] In exemplary embodiments, in the first subpixel P1 and the second subpixel P2, the first connecting electrode 11 may be installed on the opposite side of the first electrode plate 61 in the second direction Y, and the second connecting electrode 12 may be installed on the side of the first electrode plate 61 in the second direction Y. In the third subpixel P3 and the fourth subpixel P4, the first connecting electrode 11 may be installed on the side of the first electrode plate 61 in the second direction Y, and the second connecting electrode 12 may be installed on the opposite side of the first electrode plate 61 in the second direction Y.

[0089] In an exemplary embodiment, the shape of the first connecting electrode 11 may be a strip with a main body extending along a second direction Y, the first end of the first connecting electrode 11 is connected to the first electrode plate 61, the second end of the first connecting electrode 11 extends in a direction away from the second connecting electrode 12, and the first connecting electrode 11 is configured to be connected to a subsequently formed third connecting electrode.

[0090] In an exemplary embodiment, the shape of the second connecting electrode 12 may be a strip with a main body extending along the second direction Y, the first end of the second connecting electrode 12 is connected to the first electrode plate 61, the second end of the second connecting electrode 12 extends along a direction away from the first connecting electrode 11, and the second connecting electrode 12 is configured to be connected to a subsequently formed fourth connecting electrode.

[0091] In an exemplary embodiment, in the first pixel row, the first connecting electrode 11 may be installed on the side away from the second pixel row, and the edge of the first connecting electrode 11 on the side away from the second pixel row may be substantially flush with the edge of the first electrode plate 61 on the side away from the second pixel row. In the second pixel row, the first connecting electrode 11 may be installed on the side away from the first pixel row, and the edge of the first connecting electrode 11 on the side away from the first pixel row may be substantially flush with the edge of the first electrode plate 61 on the side away from the first pixel row.

[0092] In an exemplary embodiment, the width of the first connecting electrode 11 may be greater than the width of the second connecting electrode 12 in the first direction X.

[0093] In an exemplary embodiment, the second connecting electrode 12 may be located near the midpoint of the subpixel in the first direction X in each subpixel.

[0094] In an exemplary embodiment, the first connecting electrode 11, the second connecting electrode 12, and the first electrode plate 61 of each subpixel may be an integrated structure that is interconnected.

[0095] In an exemplary embodiment, the area of ​​the first electrode plate 61 in each subpixel may be basically the same so that the capacitance of the memory capacitor in each subpixel is basically the same.

[0096] In exemplary embodiments, the positions of the patterns in the first conductive layer in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetric with respect to a horizontal reference line, and the positions of the patterns in the first conductive layer in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to a horizontal reference line. The positions of the patterns in the first conductive layer in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetric with respect to a vertical reference line, and the positions of the patterns in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to a vertical reference line. The horizontal reference line may be a straight line extending along a first direction X and dividing the repeating units in a second direction Y, and the vertical reference line may be a straight line extending along a second direction Y and dividing the repeating units in a first direction X.

[0097] In exemplary embodiments, the material of the first conductive layer may be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0098] (12) Forming a second conductive layer pattern. In exemplary embodiments, forming a second conductive layer pattern may include depositing a second conductive thin film on a base on which the aforementioned pattern is formed, and then patterning the second conductive thin film by a patterning process to form a second conductive layer. Figure 6B is a schematic diagram of the second conductive layer in Figure 6A. In exemplary embodiments, the second conductive layer may be referred to as a shield layer.

[0099] In an exemplary embodiment, the second conductive layer of each subpixel on the display substrate may include at least a third connecting electrode 13 and a fourth connecting electrode 14.

[0100] In exemplary embodiments, the shape of the third connecting electrode 13 may be block-shaped (e.g., rectangular), and the third connecting electrode 13 may be located on the side of the first electrode plate 61 away from the second connecting electrode 12, and the orthographic projection of the third connecting electrode 13 at the base at least partially overlaps with the orthographic projection of the first connecting electrode 11 at the base, and the third connecting electrode 13 directly overlaps with the first connecting electrode 11. In exemplary embodiments, the third connecting electrode 13 is configured to, on the one hand, connect to a subsequently formed fifth connecting electrode, and on the other hand, to reduce the influence of light on the characteristics of the second transistor by shielding the second transistor from light, reducing the intensity of light irradiated onto the second transistor, and reducing the leakage current of the second transistor.

[0101] In exemplary embodiments, the shape of the fourth connecting electrode 14 may be block-shaped (e.g., rectangular), and the fourth connecting electrode 14 may be located on the side of the first electrode plate 61 away from the first connecting electrode 11, and the orthographic projection of the base of the fourth connecting electrode 14 at least partially overlaps with the orthographic projection of the base of the second connecting electrode 12, so that the fourth connecting electrode 14 directly overlaps with the second connecting electrode 12. The fourth connecting electrode 14 is configured to connect to a subsequently formed sixth connecting electrode.

[0102] In an exemplary embodiment, the width of the third connecting electrode 13 may be greater than the width of the fourth connecting electrode 14 in the first direction X.

[0103] In an exemplary embodiment, the second conductive layer of each repeating unit of the display board may include at least two first power lines 51, four data signal lines 52, and one compensation signal line 53.

[0104] In exemplary embodiments, the shapes of the first power line 51, data signal line 52, and compensation signal line 53 may be straight or bent with the main body extending along the second direction Y, the compensation signal line 53 may be located in the middle of the first direction X of the repeating unit, the two first power lines 51 may be located on both sides of the compensation signal line 53 in the first direction X, the first data signal line group of the four data signal lines 52 may be located on the opposite side of the first direction X of the repeating unit, and the second data signal line group of the four data signal lines 52 may be located on the first direction X side of the repeating unit.

[0105] In an exemplary embodiment, the two first power lines 51 may include a first power line 51-1 and a second power line 51-2 installed sequentially along a first direction X, the four data signal lines 52 may include a first data signal line group and a second data signal line group, the first data signal line group may include a first power line 51-1 and a second data signal line 52-2 installed sequentially along a first direction X, and the second data signal line group may include a third data signal line 52-3 and a fourth data signal line 52-4 installed sequentially along a first direction X.

[0106] In an exemplary embodiment, the first data signal line 52-1 and the compensation signal line 53 are formed to limit the first pixel row, the second data signal line 52-2 and the first power supply line 51-1 are installed in the first pixel row, the second data signal line 52-2 may be installed on the side of the first data signal line 52-1 closer to the compensation signal line 53, the first power supply line 51-1 may be installed on the side of the compensation signal line 53 closer to the first data signal line 52-1, and the first electrode plate 61, the third connecting electrode 13 and the fourth connecting electrode 14 may be installed between the second data signal line 52-2 and the first power supply line 51-1.

[0107] In an exemplary embodiment, the fourth data signal line 52-4 and the compensation signal line 53 are formed to limit the second pixel row, the second first power line 51-2 and the third data signal line 52-3 are installed in the second pixel row, the second first power line 51-2 may be installed on the side of the compensation signal line 53 closer to the fourth data signal line 52-4, the third data signal line 52-3 may be installed on the side of the fourth data signal line 52-4 closer to the compensation signal line 53, and the first electrode plate 61, the third connecting electrode 13 and the fourth connecting electrode 14 may be installed between the second first power line 51-2 and the third data signal line 52-3.

[0108] In an exemplary embodiment, the power connection block 54 may be installed on the first power line 51. The shape of the power connection block 54 may be block-shaped (rectangular), with the first end of the power connection block 54 connected to the first power line 51, and the second end of the power connection block 54 extending in a direction away from the compensation signal line 53, and the power connection block 54 is configured to be connected to the first region of the second active layer via a power connection electrode that is subsequently formed.

[0109] In exemplary embodiments, the first power line 51, data signal line 52, and compensation signal line 53 may be polylines of non-equal width. By employing polylines of variable width, not only is the layout of the pixel structure made easier, but parasitic capacitance can also be reduced.

[0110] In exemplary embodiments, the orthographic projection of the compensation signal line 53 at its base at least partially overlaps with the orthographic projection of the vertical reference line at its base, the positions of the two first power lines 51 may be substantially mirror-symmetric with respect to the vertical reference line, and the positions of the two data signal lines 52 located on the opposite side of the compensation signal line 53 in the first direction X may be substantially mirror-symmetric with respect to the vertical reference line.

[0111] In an exemplary embodiment, with respect to the third connection electrode 13, the fourth connection electrode 14, and the power connection block 54, the positions of the patterns in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetric with respect to the horizontal reference line, the positions of the patterns in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to the horizontal reference line, the positions of the patterns in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetric with respect to the vertical reference line, and the positions of the patterns in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to the vertical reference line.

[0112] (13) Forming a semiconductor layer pattern. In exemplary embodiments, as shown in Figures 7A and 7B, forming a semiconductor layer pattern may include sequentially depositing a first insulating thin film and a semiconductor thin film on a base on which the aforementioned pattern is formed, and then patterning the semiconductor thin film by a patterning process to form a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer placed on the first insulating layer. Figure 7B is a schematic diagram of the semiconductor layer in Figure 7A.

[0113] In an exemplary embodiment, the semiconductor layer of each subpixel on the display substrate may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second plate 62 of a memory capacitor, wherein the first active layer 21 may be the active layer of the first transistor T1, the second active layer 22 may be the active layer of the second transistor T2, the third active layer 23 may be the active layer of the third transistor T3, and the second plate 62 may be another transparent plate of a transparent memory capacitor, and the second plate 62 is configured to form a transparent memory capacitor with the first plate 61.

[0114] In an exemplary embodiment, for the first subpixel P1 and the second subpixel P2, the first active layer 21 and the third active layer 23 may be installed on the second direction Y side of the first electrode plate 61 of the subpixel, and the second active layer 22 may be installed on the opposite side of the second direction Y of the first electrode plate 61 of the subpixel.

[0115] In an exemplary embodiment, for the first subpixel P1, the first active layer 21 may be installed on the side of the subpixel away from the second subpixel P2, and the third active layer 23 may be installed on the side of the subpixel closer to the second subpixel P2. For the second subpixel P2, the first active layer 21 may be installed on the side of the subpixel away from the first subpixel P1, and the third active layer 23 may be installed on the side of the subpixel closer to the first subpixel P1.

[0116] In an exemplary embodiment, for the third subpixel P3 and the fourth subpixel P4, the first active layer 21 and the third active layer 23 may be installed on the opposite side of the first electrode plate 61 of the subpixel in the second direction Y, and the second active layer 22 may be installed on the side of the first electrode plate 61 of the subpixel in the second direction Y.

[0117] In an exemplary embodiment, for the third subpixel P3, the first active layer 21 may be installed on the side away from the fourth subpixel P4, and the third active layer 23 may be installed on the side closer to the fourth subpixel P4. For the fourth subpixel P4, the first active layer 21 may be installed on the side away from the third subpixel P3, and the third active layer 23 may be installed on the side closer to the third subpixel P3.

[0118] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions.

[0119] In an exemplary embodiment, the orthographic projection at the base of a first region of the first active layer 21 of each subpixel at least partially overlaps with the orthographic projection at the base of the corresponding data signal line 52, and the second region of the first active layer 21 is connected to the second electrode plate 62.

[0120] In an exemplary embodiment, the second electrode plate 62 and the first active layer 21 of each subpixel may be an integrated structure that is interconnected.

[0121] In an exemplary embodiment, the orthographic projection of the first region of the second active layer 22 of each subpixel at the base at least partially overlaps with the orthographic projection of the power connection block 54 of the first power line 51 at the base, and the orthographic projection of the second region and channel region of the second active layer 22 at the base at least partially overlaps with the orthographic projection of the third connection electrode 13 at the base, thereby allowing the first electrode plate 61 as a shielding layer to shield the channel region of the second transistor T2, preventing light from influencing the channel and ensuring the electrical characteristics of the second transistor T2.

[0122] In an exemplary embodiment, the orthogonal projection of the base of the first region of the third active layer 23 of each subpixel at least partially overlaps with the orthogonal projection of the base of the compensation signal line 53, and the orthogonal projection of the base of the second region of the third active layer 23 at least partially overlaps with the orthogonal projection of the base of the fourth connecting electrode 14 of the subpixel.

[0123] In an exemplary embodiment, the first region of the third active layer 23 in the first subpixel P1 may be connected to the first region of the third active layer 23 in the second subpixel P2, and the first region of the third active layer 23 in the third subpixel P3 may be connected to the first region of the third active layer 23 in the fourth subpixel P4.

[0124] In exemplary embodiments, the third active layer 23 in the first subpixel P1 and the third active layer 23 in the second subpixel P2 may be an integrated structure that is interconnected, and the third active layer 23 in the third subpixel P3 and the third active layer 23 in the fourth subpixel P4 may be an integrated structure that is interconnected. In this disclosure, by installing the third active layers of two adjacent subpixels in a single pixel row in an integrated structure that is interconnected, not only is space saved, but the via connection structure can also be reduced and the manufacturing process can be simplified.

[0125] In an exemplary embodiment, the orthographic projection of the base of the third active layer 23 overlaps at least partially with the orthographic projection of the base of the first power line 51.

[0126] In exemplary embodiments, the shape of the second electrode plate 62 may be rectangular, and chamfers may be provided on the corners of the rectangle, the second electrode plate 62 may be placed between the second active layer 22 and the third active layer 23 of the subpixel, the orthographic projection of the base of the second electrode plate 62 at least partially overlaps with the orthographic projection of the base of the first electrode plate 61, the second electrode plate 62 may also be a transparent intermediate electrode plate of a transparent memory capacitor, and the first electrode plate 61 and the second electrode plate 62 form a transparent first capacitor.

[0127] In an exemplary embodiment, the area of ​​the second electrode plate 62 in each subpixel may be basically the same so that the capacitance of the memory capacitor in each subpixel is basically the same.

[0128] In exemplary embodiments, the semiconductor layer can be made of metal oxides, such as oxides containing indium and tin, oxides containing tungsten and indium, oxides containing tungsten, indium and zinc, oxides containing titanium and indium, oxides containing titanium, indium and tin, oxides containing indium and zinc, oxides containing silicon, indium and tin, oxides containing indium, gallium and zinc, and the like. The semiconductor layer may be a single layer, a double layer, or a multi-layer layer.

[0129] In exemplary embodiments, the positions of the semiconductor layer patterns in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the semiconductor layer patterns in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the semiconductor layer patterns in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetric with respect to a vertical reference line, and the positions of the semiconductor layer patterns in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to a vertical reference line.

[0130] (14) Forming a second insulating layer pattern. In an exemplary embodiment, as shown in Figure 8, forming a second insulating layer pattern may include depositing a second insulating thin film on a base on which the aforementioned pattern is formed, patterning the second insulating thin film by a patterning process to form a second insulating layer pattern covering the semiconductor layer, and providing a plurality of vias in the second insulating layer.

[0131] In an exemplary embodiment, the multiple vias of each subpixel on the display substrate include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, and a sixth via V6.

[0132] In an exemplary embodiment, the orthographic projection of the first via V1 at its base at least partially overlaps the orthographic projection of the first region of the first active layer 21 at its base, and the orthographic projection of the first via V1 at its base at least partially overlaps the orthographic projection of the data signal line 52 at its base. The first via V1 is a via in a relay structure and includes two half-holes, the second insulating layer in the shallow half-hole is etched away to expose the surface of the first region of the first active layer 21, and the first and second insulating layers in the deep half-hole are etched away to expose the surface of the data signal line 52, so that the first via V1 in the relay structure consisting of two half-holes simultaneously exposes the first region of the first active layer 21 and the data signal line 52, and the first via V1 is configured such that a subsequently formed data connection electrode is connected to the first region of the first active layer 21 and the data signal line 52 via the via.

[0133] In an exemplary embodiment, the orthographic projection of the base of the second via V2 at least partially overlaps with the orthographic projection of the base of the first region of the second active layer 22, and the orthographic projection of the base of the second via V2 at least partially overlaps with the orthographic projection of the base of the power connection block 54 of the first power line 51. The second via V2 is a via in a relay structure and includes two half-holes, the second insulating layer in the shallow half-hole is etched away to expose the surface of the first region of the second active layer 22, and the first and second insulating layers in the deep half-hole are etched away to expose the surface of the power connection block 54, so that the second via V2 of the relay structure consisting of two half-holes simultaneously exposes the first region of the second active layer 22 and the power connection block 54, and the second via V2 is configured such that a subsequently formed power connection electrode is connected to the first region of the second active layer 22 and the power connection block 54 via the via.

[0134] In an exemplary embodiment, the orthographic projection of the base of the third via V3 at least partially overlaps with the orthographic projection of the base of the second region of the second active layer 22, and the orthographic projection of the base of the third via V3 at least partially overlaps with the orthographic projection of the base of the third connecting electrode 13. The third via V3 is a via in a relay structure and includes two half-holes, the second insulating layer in the shallow half-hole is etched away to expose the surface of the second region of the second active layer 22, and the first and second insulating layers in the deep half-hole are etched away to expose the surface of the third connecting electrode 13, so that the third via V3 in the relay structure consisting of two half-holes simultaneously exposes the second region of the second active layer 22 and the third connecting electrode 13, and the third via V3 is configured such that a subsequently formed fifth connecting electrode is connected to the second region of the second active layer 22 and the third connecting electrode 13 via the via.

[0135] In an exemplary embodiment, the orthographic projection of the base of the fourth via V4 at least partially overlaps with the orthographic projection of the base of the first region of the third active layer 23, and the orthographic projection of the base of the fourth via V4 at least partially overlaps with the orthographic projection of the base of the compensation signal line 53. The fourth via V4 is a via in a relay structure and includes two half-holes, the second insulating layer in the shallow half-hole is etched away to expose the surface of the first region of the third active layer 23, and the first and second insulating layers in the deep half-hole are etched away to expose the surface of the compensation signal line 53, so that the fourth via V4 in a relay structure consisting of two half-holes simultaneously exposes the first region of the third active layer 23 and the compensation signal line 53, and the fourth via V4 is configured such that a subsequently formed compensation connection electrode is connected to the first region of the third active layer 23 and the compensation signal line 53 via the via.

[0136] In an exemplary embodiment, the first regions of the third active layer in the first subpixel P1 and the second subpixel P2 are interconnected, and the first regions of the third active layer in the third subpixel P3 and the fourth subpixel P4 are interconnected, so that the first subpixel P1 and the second subpixel P2 share one fourth via V4, and the third subpixel P3 and the fourth subpixel P4 share one fourth via V4.

[0137] In an exemplary embodiment, the orthographic projection of the base of the fifth via V5 at least partially overlaps with the orthographic projection of the base of the second region of the third active layer 23, and the orthographic projection of the base of the fifth via V5 at least partially overlaps with the orthographic projection of the base of the fourth connecting electrode 14. The fifth via V5 is a via in a relay structure and includes two half-holes, the second insulating layer in the shallow half-hole is etched away to expose the surface of the second region of the third active layer 23, and the first and second insulating layers in the deep half-hole are etched away to expose the surface of the fourth connecting electrode 14, so that the fifth via V5 in a relay structure consisting of two half-holes simultaneously exposes the second region of the third active layer 23 and the fourth connecting electrode 14, and the fifth via V5 is configured such that a subsequently formed sixth connecting electrode is connected to the second region of the third active layer 23 and the fourth connecting electrode 14 via the via.

[0138] In an exemplary embodiment, the orthographic projection of the base of the sixth via V6 lies within the orthographic projection of the base of the second electrode plate 62, the second insulating layer within the sixth via V6 is etched away to expose the surface of the second electrode plate 62, and the sixth via V6 is configured such that a subsequently formed second gate electrode is connected to the second electrode plate 62 via the via.

[0139] In an exemplary embodiment, during the formation process of the second insulating layer pattern, a plurality of vias are formed using a dry etching process, and the semiconductor layer exposed within the vias is subjected to a first conductive treatment to form a first conductive region in the semiconductor layer exposed within the vias. In the first conductive treatment, the edges of the semiconductor layer covered by the second insulating layer that are close to the vias are also made conductive, that is, the semiconductor layer that is made conductive in the first treatment extends in a direction away from the vias.

[0140] (15) Forming a third conductive layer pattern. In exemplary embodiments, as shown in Figures 9A and 9B, forming a third conductive layer pattern may include depositing a third conductive thin film on a base on which the aforementioned pattern is formed, and then patterning the third conductive thin film by a patterning process to form a third conductive layer pattern on the second insulating layer. Figure 9B is a schematic diagram of the third conductive layer in Figure 9A. In exemplary embodiments, the third conductive layer may be referred to as a gate metal (GT) layer.

[0141] In an exemplary embodiment, the third conductive layer of each subpixel on the display substrate may include at least a fifth connection electrode 15, a sixth connection electrode 16, a data connection electrode 17, a power connection electrode 18, a compensation connection electrode 19, a scan signal line 30, a first gate electrode 31, a second gate electrode 32, and a third gate electrode 33.

[0142] In an exemplary embodiment, the shape of the scanning signal line 30 may be linear with the main body extending along a first direction X, and one scanning signal line 30 may form limiting two pixel rows, and the scanning signal line 30 may be located between a first pixel row (including a first subpixel P1 and a second subpixel P2) and a second pixel row (including a third subpixel P3 and a fourth subpixel P4), and the scanning signal line 30 may be configured to simultaneously control the on or off of all first transistors T1 and all third transistors T3 in four subpixels of the repeating unit.

[0143] In an exemplary embodiment, the shape of the first gate electrode 31 may be a strip extending along a second direction Y, and the first gate electrode 31 may be located on the side of the scan signal line 30 closer to the first active layer 21, with the first end of the first gate electrode 31 connected to the scan signal line 30, the second end of the first gate electrode 31 extending toward the first active layer 21, and the orthographic projection of the base of the first gate electrode 31 at least partially overlapping the orthographic projection of the base of the first active layer 21. In an exemplary embodiment, the first gate electrode 31 may also be the gate electrode of the first transistor T1, so that the scan signal line 30 can control the on or off of the first transistor T1.

[0144] In an exemplary embodiment, the shape of the second gate electrode 32 may be a strip extending along a second direction Y, the first end of the second gate electrode 32 is connected to the second electrode plate 62 via a sixth via V6, the second end of the second gate electrode 32 extends toward the second active layer 22, and the orthographic projection of the second gate electrode 32 at the base at least partially overlaps with the orthographic projection of the second active layer 22 at the base. In an exemplary embodiment, the second gate electrode 32 may also be the gate electrode of a second transistor T2 and may control the on or off state of the second transistor T2.

[0145] In an exemplary embodiment, the second gate electrode 32 is connected to the second electrode plate 62, and the second electrode plate 62 is connected to the second region of the first active layer 21, so that the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 62 (the first end of the memory capacitor) have the same potential, a first node of the pixel driving circuit is formed, and the second electrode plate 62 has the potential of the first node of the pixel driving circuit.

[0146] In an exemplary embodiment, the shape of the third gate electrode 33 may be a strip extending along a second direction Y, and the third gate electrode 33 may be located on the side of the scan signal line 30 closer to the third active layer 23, with the first end of the third gate electrode 33 connected to the scan signal line 30, the second end of the third gate electrode 33 extending toward the third active layer 23, and the orthographic projection of the base of the third gate electrode 33 at least partially overlapping the orthographic projection of the base of the third active layer 23. In an exemplary embodiment, the third gate electrode 33 may also be the gate electrode of the third transistor T3, so that the scan signal line 30 can control the on or off of the third transistor T3.

[0147] In an exemplary embodiment, in one subpixel, one scan signal line 30 is simultaneously connected to a first gate electrode 31 and a third gate electrode 33, thereby allowing the scan signal line 30 to control the on or off state of a first transistor T1 and a third transistor T3 in one subpixel.

[0148] In an exemplary embodiment, in one pixel row, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 of multiple subpixels, thereby allowing the scan signal line 30 to control the on or off state of all first transistors T1 and all third transistors T3 in one pixel row.

[0149] In an exemplary embodiment, in a repeating unit, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 of multiple subpixels, thereby allowing the scan signal line 30 to simultaneously control the on or off state of all first transistors T1 and all third transistors T3 of the repeating unit.

[0150] In an exemplary embodiment, the scanning signal line 30, the first gate electrode 31, and the third gate electrode 33 may be connected to each other in an integrated structure within at least one repeating unit.

[0151] In exemplary embodiments, the shape of the fifth connecting electrode 15 may be block-shaped (e.g., rectangular), and the fifth connecting electrode 15 may be located on the side of the second electrode plate 62 away from the scanning signal line 30, and the fifth connecting electrode 15 is simultaneously connected to the second region of the second active layer 22 and the third connecting electrode 13 via the third via V3.

[0152] In an exemplary embodiment, the third connecting electrode 13 is connected to the first connecting electrode 11, and the first connecting electrode 11 is connected to the first plate 61, so that the second electrode and the first plate 61 of the second transistor have the same potential due to the fifth connecting electrode 15. In an exemplary embodiment, the fifth connecting electrode 15 is configured to be connected to a subsequently formed tenth connecting electrode.

[0153] In exemplary embodiments, the shape of the sixth connecting electrode 16 may be block-shaped (e.g., rectangular), and the sixth connecting electrode 16 may be located on the side of the second electrode plate 62 closer to the scanning signal line 30, and the sixth connecting electrode 16 is simultaneously connected to the second region of the third active layer 23 and the fourth connecting electrode 14 via the fifth via V5.

[0154] In an exemplary embodiment, the fourth connecting electrode 14 is connected to the second connecting electrode 12, and the second connecting electrode 12 is connected to the first plate 61, so that the second electrode and the first plate 61 of the third transistor have the same potential due to the sixth connecting electrode 16.

[0155] In an exemplary embodiment, the fifth connecting electrode 15 and the sixth connecting electrode 16 realize a connection between the second electrode of the second transistor, the second electrode of the third transistor, and the first electrode plate 61 (the second terminal of the memory capacitor), and a second node is formed in the pixel driving circuit, so that the first electrode plate 61 has the potential of the second node in the pixel driving circuit.

[0156] In an exemplary embodiment, the first plate 61 has the potential of the second node in the pixel driving circuit, and the second plate 62 has the potential of the first node in the pixel driving circuit. Therefore, the first plate 61 having the potential of the second node and the second plate 62 having the potential of the first node form a memory capacitor.

[0157] In an exemplary embodiment, a transparent conductive material is used for the first electrode plate 61 and a transparent metal oxide is used for the second electrode plate 62, so the memory capacitor is a transparent capacitor.

[0158] In an exemplary embodiment, the shape of the data connection electrode 17 may be block-shaped (e.g., rectangular), and the data connection electrode 17 is simultaneously connected to the first region of the first active layer 21 and the data signal line 52 via the first via V1, thereby enabling the data signal line 52 to write a data signal to the first electrode of the first transistor T1. In an exemplary embodiment, each data signal line 52 may be connected via the first via V1 to the first region of the first active layer in one subpixel, thereby enabling four data signal lines 52 to write data signals to the first electrodes of four first transistors T1 in one repeating unit.

[0159] In an exemplary embodiment, the four data signal lines 52 may include a first data signal line 52-1, a second data signal line 52-2, a third data signal line 52-3, and a fourth data signal line 52-4, which are sequentially arranged along a first direction X. The first data signal line 52-1 may be located on the opposite side of the first direction X of the first pixel row and may be connected via a data connection electrode 17 to a first region of the first active layer in the first subpixel P1. The second data signal line 52-2 may be located on the first direction X side of the first data signal line and may be connected via a data connection electrode 17 to a first region of the first active layer in the third subpixel P3. The fourth data signal line 52-4 may be located on the first direction X side of the second pixel row and may be connected via a data connection electrode 17 to a first region of the first active layer in the fourth subpixel P4. The third data signal line 52-3 may be located on the opposite side of the first direction X of the fourth data signal line 52-4, and may be connected to the first region of the first active layer in the second subpixel P2 via the data connection electrode 17.

[0160] In exemplary embodiments, the shape of the power connection electrode 18 may be a strip extending along a first direction X, the power connection electrode 18 may be located on the side of the second electrode plate 62 away from the scan signal line 30, and the power connection electrode 18 may be simultaneously connected to the first region of the second active layer 22 and the power connection block 54 via a second via V2. The power connection block 54 is connected to the first power line 51, so that the first power line 51 writes the first power signal to the first electrode of the second transistor T2.

[0161] In an exemplary embodiment, the two first power lines 51 may include a first power line 51-1 and a second power line 51-2 that are sequentially installed along a first direction X. The first power line 51-1 may be located in a first pixel row opposite the first direction X of the compensation signal line 54 and may be connected via two power connection electrodes 18 in the first pixel row to first regions of the second active layer 22 in the first subpixel P1 and third subpixel P3, respectively. The second power line 51-2 may be located in a second pixel row on the first direction X side of the compensation signal line 54 and may be connected via two power connection electrodes 18 in the second pixel row to first regions of the second active layer 22 in the second subpixel P2 and fourth subpixel P4, respectively.

[0162] In exemplary embodiments, the first power line 51 of the first pixel row may simultaneously supply a first power signal to the pixel driving circuits of the first sub-pixel P1 and the third sub-pixel P3, and the first power line 51 of the second pixel row may simultaneously supply a first power signal to the pixel driving circuits of the second sub-pixel P2 and the fourth sub-pixel P4, so that the first power line 51 in one repeating unit has a 1:2 structure. By designing the first power line in a 1:2 structure, the display board of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a rational layout, makes full use of layout space, increases space utilization, and is advantageous for increasing resolution.

[0163] In an exemplary embodiment, two first power lines 51 in one repeating unit are symmetrically positioned with respect to the compensation signal line 53, and the second transistor T2 of the first pixel row and the second transistor T2 of the second pixel row are symmetrically positioned with respect to the compensation signal line 53. Such a symmetrical structure of the Disclosure ensures that the voltage drop written to the second transistor T2 by the first power lines is substantially the same, thereby ensuring uniformity of the display.

[0164] In an exemplary embodiment, the power supply connection electrodes 18 of the first subpixel P1 and the second subpixel P2 may be connected to each other, and the power supply connection electrodes 18 of the third subpixel P3 and the fourth subpixel P4 may be connected to each other.

[0165] In exemplary embodiments, the power supply connection electrodes 18 in the first subpixel P1 and the second subpixel P2 may be an integrated structure connected to each other, that is, the first subpixel P1 and the second subpixel P2 share one power supply connection electrode 18. The power supply connection electrodes 18 in the third subpixel P3 and the fourth subpixel P4 may also be an integrated structure connected to each other, that is, the third subpixel P3 and the fourth subpixel P4 share one power supply connection electrode 18.

[0166] In an exemplary embodiment, the power supply electrode 18 may also be a lateral power supply electrode, and the shape of the integrated power supply electrode is a strip extending along a first direction X, and is installed across a first pixel row and a second pixel row, so that the first sub-pixel P1 and the second sub-pixel P2 share one power supply electrode 18, the third sub-pixel P3 and the fourth sub-pixel P4 share one power supply electrode 18, and two first voltage lines 51 can simultaneously supply a first voltage signal to the pixel driving circuits in the four sub-pixels, so that the four pixel driving circuits in one repeating unit can share two first voltage lines 51.

[0167] In an exemplary embodiment, the orthographic projection of the base of the power connection electrode does not overlap with the orthographic projection of the base of the data signal line 52, and the orthographic projection of the base of the power connection electrode 18 overlaps at least partially with the orthographic projection of the base of the compensation signal line 53.

[0168] In exemplary embodiments, the shape of the compensation connection electrode 19 may be block-shaped (e.g., rectangular), and the compensation connection electrode 19 may be placed between the third gate electrodes 33 of two adjacent subpixels in a first direction X, and the compensation connection electrode 19 may be simultaneously connected to the first region of the third active layer 23 and the compensation signal line 53 via a fourth via V4, thereby enabling the compensation signal line 53 to write a compensation signal to the first electrode of the third transistor T3.

[0169] In an exemplary embodiment, the first regions of the third active layer in the first subpixel P1 and the second subpixel P2 are interconnected, and the first subpixel P1 and the second subpixel P2 share one fourth via V4, thus sharing one compensation connection electrode 19. The first regions of the third active layer in the third subpixel P3 and the fourth subpixel P4 are interconnected, and the third subpixel P3 and the fourth subpixel P4 share one fourth via V4, thus sharing one compensation connection electrode 19.

[0170] In an exemplary embodiment, the compensation signal line 53 can simultaneously supply compensation signals to the pixel drive circuits of four subpixels, so that the four pixel drive circuits of one repeating unit can share one compensation signal line 53, i.e., the compensation signal line 53 of one repeating unit has a 1:4 structure. By designing the compensation signal line of the display substrate of this disclosure to have a 1:4 structure, the number of signal lines is reduced, the occupied space is reduced, the structure is simple, the layout is rational, the layout space is fully utilized, the space utilization rate is increased, and it is advantageous for increasing the resolution.

[0171] In an exemplary embodiment, the compensation signal line 53 is positioned between the first and second pixel rows, and the third transistor T3 of the first pixel row and the third transistor T3 of the second pixel row are positioned symmetrically with respect to the compensation signal line 53. Such a symmetrical structure in the present disclosure ensures that the RC delay for which the compensation signal is written to the third transistor T3 is essentially the same, thereby ensuring uniformity of the display.

[0172] In exemplary embodiments, the positions of the patterns of the third conductive layer in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the patterns of the third conductive layer in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the patterns of the third conductive layer in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetric with respect to a vertical reference line, and the positions of the patterns of the third conductive layer in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to a vertical reference line.

[0173] In an exemplary embodiment, during the formation process of the third conductive layer pattern, the third conductive layer pattern is first formed using a wet etching process, and at least one connecting electrode is simultaneously connected to the second conductive layer and the semiconductor layer via a via of the relay structure. The via of the relay structure includes at least two half-holes, a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is etched away, and the first and second insulating layers in the deep half-hole are etched away, exposing the surface of the second conductive layer. This ensures that the connecting electrode is simultaneously connected to the semiconductor layer and the second conductive layer via the shallow and deep half-holes. In the exemplary embodiment, a certain distance is provided between the end of the connecting electrode located in the shallow half-hole region and the edge of the shallow half-hole, i.e., the connecting electrode does not completely cover the shallow half-hole.

[0174] In an exemplary embodiment, after forming a third conductive layer pattern using a wet etching process, the second insulating layer in areas other than the third conductive layer is etched using a dry etching process with the third conductive layer as a mask. As the second insulating layer is etched and removed, the exposed semiconductor layer is made a second conductor, forming a second conductive region.

[0175] In an exemplary embodiment, when the second conductive treatment is performed, the edge portion of the semiconductor layer covered by the third conductive layer is also made conductive. That is, the semiconductor layer that is made conductive the second time extends toward the first conductive region, forming two conductive regions in the overlapping region between the first and second conductive regions, thereby ensuring a reliable connection between the third conductive layer and the semiconductor layer.

[0176] (16) Forming a third insulating layer and a flat layer pattern. In an exemplary embodiment, as shown in Figure 10, forming the third insulating layer and the flat layer pattern may include depositing a third insulating thin film on a base on which the aforementioned pattern is formed, then applying a flat thin film, and patterning the flat thin film and the third insulating thin film by a patterning process to form a third insulating layer covering the third conductive layer and a flat layer pattern to be placed on the third insulating layer, wherein a plurality of vias are provided in the flat layer.

[0177] In an exemplary embodiment, each subpixel via on the display substrate includes at least an 11th via V11.

[0178] In an exemplary embodiment, the orthographic projection of the base of the 11th via V11 lies within the range of the orthographic projection of the base of the 5th connecting electrode 15, the 3rd insulating layer and the planar layer within the 11th via V11 are etched away to expose the surface of the 5th connecting electrode 15, and the 11th via V11 is configured such that a subsequently formed 11th connecting electrode connects to the 5th connecting electrode 15 via the via.

[0179] In exemplary embodiments, the present process may simultaneously form vias in the third insulating layer and the planar layer in a single patterning process, and the third insulating layer and the planar layer share a single halftone or graytone mask (MASK) process, effectively reducing the number of patterning processes.

[0180] (17) Forming a fourth conductive layer pattern. In exemplary embodiments, as shown in Figures 11A and 11B, forming a fourth conductive layer pattern may include depositing a fourth conductive thin film on a base on which the aforementioned pattern is formed, and then patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern on a flat layer. Figure 11B is a schematic diagram of the fourth conductive layer in Figure 11A.

[0181] In an exemplary embodiment, the fourth conductive layer of each subpixel on the display substrate may include at least a tenth connecting electrode 20 and a first electrode 70, the first electrode 70 being an anode.

[0182] In exemplary embodiments, the shape of the first electrode 70 may be rectangular, and the corners of the rectangle may be chamfered, recessed, or convex, and the orthogonal projection of the first electrode 70 on the base at least partially overlaps with the orthogonal projection of the second electrode plate 62 on the base.

[0183] In an exemplary embodiment, the shape of the tenth connecting electrode 20 may be block-shaped (e.g., rectangular), and the tenth connecting electrode 20 may be located on the side of the first electrode 70 away from the scan signal line 30, with the first end of the tenth connecting electrode 20 connected to the first electrode 70, and the second end of the tenth connecting electrode 20 extending along the direction away from the scan signal line 30 and then connected to the fifth connecting electrode 15 via the eleventh via V11.

[0184] In an exemplary embodiment, the tenth connecting electrode 20 and the first electrode 70 may be an integrated structure in which they are interconnected in at least one subpixel.

[0185] In an exemplary embodiment, the four first electrodes 70 in one repeating unit are arranged in a square, with the upper left anode connected to the pixel driving circuit of the first subpixel P1, the upper right anode connected to the pixel driving circuit of the second subpixel P2, the lower left anode connected to the pixel driving circuit of the third subpixel P3, and the lower right anode connected to the pixel driving circuit of the fourth subpixel P4. In several possible implementations, the arrangement of the anodes can be adjusted according to the actual needs, and this disclosure is not specifically limited thereto.

[0186] In exemplary embodiments, the material of the first conductive layer may be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0187] In exemplary embodiments, the positions of the patterns of the fourth conductive layer in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the patterns of the fourth conductive layer in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to a horizontal reference line, the positions of the patterns of the fourth conductive layer in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetric with respect to a vertical reference line, and the positions of the patterns of the fourth conductive layer in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetric with respect to a vertical reference line.

[0188] In an exemplary embodiment, the first electrode 70 may serve as an auxiliary capacitor for the memory capacitor. The first electrode 70 is connected to the tenth connecting electrode 20, which is connected to the first plate 61 via the fifth connecting electrode 15, the third connecting electrode 13, and the first connecting electrode 11. Thus, the first electrode 70 has the potential of the second node in the pixel driving circuit. As a result, the first electrode 70 having the potential of the second node and the second plate 62 having the potential of the first node form an auxiliary capacitor, and the auxiliary capacitor and the memory capacitor are connected in parallel. In this disclosure, by forming an auxiliary capacitor using an anode and connecting the auxiliary capacitor and the memory capacitor in parallel, the capacitance value of the memory capacitor can be effectively increased, and the plate area can be reduced while maintaining the capacitance value of the memory capacitor, thereby effectively reducing the occupied area.

[0189] (18) Form a pixel definition layer. In an exemplary embodiment, as shown in Figure 12, forming a pixel definition layer pattern may include applying a pixel definition thin film to a base on which the aforementioned pattern is formed, and then patterning the pixel definition thin film by a patterning process to form a pixel definition layer that covers the fourth conductive layer.

[0190] In an exemplary embodiment, a pixel aperture K is opened in the pixel definition layer of each subpixel on the display substrate, the pixel definition thin film within the pixel aperture K is removed, a portion of the surface of the first electrode 70 is exposed, and the orthogonal projection of the pixel aperture K at the base is located within the range of the orthogonal projection of the base of the first electrode 70.

[0191] In exemplary embodiments, the shape of the pixel aperture K may be similar to the shape of the first electrode 70 in a plane parallel to the base, and the cross-sectional shape of the pixel aperture K may be rectangular, trapezoidal, or the like in a plane perpendicular to the base.

[0192] In exemplary embodiments, the shape of the pixel aperture may be one or more of the following: triangle, rectangle, trapezoid, parallelogram, pentagon, hexagon, circle, or ellipse.

[0193] In exemplary embodiments, the shapes of the pixel apertures of the four subpixels may be the same or different. The areas of the pixel apertures of the four subpixels may be the same or different.

[0194] In an exemplary embodiment, the shapes and areas of the pixel apertures of the four subpixels may differ to accommodate the transmittance of different subpixel filters, thereby enabling the four subpixel light-emitting devices to emit the same brightness at different currents, maximizing the lifespan of the four subpixel light-emitting devices and ensuring the product's lifespan.

[0195] In exemplary embodiments, at least one blocking groove may be further provided in the pixel definition layer of each repeating unit of the display substrate, the shape of which the blocking groove M may be a strip with a main body extending along a first direction X or a second direction Y, or it may be provided between adjacent subpixels in the first direction X or the second direction Y, and the blocking groove M is configured to block the subsequently formed organic light-emitting layer, block the lateral propagation path of hole carriers, eliminate lateral leakage current, and eliminate lateral crosstalk of subpixels.

[0196] In exemplary embodiments, the pixel definition layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc.

[0197] (19) Forming the organic light-emitting layer and cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and cathode pattern may include first forming the organic light-emitting layer pattern, which is connected to the first electrode 70 via the pixel aperture K, and then forming the cathode, which is connected to the organic light-emitting layer.

[0198] In exemplary embodiments, the organic light-emitting layer may include an emissive layer (EML) and one or more layers selected from a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In exemplary embodiments, the organic light-emitting layer may be formed by deposition using a fine metal mask (FMM) or an open mask, or by employing an inkjet process.

[0199] (20) Forming a package structure layer pattern. In an exemplary embodiment, forming a package structure layer pattern may include depositing a first inorganic thin film using an open mask to form a first package layer, then inkjet printing an organic material onto the first package layer by an inkjet printing method, curing to form a film, and then forming a second package layer, and subsequently depositing a second inorganic thin film using an open mask to form a third package layer, wherein the first, second, and third package layers constitute a package structure layer. The first and third package layers may employ one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), carbon silicon nitride (SiCN), and silicon nitride (SiON), and may be single layers, multilayer layers, or composite layers. The second package layer may employ a resin material and form an inorganic / organic / inorganic laminated structure, where the organic material layer is placed between two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0200] This completes the manufacturing of a display substrate according to an exemplary embodiment of the present disclosure. The display substrate may include a drive circuit layer installed on a base, a light-emitting structure layer installed on the side of the drive circuit layer away from the base, and a package structure layer installed on the side of the light-emitting structure layer away from the base. In a direction perpendicular to the base, the drive circuit layer may include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a planar layer installed sequentially on the base; the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode; and the package structure layer may include a first package layer, a second package layer, and a third package layer that are stacked.

[0201] In an exemplary embodiment, for a display substrate having a color film structure layer, a third conductive layer may be formed first, followed by a third insulating layer, then a red color film layer, a green color film layer, a blue color film layer, and then a flat layer, although this is omitted here.

[0202] In exemplary embodiments, the base may be a flexible base or a rigid base. The rigid base may be one or more of glass and quartz, but is not limited thereto. The flexible base may be one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and woven fibers, but is not limited thereto. In exemplary embodiments, the flexible base may include a laminated first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials for the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials for the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx) to improve the hydroxyl resistance of the base. The semiconductor layer may be amorphous silicon (a-si).

[0203] In exemplary embodiments, the first conductive layer, the second conductive layer, and the third conductive layer may be made of a metallic material, for example, one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, for example, aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multilayer composite structure, for example, Mo / Cu / Mo. The first insulating layer, the second insulating layer and the third insulating layer may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The flat layer may be made of an organic material, for example, a resin.

[0204] Currently, conventional display devices have problems such as low aperture ratio and light leakage from pixels. Research by the inventors of this invention has shown that the above problems are due to an unreasonable arrangement of signal lines. In a conventional repeating unit of a display device, the arrangement of one compensation signal line, two first power lines, and four data signal lines is as follows: the compensation signal line is placed between the first and second pixel rows, two data signal lines are placed on the side of the first pixel row away from the compensation signal line, one first power line is placed on the side of the two data signal lines away from the compensation signal line, the other two data signal lines are placed on the side of the second pixel row away from the compensation signal line, another first power line is placed on the side of the two data signal lines away from the compensation signal line, and the pixel driving circuit is placed between the data signal line and the compensation signal line. Because only one compensation signal line is installed between the first and second pixel rows, the distance between the first and third subpixels in the first pixel row and the second and fourth subpixels in the second pixel row becomes shorter. This makes the pixel aperture more susceptible to loss, reducing the aperture ratio and increasing the risk of light leakage from pixels, resulting in the light leakage problem. Furthermore, for adjacent first and second repeating units in the first direction, five signal lines (two data signal lines for each pixel row and a first power line shared by both pixel rows) are installed between the second pixel row of the first repeating unit and the first pixel row of the second repeating unit. This increases the distance between the second and fourth subpixels in the second pixel row of the first repeating unit and the first and third subpixels in the first pixel row of the second repeating unit, resulting in a relatively large amount of wasted space.

[0205] Embodiments of the present disclosure provide a display substrate with a bottom emission structure that can effectively increase the aperture ratio and reduce the risk of light leakage from pixels by adjusting the arrangement of signal lines. The arrangement of one compensation signal line, two first power lines, and four data signal lines in one repeating unit of the present disclosure is such that the compensation signal line is located in the middle of the first direction of the repeating unit (between the first and second pixel rows), the first first power line is located on the side of the first pixel row closer to the compensation signal line, the second first power line is located on the side of the second pixel row closer to the compensation signal line, the two data signal lines are located on the side of the first pixel row further away from the compensation signal line, and the other two data signal lines are The second pixel row is positioned away from the compensation signal line, and the arrangement order of the signal lines changes to the first data signal line, the second data signal line, the first power line, the compensation signal line, the second power line, the third data signal line, and the fourth data signal line. Furthermore, the pixel drive circuit in the first pixel row is positioned between the second data signal line and the first power line, and the pixel drive circuit in the second pixel row is positioned between the second power line and the third data signal line. In this disclosure, the first power line and the compensation signal line are positioned in the middle of the repeating unit, and the data signal lines are positioned on both sides of the repeating unit, thereby effectively balancing the distance distribution of the opaque metal signal lines between subpixels. Since one compensation signal line and two first power lines are installed between the first and second pixel rows, the distance between the subpixels of the first and second pixel rows is increased. This not only avoids pixel aperture loss and effectively increases the aperture ratio, but also reduces the risk of pixel light leakage and effectively eliminates it. Furthermore, since four signal lines (two data signal lines for each pixel row) are installed between the second pixel row of the first repeating unit and the first pixel row of the second repeating unit, the distance between the subpixels of the first and second repeating units is shortened, which is advantageous for saving space and improving resolution.

[0206] In conventional display devices, the first power line in each pixel row is located away from the compensation signal lines of the two data signal lines. Therefore, in each pixel row, a power connection line extending along the first direction X (lateral direction) is installed to connect the first power line to the second transistor, and the orthographic projection of the base of the power connection line must coincide with the orthographic projection of the base of the two data signal lines. In other words, in conventional structures, the power connection line cross-overlaps with all four data signal lines.

[0207] In the embodiments of this disclosure, the first power line is positioned on the side of the pixel row closer to the compensation signal line, and the data signal line is positioned on the side of the pixel row further away from the compensation signal line. As a result, the orthogonal projection of the base of the power connection electrode, which acts as a lateral power connection line, does not overlap with the orthogonal projection of the base of the data signal line. That is, the power connection electrode in the embodiments of this disclosure does not cross-line overlap with any of the four data signal lines, but only with one compensation signal line. By reducing the cross-line structure in the embodiments of this disclosure, process accuracy can be effectively improved and product yield can be effectively increased.

[0208] In the embodiments of this disclosure, two power connection electrodes are installed in the repeating unit, and each of the two power connection electrodes is connected to two first power lines, thereby forming a ring structure for transmitting the first power signal within the repeating unit, which is advantageous for improving the product yield rate. For example, if there is a short-circuit failure at a position where the power connection electrodes straddle the compensation signal line, the short-circuit failure can be repaired by cutting one of the power connection electrodes, thereby improving the product yield rate. Also, for example, if there is a short-circuit failure at a position where the third active layer straddles the first power line, the short-circuit failure can be repaired by cutting one of the first power lines, thereby improving the product yield rate.

[0209] In the embodiments of this disclosure, by installing two first power lines on both sides of the compensation signal line, the first power lines, which have a constant potential, can effectively shield the compensation signal line from the influence of jump signals in the pixel driving circuit, thereby improving the accuracy of external compensation and enhancing display effect and display quality.

[0210] In the embodiments of this disclosure, structures such as the first power line, data signal line, and compensation signal line are placed in the SHIELD layer and located on the side closer to the base of the semiconductor layer, while structures such as the scanning signal line and gate electrodes of multiple transistors are placed in the GT layer and located on the side further away from the base of the semiconductor layer. This not only reduces the number of conductive layers by one, but also reduces the patterning process for the relay vias and the patterning process for the relay conductive layer. As a result, the manufacturing process for the drive structure layer requires only six patterning processes, reducing the number of patterning processes, effectively improving manufacturing efficiency, effectively lowering production costs, and maximizing the product yield.

[0211] In the embodiments of this disclosure, a 3T1C pixel drive circuit with one scan signal line is employed, and the single scan signal line is connected to the first and third transistors in the pixel drive circuit. By reducing the number of scan signal lines, the structure of the pixel drive circuit is simplified, the area occupied by the pixel drive circuit is reduced, and it is advantageous for realizing high-resolution display. Furthermore, since one repeating unit is driven by only one scan signal line, the number of corresponding gate drive circuits (GOA) and clock signal lines (CLK) can be doubled, which is advantageous for effectively reducing the area occupied by the gate drive circuits and clock signal lines, enabling a narrow bezel and enhancing the product's competitive advantage.

[0212] In the embodiments of this disclosure, a transparent memory capacitor is constructed using a transparent conductive layer and a transparent semiconductor layer. This allows light to pass through the transparent memory capacitor and be emitted, enabling the memory capacitor to be placed within the pixel aperture. This not only effectively increases the capacitance of the memory capacitor but also effectively increases the pixel aperture ratio.

[0213] The pixels in the embodiments of this disclosure are arranged in a square pattern, and by employing a non-mesh first power line structure, the pixel aperture ratio can be effectively increased, improving the display effect and making it more suitable for display-type displays.

[0214] The manufacturing process disclosed herein is highly compatible with existing manufacturing processes, is easy to implement and realize, offers high production efficiency, low manufacturing costs, and a high yield rate.

[0215] Figure 13 is an equivalent circuit diagram of a pixel driving circuit in another repeating unit of an exemplary embodiment of the present disclosure, and Figure 14 is a schematic planar structure of another display board of an exemplary embodiment of the present disclosure. As shown in Figures 13 and 14, the pixel driving circuit and the main body structure of the display board of this embodiment are basically the same as those of the embodiments shown in Figures 3 and 4, the difference being that one first power line 51 is installed in one repeating unit of this embodiment.

[0216] In exemplary embodiments, at least one repeating unit may comprise one scan signal line 30, one first power line 51, four data signal lines 52, and one compensation signal line 53, and the shape, position, and connection relationship with the pixel driving circuit of the scan signal line 30, data signal line 52, and compensation signal line 53 may be basically the same as in the embodiments described above. The pixel driving circuit of at least one subpixel may include a first transistor T1, a second transistor T2, a third transistor T3, and a memory capacitor 60, and the memory capacitor 60 may include at least a first plate 61 and a second plate 62 as capacitor plates, and the associated connection structure is basically the same as in the embodiments described above and is omitted here.

[0217] In an exemplary embodiment, the first power line 51 may be installed on the first direction X side of the compensation signal line 53, that is, the first power line 51 may be installed on the side of the second pixel row closer to the compensation signal line 53. In another exemplary embodiment, the first power line 51 may be installed on the opposite side of the first direction X of the compensation signal line 53, that is, the first power line 51 may be installed on the side of the first pixel row closer to the compensation signal line 53.

[0218] In an exemplary embodiment, the shape of the power supply connection electrode 18 may be a strip extending along the first direction X, the power supply connection electrode 18 in the first subpixel P1 and the second subpixel P2 may be an integral structure connected to each other, and the power supply connection electrode 18 in the third subpixel P3 and the fourth subpixel P4 may be an integral structure connected to each other.

[0219] In an exemplary embodiment, the first power line 51 is typically located in the second pixel row. The first end of the power connection electrode 18 is connected to a first region of the second active layer 22 of the first pixel row via a second via V2 of the first pixel row, and the second end of the power connection electrode 18 extends to the second pixel row along a first direction X and is simultaneously connected to the first region of the second active layer 22 of the second pixel row and the first power line 51 via a second via V2 of the second pixel row, thereby enabling the first power line 51 to write the first power signal to the first electrodes of the four second transistors T2 in the two pixel rows.

[0220] In an exemplary embodiment, one first power line 51 can simultaneously supply a first power signal to the pixel drive circuits in four subpixels, so that the first power lines 51 in one repeating unit have a 1:4 structure. By designing the first power lines in a 1:4 structure, the display board of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a rational layout, makes full use of layout space, increases space utilization, and is advantageous for increasing resolution.

[0221] In an exemplary embodiment, the power connection electrode 18 may also be a lateral power connection line, the orthographic projection of the base of the power connection electrode 18 does not overlap with the orthographic projection of the base of the data signal line 52, and the orthographic projection of the base of the power connection electrode 18 at least partially overlaps with the orthographic projection of the base of the compensation signal line 53.

[0222] In an exemplary embodiment, for two adjacent subpixels in a repeating unit in a first direction X, a subpixel without a first power line 51 is called a subpixel without a power line, and a subpixel with a first power line 51 is called a subpixel with a power line. The first distance between the memory capacitor and the compensation signal line in a subpixel without a power line may be greater than or equal to the second distance between the memory capacitor and the first power line in a subpixel with a power line. In an exemplary embodiment, the distance between the memory capacitor and the compensation signal line may be the maximum distance between at least one capacitor plate of the memory capacitor and the compensation signal line, and the distance between the memory capacitor and the first power line may be the maximum distance between at least one capacitor plate of the memory capacitor and the first power line.

[0223] For example, let's consider the case where the first power line 51 is installed in the second pixel row. In the first pixel row, there is a first distance L1 between the right edge of the first electrode plate 61 on the side closer to the compensation signal line 53 and the left edge of the compensation signal line 53 on the side closer to the first electrode plate 61. In the second pixel row, there is a second distance L2 between the left edge of the first electrode plate 61 on the side closer to the first power line 51 and the right edge of the first power line 51 on the side closer to the first electrode plate 61. Let's also consider the case where the first power line 51 is installed in the first pixel row. In the first pixel row, there is a second distance L2 between the right edge of the second electrode plate 62 on the side closer to the first power line 51 and the left edge of the first power line 51 on the side closer to the second electrode plate 62. In the second pixel row, there is a first distance L1 between the left edge of the second electrode plate 62 on the side closer to the compensation signal line 53 and the right edge of the compensation signal line 53 on the side closer to the second electrode plate 62. The first distance L1 may be greater than or equal to the second distance L2, and the first distance L1 and the second distance L2 may be the size in the first direction X.

[0224] In an exemplary embodiment, both the first distance L1 and the second distance L2 may be greater than the minimum distance between the edge of the compensation signal line 53 closest to the first power line 51 and the edge of the first power line 51 closest to the compensation signal line 53.

[0225] In exemplary embodiments, the first distance L1 may be 3 μm or more.

[0226] In this disclosure, by setting the distance between the memory capacitor and the compensation signal line, the influence of jump signals in the pixel driving circuit on the compensation signal line can be effectively reduced, thereby ensuring the accuracy of external compensation. A first power line is installed between the pixel driving circuit and the compensation signal line in a sub-pixel with a power line, and the first power line, which has a constant potential, can effectively shield the influence of jump signals in the pixel driving circuit on the compensation signal line. Therefore, while ensuring the accuracy of external compensation, the distance between the memory capacitor and the compensation signal line can be maintained or appropriately reduced.

[0227] The display substrate provided in the embodiments of this disclosure has the same technical effects as the embodiments described above, namely, it can effectively increase the aperture ratio, reduce the risk of light leakage from pixels, effectively improve process accuracy, and effectively improve the yield rate of products. In addition, in the embodiments of this disclosure, by reducing the number of first power lines by one, the space utilization rate can be effectively increased, which is advantageous for improving resolution. In the embodiments of this disclosure, by setting the distance between the memory capacitor and the compensation signal line in different sub-pixels, the influence of jump signals in the pixel driving circuit on the compensation signal line can be effectively reduced, ensuring the accuracy of external compensation and ensuring display effect and display quality.

[0228] Figure 15 is an equivalent circuit diagram of a pixel driving circuit in yet another repeating unit of an exemplary embodiment of the present disclosure, and Figure 16 is a schematic diagram of the structure of yet another display board of an exemplary embodiment of the present disclosure. As shown in Figures 15 and 16, the pixel driving circuit and the main body structure of the display board of this embodiment are basically the same as those of the embodiments shown in Figures 3 and 4, the difference being that one repeating unit of this embodiment is provided with one first power line 51 and two compensation signal lines 53.

[0229] In exemplary embodiments, at least one repeating unit may comprise one scan signal line 30, one first power line 51, four data signal lines 52, and two compensation signal lines 53, and the shape, position, and connection relationship of the scan signal line 30 and the data signal lines 52 to the pixel driving circuit may be basically the same as in the embodiments shown in Figures 3 and 4. The pixel driving circuit for at least one subpixel may comprise a first transistor T1, a second transistor T2, a third transistor T3, and a memory capacitor 60, and the memory capacitor 60 may include at least a first plate and a second plate as capacitor plates, and the associated connection structure is basically the same as in the embodiments described above and is omitted here.

[0230] In an exemplary embodiment, one first power line 51 may be located in the middle of the first direction X of the repeating unit, and one first power line 51 may form two pixel rows, a first pixel row and a second pixel row. Two compensation signal lines 53 may include a first compensation signal line 53-1 and a second compensation signal line 53-2 that are installed sequentially along the first direction X.

[0231] In an exemplary embodiment, the first compensation signal line 53-1 may be installed on the side of the first power line 51 closer to the first data signal line group, and the storage capacitor for the first pixel row may be installed between the second data signal line 52-2 and the first compensation signal line 53-1. The second compensation signal line 53-2 may be installed on the side of the first power line 51 closer to the second data signal line group, and the storage capacitor for the second pixel row may be installed between the second compensation signal line 53-2 and the third data signal line 52-3.

[0232] In an exemplary embodiment, at least one repeating unit further comprises two compensation connection electrodes 19, the two compensation connection electrodes 19 may each be located in the middle region of the repeating unit in the second direction Y. The shape of each compensation connection electrode 19 may be a strip extending along the first direction X, and each compensation connection electrode 19 may be installed across a first pixel row and a second pixel row. The first end of each compensation connection electrode 19 is connected to a first compensation signal line 53-1 and the first electrode of a third transistor T3 in the first pixel row, and the second end of each compensation connection electrode 19 is connected to a second compensation signal line 53-2 and the first electrode of a third transistor T3 in the second pixel row. In this way, the two compensation signal lines 53 and the two compensation connection electrodes 19 in the repeating unit form an annular structure for transmitting compensation signals.

[0233] In an exemplary embodiment, the orthographic projection of the compensation connection electrode 19 on the display substrate plane does not overlap with the orthographic projection of the data signal line 52 on the display substrate plane.

[0234] In an exemplary embodiment, the orthographic projection of the compensating connection electrode 19 on the display substrate plane overlaps at least partially with the orthographic projection of the first power line 51 on the display substrate plane.

[0235] In an exemplary embodiment, taking four subpixels of one repeating unit as an example, the manufacturing process of the display substrate in this embodiment may include the following operations.

[0236] (21) A first conductive layer pattern is formed. In the exemplary embodiment, the process of forming the first conductive layer and the structure of the first conductive layer are basically the same as in the embodiment described above.

[0237] (22) Forming the second conductive layer pattern. In exemplary embodiments, as shown in Figures 17A and 17B, the process of forming the second conductive layer and the structure of the second conductive layer are basically the same as in the embodiments described above, the difference being that each repeating unit in this embodiment includes one first power line 51 and two compensation signal lines 53, and Figure 17B is a schematic diagram of the second conductive layer in Figure 17A.

[0238] In an exemplary embodiment, the shape and position of the third connecting electrode 13, the fourth connecting electrode 14, and the four data signal lines 52 in the second conductive layer of this embodiment are basically the same as in the previously described embodiment.

[0239] In exemplary embodiments, the shapes of the first power line 51, data signal line 52, and compensation signal line 53 may be straight or bent with the main body extending along the second direction Y, the first power line 51 may be located in the middle of the first direction X of the repeating unit, the two compensation signal lines 53 may be located on both sides of the first direction X of the first power line 51, two of the four data signal lines 52 may be located on the opposite side of the first direction X of the repeating unit, and the other two of the four data signal lines 52 may be located on the first direction X side of the repeating unit.

[0240] In an exemplary embodiment, the two compensation signal lines 53 may include a first compensation signal line 53-1 and a second compensation signal line 53-2 that are installed sequentially along a first direction X.

[0241] In an exemplary embodiment, the first data signal line 52-1 and the first power line 51 may be formed to limit the first pixel row, the second data signal line 52-2 and the first compensation signal line 53-1 are installed in the first pixel row, the second data signal line 52-2 may be installed on the side of the first data signal line 52-1 closer to the first power line 51, the first compensation signal line 53-1 may be installed on the side of the first power line 51 closer to the first data signal line 52-1, and the first electrode plate 61, third connecting electrode 13 and fourth connecting electrode 14 of the first pixel row may be installed between the second data signal line 52-2 and the first compensation signal line 53-1.

[0242] In an exemplary embodiment, the fourth data signal line 52-4 and the first power line 51 may be formed to limit the second pixel row, the second compensation signal line 53-2 and the third data signal line 52-3 may be installed in the second pixel row, the second compensation signal line 53-2 may be installed on the side of the first power line 51 closer to the fourth data signal line 52-4, the third data signal line 52-3 may be installed on the side of the fourth data signal line 52-4 closer to the first power line 51, and the first electrode plate 61, third connecting electrode 13 and fourth connecting electrode 14 of the second pixel row may be installed between the second compensation signal line 53-2 and the third data signal line 52-3.

[0243] In an exemplary embodiment, a power connection block 54 may be connected to the first power line 51, the shape of the power connection block 54 may be block-shaped, and the power connection block 54 is configured to be connected to the first region of the second active layer via a power connection electrode formed subsequently.

[0244] In exemplary embodiments, the orthographic projection of the first power line 51 at its base at least partially overlaps with the orthographic projection of the vertical reference line at its base, the positions of the two compensation signal lines 53 may be substantially mirror-symmetric with respect to the vertical reference line, and the positions of the two data signal lines 52 located on the opposite side of the first direction X of the first power line 51 and the positions of the two data signal lines 52 located on the first direction X side of the first power line 51 may be substantially mirror-symmetric with respect to the vertical reference line.

[0245] (23) Form a semiconductor layer pattern. In an exemplary embodiment, as shown in Figures 18A and 18B, the semiconductor layer formation process and the structure of the semiconductor layer are basically the same as in the above-described embodiment, the difference being that the third active layer 23 of each subpixel in this embodiment is set up separately, and Figure 18B is a schematic diagram of the semiconductor layer structure in Figure 18.

[0246] In an exemplary embodiment, the shape and position of the first active layer 21, the second active layer 22, and the second electrode plate 62 of the memory capacitor in the semiconductor layer of this embodiment are basically the same as in the previously described embodiment.

[0247] In an exemplary embodiment, the shape of the third active layer 23 of each subpixel may be a strip extending along a first direction X, wherein the orthographic projection of the base at one end of the third active layer 23 at least partially overlaps with the orthographic projection of the base of the fourth connecting electrode 14 of the subpixel, and the orthographic projection of the base at the other end of the third active layer 23 at least partially overlaps with the orthographic projection of the base of the compensation signal line 53.

[0248] In an exemplary embodiment, the third active layer 23 is not connected in the first subpixel P1 and the second subpixel P2, the third active layer 23 is not connected in the third subpixel P3 and the fourth subpixel P4, and the orthographic projection of the base of the third active layer 23 does not overlap with the orthographic projection of the base of the first power line 51.

[0249] (24) Forming a second insulating layer pattern. In an exemplary embodiment, as shown in Figure 19, the process of forming the second insulating layer pattern and the structure of the multiple vias are basically the same as in the above-described embodiment, the difference being that this embodiment further includes a seventh via V7.

[0250] In the exemplary embodiment, the positions and roles of the first via V1, third via V3, fourth via V4, fifth via V5, and sixth via V6 are essentially the same as in the previously described embodiment.

[0251] In an exemplary embodiment, the orthographic projection of the base of the second via V2 lies within the range of the orthographic projection of the base of the first region of the second active layer 22, the second insulating layer within the second via V2 is etched away to expose the surface of the first region of the second active layer 22, and the second via V2 is configured such that a subsequently formed second connecting electrode is connected to the first region of the second active layer 22 via the via.

[0252] In an exemplary embodiment, each subpixel further comprises a seventh via V7. The orthographic projection of the base of the seventh via V7 lies within the orthographic projection of the base of the power connection block 54 of the first power line 51, and the first and second insulating layers within the seventh via V7 are etched away to expose the surface of the power connection block 54, and the seventh via V7 is configured such that a subsequently formed power connection electrode is connected to the power connection block 54 via the via.

[0253] In this exemplary embodiment, the difference from the previously described embodiment is that a fourth via V4 is provided for each subpixel; that is, the first subpixel P1 and the second subpixel P2 do not share the fourth via V4, and the third subpixel P3 and the fourth subpixel P4 do not share the fourth via V4.

[0254] (25) Form the third conductive layer pattern. In an exemplary embodiment, as shown in Figures 20A and 20B, the formation process of the third conductive layer and the structure of the third conductive layer are basically the same as in the above-described embodiment. The difference is that the connection structure between the power connection electrode 18 and the compensation connection electrode 19 in this embodiment is different, and Figure 20B is a schematic diagram of the third conductive layer in Figure 20A.

[0255] In this exemplary embodiment, the shapes and positions of the fifth connecting electrode 15, sixth connecting electrode 16, data connecting electrode 17, scan signal line 30, first gate electrode 31, second gate electrode 32, and third gate electrode 33 in the third conductive layer of this embodiment are basically the same as in the previously described embodiment.

[0256] In an exemplary embodiment, the shape of the power connection electrode 18 may be a strip extending along a first direction X, and the power connection electrode 18 may be located on the side of the second electrode plate 62 away from the scan signal line 30, and may be located across the first and second pixel rows, with the first end of the power connection electrode 18 connected to a first region of the second active layer 22 of the first pixel row via a second via V2 of the first pixel row, the second end of the power connection electrode 18 connected to a first region of the second active layer 22 of the second pixel row via a second via V2 of the second pixel row, and the middle region between the first and second ends of the power connection electrode 18 connected to a power connection block 54 via a seventh via V7. The power connection block 54 is connected to a first power line 51, so that the first power line 51 writes a first power signal to the first electrode of the second transistor T2.

[0257] In an exemplary embodiment, the first power line 51 can simultaneously supply the first power signal to four pixel drive circuits of the first and second pixel rows, so that the first power line 51 in one repeating unit has a 1:4 structure. By designing the first power line in a 1:4 structure, the display board of the present disclosure saves the number of signal lines, reduces the occupied space, has a simple structure, a rational layout, makes full use of layout space, increases space utilization, and is advantageous for increasing resolution.

[0258] In an exemplary embodiment, the power connection electrode 18 may also be a lateral power connection line, the orthographic projection of the base of the power connection electrode 18 does not overlap with the orthographic projection of the base of the data signal line 52, and the orthographic projection of the base of the power connection electrode 18 at least partially overlaps with the orthographic projection of the base of the compensation signal line 53.

[0259] In an exemplary embodiment, the shape of the compensation connection electrode 19 may be a strip extending along a first direction X, or it may be installed across a first pixel row and a second pixel row. The first end of the compensation connection electrode 19 is simultaneously connected to the first region of the third active layer 23 of the first pixel row and the compensation signal line 53 via a fourth via V4 of the first pixel row, and the second end of the compensation connection electrode 19 is simultaneously connected to the first region of the third active layer 23 of the second pixel row and the compensation signal line 53 via a fourth via V4 of the second pixel row, thereby enabling the compensation signal line 53 to write a compensation signal to the first electrode of the third transistor T3.

[0260] In an exemplary embodiment, the two compensation signal lines 53 may include a first compensation signal line 53-1 and a second compensation signal line 53-2, which are sequentially installed along a first direction X. The first compensation signal line 53-1 may be located in a first pixel row on the opposite side of the first direction X of the first power line 51 and may be connected via compensation connection electrodes 19 to first regions of the third active layer 23 in the first subpixel P1 and third subpixel P3, respectively. The second compensation signal line 53-2 may be located in a second pixel row on the first direction X side of the first power line 51 and may be connected via compensation connection electrodes 19 to first regions of the third active layer 23 in the second subpixel P2 and fourth subpixel P4, respectively.

[0261] In an exemplary embodiment, the third active layers of the first subpixel P1 and the second subpixel P2 are not connected, and the third active layers of the third subpixel P3 and the fourth subpixel P4 are not connected. However, the present disclosure provides a compensation connection electrode 19 that spans the first and second pixel rows, and the compensation connection electrode 19 may be a lateral compensation connection line. Thus, the first subpixel P1 and the second subpixel P2 share one compensation connection electrode 19, the third subpixel P3 and the fourth subpixel P4 share one compensation connection electrode 19, and two compensation signal lines 53 can simultaneously provide compensation signals to the pixel driving circuits in the four subpixels. Therefore, the four subpixels of one repeating unit can share two compensation signal lines 53, and the compensation signal lines 53 of one repeating unit have a 1:2 structure. The display board disclosed herein is designed with a 1:2 compensation signal line structure, thereby saving the number of signal lines, reducing the occupied space, resulting in a simple structure, a rational layout, efficient use of layout space, increased space utilization, and advantages in increasing resolution.

[0262] In exemplary embodiments, the present disclosure is advantageous in improving product yield by providing a compensation connection electrode 19 that spans a first pixel row and a second pixel row, thereby forming an annular structure in the region where the compensation signal line 53 is connected to the third transistor T3 in a repeating unit. For example, if a power connection electrode 18, which serves as a lateral power connection line, has a short-circuit fault at a position that spans the compensation signal line 53, the short-circuit fault can be repaired by cutting one of the compensation signal lines 53, thereby improving product yield. Similarly, if a compensation connection electrode 19 has a short-circuit fault at a position that spans the first power line 51, the short-circuit fault can be repaired by cutting one of the compensation connection electrodes 19, thereby improving product yield.

[0263] In an exemplary embodiment, the orthographic projection of the base of the compensating connection electrode 19 does not overlap with the orthographic projection of the base of the data signal line 52, and the orthographic projection of the base of the compensating connection electrode 19 overlaps at least partially with the orthographic projection of the base of the first power line 51.

[0264] In an exemplary embodiment, the positions of the two compensation signal lines 53 are substantially mirror-symmetric with respect to the vertical reference line, and the third transistor T3 of the first pixel row and the third transistor T3 of the second pixel row are substantially mirror-symmetric with respect to the vertical reference line. Thus, such a symmetric structure in the present disclosure ensures that the RC delay of the compensation signal written to the third transistor T3 is essentially the same, thereby ensuring uniformity of the display.

[0265] (26) The process of subsequently forming the third insulating layer, the flat layer, the fourth conductive layer, the pixel definition layer, the organic light-emitting layer, the cathode and the package structure layer is basically the same as in the above embodiment and is therefore omitted here.

[0266] In the display substrate provided in the embodiments of this disclosure, the first power line and compensation signal line are installed in the middle of the repeating unit, and the data signal line is installed on both sides of the repeating unit, effectively balancing the distance distribution of the opaque metal signal line between subpixels. This similarly provides the technical effects of the previously described embodiments, namely effectively increasing the aperture ratio, reducing the risk of light leakage from pixels, effectively improving process accuracy, and effectively improving the product yield. Furthermore, in the embodiments of this disclosure, by installing a separate third active layer for each subpixel, the orthographic projection on the base of the third active layer does not overlap with the orthographic projection on the base of the first power line, thereby effectively reducing the extension length of the semiconductor trace, effectively avoiding the impact of differences in the conductorization process on external compensation, ensuring the accuracy of external compensation, and ensuring display effect and display quality. Moreover, in the embodiments of this disclosure, by installing a compensation connection electrode that spans the first and second pixel rows, a ring structure is formed in the region where the compensation signal line is connected to the third transistor, which facilitates short-circuit repair and is advantageous in improving the product yield.

[0267] Figure 21 is an equivalent circuit diagram of a pixel driving circuit in yet another repeating unit of an embodiment of the present disclosure, and Figure 22 is a schematic diagram of the structure of yet another display board of an embodiment of the present disclosure. As shown in Figures 21 and 22, the pixel driving circuit and the main body structure of the display board of this embodiment are basically the same as those of the embodiments shown in Figures 15 and 16, the difference being that one compensation signal line 53 is installed in one repeating unit of this embodiment.

[0268] In exemplary embodiments, at least one repeating unit may comprise one scan signal line 30, one first power line 51, four data signal lines 52, and one compensation signal line 53, and the shape, position, and connection relationship with the pixel driving circuit of the scan signal line 30, data signal line 52, and first power line 51 may be basically the same as in the embodiments shown in Figures 15 and 16. The pixel driving circuit of at least one subpixel may comprise a first transistor T1, a second transistor T2, a third transistor T3, and a memory capacitor 60, and the memory capacitor 60 may include at least a first plate 61 and a second plate 62 as capacitor plates, and the associated connection structure is basically the same as in the embodiments described above and is omitted here.

[0269] In an exemplary embodiment, the compensation signal line 53 may be located on the first direction X side of the first power line 51, that is, the compensation signal line 53 may be located on the side of the second pixel row closer to the first power line 51. In another exemplary embodiment, the compensation signal line 53 may be located on the opposite side of the first direction X of the first power line 51, that is, the compensation signal line 53 may be located on the side of the first pixel row closer to the first power line 51.

[0270] In an exemplary embodiment, the shape and position of the compensation connection electrode 19 are basically the same as those of the embodiment shown in FIG. 15 and FIG. 16, with the difference that: a first end of the compensation connection electrode 19 is simultaneously connected to a first region of a third active layer 23 of one pixel column and a compensation signal line through a fourth via V4 of said pixel column, and a second end of the compensation connection electrode 19 is connected to a first region of a third active layer 23 of another pixel column through a fourth via V4 of said pixel column. Thereby, it is implemented that one compensation signal line 53 writes compensation signals to first electrodes of four third transistors T3 in two pixel columns, forming a 1-to-4 structure of compensation signal lines, which saves the number of signal lines, reduces occupied space, has a concise structure and reasonable layout, makes full use of layout space, improves space utilization, and is advantageous for increasing resolution.

[0271] In an exemplary embodiment, the compensation connection electrode 19 may be a horizontal compensation connection line, an orthographic projection of the compensation connection electrode 19 on the base does not overlap with an orthographic projection of the data signal line 52 on the base, and an orthographic projection of the compensation connection electrode 19 on the base at least partially overlaps with an orthographic projection of the first power line 51 on the base.

[0272] In an exemplary embodiment, an example is described where the compensation signal line 53 is disposed in the second pixel column. In the first pixel column, a third distance L3 is provided between the right edge of the first electrode plate 61 on a side close to the first power supply line 51 and the left edge of the first power supply line 51 on a side close to the first electrode plate 61. In the second pixel column, a fourth distance L4 is provided between the left edge of the first electrode plate 61 on a side close to the compensation signal line 53 and the right edge of the compensation signal line 53 on a side close to the first electrode plate 61. In another exemplary embodiment, an example is described where the compensation signal line 53 is disposed in the first pixel column. In the first pixel column, a fourth distance L4 is provided between the right edge of the second electrode plate 62 on a side close to the compensation signal line 53 and the left edge of the compensation signal line 53 on a side close to the second electrode plate 62. In the second pixel column, a third distance L3 is provided between the left edge of the second electrode plate 62 on a side close to the first power supply line 51 and the right edge of the first power supply line 51 on a side close to the second electrode plate 62. Both the third distance L3 and the fourth distance L4 may be greater than the minimum distance between the edge of the first power supply line 51 on a side close to the compensation signal line 53 and the edge of the compensation signal line 53 on a side close to the first power supply line 51, and the third distance L3 and the fourth distance L4 may each be a size in the first direction X.

[0273] In an exemplary embodiment, the fourth distance L4 may be 3 μm or more.

[0274] In the present disclosure, by setting the distance between the storage capacitor and the first power supply line in a sub-pixel without a compensation line, space utilization can be effectively improved on the premise that the accuracy of external compensation can be ensured, which is advantageous for improving resolution.

[0275] The display substrate provided in the embodiments of this disclosure has the same technical effects as the embodiments described above, namely, it can effectively increase the aperture ratio, reduce the risk of light leakage from pixels, effectively improve process accuracy, and effectively improve the product yield. Furthermore, in the embodiments of this disclosure, the space utilization rate can be effectively increased by reducing the number of compensation signal lines by one, which is advantageous for improving resolution. In the embodiments of this disclosure, the space utilization rate can be further increased and the resolution further improved by setting the distance between the memory capacitor and the first power line in different sub-pixels, provided that the accuracy of external compensation can be ensured.

[0276] Figure 23 is a schematic diagram of yet another display board structure of an exemplary embodiment of the present disclosure. As shown in Figure 23, the pixel driving circuit and the main body structure of the display board of this embodiment are basically the same as those of the embodiment shown in Figure 22, the difference being that the first active layer in the first subpixel and the fourth subpixel of this embodiment does not overlap with the data signal line.

[0277] In an exemplary embodiment, at least one repeating unit may include one scan signal line 30, one first power line 51, four data signal lines 52, and one compensation signal line 53, the compensation signal line 53 may be located on the first direction X side of the first power line 51.

[0278] In exemplary embodiments, the shape and connection structure of the data connection electrodes 17 in the second subpixel P2 and the third subpixel P3 are basically the same as in the embodiments described above. The shape of the data connection electrodes 17 in the first subpixel P1 and the fourth subpixel P4 may be L-shaped, the first end of the data connection electrode 17 is simultaneously connected via via to the first region of the first active layer and to the data bridge electrode, the second end of the data connection electrode 17 is connected via via to the data signal line, and the orthographic projection of the base of the data connection electrode 17 at least partially overlaps with the orthographic projection of the base of the data signal line 52.

[0279] In an exemplary embodiment, the orthographic projection of the base of the first active layer in the first subpixel P1 and the fourth subpixel P4 does not overlap with the orthographic projection of the base of the data signal line 52.

[0280] In an exemplary embodiment, taking four subpixels of one repeating unit as an example, the manufacturing process of the display substrate in this embodiment may include the following operations.

[0281] (31) Form the first conductive layer pattern. In an exemplary embodiment, as shown in Figure 24, the process of forming the first conductive layer and the structure of the first conductive layer are basically the same as in the embodiments described above.

[0282] (32) Form a second conductive layer pattern. In an exemplary embodiment, as shown in Figures 25A and 25B, the formation process of the second conductive layer and the structure of the second conductive layer are basically the same as in the above-described embodiment, the difference being that the second conductive layer in this embodiment further includes a data bridge electrode 41 and a compensation bridge electrode 42, and Figure 25B is a schematic diagram of the second conductive layer in Figure 25A.

[0283] In an exemplary embodiment, the shape and position of the third connecting electrode 13, the fourth connecting electrode 14, and the four data signal lines 52 in the second conductive layer of this embodiment are basically the same as in the previously described embodiment.

[0284] In exemplary embodiments, the shapes of the first power line 51, data signal line 52, and compensation signal line 53 may be straight or bent, with the main body extending along the second direction Y, the first power line 51 may be located in the middle of the repeating unit in the first direction X, and the compensation signal line 53 may be located on the first direction X side of the first power line 51.

[0285] In an exemplary embodiment, the shape of the data bridge electrode 41 may be block-shaped (rectangular), and the data bridge electrode 41 may be installed between the fourth connection electrode 14 and the data signal line 52 in the first subpixel P1 and the fourth subpixel P4, and the data bridge electrode 41 is configured to be connected to the data signal line via a subsequently formed data connection electrode.

[0286] In an exemplary embodiment, the shape of the compensation bridge electrode 42 may be block-shaped (rectangular), and the compensation bridge electrode 42 may be installed between the fourth connection electrode 14 and the first power line 51 in the first pixel row, and the compensation bridge electrode 42 is configured to be connected to the compensation signal line via a subsequently formed compensation connection electrode.

[0287] In an exemplary embodiment, the first electrode plate 61, third connection electrode 13, fourth connection electrode 14, data bridge electrode 41, and compensation bridge electrode 42 of the first pixel row may be installed between the second data signal line 52-2 and the first power line 51, and the first electrode plate 61, third connection electrode 13, fourth connection electrode 14, and data bridge electrode 41 of the second pixel row may be installed between the compensation signal line 53 and the third data signal line 52-3.

[0288] (33) Form a semiconductor layer pattern. In an exemplary embodiment, as shown in Figures 26A and 26B, the semiconductor layer formation process and the structure of the semiconductor layer are basically the same as in the above-described embodiment, the only difference being that the first active layer 21 of the first subpixel P1 and the fourth subpixel P4 does not overlap with the data signal line 51, and Figure 26B is a schematic diagram of the semiconductor layer in Figure 26A.

[0289] In an exemplary embodiment, the shape and position of the second active layer 22 and the second electrode plate 62 of the memory capacitor in the semiconductor layer of this embodiment are basically the same as in the previously described embodiment.

[0290] In an exemplary embodiment, the shape of the first active layer 21 of each sub-pixel may be a strip shape extending along the first direction X. In the first sub-pixel P1 and the fourth sub-pixel P4, the orthographic projection of the first region of the first active layer 21 on the base at least partially overlaps the orthographic projection of the data bridge electrode 41 on the base, the second region of the first active layer 21 is connected to the second electrode plate 62, and the orthographic projection of the first active layer 21 on the base does not overlap the orthographic projection of the data signal line 52 on the base. In the second sub-pixel P2 and the third sub-pixel P3, the orthographic projection of the first region of the first active layer 21 on the base at least partially overlaps the orthographic projection of the corresponding data signal line 52 on the base, and the second region of the first active layer 21 is connected to the second electrode plate 62.

[0291] In an exemplary embodiment, the shape of the third active layer 23 of each sub-pixel may be a strip shape extending along the first direction X. In the first sub-pixel P1 and the third sub-pixel P3, the orthographic projection of one end of the third active layer 23 on the base at least partially overlaps the orthographic projection of the fourth connection electrode 14 of the current sub-pixel on the base, and the orthographic projection of the other end of the third active layer 23 on the base at least partially overlaps the orthographic projection of the compensation bridge electrode 42 on the base. In the second sub-pixel P2 and the fourth sub-pixel P4, the orthographic projection of one end of the third active layer 23 on the base at least partially overlaps the orthographic projection of the fourth connection electrode 14 of the current sub-pixel on the base, and the orthographic projection of the other end of the third active layer 23 on the base at least partially overlaps the orthographic projection of the compensation signal line 53 on the base.

[0292] In an exemplary embodiment, the orthographic projection of the third active layer 23 of each sub-pixel on the base does not overlap the orthographic projection of the first power supply line 51 on the base.

[0293] (34) Forming a second insulating layer pattern. In an exemplary embodiment, as shown in FIG. 27, the formation process of the second insulating layer pattern and the structure of the plurality of vias are basically the same as those in the foregoing embodiments, and the difference is that in this embodiment, an eighth via V8 is further provided.

[0294] In this exemplary embodiment, the positions and roles of the third via V3, the fifth via V5, and the sixth via V6 are essentially the same as in the previously described embodiment.

[0295] In an exemplary embodiment, in the first subpixel P1 and the fourth subpixel P4, the orthographic projection of the first via V1 on the base at least partially overlaps with the orthographic projection of the first region of the first active layer 21 on the base, and the orthographic projection of the first via V1 on the base at least partially overlaps with the orthographic projection of the data bridge electrode 41 on the base, wherein the first via V1 is a via of a relay structure and includes two half-holes, the second insulating layer in the shallow half-hole is etched away to expose the surface of the first region of the first active layer 21, and the first and second insulating layers in the deep half-hole are etched away to expose the surface of the data bridge electrode 41, thereby the first via V1 of the relay structure consisting of two half-holes simultaneously exposes the first region of the first active layer 21 and the data bridge electrode 41. In the second subpixel P2 and the third subpixel P3, the orthographic projection of the base of the first via V1 lies within the range of the first region of the first active layer 21 and the orthographic projection of the base of the data signal line 52. The first via V1 is a via in the relay structure, and the connection structure is basically the same as in the embodiment described above.

[0296] In an exemplary embodiment, the orthographic projection of the base of the second via V2 of each subpixel lies within the range of the orthographic projection of the base of the first region of the second active layer 22, the second insulating layer within the second via V2 is etched away, and the surface of the first region of the second active layer 22 is exposed.

[0297] In an exemplary embodiment, in the first subpixel P1 and the third subpixel P3, the orthographic projection of the base of the fourth via V4 at least partially overlaps with the orthographic projection of the base of the first region of the third active layer 23, and the orthographic projection of the base of the fourth via V4 at least partially overlaps with the orthographic projection of the base of the compensation bridge electrode 42. The fourth via V4 is a via of a relay structure and includes two half-holes, the second insulating layer in the shallow half-hole is etched away to expose the surface of the first region of the third active layer 23, and the first and second insulating layers in the deep half-hole are etched away to expose the surface of the compensation bridge electrode 42, thereby the fourth via V4 of the relay structure consisting of two half-holes simultaneously exposes the first region of the third active layer 23 and the compensation bridge electrode 42. In the second subpixel P2 and the fourth subpixel P4, the orthographic projection at the base of the fourth via V4 is located within the range of the first region of the third active layer 23 and the orthographic projection at the base of the compensation signal line 53. The fourth via V4 is a via in the relay structure, and the connection structure is basically the same as in the previously described embodiment.

[0298] In an exemplary embodiment, each subpixel further comprises a seventh via V7. The orthographic projection of the base of the seventh via V7 lies within the range of the orthographic projection of the base of the first power line 51, and the first and second insulating layers within the seventh via V7 are etched away to expose the surface of the first power line 51.

[0299] In an exemplary embodiment, the first subpixel P1 and the fourth subpixel P4 further comprise an eighth via V8. The orthographic projection of the base of the eighth via V8 lies within the range of the orthographic projection of the base of the data signal line 52, and the first and second insulating layers within the eighth via V8 are etched away to expose the surface of the data signal line 52.

[0300] (35) Form the third conductive layer pattern. In an exemplary embodiment, as shown in Figures 28A and 28B, the formation process of the third conductive layer and the structure of the third conductive layer are basically the same as in the above-described embodiment. The difference is that the connection structure between the power supply connection electrode 18 and the compensation connection electrode 19 in this embodiment is different, and Figure 28B is a schematic diagram of the third conductive layer in Figure 28A.

[0301] In this exemplary embodiment, the shapes and positions of the fifth connecting electrode 15, the sixth connecting electrode 16, the scanning signal line 30, the first gate electrode 31, the second gate electrode 32, and the third gate electrode 33 in the third conductive layer of this embodiment are basically the same as in the previously described embodiment.

[0302] In an exemplary embodiment, the shape of the data connection electrode 17 in the first subpixel P1 and the fourth subpixel P4 may be L-shaped, and the first end of the data connection electrode 17 is simultaneously connected to the first region of the first active layer 21 and the data bridge electrode 41 via the first via V1, and the second end of the data connection electrode 17 is connected to the data signal line 52 via the eighth via V8. The shape of the data connection electrode 17 in the second subpixel P2 and the third subpixel P3 may be block-shaped, and the data connection electrode 17 is simultaneously connected to the first region of the first active layer 21 and the data signal line 52 via the first via V1, and the connection structure is basically the same as in the embodiment described above.

[0303] In an exemplary embodiment, the data connection electrode 17 in the first subpixel P1 is connected to the first data signal line 52-1, and the orthographic projection of the base of the data connection electrode 17 at least partially overlaps with the orthographic projection of the base of the second data signal line 52-2. The data connection electrode 17 in the fourth subpixel P4 is connected to the fourth data signal line 52-4, and the orthographic projection of the base of the data connection electrode 17 at least partially overlaps with the orthographic projection of the base of the third data signal line 52-3.

[0304] In an exemplary embodiment, the shape of the power supply connection electrode 18 may be a strip extending along a first direction X, and the power supply connection electrode 18 may be installed on the side of the second electrode plate 62 away from the scan signal line 30, and may be installed spanning the first pixel row and the second pixel row, with the first end of the power supply connection electrode 18 connected to the first region of the second active layer 22 of the first pixel row via a second via V2 of the first pixel row, the second end of the power supply connection electrode 18 connected to the first region of the second active layer 22 of the second pixel row via a second via V2 of the second pixel row, and the middle region between the first and second ends of the power supply connection electrode 18 connected to the first power line 51 via a seventh via V7, thereby enabling the first power line 51 to write the first power supply signal to the first electrode of the second transistor T2.

[0305] In an exemplary embodiment, the power connection electrode 18 may also be a lateral power connection line, the orthographic projection of the base of the power connection electrode 18 does not overlap with the orthographic projection of the base of the data signal line 52, and the orthographic projection of the base of the power connection electrode 18 at least partially overlaps with the orthographic projection of the base of the compensation signal line 53.

[0306] In an exemplary embodiment, the shape of the compensation connection electrode 19 may be a strip extending along a first direction X, and the compensation connection electrode 19 may be installed across a first pixel row and a second pixel row. The first end of the compensation connection electrode 19 is simultaneously connected to a first region of the third active layer 23 of the first pixel row and the compensation bridge electrode 42 via a fourth via V4 of the first pixel row, and the second end of the compensation connection electrode 19 is simultaneously connected to a first region of the third active layer 23 of the second pixel row and the compensation signal line 53 via a fourth via V4 of the second pixel row, thereby enabling the compensation signal line 53 to write a compensation signal to the first electrode of the third transistor T3.

[0307] In an exemplary embodiment, the orthographic projection of the base of the compensating connection electrode 19 does not overlap with the orthographic projection of the base of the data signal line 52, and the orthographic projection of the base of the compensating connection electrode 19 overlaps at least partially with the orthographic projection of the base of the first power line 51.

[0308] (36) The process of subsequently forming the third insulating layer, the flat layer, the fourth conductive layer, the pixel definition layer, the organic light-emitting layer, the cathode and the package structure layer is basically the same as in the above-described embodiment and is therefore omitted here.

[0309] In the display substrate provided in the embodiments of this disclosure, the first power line and compensation signal line are installed in the middle of the repeating unit, and the data signal line is installed on both sides of the repeating unit, effectively balancing the distance distribution of the opaque metal signal line between subpixels, thereby having the same technical effects as the above embodiments, namely effectively increasing the aperture ratio, reducing the risk of light leakage from pixels, effectively improving process accuracy, and effectively improving the product yield. In the embodiments of this disclosure, by installing one first power line and one compensation signal line, the space utilization rate can be effectively increased, which is advantageous for improving resolution. In the embodiments of this disclosure, by installing a separate third active layer for each subpixel, the orthographic projection on the base of the third active layer does not overlap with the orthographic projection on the base of the first power line, thereby effectively reducing the extension length of the semiconductor trace, effectively avoiding the impact on external compensation due to differences in the conductorization process, ensuring the accuracy of external compensation, and ensuring display effect and display quality. Furthermore, in the embodiments of this disclosure, by installing data bridge electrodes on the first and fourth subpixels, the outer data signal lines can be connected to the first transistor via data connection electrodes made of metallic material. This avoids the need for cross-line overlap tracing using a conductive semiconductor layer, effectively avoids display inconsistencies due to conductive resistance differences, and improves display effect and display quality.

[0310] Although this embodiment describes the structure shown in Figure 22, the structures of the data connection electrode and data bridge electrode in this embodiment can be similarly applied to the embodiments shown in Figures 4, 14, and 16.

[0311] The structures and manufacturing processes described herein are illustrative only, and in exemplary embodiments, corresponding structures can be modified and patterning processes added or removed according to actual needs, and this disclosure is not limited thereto.

[0312] In exemplary embodiments, the display substrate of the present disclosure may be applied to display devices having pixel driving circuits, such as OLEDs, quantum dot displays (QLEDs), light-emitting diode displays (Micro LEDs or Mini LEDs), or quantum dot light-emitting diode displays (QDLEDs), and the present disclosure is not limited herein.

[0313] Exemplary embodiments of this disclosure further provide a method for manufacturing a display substrate, wherein the display substrate comprises a plurality of repeating units, and the manufacturing method is: The repeating unit comprises at least one first power line, at least one compensation signal line, at least two data signal line groups, and a plurality of subpixels, the plurality of subpixels forming at least two pixel rows and at least two pixel columns, the data signal line group including at least one data signal line, at least one subpixel including a pixel driving circuit, the pixel driving circuit including at least a memory capacitor, the first power line and the compensation signal line being installed between two adjacent pixel columns in the repeating unit, the at least two data signal line groups being installed on both sides of the pixel row direction of the repeating unit, the memory capacitor being installed between the data signal line and the first power line, or the memory capacitor being installed between the data signal line and the compensation signal line.

[0314] This disclosure further provides a display device comprising a display substrate of the above-described embodiment. The display device may be a product or component having a display function, such as a mobile phone, tablet, television, monitor, laptop, digital frame, or navigator.

[0315] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are illustrative and not restrictive. Therefore, this disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the embodiments and details without departing from the scope of this disclosure. [Explanation of Symbols]

[0316] 11 - First connecting electrode 12 - Second connecting electrode 13 - Third connecting electrode 14 - 4th connecting electrode 15 - 5th connecting electrode 16 - 6th connecting electrode 17-Data connection electrode 18-Power connection electrode 19-Compensation connection electrode 20 - 10th connecting electrode 21 - 1st active layer 22 - 2nd active layer 23 - Third active layer 30 - Scanning signal line 31 - First gate electrode 32 - Second gate electrode 33 - Third gate electrode 41 - Data bridge electrode 42 - Compensation bridge electrode 51 - First power line 52 - Data signal line 53 - Compensation signal line 60 - Memory capacitor 61 - First electrode plate 62 - Second electrode plate 70 - First electrode 100 - Repeating unit

Claims

1. A display board comprising a plurality of repeating units, at least one repeating unit comprising at least one first power line, at least one compensation signal line, at least two data signal line groups and a plurality of subpixels, the plurality of subpixels forming at least two pixel rows and at least two pixel columns, the data signal line group comprising at least two data signal lines, at least one subpixel comprising a pixel driving circuit, the pixel driving circuit comprising at least a storage capacitor, the first power line and the compensation signal line being installed between two adjacent pixel columns in the repeating unit, the at least two data signal line groups being installed on both sides of the pixel row direction of the repeating unit, the storage capacitor being installed between the data signal line and the first power line, or the storage capacitor being installed between the data signal line and the compensation signal line.

2. The repeating unit includes one compensation signal line and two first power lines, the two first power lines include a first first power line and a second first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the compensation signal line is installed between the first pixel row and the second pixel row in the repeating unit, the first data signal line group is installed on the side of the first pixel row away from the compensation signal line, and the second data The display board according to claim 1, wherein the signal line group is installed on the side of the second pixel row away from the compensation signal line, the first power supply line is installed on the side of the compensation signal line closer to the first data signal line group, the storage capacitor in the first pixel row is installed between the first data signal line group and the first power supply line, the second power supply line is installed on the side of the compensation signal line closer to the second data signal line group, and the storage capacitor in the second pixel row is installed between the second data signal line group and the second power supply line.

3. The display board according to claim 2, wherein at least one repeating unit further comprises two power connection electrodes, the shape of which the power connection electrodes are strip-shaped extending along the pixel row direction and installed across the first pixel row and the second pixel row, one end of which is connected to the first power line and the other end of which is connected to the second power line, forming an annular structure for transmitting a first power signal within the repeating unit.

4. The display board according to claim 2, wherein at least one repeating unit further comprises a power connection electrode, the shape of which the power connection electrode is a strip extending along the pixel row direction and installed across the first pixel row and the second pixel row, the orthographic projection of the power connection electrode on the display board plane does not overlap with the orthographic projection of the data signal line on the display board plane, and the orthographic projection of the power connection electrode on the display board plane at least partially overlaps with the orthographic projection of the compensation signal line on the display board plane.

5. The display board according to claim 1, wherein the repeating unit includes one compensation signal line and one first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the compensation signal line is installed between the first pixel row and the second pixel row in the repeating unit, the first data signal line group is installed on the side of the first pixel row away from the compensation signal line, the second data signal line group is installed on the side of the second pixel row away from the compensation signal line, the first power line is installed on the side of the compensation signal line closer to the second data signal line group, the storage capacitor in the first pixel row is installed between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel row is installed between the second data signal line group and the first power line.

6. The display board according to claim 5, wherein the memory capacitor includes at least two capacitor plates, and in the first pixel row, the edge of at least one capacitor plate on the side closer to the compensation signal line has a first distance from the edge of the compensation signal line on the side closer to the capacitor plate, and in the second pixel row, the edge of at least one capacitor plate on the side closer to the first power line has a second distance from the edge of the first power line on the side closer to the capacitor plate, and the first distance is greater than or equal to the second distance.

7. The display board according to claim 1, wherein the repeating unit includes one compensation signal line and one first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the compensation signal line is installed between the first pixel row and the second pixel row in the repeating unit, the first data signal line group is installed on the side of the first pixel row away from the compensation signal line, the second data signal line group is installed on the side of the second pixel row away from the compensation signal line, the first power line is installed on the side of the compensation signal line closer to the first data signal line group, the storage capacitor in the first pixel row is installed between the first data signal line group and the first power line, and the storage capacitor in the second pixel row is installed between the second data signal line group and the compensation signal line.

8. The display board according to claim 7, wherein the memory capacitor includes at least two capacitor plates, and in the first pixel row, the edge of at least one capacitor plate closest to the first power line has a second distance from the edge of the first power line closest to the capacitor plate, and in the second pixel row, the edge of at least one capacitor plate closest to the compensation signal line has a first distance from the edge of the compensation signal line closest to the capacitor plate, and both the first distance and the second distance are greater than the distance between the edge of the compensation signal line closest to the first power line and the edge of the first power line closest to the compensation signal line.

9. The repeating unit includes one first power line and two compensation signal lines, the two compensation signal lines include a first compensation signal line and a second compensation signal line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the first power line is installed between the first pixel row and the second pixel row in the repeating unit, the first data signal line group is installed on the side of the first pixel row away from the first power line, and the second data The display board according to claim 1, wherein the data signal line group is installed on the side of the second pixel row away from the first power line, the first compensation signal line is installed on the side of the first power line closer to the first data signal line group, the memory capacitor in the first pixel row is installed between the first data signal line group and the first compensation signal line, the second compensation signal line is installed on the side of the first power line closer to the second data signal line group, and the memory capacitor in the second pixel row is installed between the second data signal line group and the second compensation signal line.

10. The display substrate according to claim 9, wherein at least one repeating unit further comprises two compensating connection electrodes, the shape of which the compensating connection electrodes are strip-shaped extending along the pixel row direction and installed across the first and second pixel rows, one end of which is connected to the first compensating signal line and the other end of which is connected to the second compensating signal line, forming an annular structure for transmitting a compensation signal within the repeating unit.

11. The display board according to claim 9, wherein at least one repeating unit further comprises two compensating connection electrodes, the shape of which the compensating connection electrodes are strip-shaped extending along the pixel row direction and installed across the first pixel row and the second pixel row, the orthogonal projection of the compensating connection electrodes on the display board plane does not overlap with the orthogonal projection of the data signal lines on the display board plane, and the orthogonal projection of the compensating connection electrodes on the display board plane at least partially overlaps with the orthogonal projection of the first power line on the display board plane.

12. The repeating unit includes one compensation signal line and one first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, the at least two pixel rows include a first pixel row and a second pixel row, the first power line is installed between the first pixel row and the second pixel row in the repeating unit, the first data signal line group is installed on the side of the first pixel row away from the first power line, the second data signal line group is installed on the side of the second pixel row away from the first power line, and the compensation signal line is the second data of the first power line The display board according to claim 1, wherein the storage capacitor in the first pixel row is installed on the side closer to the signal line group, the storage capacitor in the second pixel row is installed between the second data signal line group and the compensation signal line, or the compensation signal line is installed on the side of the first power line closer to the first data signal line group, the storage capacitor in the first pixel row is installed between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel row is installed between the second data signal line group and the first power line.

13. The display board according to claim 12, wherein the memory capacitor includes at least two capacitor plates, and in the first pixel row, the edge of at least one capacitor plate closest to the first power line has a third distance from the edge of the first power line closest to the capacitor plate, and in the second pixel row, the edge of at least one capacitor plate closest to the compensation signal line has a fourth distance from the edge of the compensation signal line closest to the capacitor plate, or, in the first pixel row, the edge of at least one capacitor plate closest to the compensation signal line has a fourth distance from the edge of the compensation signal line closest to the capacitor plate, and in the second pixel row, the edge of at least one capacitor plate closest to the first power line has a third distance from the edge of the first power line closest to the capacitor plate, and both the third distance and the fourth distance are greater than the distance between the edge of the compensation signal line closest to the first power line and the edge of the first power line closest to the compensation signal line.

14. The display substrate according to any one of claims 1 to 13, wherein the memory capacitor includes at least two capacitor plates, and in at least one pixel row, the distance between the edge of at least one capacitor plate closest to the compensation signal line and the edge of the compensation signal line closest to the capacitor plate is 3 μm or more.

15. A method for manufacturing a display board, wherein the display board includes a plurality of repeating units, and the manufacturing method is A method for manufacturing a display board, comprising: forming at least one repeating unit with at least one first power line, at least one compensation signal line, at least two data signal line groups, and a plurality of subpixels, the plurality of subpixels forming at least two pixel rows and at least two pixel columns, the data signal line group including at least one data signal line, at least one subpixel including a pixel driving circuit, the pixel driving circuit including at least a storage capacitor, the first power line and the compensation signal line being installed between two adjacent pixel columns in the repeating unit, the at least two data signal line groups being installed on both sides of the pixel row direction of the repeating unit, the storage capacitor being installed between the data signal line and the first power line, or the storage capacitor being installed between the data signal line and the compensation signal line.

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