Pixel driving circuit, display panel, and display device

Abstract

This application provides a pixel driving circuit, a display panel (1), and a display device. The pixel driving circuit includes a sub-pixel driving module (10), a compensation signal terminal (Cm), and a compensation module (20). The compensation module (20) includes a compensation control terminal (P2), a compensation signal input terminal (P1), a first signal input terminal (P3), and a driving signal output terminal (P4). The compensation control terminal (P2) is connected to a scan line (Sn), the compensation signal input terminal (P1) is connected to the compensation signal terminal (Cm), the first signal input terminal (P3) is connected to a first power signal line (41), and the driving signal output terminal (P4) is connected to a second node (N2) of the sub-pixel driving module (10). The compensation module (20) processes the compensation signal and the first power signal and is used to output a driving voltage to the second node (N2) so that the driving current flows through the light-emitting element (14). By adjusting the compensation signal, the driving voltage at the second node (N2) is adjusted, thereby making the driving current equal to a preset target value. The pixel driving circuit can compensate for the driving voltage, thus avoiding the impact of power supply voltage drops on the display.

Description

Technical Field

[0001] <Cross-Reference to Related Applications> This application claims the priority of the Chinese Patent Application with the application number 202311151065.1 filed with the China National Intellectual Property Administration on September 7, 2023, and the entire content thereof is incorporated into this application by reference.

[0002] The present application relates to the field of display technology, and in particular to a pixel driving circuit, a display panel and a display device. Background Art

[0003] With the development and progress of display technology, Organic Light-Emitting Diodes (hereinafter referred to as "OLED"), compared with Liquid Crystal Display (hereinafter referred to as "LCD"), have such advantages as no backlight requirement, high contrast, self-luminescence, fast response, wide viewing angle, high brightness, vivid colors, thinness and light weight, applicability to flexible panels, wide operating temperature range, and relatively simple structure and manufacturing process, and have attracted attention as a next-generation display technology.

[0004] Currently, in Active-Matrix Organic Light-Emitting Diode (hereinafter referred to as "AMOLED") display technology, a storage capacitor is usually used to maintain the operation of the driving transistor until the next scanning cycle arrives. Since AMOLED stores information through the storage capacitor and performs the lighting and extinguishing operations of each pixel, each pixel continues to emit light within one frame period. Compared with Passive-Matrix Organic Light-Emitting Diode (hereinafter referred to as "PMOLED") display technology, AMOLED display technology has lower requirements for the efficiency and stability of luminescent materials, and also has relatively low power consumption. Therefore, AMOLED is more suitable than PMOLED for manufacturing display panels with larger size and higher resolution.

[0005] However, in large OLED display panels, the same power supply typically provides power voltage to multiple pixel drive circuits. Because the power wiring lengths of the pixel drive circuits, located in different positions, differ, their impedances and attenuations vary. As a result, the actual power voltage applied to each pixel element differs, causing the drive current flowing through each light-emitting element to deviate from the target drive current. This leads to brightness unevenness and affects the display effect. [Overview of the project] [Problems that the invention aims to solve]

[0006] This application provides a pixel driving circuit, a display panel, and a display device, with the aim of solving the problem in the prior art where, due to voltage drops in the power supply, the driving current flowing to each light-emitting element differs from the target driving current, resulting in uneven brightness of the display panel. [Means for solving the problem]

[0007] To solve the above technical problems, a first aspect of this application provides a pixel driving circuit. The pixel driving circuit includes a sub-pixel driving module, the sub-pixel driving module includes a data writing unit, a data storage unit, a sub-pixel driving unit and a light-emitting unit, wherein in the data writing unit, a control terminal is connected to a scan line, a first terminal is connected to a data line and a second terminal is connected to a first node, in the sub-pixel driving unit, a control terminal is connected to the first node, a first terminal is connected to a second node and a second terminal is connected to a first electrode of the light-emitting unit, the first terminal and second terminal of the data storage unit are connected to the first node and the second node, respectively and the second electrode of the light-emitting unit is connected to a second power signal line, where the pixel driving circuit further includes a compensation signal terminal and a compensation module, the compensation module includes a compensation control terminal, a compensation signal input terminal, a first signal input terminal and a driving signal output terminal, the compensation control terminal is connected to the scan line and the compensation signal input The power terminal is connected to the compensation signal terminal, the first signal input terminal is connected to the first power signal line, and the drive signal output terminal is connected to the second node, where the data writing unit and the compensation module respond to the signal control of the scan line, the data writing unit controls the on or off of the control terminal of the sub-pixel drive unit and writes the data signal of the data line to the data storage unit, the compensation signal terminal is used to supply a compensation signal to the compensation module, the compensation module is used to process the compensation signal and the first power signal supplied by the first power signal line to output a drive voltage, after the sub-pixel drive unit is turned on, the drive voltage is output to the second node by the compensation module so that the drive current passes through the light-emitting unit, and the drive voltage of the second node adjusts the compensation signal so that the drive current is equal to a preset target value.

[0008] Here, the compensation module includes a compensation write unit, a compensation drive unit, and a compensation storage unit, wherein in the compensation write unit, the control terminal is connected to the scan line as the compensation control terminal, the first terminal is connected to the compensation signal terminal as the compensation signal input terminal, and the second terminal is connected to the third node, wherein in the compensation drive unit, the control terminal is connected to the third node, the first terminal is connected to the first power signal line as the first signal input terminal, and the second terminal is connected to the second node as a drive signal output terminal, and the first and second terminals of the compensation storage unit are connected to the third node and the fourth node, respectively, and the fourth node is connected to the first power signal line and the first The data writing unit and the compensation writing unit are provided between the signal input terminals of the scan line and, in response to the signal control of the scan line, when the signal of the scan line is at an effective level, the data writing unit and the compensation writing unit turn on simultaneously and write the data signal of the data line to the data storage unit, write the compensation signal provided from the compensation signal terminal to the compensation storage unit, the data writing unit controls the sub-pixel drive unit to turn on, and the compensation writing unit controls the compensation drive unit to turn on, thereby outputting the drive signal of the first power signal line and the compensation signal to the second node.

[0009] Here, the compensation module further includes a voltage divider unit, the first terminal of which is connected to a fourth node, the second terminal of which is connected to the first power signal line, and the voltage divider unit is used to adjust the voltage of the second node.

[0010] The sub-pixel driving unit includes a first driving transistor, the compensation driving unit includes a second driving transistor, the data writing unit includes a first switching transistor, the compensation writing unit includes a second switching transistor, the data storage unit includes a first storage capacitor, the compensation storage unit includes a second storage capacitor, and the voltage divider unit includes a voltage divider resistor.

[0011] To solve the above technical problems, a second aspect of this application provides a display panel. The display panel includes a plurality of pixel drive circuits, a plurality of scan lines, a plurality of data lines, a plurality of first power signal lines, and a plurality of compensation lines, wherein the plurality of drive circuits are arranged in a matrix, and the pixel drive circuits are the pixel drive circuits described in the first embodiment; the plurality of scan lines are provided between two adjacent rows of the pixel drive circuits and extend along the row direction, and the pixel drive circuits in the same row are connected to the corresponding same scan line; the plurality of data lines are provided between two adjacent columns of the pixel drive circuits and extend along the column direction, and the pixel drive circuits in the same column are connected to the corresponding same data line; the plurality of first power signal lines are provided between two adjacent rows or two columns of the pixel drive circuits and extend along the row direction or column direction, and the pixel drive circuits are connected to one of the adjacent first power signal lines; and the plurality of compensation lines correspond one-to-one with the pixel drive circuits and are electrically connected, and are used to provide compensation signals to the pixel drive circuits, adjusting the drive voltage of each pixel drive circuit so that the drive voltage of each pixel drive circuit is equal to the target drive voltage.

[0012] Here, the display panel further includes a voltage collection module, the voltage collection module includes a collection control unit and a control signal generation unit, the control signal generation unit is connected to the control terminal of the collection control unit, the collection terminal of the collection control unit is connected to the pixel drive circuit, and the collection control unit collects the drive voltage of the pixel drive circuit during the drive phase in response to the control signal of the control signal generation unit.

[0013] The acquisition control unit includes a plurality of acquisition control subunits, the control terminals of each of the plurality of acquisition control subunits are connected to the control signal generation unit, the first terminals of each of the plurality of acquisition control units are connected to the corresponding pixel driving circuit, the acquisition control subunit includes a third switching transistor, the control signal generation unit includes a shift register, the shift register is used to generate minute-time control signals, and the acquisition control subunit is minute-time controlled to sequentially acquire the driving voltage of each row or column of the pixel driving circuit.

[0014] Here, the display panel further includes a data processing module and a power management module, the two terminals of the data processing module being connected to the output terminal of the acquisition control unit and the pixel driving circuit, respectively, the data processing module being used to collect the driving voltage collected by the acquisition control unit and calculating the value of a compensation signal based on the collected driving voltage, transmitting the calculated value of the compensation signal to the power management module, and the power management module transmitting the compensation signal to the corresponding pixel driving circuit based on the obtained value of the compensation signal.

[0015] Here, the first terminal of the acquisition control subunit is connected to the second node of the pixel drive circuit, and the signal connection line between a part of the pixel drive circuit and the acquisition control subunit has a straight section and a bent section, and the length of the bent section of the signal connection line gradually increases along the direction of the pixel drive circuit closer to the acquisition control unit, so that the total length of each signal connection line becomes the same.

[0016] To solve the above technical problems, a third aspect of this application provides a display device. The display device includes a display panel, a scanning drive module, and a data drive module, wherein the display panel is the display panel described in the second aspect, the scanning drive module is used to provide scanning signals to the display panel, and the data drive module is used to provide data signals to the display panel.

[0017] The advantageous effect of this application is that, unlike the prior art, this application provides a pixel driving circuit, a display panel, and a display device. The pixel driving circuit includes a sub-pixel driving module, a compensation signal terminal, and a compensation module. By connecting the compensation control terminal of the compensation module to the same scan line as the sub-pixel driving module, the compensation module and the sub-pixel driving module can operate simultaneously. By connecting the first signal input terminal of the compensation module to a first power signal line, the drive signal output terminal to a second node of the pixel driving circuit, and the compensation signal input terminal to a compensation signal terminal, the compensation module can adjust the drive signal from the first power supply and the compensation signal from the compensation signal terminal during the driving stage of the sub-pixel driving module, and output this to the pixel driving circuit via the drive signal output terminal. This compensates for the voltage drop due to the length of the first power signal line, adjusts the drive current flowing through the light-emitting element to be equal to a preset target value, avoids the problem of uneven brightness of the display panel due to the drive current differing from the target value due to power supply voltage drop, and improves display quality. [Brief explanation of the drawing]

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings that may be used in the description of the embodiments are briefly described below. Clearly, the drawings in the following description represent only a few embodiments of this application. Those skilled in the art can obtain other drawings from these without any creative effort. [Figure 1] This is a schematic diagram showing the structure of a pixel driving circuit according to one embodiment of the prior art. [Figure 2] This is a schematic diagram showing the structure of a pixel driving circuit according to the first embodiment of this application. [Figure 3] This is a schematic diagram showing the structure of a pixel driving circuit according to the second embodiment of this application. [Figure 4] This is a schematic diagram showing the structure of a pixel driving circuit according to the third embodiment of this application. [Figure 5] This is a schematic diagram showing the structure of a display panel according to the first embodiment of this application. [Figure 6] It is a schematic diagram showing the structure of a display panel according to a second embodiment of the present application. [Figure 7] It is a schematic diagram showing the structure of a display panel according to a third embodiment of the present application. [Figure 8] It is a schematic diagram showing the structure of a display panel according to a fourth embodiment of the present application. [Figure 9] It is a schematic diagram showing the structure of a display device according to an embodiment of the present application.

Mode for Carrying Out the Invention

[0019] Hereinafter, the technical solution in the embodiments of the present application will be described in detail with reference to the drawings of the specification.

[0020] The following is not intended to limit the present application, and specific details such as specific system configurations, interfaces, and techniques are exemplified to deepen the understanding of the present application.

[0021] Hereinafter, the technical solution in the embodiments of the present application will be described clearly and completely with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art without any inventive effort based on the embodiments of the present application shall fall within the scope of protection of the present application.

[0022] The terms “first,” “second,” and “third” in this application are used for descriptive purposes only and should not be understood as indicating the number of technical features described. Therefore, features defined as “first,” “second,” and “third” may explicitly or implicitly include at least one of these features. In the description of this application, “multiple” means at least two, e.g., two, three, etc., unless otherwise clearly and specifically defined. All directional indicators (up, down, left, right, front, back, etc.) in the embodiments of this application are used solely to describe the relative positions of each component in a particular posture (as shown in the drawings), a sports situation, etc., and the directional indicators change accordingly as the particular posture changes. Furthermore, the terms “includes” and “have” and their variations are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units may, but is not limited to, include steps or units not listed, or other steps or units, or other steps or units specific to such a process, method, product, or device.

[0023] As used herein, “Embodiments” means that certain features, structures, or characteristics described with reference to an embodiment may be included in at least one embodiment of this application. The occurrence of such phrase in different parts of the specification does not necessarily refer to the same embodiment, nor does it represent mutually exclusive, independent, or alternative embodiments. The embodiments described herein can be combined with other embodiments, as will be explicitly and implicitly understood by those skilled in the art.

[0024] Referring to Figure 1, Figure 1 is a schematic diagram showing the structure of a pixel driving circuit according to one embodiment of the prior art. The pixel driving circuit 100a in this embodiment is a general 2T1C driving circuit, and the pixel driving circuit 100a includes a switching transistor M02, a driving transistor M01, and a storage capacitor C01. The operating principle of the pixel driving circuit 100a is that when the scanning signal Vgate is at an effective level, the switching transistor M02 conducts, and at the same time a data signal is input to the data line Dm, the data signal Vdata is written to the storage capacitor C01, the driving transistor M01 conducts, and the light-emitting unit emits light. When the scanning signal Vgate is at an ineffective level, the storage capacitor C01 discharges, maintaining the driving transistor M01 in a conducting state, and the power supply VDD continues to supply current to the light-emitting unit. The current flowing through the light-emitting unit is controlled by the switching transistor M02 and satisfies the following equation (1):

[0025] JPEG2026531085000002.jpg10170

[0026] Here, VDD represents the voltage of the constant current source, W and L represent the channel width and channel length of the drive transistor, respectively, μ represents the effective carrier mobility, Cox represents the capacitance per unit area of ​​the gate insulating film of the drive transistor, Vdata represents the data signal input from the data line, and Vth represents the threshold voltage of the drive transistor.

[0027] Here, W and L are already determined when designing the drive transistor, and Cox is determined by the thickness and material of the gate insulating film; these parameters cannot be changed. Therefore, the parameters that affect the magnitude of the drive current, i.e., the main variable parameters that affect the brightness of the light-emitting unit, are μ, VDD, Vdata, and Vth. Of these, μ and Vth are important parameters for measuring the performance of the drive transistor, while VDD and Vdata are determined by the external input.

[0028] Currently, all pixel driver circuits 100a in the panel are connected to the same power supply. As a result, the wiring path for VDD to reach each level of pixel driver circuit 100a is different, meaning the length of the VDD signal wiring for each level of pixel driver circuit 100a is different. Consequently, the actual VDD value for each level of pixel driver circuit 100a is also different, resulting in different currents flowing through the OLED, ultimately leading to different luminescence brightness and affecting the display uniformity of the panel.

[0029] To solve the above technical problems, this application proposes a pixel driving circuit that overcomes the aforementioned drawbacks.

[0030] The present application will be described in detail below with reference to the drawings and embodiments.

[0031] Referring to Figure 2, Figure 2 is a schematic diagram showing the structure of a pixel driving circuit according to the first embodiment of this application. This embodiment provides a pixel driving circuit 100, which includes a sub-pixel driving module 10, a compensation module 20, and a compensation signal terminal Cm.

[0032] Here, the sub-pixel driving module 10 includes a data writing unit 11, a data storage unit 13, a sub-pixel driving unit 12, and a light-emitting unit 14. In the data writing unit 11, the control terminal is connected to the scan line Sn, the first terminal is connected to the data line Dm, and the second terminal is connected to the first node N1. In the sub-pixel driving unit 12, the control terminal is connected to the first node N1, the first terminal is connected to the second node N2, and the second terminal is connected to the first electrode of the light-emitting unit 14. The first and second terminals of the data storage unit 13 are connected to the first node N1 and the second node N2, respectively. The second electrode of the light-emitting unit 14 is connected to the second power signal line 42.

[0033] Here, the compensation module 20 includes a compensation control terminal P2, a compensation signal input terminal P1, a first signal input terminal P3, and a drive signal output terminal P4. Specifically, the compensation control terminal P2 is connected to the scan line Sn, the compensation signal input terminal P1 is connected to the compensation signal terminal Cm, the first signal input terminal P3 is connected to the first power signal line 41, and the drive signal output terminal P4 is connected to the second node N2.

[0034] When driving the pixel driving circuit 100, the scan line Sn supplies the scan signal Vgate to the sub-pixel module and the compensation module 20. The data writing unit 11 and the compensation module 20 control the on / off state of the control terminal of the sub-pixel driving unit 12 in accordance with the signal control of the scan line Sn, and the data signal Vdata of the data line DM is written to the data storage unit 13. At the same time, the compensation signal from the compensation signal terminal Cm is input to the compensation module 20, and the compensation module 20 processes the compensation signal and the first power supply signal supplied from the first power supply signal line 41 to output a drive voltage. After the sub-pixel driving unit 12 is turned on, the compensation module 20 transmits the drive voltage to the second node N2, causing the drive current to pass through the light-emitting unit 14 and light up the light-emitting unit 14. By adjusting the compensation signal, the drive voltage at the second node N2 can be adjusted, and the drive current flowing through the light-emitting unit 14 can be made equal to a preset target value.

[0035] In this embodiment, the compensation module 20 and the sub-pixel drive module 10 are connected to the same scan line Sn, that is, the compensation module 20 and the sub-pixel drive module 10 are controlled by the same scan signal Vgate, so that during the drive phase of the sub-pixel drive module 10, the compensation module 20 provides a drive voltage signal to the sub-pixel drive module 10 in synchronization. The scan line Sn provides the scan signal Vgate to the compensation module 20 and the sub-pixel drive module 10, and when the scan signal Vgate is at an effective level, the data writing unit 11 of the sub-pixel drive module 10 turns on, and the compensation module 20 also turns on in synchronization. The data line Dm provides the data signal Vdata to the data writing unit 11, and the data writing unit 11 controls that the signal is written to the storage unit and turns on the sub-pixel drive unit 12. The compensation signal terminal Cm provides a compensation signal to the compensation module 20, and the first power signal line 41 provides a first power signal to the compensation module 20. After the compensation module 20 is turned on, it processes the compensation signal and the first power signal to output a drive voltage, which is then output to the second node N2. The drive current passes through the light-emitting unit 14, causing the light-emitting unit 14 to emit light.

[0036] In this embodiment, the first power supply signal is the power supply VDD signal, and the second power supply signal is the power supply VSS signal. Specifically, the magnitude of the compensation signal can be adjusted to compensate the drive voltage of the sub-pixel drive module 10 accordingly, so that the drive voltage supplied from the compensation module 20 to the sub-pixel drive module 10 becomes equal to the target drive voltage, and as a result the drive current flowing through the light-emitting unit 14 matches a preset target value. In the pixel drive circuit 100 within the display panel 1, the drive voltage of the pixel drive circuit 100 differs at different locations due to the different lengths of the first power supply signal line 41, and as a result, the display brightness between different pixels ultimately differs, resulting in an uneven display of the display panel 1. In this embodiment, the above configuration can compensate for the difference between the drive voltage of the pixel drive circuit 100 and the target drive voltage, overcome the deviation in the drive voltage of the pixel drive circuit 100 caused by the difference in the length of the wiring of the first power supply signal line 41, and make the display brightness of each pixel unit of the display panel 1 more uniform.

[0037] As shown in Figure 3, Figure 3 is a schematic diagram showing the structure of a pixel driving circuit according to the second embodiment of this application. In this embodiment, the compensation module 20 includes a compensation writing unit 21, a compensation driving unit 22, and a compensation storage unit 23. In the compensation writing unit 21, the control terminal is connected to the scan line Sn as a compensation control terminal P2, the first tip is connected to the compensation signal terminal Cm as a compensation signal input terminal P1, and the second terminal is connected to the third node N3. In the compensation driving unit 22, the control terminal is connected to the third node N3, the first terminal is connected to the first signal input terminal P3, and the second terminal is connected to the second node N2 as a drive signal output terminal P4. The first and second terminals of the compensation storage unit 23 are connected to the third node N3 and the fourth node N4, respectively, and the fourth node N4 is provided between the first power signal line 41 and the first signal input terminal P3.

[0038] The specific configuration and functions of the sub-pixel driving module 10 are the same as or similar to those of the sub-pixel driving module 10 designed in the above-described embodiment; refer to the above description for details.

[0039] Specifically, during display driving, the scan line Sn supplies the scan signal Vgate, and when the scan signal Vgate is at an effective level, the compensation writing unit 21 and the data writing unit 11 are turned on. Here, the data line Dm supplies the data signal Vdata, the data writing unit 11 writes the data signal Vdata to the data storage unit 13, the compensation signal terminal Cm supplies a compensation signal, and the compensation writing unit 21 writes the compensation signal to the compensation storage unit 23. In the next stage, the compensation writing unit 21 controls the compensation drive unit 22 to turn on, and the data writing unit 11 controls the sub-pixel drive unit 12 to turn on. A path is formed between the first power signal line 41, the first and second terminals of the compensation drive unit 22, the first and second terminals of the sub-pixel drive unit 12, the light-emitting unit 14, and the second power signal line 42, causing the light-emitting unit 14 to emit light. In the next stage, the scan signal Vgate changes to an invalid level, the compensation write unit 21 and the data write unit 11 turn off, the compensation storage unit 23 discharges to maintain the ON state of the compensation drive unit 22, and the data storage unit 13 discharges to maintain the ON state of the subpixel drive unit 12, thereby the first power signal continuously supplies drive current to the light-emitting unit 14 and maintains the brightness of the light-emitting unit 14.

[0040] In this embodiment, by introducing a compensation signal, the first power supply signal is compensated so that the drive current flowing through the light-emitting unit 14 is equal to a preset target value. This avoids the problem of deviation between the drive current flowing through the light-emitting unit 14 and the set target value, which is caused by deviations in the first power supply signal resulting from differences in the length of the first power supply signal line 41 of the pixel drive circuit 100, and improves the display uniformity of the display panel 1. Furthermore, within the display panel 1, the pixel drive circuits 100 are located in different positions, so the lengths of the first power supply signal line 41 differ, and the deviation between the drive current and the target value also differs. In this embodiment, by adjusting the magnitude of the compensation signal, the first power supply signal of the pixel drive circuit 100 can be compensated accordingly, and the drive current can be made to match a preset target value, thereby solving the aforementioned problem and compensating for the brightness difference between different pixel drive circuits 100.

[0041] Specifically, in this embodiment, the compensation module 20 further includes a voltage divider unit 24, the first terminal of which is connected to the fourth node N4, and the second terminal of which is connected to the first power signal line 41. That is, the first signal input terminal P3 is connected to the first power signal line 41 via the voltage divider unit 24. The voltage divider unit 24 is used to adjust the voltage of the second node N2 and also to protect the compensation drive unit 22 and the sub-pixel drive unit 12.

[0042] As shown in Figure 4, Figure 4 is a schematic diagram showing the structure of a pixel driving circuit according to the third embodiment of this application. In this embodiment, the sub-pixel driving unit 12 includes a first driving transistor M1, the compensation driving unit 22 includes a second driving transistor M3, the data writing unit 11 includes a first switching transistor M2, the compensation writing unit 21 includes a second switching transistor M4, the data storage unit 13 includes a first storage capacitor C1, the compensation storage unit 23 includes a second storage capacitor C2, and the voltage divider unit 24 includes a voltage divider resistor R. Specifically, the first driving transistor M1, the second driving transistor M3, the first switching transistor M2, and the second switching transistor M4 may be thin-film transistors or field-effect transistors. In this embodiment, they are set as metal oxide semiconductor field-effect transistors (MOSFETs), and specifically, they may be either P-type or N-type, and can be set according to actual requirements, and in this embodiment, a P-type transistor will be described as an example. In this embodiment, the light-emitting unit 14 is a current-driven light-emitting element, which may be, for example, a light-emitting diode (LED), a micro-light-emitting diode (Micro LED), a sub-millimeter-wave light-emitting diode (Mini LED), or an organic light-emitting diode (OLED), and can be set according to the actual needs. In this embodiment, an OLED will be described as an example.

[0043] In this embodiment, the second switch transistor M4 and the second drive transistor M3 are switches that control the first power supply signal, the second storage capacitor C2 is a switch that controls the ON state of the second drive transistor M3, the second switch transistor M4 is a switch that controls the magnitude of the charge voltage of the second storage capacitor C2, and the compensation signal is a compensation data signal Vdata that compensates for the first power supply signal. Specifically, the second switch transistor M4 is turned ON by the scan signal Vgate, and when the scan signal reaches an effective level, the first switching transistor M2 and the second switch transistor M4 are turned ON, the data line Dm charges the first storage capacitor C1, and the compensation signal terminal Cm charges the second storage capacitor C2. At the same time, the first drive transistor M1 and the third drive transistor are turned ON, and the drive current flows from the first power supply signal line 41 through the voltage divider resistor R, the second drive transistor M3, the first drive transistor M1, and the light-emitting unit 14 to the second power supply signal line 42, forming a light-emitting path. Here, the drive current determines the degree to which the second drive transistor M3 is turned ON. That is, equations (2) and (3) below hold true.

[0044] JPEG2026531085000003.jpg6170

[0045] JPEG2026531085000004.jpg14170

[0046] Here, VDDm is the voltage at the second node N2 of the pixel driving circuit 100, Ic is the driving current, R is the resistance value of the voltage divider resistor R, Vth is the threshold voltage of the second driving transistor M3, Vcm is the compensation voltage of the compensation signal, and W, L, μ, Cox, and VDD are the same as in the previously described embodiment, so a detailed explanation is omitted here.

[0047] Substituting equation (3) into equation (2), we obtain the following equation (4).

[0048] JPEG2026531085000005.jpg20170

[0049] The voltage value of VDDm can be obtained from equation (4) above. Since the VDD of the different pixel driving circuits 100 are different, VDDm can be adjusted by controlling the value of the compensation voltage Vcm of the compensation signal, thereby matching the voltage value at the second node N2 of each pixel driving circuit 100 to the target driving voltage.

[0050] In this embodiment, by introducing a compensation signal, the first power supply signal of the pixel drive circuit 100 is compensated, the drive voltage of the sub-pixel drive circuit 100 (i.e., the voltage at the second node N2) is matched to the target drive voltage, and the drive current flowing through the light-emitting unit 14 is matched to a preset target value. This avoids the problem of reduced display brightness caused by a deviation between the drive voltage and the target drive voltage due to a power supply voltage drop by the first power supply signal line 41. Furthermore, by adjusting the compensation voltage of the compensation signal, the drive voltage of the pixel circuit can always be maintained at the target drive voltage, thus avoiding the problem of brightness reduction due to circuit aging.

[0051] As shown in Figure 5, Figure 5 is a schematic diagram showing the structure of a display panel 1 according to the first embodiment of this application. In this embodiment, a display panel 1 is provided. The display panel 1 includes a plurality of pixel driving circuits 100, a plurality of scan lines Sn, a plurality of data lines Dm, a plurality of first power signal lines 41, and a plurality of compensation lines.

[0052] Here, the multiple pixel driving circuits 100 are arranged in a matrix, and the configuration and function of the pixel driving circuits 100 are the same as or similar to the pixel driving circuits 100 described in the above embodiment, and can achieve the same technical effects. Details have been described above and will not be repeated here.

[0053] Here, the scan line Sn is used to supply the scan signal Vgate to the pixel drive circuit 100, and multiple scan lines Sn are provided between two adjacent rows of pixel drive circuits 100, extending along the row direction. Pixel drive circuits 100 in the same row are connected to the corresponding same scan line Sn.

[0054] Here, the data line Dm is used to supply the data signal Vdata to the pixel drive circuit 100, and multiple data lines Dm are provided between two adjacent rows of pixel drive circuits 100, extending along the row direction. Pixel drive circuits 100 in the same row are connected to the corresponding same data line Dm.

[0055] Here, the first power signal line 41 is used to supply a first power signal to the pixel drive circuit 100, and multiple first power signal lines 41 are provided between two adjacent rows or two adjacent columns of pixel drive circuits 100, respectively, and extend along the row or column direction. Each pixel drive circuit 100 is connected to one adjacent first power signal line 41.

[0056] Here, multiple compensation lines correspond one-to-one with the pixel driving circuit 100 and are electrically connected to it, and are used to supply compensation signals to the pixel driving circuit 100 to adjust the driving voltage of the pixel driving circuit 100. As a result, the driving voltage of each pixel driving circuit 100 becomes equal to the target driving voltage.

[0057] In this embodiment, the display panel 1 introduces multiple compensation lines and electrically connects each pixel drive circuit 100 in a one-to-one correspondence. This individually compensates the drive voltage of each pixel drive circuit 100, resulting in the drive voltage of each drive circuit becoming equal to the target drive voltage, the brightness of each pixel drive circuit 100 becoming uniform, and improving the display uniformity of the display panel 1. Furthermore, because the lengths of the first power signal lines 41 of the pixel drive circuits 100 located at different positions are different, the power supply voltage drops also differ. As a result, the drive voltage of the pixel drive circuits 100 located at different positions changes, avoiding the problem of uneven brightness of the display panel 1.

[0058] As shown in Figure 6, Figure 6 is a schematic diagram showing the structure of a display panel according to the second embodiment of this application. In this embodiment, the display panel 1 further includes a voltage collection module 50, a data processing module 60, and a power management module 70.

[0059] The voltage acquisition module 50 includes an acquisition control unit 51 and a control signal generation unit 52. The control signal generation unit 52 is connected to the control terminal of the acquisition control unit 51, and the acquisition terminal of the acquisition control unit 51 is connected to the pixel drive circuit 100. The acquisition control unit 51 acquires the drive voltage during the drive phase of the pixel drive circuit 100 in response to the control signal from the control signal generation unit 52.

[0060] Here, both terminals of the data processing module 60 are connected to the output terminals of the acquisition control unit 51 and the pixel driving circuit 100, respectively. The data processing module 60 collects the drive voltage acquired by the acquisition control unit 51, calculates the value of the compensation signal based on the acquired drive voltage, and transmits the calculated value of the compensation signal to the power management module 70. Based on the obtained value of the compensation signal, the power management module 70 transmits the compensation signal to the corresponding pixel driving circuit 100 via the corresponding compensation line, and compensates the drive voltage of each pixel driving circuit 100.

[0061] Specifically, as explained above, since the first power supply voltage VDD that the first power supply signal reaches each pixel drive circuit 100 is different, if other parameters are the same, equation (4) above shows that the drive voltage VDDm of the pixel drive circuits 100 at different locations will be different. Here, M represents the location of the pixel drive circuit 100. Therefore, it is necessary to compensate the drive voltage VDDm with the value of the compensation voltage Vcm of the compensation signal.

[0062] In this embodiment, during the driving phase of the pixel driving circuit 100, the voltage acquisition module 50 acquires the driving voltage of the pixel driving circuit 100, and the actual value of the driving voltage VDDm of the pixel driving circuit 100 is acquired. The data processing module 60 acquires the acquired actual value of the driving voltage VDDm, performs calculation processing based on the actual value of the driving voltage VDDm and a preset value of the first power supply voltage, and acquires the compensation voltage of the compensation signal corresponding to the pixel driving circuit 100.

[0063] Specifically, based on equation (4) above, the formula for calculating the compensation signal is obtained as follows.

[0064] JPEG2026531085000006.jpg15170

[0065] The data processing unit can calculate the value of the compensation voltage required for the pixel drive circuit 100 based on equation (5) above, and transmits the calculated value of the compensation voltage to the power management module 70. Based on the value of the compensation voltage, the power management module 70 outputs a corresponding compensation signal to the pixel drive circuit 100 via the corresponding compensation line, thereby compensating the drive voltage of the pixel drive circuit.

[0066] Specifically, during the test development phase or initial display phase of the display panel 1, an initial compensation signal is provided to each level of pixel drive circuit 100. This compensation signal can be calculated based on equation (5) described above. Specifically, VDD is a preset target value of the first power supply signal, and VDDm can be obtained by the voltage acquisition module 50 by acquiring the pixel drive circuit 100 with the shortest first power supply signal line 41. Then, the initial value of the compensation signal is calculated based on equation (5) described above. This initial compensation signal is then used to compensate each pixel drive circuit 100, and then the voltage acquisition module 50 acquires the actual value of the drive voltage VDDm of each pixel drive circuit 100. This allows the actual value of the first power supply signal that reached each pixel drive circuit 100 to be calculated based on equation (4), and further, the compensation voltage Vcm of the compensation signal actually required for each pixel drive circuit 100 is calculated based on equation (5). Then, the compensation voltage is provided to each pixel drive circuit 100 via the power management module 70, matching the drive voltage of each pixel drive circuit 100 to the target drive voltage, thereby avoiding drive voltage differences and display differences due to differences in the position of sub-pixels.

[0067] In a specific embodiment, the display panel 1 collects the drive voltage of each pixel drive circuit 100 at regular intervals, adjusts the compensation signal once based on the collected voltage value, thereby maintaining the drive voltage value of each pixel drive circuit 100 at a target drive voltage value at all times.

[0068] Alternatively, since the length of the first power signal line 41 of each level's pixel drive circuit 100 is fixed and does not change over time, the first power voltage drop of each pixel drive circuit 100 does not change fundamentally. Therefore, after the initial detection and compensation, there is no need to detect and adjust the compensation signal. Furthermore, during the test development phase of the display panel 1, after collecting the necessary compensation signals for each pixel drive circuit 100 using the above detection and compensation method, the drive voltage of each pixel drive circuit 100 of all sample panels can be compensated based on these compensation signals. In other words, the display panel 1 does not need to be equipped with a voltage detection module or a data processing module 60 after shipment, thus simplifying the display panel 1.

[0069] Referring to Figure 7, which is a schematic diagram showing the structure of a display panel according to the third embodiment of this application. In this embodiment, the acquisition control unit 51 includes a plurality of acquisition control subunits 511, the control terminals of each acquisition control subunit 511 are connected to a control signal generation unit 52, and the first terminals of each acquisition control subunit 511 are connected to the corresponding pixel driving circuit 100. The control signal generation unit 52 includes a shift register and is used to generate time-division control signals, thereby controlling the acquisition control subunits 511 in a time-division manner to sequentially acquire the drive voltage of each row or column of the pixel driving circuit 100.

[0070] Specifically, the acquisition control subunit 511 includes a third switch transistor M05, the gate of which is connected to the corresponding output terminal of the shift register, the source of which is connected to the data processing module 60, and the drain of which is connected to the second node N2 of the corresponding pixel driving circuit 100.

[0071] Specifically, the control signal generation unit 52 generates a time-division control signal based on the frame start signal STV and the pulse trigger signal CPV. Here, the frame start signal STV is the same as the frame start signal STV used to generate the scan signal Vgate. When each pixel drive circuit 100 is driven, the control signal generation unit 52 controls the first switching transistor M2 and the second drive transistor M3 to turn on, and at the same time, the corresponding third transistor is also turned on. The accuracy of the collected drive voltage is ensured by collecting the actual value of the drive voltage of the second node N2 during the drive section of the pixel drive circuit 100.

[0072] Specifically, the control signal generation unit 52 includes multiple cascaded D flip-flops 521, the specific number of D flip-flops 521 matching the number of pixel drive circuits 100. The Q output terminals of the D flip-flops 521 are connected one-to-one with the control terminals of the third switch transistor M5, so that the third switch transistor turns on in conjunction with the driving of each corresponding pixel drive circuit 100, and the drive voltage of each pixel drive circuit 100 can be collected.

[0073] Referring to Figure 8, which is a schematic diagram showing the structure of a display panel according to the fourth embodiment of this application. In the fourth embodiment, the first terminal of the acquisition control subunit 511 is connected to the second node N2 of the pixel drive circuit 100, and the signal connection line 43 between a part of the pixel drive circuit 100 and the acquisition control subunit 511 has a straight section 431 and a bent section 432. The total length of the bent section 432 of the signal connection line 43 of the pixel drive circuit 100 gradually increases along the direction in which the pixel drive circuit 100 approaches the acquisition control unit 51, so that the total length of each signal connection line 43 is the same. For example, the far-end signal connection line 43 may not have a bent section 432, while the near-end signal connection line 43 may have one or more bent sections 432 depending on the specific length. The wiring length of each bent section 432 can be set according to actual needs. For example, if there is a large area available for installing the bent section 432, the wiring length of the bent section 432 can be made slightly longer, and if there is a relatively limited area available for installing the bent section 432, the wiring length of the bent section 432 can be made slightly shorter.

[0074] Because there is a distinction between near and far voltage detection points for VDDm, a bend is provided in the signal connection line between a portion of the pixel driving circuit 100 and the acquisition control subunit 511 to reduce the influence of the path. Specifically, the bend may consist of meandering wiring. The far-end detection point is directly routed back, and since the path to the near-end detection point is longer than that to the far-end point, meandering wiring is performed in the blank area of ​​the panel to increase the path length. Ultimately, the path to each detection point becomes the same, resulting in a higher detected voltage level.

[0075] Referring to Figure 9, Figure 9 is a schematic diagram showing the structure of a display device according to one embodiment of this application. This embodiment provides a display device, which includes a display panel 1, a scanning drive module 2, and a data drive module 3.

[0076] Here, the specific configuration and functions of display panel 1 are the same as or similar to those of display panel 1 according to the above embodiment, and can achieve the same technical effects. Please refer to the detailed explanation above. It will not be repeated here.

[0077] Here, the scanning drive module 2 is electrically connected to the display panel 1 via the scanning line Sn and is used to supply the scanning signal Vgate to the display panel 1. The data drive module 3 is electrically connected to the display panel 1 via the data line Dm and is used to supply the data signal Vdata to the display panel 1, thereby causing the display panel 1 to display the corresponding screen.

[0078] The above describes embodiments of the present application and does not limit the scope of the patent of this application. Any equivalent structural or process transformations performed using the contents of the specification and drawings of this application, or any other related technical applications that are directly or indirectly applied, are similarly included within the scope of the patent protection of this application. [Explanation of symbols]

[0079] 1: Display Panel 2: Scanning drive module 3: Data-driven module 100a / 100: Pixel driving circuit 10: Sub-pixel drive module 11: Data writing unit 12: Sub-pixel drive unit 13: Data storage unit 14: Light-emitting unit 20: Compensation Module 21: Compensation writing unit 22: Compensation drive unit 23: Compensation memory unit 24: Voltage dividing unit 41: First power signal line 42: Second power signal line 43: Signal connection wire 431: Straight section 432: Bending section 50: Voltage collection module 51: Collection and control unit 511: Collection and control subunit 52: Control signal generation unit 521: Type D flip-flop 60: Data Processing Module 70: Power Management Module Sn: scan line Dm: Data line M01: Drive Transistor M02: Switching Transistor C01: Storage Capacitor Cm: Compensation signal terminal P1: Compensation signal input terminal P2: Compensation control terminal P3: First signal input terminal P4: Drive signal output terminal N1: First node N2: Second node N3: Third node N4: The fourth node M1: First drive transistor M2: First switching transistor M3: Second drive transistor M4: Second switching transistor M5: Third switching transistor R: Voltage divider resistor

Claims

1. A pixel driving circuit including a sub-pixel driving module, wherein the sub-pixel driving module includes a data writing unit, a data storage unit, a sub-pixel driving unit, and a light-emitting unit. In the data writing unit, the control terminal is connected to the scan line, the first terminal is connected to the data line, and the second terminal is connected to the first node. In the sub-pixel driving unit, the control terminal is connected to the first node, the first terminal is connected to the second node, and the second terminal is connected to the first electrode of the light-emitting unit. The first and second terminals of the data storage unit are connected to the first and second nodes, respectively, and the second electrode of the light-emitting unit is connected to the second power signal line. Here, the pixel driving circuit further includes a compensation signal terminal and a compensation module, the compensation module includes a compensation control terminal, a compensation signal input terminal, a first signal input terminal and a driving signal output terminal, the compensation control terminal is connected to the scan line, the compensation signal input terminal is connected to the compensation signal terminal, the first signal input terminal is connected to the first power signal line, and the driving signal output terminal is connected to the second node. Here, the data writing unit and the compensation module respond to the signal control of the scan line, the data writing unit controls the on or off of the control terminal of the sub-pixel drive unit, and writes the data signal of the data line to the data storage unit. The compensation signal terminal is used to supply a compensation signal to the compensation module, and the compensation module is used to process the compensation signal and the first power signal supplied by the first power signal line to output a drive voltage. A pixel driving circuit characterized in that, after the sub-pixel driving unit is turned on, the driving voltage is output to the second node by the compensation module so that the driving current passes through the light-emitting unit, and the driving voltage of the second node is adjusted by adjusting the compensation signal so that the driving current is equal to a preset target value.

2. The pixel driving circuit according to claim 1, characterized in that, during the driving stage of the sub-pixel driving module, the compensation module and the sub-pixel driving module are connected to the same scan line so that the compensation module provides the driving voltage to the sub-pixel driving module in a synchronous manner.

3. The compensation module includes a compensation write unit, a compensation drive unit, and a compensation storage unit, wherein in the compensation write unit, a control terminal is connected to the scan line as the compensation control terminal, a first terminal is connected to the compensation signal terminal as the compensation signal input terminal, and a second terminal is connected to a third node; in the compensation drive unit, a control terminal is connected to the third node, a first terminal is connected to the first power signal line as the first signal input terminal, and a second terminal is connected to the second node as a drive signal output terminal; the first and second terminals of the compensation storage unit are connected to the third node and the fourth node, respectively, and the fourth node is provided between the first power signal line and the first signal input terminal. The pixel driving circuit according to claim 2, characterized in that, in response to the signal control of the scan line, the data writing unit and the compensation writing unit turn on simultaneously when the signal of the scan line is at an effective level, and write the data signal of the data line to the data storage unit, write the compensation signal provided from the compensation signal terminal to the compensation storage unit, the data writing unit controls the sub-pixel driving unit to turn on, and the compensation writing unit controls the compensation driving unit to turn on, thereby outputting the drive signal of the first power signal line and the compensation signal to the second node.

4. The pixel driving circuit according to claim 3, characterized in that when the signal of the scan line becomes invalid, the compensation writing unit and the data writing unit are turned off, the compensation storage unit is discharged to maintain the ON state of the compensation driving unit, and the data storage unit is discharged to maintain the ON state of the sub-pixel driving unit, thereby the first power supply signal continuously supplies the driving current to the light-emitting unit and maintains the brightness of the light-emitting unit.

5. The pixel driving circuit according to claim 3, wherein the compensation module further includes a voltage divider unit, the first terminal of the voltage divider unit is connected to a fourth node, the second terminal of the voltage divider unit is connected to the first power signal line, and the voltage divider unit is used to adjust the voltage of the second node.

6. The pixel driving circuit according to claim 5, wherein the sub-pixel driving unit includes a first driving transistor, the compensation driving unit includes a second driving transistor, the data writing unit includes a first switching transistor, the compensation writing unit includes a second switching transistor, the data storage unit includes a first storage capacitor, the compensation storage unit includes a second storage capacitor, and the voltage divider unit includes a voltage divider resistor.

7. The pixel driving circuit according to claim 6, characterized in that the first driving transistor, the second driving transistor, the first switching transistor, and the second switching transistor are thin-film transistors or field-effect transistors, and the light-emitting unit is a current-driven light-emitting element.

8. A display panel including multiple pixel driving circuits, multiple scan lines, multiple data lines, multiple first power signal lines, and multiple compensation lines, The multiple drive circuits are arranged in a matrix, and the pixel drive circuit is the pixel drive circuit described in claim 1. Each of the scan lines is provided between two adjacent rows of the pixel drive circuits, extends along the row direction, and the pixel drive circuits in the same row are connected to the corresponding same scan line. Each of the data lines is provided between two adjacent rows of the pixel drive circuits, extends along the row direction, and the pixel drive circuits in the same row are connected to the corresponding same data line. The multiple first power signal lines are each provided between two adjacent rows or two columns of the pixel drive circuits, extending along the row or column direction, and each pixel drive circuit is connected to one of the adjacent first power signal lines. A display panel characterized in that a plurality of compensation lines are electrically connected to the pixel driving circuit in a one-to-one correspondence and are used to provide a compensation signal to the pixel driving circuit, and the driving voltage of each pixel driving circuit is adjusted so that the driving voltage of each pixel driving circuit is equal to the target driving voltage.

9. The display panel further includes a voltage acquisition module, the voltage acquisition module includes an acquisition control unit and a control signal generation unit, the control signal generation unit is connected to the control terminal of the acquisition control unit, and the acquisition terminal of the acquisition control unit is connected to the pixel driving circuit. The display panel according to claim 8, characterized in that the collection control unit collects the drive voltage of the pixel drive circuit during the drive stage in response to the control signal of the control signal generation unit.

10. The acquisition control unit includes a plurality of acquisition control subunits, the control terminals of each of the plurality of acquisition control subunits are connected to the control signal generation unit, and the first terminals of each of the plurality of acquisition control units are connected to the corresponding pixel driving circuit. The display panel according to claim 9, characterized in that the acquisition control subunit includes a third switching transistor, the control signal generation unit includes a shift register, the shift register is used to generate a minute-by-minute control signal, and the acquisition control subunit is minute-by-minute controlled to sequentially acquire the drive voltage of each row or column of the pixel drive circuit.

11. The display panel according to claim 10, wherein the control signal generation unit includes a plurality of cascaded D-type flip-flops, and the Q output terminals of the D-type flip-flops are connected in a one-to-one correspondence to the control terminals of the third switching transistors.

12. The display panel according to claim 10, characterized in that the control signal generation unit is used to generate the minute-time control signal based on the frame start signal and the pulse trigger signal.

13. The display panel according to claim 9, further comprising a data processing module and a power management module, wherein both terminals of the data processing module are connected to the output terminal of the acquisition control unit and the pixel driving circuit, respectively, and the data processing module is used to collect the driving voltage collected by the acquisition control unit and calculates a compensation signal value based on the collected driving voltage, transmits the calculated compensation signal value to the power management module, and the power management module transmits the compensation signal to the corresponding pixel driving circuit based on the obtained compensation signal value.

14. The display panel according to claim 13, characterized in that the gate of the third switching transistor is connected to the corresponding output terminal of the shift register, the source of the third switching transistor is connected to the data processing module, and the drain of the third switching transistor is connected to the corresponding second node of the pixel driving circuit.

15. The display panel according to claim 13, which is used to provide an initial compensation signal to each level of the pixel drive circuit via a data processing module and a power management module during the test development stage or initial display stage of the display panel, and after collecting the actual values ​​of the drive voltage of each of the pixel drive circuits via a voltage acquisition module, the data processing module calculates a compensation voltage based on the actual values ​​of the drive voltage and compensates each of the corresponding pixel drive circuits with the compensation voltage via the power management module.

16. The display panel according to claim 15, characterized in that the voltage acquisition module acquires the drive voltage of each pixel drive circuit once at regular intervals and adjusts the compensation signal once based on the acquired voltage value.

17. The display panel according to claim 10, wherein the first terminal of the acquisition control subunit is connected to the second node of the pixel drive circuit, the signal connection line between a part of the pixel drive circuit and the acquisition control subunit has a straight section and a bent section, the length of the bent section of the signal connection line gradually increases along the direction in which the pixel drive circuit approaches the acquisition control unit, and thereby the total length of each signal connection line becomes the same.

18. The display panel according to claim 17, characterized in that the bent portion is a meandering wiring.

19. A display device including a display panel, a scanning drive module and a data drive module, The display panel is the display panel described in claim 8, The scanning drive module is used to provide a scanning signal to the display panel. The display device is characterized in that the data drive module is used to provide data signals to the display panel.

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