Semiconductor structure and method for manufacturing the same

Abstract

This disclosure provides a semiconductor structure and a method for manufacturing the same, the semiconductor structure comprising at least a lower conductive layer, a barrier portion, a three-dimensional structure, contact holes, a first conductive layer, and a first isolation layer, wherein the plane on which the barrier portion is located is above the plane on which the lower conductive layer is located, and the vertical projection of the barrier portion and the lower conductive layer has an overlapping region, the three-dimensional structure comprises a first part and a second part, the top surface of the barrier portion is higher than the bottom surface of the second part and lower than the bottom surface of the first part or is flush with the bottom surface of the first part, the first part is located at least partially directly above the overlapping region, the plane on which the first conductive layer is located is higher than the top surface of the three-dimensional structure, the contact holes are directly connected to the first conductive layer, the lower conductive layer is electrically connected to the first conductive layer via the contact holes, the contact holes are located on the side of the first part far from the second part, and the first isolation layer is used to fill the region between the contact holes and the three-dimensional structure and the region between different contact holes.

Description

Technical Field

[0001] (Cross-reference to Related Applications) The present application claims priority to the Chinese Patent Application filed with the China National Intellectual Property Administration on August 16, 2024, with the application number 202411133716.9 and the title of the invention "Semiconductor structure and manufacturing method thereof", and the entire content of the Chinese Patent Application is incorporated into the present application by reference.

[0002] Embodiments of the present application relate to the field of semiconductors, and in particular to a semiconductor structure and a manufacturing method thereof.

Background Art

[0003] In the manufacturing process of a semiconductor structure, it is necessary to form a film layer with a specific shape through deposition and etching. However, the specific effect of material deposition and etching is related to the morphology of the target structure. For example, when depositing a material to fill a trench having a high aspect ratio, hollow voids are easily formed. When the actual effect of material deposition or etching deviates from the expected effect, it may affect the actual performance of the final structure.

Summary of Invention

Means for Solving the Problems

[0004] Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, which is beneficial to solving at least the problem of signal crosstalk between contact holes.

[0005] According to some embodiments of this application, one embodiment of the embodiments of this application provides a semiconductor structure comprising a lower conductive layer, a barrier portion, a three-dimensional structure, a contact hole, a first conductive layer, and a first isolation layer, wherein the plane on which the barrier portion is located is above the plane on which the lower conductive layer is located, and the vertical projections of the barrier portion and the lower conductive layer have an overlapping region, and the three-dimensional structure comprises a first part and a second part, wherein the top surface of the barrier portion is higher than the bottom surface of the second part and lower than the bottom surface of the first part The first part is low or flush with the bottom surface of the first part, the first part is located at least partially directly above the superimposed area, the plane on which the first conductive layer is located is higher than the top surface of the three-dimensional structure, the contact holes are directly connected to the first conductive layer, the lower conductive layer is electrically connected to the first conductive layer through the contact holes, the contact holes are located on the side of the first part furthest from the second part, and the first isolation layer is used to fill the area between the contact holes and the three-dimensional structure, and the area between different contact holes.

[0006] In some embodiments, the semiconductor structure further includes a second conductive layer, the barrier portion belongs to a part of the second conductive layer, the lower conductive layer is electrically connected to the second conductive layer via a first conductive plug, and the second conductive layer is electrically connected to the first conductive layer via a contact hole.

[0007] In some embodiments, the second conductive layer further includes a signal transmission section, the signal transmission section being separated from the barrier section, the barrier section being located between the signal transmission section and the second section, and the lower conductive layer being electrically connected to the contact holes via the signal transmission section.

[0008] In some embodiments, the vertical direction is perpendicular to a first horizontal direction, and the semiconductor structure further includes a plurality of contact holes arranged along the first horizontal direction, and a barrier portion extending along the first horizontal direction, wherein each contact hole is electrically connected to the underlying conductive layer via a corresponding second signal line in the signal transmission portion, and the barrier portion is located between the second signal line corresponding to any of the contact holes and the second portion.

[0009] In some embodiments, the vertical direction is perpendicular to a first horizontal direction and a second horizontal direction, the first horizontal direction is perpendicular to the second horizontal direction, the semiconductor structure further includes a plurality of the contact holes arranged along the first horizontal direction, and the barrier portion includes a plurality of the barrier blocks arranged along the first horizontal direction, and in a projection plane perpendicular to the vertical direction, the plurality of the contact holes and the plurality of the barrier blocks are alternately arranged in the first horizontal direction and offset in the second horizontal direction.

[0010] In some embodiments, the second conductive layer includes a plurality of second signal lines, the lower conductive layer transmits electrical signals to the contact holes via the second signal lines, the second signal lines extend below at least a portion of the first portion, and the barrier portion includes the portion on which the second signal lines extend below the first portion.

[0011] In some embodiments, the second conductive layer further includes redundant wires, the redundant wires are not provided with the contact holes, and the barrier portion further includes the portion in which the redundant wires extend below the first portion.

[0012] In some embodiments, the second conductive layer further includes a second dummy wiring, the width of which is smaller than the width of the second signal line, the second dummy wiring is used to equalize the conductive material density in different regions of the second conductive layer, and the barrier portion further includes a portion in which the second dummy wiring extends below the first portion.

[0013] In some embodiments, the barrier portion surrounds the three-dimensional structure.

[0014] In some embodiments, the three-dimensional structure is a capacitor electrode, and the capacitor electrode includes an upper electrode of a memory capacitor, or an upper or lower electrode of a non-memory capacitor.

[0015] According to some embodiments of this application, another embodiment of the embodiments of this application further provides a method for manufacturing a semiconductor structure, the method for manufacturing the semiconductor structure comprising the steps of sequentially forming a lower conductive layer and a barrier portion, wherein the plane on which the barrier portion is located is above the plane on which the lower conductive layer is located, and the vertical projections of the barrier portion and the lower conductive layer have an overlapping region; and forming a three-dimensional structure, the three-dimensional structure comprising a first part and a second part, wherein the top surface of the barrier portion is higher than the bottom surface of the second part and lower than the bottom surface of the first part, or is flush with the bottom surface of the first part. The first part includes a step located at least partially directly above the superimposed area; a step of forming a first isolation layer, the first isolation layer being used to fill the area above the lower conductive layer and the barrier portion, the top surface of the first isolation layer being higher than the top surface of the three-dimensional structure, the first isolation layer being located on the side of the first part away from the second part and covering the side wall of the first part; and a step of forming a contact hole and a first conductive layer, the contact hole penetrating the first isolation layer, and the first conductive layer being electrically connected to the lower conductive layer through the contact hole. [Brief explanation of the drawing]

[0016] [Figure 1] This is a front view of a semiconductor structure according to some embodiments of this application. [Figure 2] Figure 1 is a plan view of the semiconductor structure shown. [Figure 3] This is a front view of a semiconductor structure. [Figure 4] Figure 3 is a plan view of the semiconductor structure. [Figure 5] This is a front view of a semiconductor structure according to some embodiments of this application. [Figure 6] This is a front view of a semiconductor structure according to some embodiments of this application. [Figure 7] This is a plan view corresponding to the semiconductor structure shown in Figure 6, according to some embodiments of this application. [Figure 8] This is a plan view corresponding to the semiconductor structure shown in Figure 6, according to some other embodiments of this application. [Figure 9] It is a front view of a semiconductor structure. [Figure 10] It is a front view of a semiconductor structure according to some embodiments of the present application. [Figure 11] It is a plan view corresponding to the semiconductor structure shown in FIG. 10 according to some embodiments of the present application. [Figure 12] It is a plan view corresponding to the semiconductor structure shown in FIG. 10 according to some embodiments of the present application. [Figure 13] It is a plan view of a semiconductor structure according to some embodiments of the present application. MODE FOR CARRYING OUT THE INVENTION

[0017] One or more embodiments are exemplarily described by the illustrations in the corresponding drawings. These exemplary descriptions do not constitute a limitation on the embodiments, and unless otherwise specified, the figures in the drawings do not constitute a limitation on proportionality.

[0018] Hereinafter, each embodiment of the present application will be described in detail with reference to the accompanying drawings. However, those skilled in the art can understand that numerous technical details are set forth in each embodiment of the present application to enable the reader to better understand the present application. Nevertheless, the technical solutions for which protection is sought in the present application can be implemented without these technical details and without various changes and modifications based on the respective embodiments described below.

[0019] FIG. 1 is a front view of a semiconductor structure according to some embodiments of the present application. FIG. 2 is a plan view of the semiconductor structure shown in FIG. 1. Referring to FIGS. 1 and 2, the semiconductor structure includes a lower conductive layer 21, a barrier portion 22, a three-dimensional structure 20, a contact hole 23, a first conductive layer 25, and a first isolation layer 265. The plane where the barrier portion 22 is located is above the plane where the lower conductive layer 21 is located, and the projection of the barrier portion 22 and the lower conductive layer 21 in the vertical direction Z has an overlapping region 212. The three-dimensional structure 20 includes a first portion 201 and a second portion 202, the top surface of the barrier portion 22 is higher than the bottom surface of the second portion 202, and lower than the bottom surface of the first portion 201 or flush with the bottom surface of the first portion 201. The first portion 201 is located at least partially directly above the overlapping region 212. The plane where the first conductive layer 25 is located is higher than the top surface of the three-dimensional structure 20, the contact hole 23 is directly connected to the first conductive layer 25, the lower conductive layer 21 is electrically connected to the first conductive layer 25 through the contact hole 23, and the contact hole 23 is located on a side of the first portion 201 away from the second portion 202. The first isolation layer 265 is used to fill the region between the contact hole 23 and the three-dimensional structure 20, and the region between different contact holes 23.

[0020] In the embodiment of the present application, by providing the barrier portion 22 and positioning at least a part of the three-dimensional structure 20 (that is, at least a part of the first portion 201) on the barrier portion 22, it is advantageous to raise the bottom position of at least a part of the three-dimensional structure 20, thereby reducing the aspect ratio of the three-dimensional structure 20 in this part, avoiding the formation of a recess toward the second portion 202 caused by an excessively high aspect ratio of the sidewall of the first portion 201, further, when the first isolation layer 265 fills and covers the sidewall of the first portion 201, it avoids gaps caused by the existence of the recess, further avoids expansion and transfer of a single gap and communication between different gaps, and avoids signal crosstalk and even short circuit between different contact holes caused by the existence of gaps.

[0021] Figure 3 is a front view of the semiconductor structure. Figure 4 is a plan view of the semiconductor structure shown in Figure 3. Referring to Figure 3, if no barrier is provided, a recessed portion 101 is formed on the side wall of the three-dimensional structure 10 facing the contact hole 12 due to a high aspect ratio. The inventors of this application have found that the recessed portion 101 usually appears in a region relatively close to the bottom of the first part 201. When depositing the isolation material to form the first isolation layer 165, it is difficult to completely fill the inside of the recessed portion 101 due to shielding by the upper structure of the recessed portion 101 and the filling angle, making it easy for a first void 102 to be formed. Furthermore, referring to Figure 4, after forming the isolation layer 165, vias that expose the bottom conductive layer 11 are formed by etching, and then the vias are filled to form the contact hole 12. However, the inventors of this application have found that voids are also formed between different vias in the isolation layer 165, and these are referred to as second voids 121. The first void 102 may be connected in a sheet-like manner in the first horizontal direction 12, and since both the first void 102 and the second void 121 may expand, vias may communicate with either or both of the first void 102 or the second void 121. When the conductive material is deposited to form the contact hole 12, some of the conductive material may also fill the first void 102 and the second void 121, which may cause crosstalk and even short circuits when different contact holes 12 transmit electrical signals.

[0022] The embodiments of this application will be described in more detail below with reference to the drawings.

[0023] Referring to Figure 1, in some embodiments, the lower conductive layer 21 is connected via a second conductive plug 24 to the source, drain, or gate of a transistor (not shown) located in the active region, and no other conductive layers are provided below the plane in which the lower conductive layer 21 is located, and the locations of the gates of different transistors do not conform to the definition of "conductive layer" in this application. The cross-sectional shape of the lower conductive layer 21 is related to the cross-sectional position in the front view, and the cross-sectional shape may differ at different cross-sectional positions. Referring to Figure 2, the lower conductive layer 21 includes at least a plurality of lower signal lines 211, each of which is connected to a corresponding contact hole 23 and used to transmit an electrical signal. The plurality of lower signal lines 211 shown in Figure 2 are multiple straight lines of the same length and parallel to each other, but in practice, each lower signal line 211 may have a different length from an adjacent lower signal line 211, may be a bent line, and there is no restriction that different lower signal lines 211 must be parallel to each other.

[0024] It should be explained that the "plane in which a structure is located" as referred to in this application, for example, the plane in which the barrier portion 22 is located and the plane in which the lower conductive layer 21 is located, are both defined by the bottom surface of the corresponding structure; that is, the plane in which a structure is located refers to the plane in which the bottom surface of that structure is located. In some embodiments, the definition of a "conductive layer" is that the conductive layer has a two-dimensional top surface and a bottom surface; that is, the top surface of the conductive layer at different positions is flush with the surface, and the bottom surface at different positions is flush with the surface. Furthermore, the embodiments of this application are not limited to the top surface of the barrier portion 22; the top surface of the barrier portion 22 may be a plane or a three-dimensional surface.

[0025] In some embodiments, the projection of the barrier portion 22 in the vertical direction Z is entirely within the projection of the underlying conductive layer 22, where the side of the barrier portion 22 toward the second portion 202 may be within the projection of the underlying conductive layer 22, or it may be flush with the side of the underlying conductive layer 21 closer to the second portion 202. In yet another embodiment, in the vertical direction Z, the projection of the barrier portion 22 partially overlaps with the projection of the underlying conductive layer 21, i.e., the projection of the side of the barrier portion 22 farther from the second portion 202 is within the projection of the underlying conductive layer 21, and the projection of the side of the underlying conductive layer 21 closer to the second portion 202 is within the projection of the barrier portion 22.

[0026] In some embodiments, the top surface of part 1 201 is lower than the top surface of part 2 202, or is flush with the top surface of part 2 202. The lower top surface of part 1 201 than the top surface of part 2 202 may be the actual design, or it may have been originally designed to be flush, but due to subsequent process reasons, the top surface of part 1 201 is actually lower than the top surface of part 2 202 or is flush with the top surface of part 2 202. For example, the top surfaces of part 1 201 and part 2 202 are continuous surfaces.

[0027] In some embodiments, the semiconductor structure is provided with a second isolation layer 261. The second isolation layer 261 is used to isolate the underlying conductive layer 21 from the transistor in the active region and is also used to support the underlying conductive layer 21. The underlying conductive layer 21 can be obtained by etching the second isolation layer 261 to form grooves in a predetermined pattern and then filling those grooves. In other embodiments, the second isolation layer includes a first sublayer located below the underlying conductive layer and a second sublayer located in the same layer as the underlying conductive layer, i.e., first the first sublayer is formed, then material is deposited and etched to form the underlying conductive layer 21, and finally the voids in the underlying conductive layer are filled to form the second sublayer. All “isolation layers” referred to in this application may consist of multiple sublayers and may be manufactured by different process methods, and this application does not limit the actual number of layers or manufacturing methods of any film layer.

[0028] In some embodiments, the lower conductive layer 21 further includes lower redundant lines, the width and material of which are the same as the lower signal lines, but the lower redundant lines differ in that they are not electrically connected to any contact holes. In yet another embodiment, the lower conductive layer further includes lower dummy wiring, the material of which is usually the same as that of the lower signal lines, but its width is less than or equal to the width of the lower signal lines, and the lower dummy wiring is not electrically connected to any contact holes. The role of the lower dummy wiring is to equalize the density of conductive material in different regions, so that the lower conductive layer 21 has a relatively uniform stress distribution. The method of forming the lower dummy wiring and lower redundant lines may be the same as the method of forming the lower signal lines.

[0029] In some embodiments, the three-dimensional structure 20 is a conductive structure and at least partially overlaps the projection of the second part 202 and the lower conductive layer 21 in the vertical Z direction. The semiconductor structure is further provided with a third isolation layer 262, which is used to isolate the lower conductive layer 21 from the three-dimensional structure 20. In other embodiments, the third isolation layer 262 may not be provided if the projection of the second part 202 of the three-dimensional structure 20 and the lower conductive layer 21 in the vertical Z direction do not overlap, or if the bottom surface of the second part 202 of the three-dimensional structure 20 is an insulating material. All "projections" referred to in this application are "orthographic projections".

[0030] It should be noted that the three-dimensional structure 20 in this application may include multiple complete film layers, may include a complete film layer and several partial film layers simultaneously, or may consist entirely of partial film layers. In other words, this application does not limit the material, the number of film layers, or the completeness of the film layers of the three-dimensional structure 20.

[0031] In some embodiments, the semiconductor structure is further provided with a fourth isolation layer 263, and the barrier portion 22 is provided on the fourth isolation layer 263, i.e., the top surface of the fourth isolation layer 263 is flush with the bottom surface of the barrier portion 22. One of the main purposes of providing the fourth isolation layer 263 is to adjust the height of the barrier portion 22, and by extension, the height of the bottom surface of at least part of the first portion 201, which is advantageous in avoiding the appearance of depressions in the side walls of the first portion 201 facing the contact holes 23, and in ensuring complete filling of the first isolation layer 265. It should be noted that the fourth isolation layer 263 must not be too thick; otherwise, it may affect the thickness of the three-dimensional structure in the second horizontal direction Y, potentially causing problems such as stress concentration at the bottom of the three-dimensional structure 20 or a reduction in the isolation effect. The isolation effect here refers to isolating conductive materials located on opposite sides of the three-dimensional structure 20 in the second horizontal direction Y, thereby avoiding problems such as charge leakage and signal interference.

[0032] In some embodiments, in the vertical direction Z, the thickness of the fourth isolation layer 263 is 1.5% to 5% of the maximum thickness of the three-dimensional structure 20, for example, 2%, 2.5%, 3%, 3.5%, or 4.5%.

[0033] In some embodiments, the semiconductor structure is further provided with a fifth isolation layer 264, which is used to isolate the barrier portion 22 from the three-dimensional structure 20. In some embodiments, if the barrier portion 22 is made of an insulating material, or if the surface of the three-dimensional structure 20 facing the barrier portion 22 is made of an insulating material, the fifth isolation layer may not be provided. Understandably, in the second horizontal direction Y, a fifth isolation layer 264 is provided for isolation between the barrier portion 22 and the second portion 202, and the fifth isolation layer 264 in that portion also performs a barrier function. Therefore, when the fifth isolation layer 264 is provided, only a portion of the first portion 201 is located directly above the barrier portion 22, but the first portion 201 is located entirely above the fifth isolation layer 264. In this application, "above" means directly above unless otherwise specified.

[0034] Figure 5 is a front view of a semiconductor structure according to several embodiments of the present application. Referring to Figure 5, the semiconductor structure further includes a second conductive layer 37 (the extent of the second conductive layer 37 is marked with a dashed frame), the barrier portion 32 belongs to a part of the second conductive layer 37, the lower conductive layer 31 is electrically connected to the second conductive layer 37 via a first conductive plug 38, and the second conductive layer 37 is electrically connected to the first conductive layer 35 via contact holes 33. In this embodiment, since the second conductive layer 37 is a conductive material, if the surface of the three-dimensional structure 30 facing the barrier portion 32 is an insulating material, the fifth isolation layer 364 may not be provided; otherwise, the fifth isolation layer 364 should be provided. In this embodiment, the purpose of providing the fourth isolation layer 363 is to adjust the spacing between different conductive layers, which is advantageous in reducing signal crosstalk between different conductive layers.

[0035] In the embodiment shown in Figure 5, the side of the dashed frame marking the extent of the second conductive layer 37 toward the second part 302 extends beyond the side of the barrier portion 32 toward the second part 302, but this is simply to clearly indicate that the extent of the second conductive layer 37 includes a portion of the barrier portion 32. In different embodiments, the side of the second conductive layer 37 toward the second part 302 may be flush with the side of the barrier portion 32 toward the second part 302, or it may be closer to the second part 302 relative to the side of the barrier portion 32 toward the second part 302. Furthermore, in some embodiments, the side of the barrier portion 32 toward the second part 302 is the side of the second conductive layer 37 toward the second part 302.

[0036] Figure 6 is a front view of a semiconductor structure according to some embodiments of the present application. Referring to Figure 6, the three-dimensional structure 40 includes a first part 401 and a second part 402, and the second conductive layer 47 further includes a signal transmission section 472, the signal transmission section 472 and the barrier section 471 are electrically isolated from each other, the barrier section 471 is located between the signal transmission section 472 and the second part 402, and the lower conductive layer 41 is electrically connected to the contact holes 43 via the signal transmission section 472. In other words, although the signal transmission section 472 and the barrier section 471 belong to the same conductive layer, they are electrically separated and different parts, the barrier section 471 is not electrically connected to the contact holes 43, and electrical signals are transmitted between different conductive layers only via the signal transmission section 472. By separating the signal transmission section 472 and the barrier section 471, it is advantageous to avoid the three-dimensional structure 40 affecting the electrical signals transmitted by the signal transmission section 472 through the barrier section 471, and such an effect may become more pronounced if there is a change in the potential of the three-dimensional structure 40.

[0037] Figure 7 is a plan view corresponding to the semiconductor structure shown in Figure 6, according to some embodiments of the present application. Referring to Figure 7, the vertical direction Z is perpendicular to the first horizontal direction X, and the semiconductor structure further includes a plurality of contact holes 43 arranged along the first horizontal direction X, and a barrier portion 471 extending along the first horizontal direction X, each contact hole 43 being electrically connected to an underlying conductive layer (not shown) via a corresponding second signal line in a signal transmission portion 472, and the barrier portion 471 is located between the second signal line corresponding to any contact hole 43 and the second portion 402. By providing the barrier portion 471 to extend along the first horizontal direction X, it is advantageous to avoid the appearance of a first void in the first horizontal direction X, and further to avoid communication with a second void 431 that may exist between the first void and an adjacent contact hole 43, thereby advantageous to avoid or reduce signal crosstalk between different contact holes. It should be explained that the above-mentioned "different contact holes" include adjacent contact holes and non-adjacent contact holes in the first horizontal direction X.

[0038] Figure 8 is a plan view corresponding to the semiconductor structure shown in Figure 6, according to some other embodiments of the present application. Referring to Figure 8, the vertical direction Z is perpendicular to the first horizontal direction X and the second horizontal direction Y, and the first horizontal direction X is perpendicular to the second horizontal direction Y. The semiconductor structure further includes a plurality of contact holes 43 arranged along the first horizontal direction X, and the barrier portion 471 includes a plurality of barrier blocks 47a arranged along the first horizontal direction X, wherein in a projection plane perpendicular to the vertical direction Z, the plurality of contact holes 43 and the plurality of barrier blocks 47a are alternately arranged in the first horizontal direction X and offset in the second horizontal direction Y. This allows the first void 403 formed between adjacent barrier blocks 47a and the second void 431 located between adjacent contact holes 43 to be offset in the first horizontal direction X when the barrier portion 471 is not a single integrated structure but includes multiple barrier blocks that are separated from each other. This prevents the first void 403 and the second void 431 from communicating during the expansion process, and prevents the second void 431 at different locations from communicating through the first void 403. Furthermore, it reduces signal crosstalk between different contact holes 43 caused by the filling of the void with a conductive medium. Additionally, by offsetting the areas in which the first void 403 and the second void 431 can be formed, some of the first void 403 separates and moves during the device manufacturing process, which is advantageous in preventing the appearance of voids in areas where the second void 431 did not originally exist. In some other embodiments, in a projection plane perpendicular to the vertical direction, a plurality of contact holes and a plurality of barrier blocks are arranged in alignment in a first horizontal direction, i.e., each contact hole has a corresponding barrier block, and the contact holes and the corresponding barrier blocks are aligned in the first horizontal direction. This is advantageous in avoiding the formation of a first void between the contact holes and the first or second part, and in avoiding the presence of the first void affecting the stress and support strength of the contact holes.

[0039] Figure 9 is a front view of the semiconductor structure. Referring to Figure 9, if the semiconductor structure includes a second conductive layer 53, but the second conductive layer 53 does not include a barrier portion, and the distance L1 between the second conductive layer 53 and the three-dimensional structure 50 is within the target range, then after filling with isolation layer material, a third void 503 may be formed between the second conductive layer 53 or the first conductive plug 52 and the three-dimensional structure 50. This third void 503 communicates with the first void 502 in the recess 501, forming a larger void, which may further affect the support strength of the device. Furthermore, in the semiconductor structure manufacturing process, even if the design distance between the second conductive layer 53 and the three-dimensional structure 50 is not within the target range, in the formation process of the three-dimensional structure 50, some of the etched portions 504 located between the second conductive layer 53 and the three-dimensional structure 50 are not effectively etched. Therefore, the minimum distance between the three-dimensional structure 50 and the adjacent structure is essentially the distance to the etched portions 504, and this distance may be smaller than the design distance and fall within the target range, causing the third void 503 to occur.

[0040] Figure 10 is a front view of a semiconductor structure according to some embodiments of the present application. Referring to Figure 10, the second conductive layer 67 includes a plurality of second signal lines (not shown), the lower conductive layer 61 transmits electrical signals to the contact holes 63 via the second signal lines, the second signal lines extend below at least a portion of the first portion 601, and the barrier portion 671 includes the portion to which the second signal lines extend below the first portion 601. The second conductive layer 67 does not have a layout that separates the signal transmission portion and the barrier portion 671, which is advantageous in simplifying the formation process of the second conductive layer 67 and at the same time increasing the deformation resistance capability of the barrier portion 671.

[0041] Figure 11 is a plan view corresponding to the semiconductor structure shown in Figure 10, according to some embodiments of the present application. Referring to Figure 11, the second conductive layer 67 further includes redundant lines 67b, which do not have contact holes 63, and the barrier portion 671 further includes the portion in which the redundant lines 67b extend below the first portion 601. The difference between the redundant line 67b and the second signal line 67a is that the second signal line 67a is connected to a contact hole 63 and used for transmitting electrical signals, whereas the redundant line 67b does not have a corresponding contact hole 63 and is not used for transmitting electrical signals. However, both the second signal line 67a and the redundant line 67b may be connected to the lower conductive layer via a first conductive plug, and both typically have the same width. The presence of the redundant line 67b may be a spare to replace a damaged second signal line, or it may be redundancy in the layout design to make the layout design applicable to different projects. It should be explained that any second signal line that is unable to perform its signal transmission function is considered a damaged second signal line, and this includes, but is not limited to, a second signal line that is disconnected from the signal transmission channel with the underlying conductive layer, or a second signal line whose resistance is too high to meet the design requirements, or a second signal line whose actual length and width are smaller than the design length and width.

[0042] Figure 12 is a plan view corresponding to the semiconductor structure shown in Figure 10, according to some embodiments of the present application. Referring to Figure 12, the second conductive layer 67 further includes dummy wiring 67c, the width of which is smaller than the width of the second signal line 67a. The dummy wiring 67c is used to equalize the density of conductive material in different regions of the second conductive layer 67, and the barrier portion 671 further includes the portion in which the second dummy wiring 67c extends below the first portion 601. In some embodiments, only dummy wiring 67c is provided and redundant lines 67b are not provided, or only redundant lines 67b are provided and dummy wiring 67c is not provided.

[0043] Furthermore, the "conductive material" mentioned above refers to the second signal line, or the second signal line and redundant lines, and differs depending on whether or not redundant lines are provided in the embodiment. The dummy wiring 67c can be used not only to equalize the density of conductive material in different regions of the second conductive layer 67, but also to increase the density of conductive material in a certain region. For example, in regions where the second signal line and redundant lines are not provided, the dummy wiring can be extended below at least a portion of the first part to realize the role of a barrier.

[0044] Figure 13 is a plan view of a semiconductor structure according to some embodiments of the present application. Referring to Figure 13, the barrier portion 705 surrounds the three-dimensional structure 70. The barrier portion 705 surrounding the three-dimensional structure 70 means that the barrier portion 705 is located on at least both sides of the three-dimensional structure 70, and "at least both sides" includes not only adjacent sides but also opposing sides. A barrier portion 705 located on any one side of the three-dimensional structure 70 may be a continuous, integral structure extending in the same direction as the corresponding portion of the three-dimensional structure 70, or it may be a separate structure including a plurality of barrier blocks or a portion including a plurality of second signal lines extending below a portion of the first portion 701. Furthermore, if the barrier portion 705 surrounds at least adjacent sides of the three-dimensional structure 70, the barrier portions 705 located on adjacent sides may be continuous, thus simplifying the manufacturing process of the barrier portion. Figure 13 shows an example in which the barrier portion 705 surrounds the three-dimensional structure 70 and includes at least a portion of the barrier portion 705 that extends below the first portion 701 of the plurality of second signal lines 703.

[0045] In some embodiments, referring to Figure 13, the three-dimensional structure 70 is an annular structure. Here, the three-dimensional structure 70 can surround the target structure 704, with the second part 702 surrounding the target structure 704. Furthermore, the three-dimensional structure 70 can also cover the top of the target structure 704. The three-dimensional structure 70 may be a functional structure that serves to shield or support the target structure 704, or it may be a substructure that realizes a specific function together with the target structure 704. In some embodiments, the target structure may be a memory capacitor, and the three-dimensional structure 70 is an upper electrode connected to the upper plate of the memory capacitor.

[0046] In some embodiments, the three-dimensional structure 70 is a capacitor electrode, and the capacitor electrode includes the upper electrode of a memory capacitor, or the upper or lower electrode of a non-memory capacitor. A memory capacitor refers to a capacitor connected to a memory transistor in a memory cell, and is generally used in dynamic random access memory, where the gate of the memory transistor is connected to the word line, the source is connected to the bit line, and the drain is connected to the memory capacitor.

[0047] This application further provides a method for manufacturing a semiconductor structure, referring to Figure 1, the method for manufacturing a semiconductor structure is a step of sequentially forming a lower conductive layer 21 and a barrier portion 22, wherein the plane on which the barrier portion 22 is located is above the plane on which the lower conductive layer 21 is located, and the projection of the barrier portion 22 and the lower conductive layer 21 in the vertical direction Z has an overlapping region 212, and a step of forming a three-dimensional structure 20, wherein the three-dimensional structure 20 includes a first portion 201 and a second portion 202, the top surface of the barrier portion 22 is higher than the bottom surface of the second portion 202 and lower than the bottom surface of the first portion 201 or is flush with the bottom surface of the first portion 201, and the first portion 201 is The method includes the steps of: positioning at least partially directly above the superimposed region 212; forming a first isolation layer 265, the first isolation layer 265 being used to fill the region above the lower conductive layer 21 and the barrier portion 22, the top surface of the first isolation layer 265 being higher than the top surface of the three-dimensional structure 20, the first isolation layer 265 being located on the side of the first portion 201 far from the second portion 202 and covering the side wall of the first portion 201; and forming a contact hole 23 and a first conductive layer 25, the contact hole 23 penetrating the first isolation layer 265, and the first conductive layer 25 being electrically connected to the lower conductive layer 21 via the contact hole 23.

[0048] It should be explained that sequentially forming the lower conductive layer 21 and the barrier portion 22 is merely limited to forming the lower conductive layer 21 before the barrier portion 22. Other process steps, such as forming various isolation layers, may exist between the step of forming the lower conductive layer 21 and the step of forming the barrier portion 22, and this application is not limited to such steps.

[0049] A person skilled in the art will understand that the embodiments described above are specific examples of realizing the present application, and that in actual application, various formal and detailed modifications can be made without departing from the spirit and scope of the present application. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present application, and therefore the scope of protection of the present application should be limited to the scope defined by the claims.

Claims

1. It is a semiconductor structure, It includes a lower conductive layer, a barrier portion, a three-dimensional structure, contact holes, a first conductive layer, and a first isolation layer. The plane on which the barrier portion is located is above the plane on which the lower conductive layer is located, and the vertical projections of the barrier portion and the lower conductive layer have an overlapping region. The three-dimensional structure comprises a first part and a second part, wherein the top surface of the barrier part is higher than the bottom surface of the second part and lower than the bottom surface of the first part, or is flush with the bottom surface of the first part, and the first part is at least partially located directly above the overlapping region. The plane on which the first conductive layer is located is higher than the top surface of the three-dimensional structure, the contact holes are directly connected to the first conductive layer, the lower conductive layer is electrically connected to the first conductive layer via the contact holes, and the contact holes are located on the side of the first part that is farther from the second part. The first isolation layer is a semiconductor structure used to fill the region between the contact holes and the three-dimensional structure, and the region between different contact holes.

2. The present invention further includes a second conductive layer, the barrier portion being part of the second conductive layer, the lower conductive layer being electrically connected to the second conductive layer via a first conductive plug, and the second conductive layer being electrically connected to the first conductive layer via a contact hole. The semiconductor structure according to claim 1.

3. The second conductive layer further includes a signal transmission section, the signal transmission section is separated from the barrier section, the barrier section is located between the signal transmission section and the second section, and the lower conductive layer is electrically connected to the contact hole via the signal transmission section. The semiconductor structure according to claim 2.

4. The aforementioned vertical direction is perpendicular to the first horizontal direction, and the semiconductor structure further includes a plurality of contact holes arranged along the first horizontal direction and a barrier portion extending along the first horizontal direction, wherein each contact hole is electrically connected to the lower conductive layer via a corresponding second signal line in the signal transmission section, and the barrier portion is located between the second signal line corresponding to any of the contact holes and the second portion. The semiconductor structure according to claim 3.

5. The aforementioned vertical direction is perpendicular to the first horizontal direction and the second horizontal direction, the first horizontal direction is perpendicular to the second horizontal direction, the semiconductor structure further includes a plurality of contact holes arranged along the first horizontal direction, the barrier portion includes a plurality of barrier blocks arranged along the first horizontal direction, and in a projection plane perpendicular to the vertical direction, the plurality of contact holes and the plurality of barrier blocks are alternately arranged in the first horizontal direction and offset in the second horizontal direction. The semiconductor structure according to claim 3.

6. The second conductive layer includes a plurality of second signal lines, the lower conductive layer transmits electrical signals to the contact holes via the second signal lines, the second signal lines extend below at least a portion of the first part, and the barrier portion includes the portion to which the second signal lines extend below the first part. The semiconductor structure according to claim 3.

7. The second conductive layer further includes redundant wires, the redundant wires are not provided with the contact holes, and the barrier portion further includes a portion in which the redundant wires extend below the first portion. The semiconductor structure according to claim 6.

8. The second conductive layer further includes a second dummy wiring, the width of which is smaller than the width of the second signal line, the second dummy wiring is used to equalize the conductive material density in different regions of the second conductive layer, and the barrier portion further includes a portion in which the second dummy wiring extends below the first portion. The semiconductor structure according to claim 6 or 7.

9. The barrier portion surrounds the three-dimensional structure. The semiconductor structure according to claim 1.

10. The three-dimensional structure is a capacitor electrode, and the capacitor electrode includes the upper electrode of a memory capacitor, or the upper or lower electrode of a non-memory capacitor. The semiconductor structure according to claim 1.

11. A method for manufacturing a semiconductor structure, A step of sequentially forming a lower conductive layer and a barrier portion, wherein the plane on which the barrier portion is located is above the plane on which the lower conductive layer is located, and the vertical projection of the barrier portion and the lower conductive layer has an overlapping region. A step of forming a three-dimensional structure, wherein the three-dimensional structure includes a first part and a second part, the top surface of the barrier part is higher than the bottom surface of the second part and lower than the bottom surface of the first part or is flush with the bottom surface of the first part, and the first part is at least partially located directly above the overlapping region, A step of forming a first isolation layer, wherein the first isolation layer is used to fill the area above the lower conductive layer and the barrier portion, the top surface of the first isolation layer is higher than the top surface of the three-dimensional structure, the first isolation layer is located on the side of the first portion that is farther from the second portion, and covers the side wall of the first portion. The process includes the step of forming a contact hole and a first conductive layer, wherein the contact hole penetrates the first isolation layer and the first conductive layer is electrically connected to the underlying conductive layer through the contact hole. A method for manufacturing semiconductor structures.

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