Waveform recognition mixed signal measurement system for reducing bus traffic in system-on-chip devices

Abstract

A method implemented by a processor for managing system-on-a-chip (SoC) bus traffic includes receiving a mixed signal in a computing device including the SoC. One or more polarity changes in the slope of the waveform corresponding to the mixed signal are detected. One or more analog-to-digital converters (ADCs), or portions of the SoC bus traffic related to ADC operation, are selectively disabled between one or more polarity changes in the waveform slope.

Description

Technical Field

[0001] (Cross-Reference to Related Application)

[0001] This application claims priority to U.S. Patent Application No. 18 / 464,136, entitled "WAVEFORM-AWARE MIXED SIGNAL MEASUREMENT SYSTEM FOR BUS TRAFFIC REDUCTION IN SYSTEM-ON-A-CHIP DEVICES," filed on September 8, 2023, the disclosure of which is hereby expressly incorporated herein by reference in its entirety. Background Art

[0002]

[0002] Aspects of the present disclosure relate to computing devices, and more specifically to power optimization and waveform-aware mixed signal measurement systems for bus traffic reduction in system-on-chip (SoC) devices.

[0003]

[0003] Mobile or portable computing devices include cellular phones, laptop, palmtop and tablet computers, portable digital assistants (PDAs), portable game consoles, and other portable electronic devices. Mobile computing devices are formed of many electrical components that consume power and generate heat. Components (or computing devices) may include, among others, system-on-chip (SoC) devices, graphics processing unit (GPU) devices, neural processing unit (NPU) devices, digital signal processors (DSPs), and modems.

[0004]

[0004] Measuring and monitoring power and thermal conditions for mobile computing devices and in automotive applications is important to mitigate safety issues. Power, thermal, and sensor parameters of SoC devices can be periodically monitored on-chip and off-chip for auxiliary chipsets. However, such measurements and monitoring can result in significant sparsity in data acquisition, as well as additional traffic on the SoC bus and thermal and power dissipation, which can impair SoC performance. [Overview of the Initiative]

[0005]

[0005] In some aspects of the present disclosure, a method implemented by a processor includes receiving a mixed signal in a computing device including a system-on-a-chip (SoC). The method implemented by a processor further includes detecting one or more polarity changes in the slope of a waveform corresponding to the mixed signal. The method implemented by a processor also includes selectively disabling one or more of an analog-to-digital converter (ADC) or at least a portion of SoC bus traffic related to ADC operation between one or more polarity changes in the slope of the waveform.

[0006]

[0006] Various aspects of the present disclosure relate to devices including means for receiving mixed signals in a computing device including a system-on-a-chip (SoC). The devices further include means for detecting one or more polarity changes in the slope of a waveform corresponding to the mixed signal. The devices further include means for selectively disabling one or more of an analog-to-digital converter (ADC) or at least a portion of SoC bus traffic associated with ADC operation between one or more polarity changes in the slope of the waveform.

[0007]

[0007] In some aspects of the present disclosure, a non-temporary computer-readable medium recording non-temporary program code is disclosed. The program code is executed by a processor and includes program code for receiving mixed signals in a computing device including a system-on-a-chip (SoC). The program code also includes program code for detecting one or more polarity changes in the slope of a waveform corresponding to the mixed signal. The program code further includes program code for selectively disabling one or more analog-to-digital converters (ADCs) or at least a portion of SoC bus traffic related to ADC operation between one or more polarity changes in the slope of the waveform.

[0008]

[0008] Various aspects of the present disclosure relate to systems for mixed signal management. The system includes a detection device for detecting one or more polarity changes of the slope of waveforms corresponding to one or more mixed signals in a computing device including a system-on-a-chip (SoC). The system also includes a mixed signal controller for controlling SoC bus traffic or an analog-to-digital converter (ADC) based on one or more polarity changes of the slope of waveforms corresponding to one or more mixed signals.

[0009]

[0009] The above provides a fairly broad overview of the features and technical advantages of the present disclosure so that the following "Modes for Carrying Out the Invention" may be better understood. Additional features and advantages of the present disclosure will be described below. It should be understood by those skilled in the art that the present disclosure can be readily used as a basis for modifying or designing other structures to accomplish the same objectives of the present disclosure. It should also be recognized by those skilled in the art that such equivalent structures do not deviate from the teachings of the present disclosure as described in the appended claims. Novel features that are considered unique to the present disclosure will be better understood, along with further objectives and advantages, with respect to both their organization and method of operation, by examining the following descriptions in relation to the appended drawings. However, it should be clearly understood that each of the drawings is provided for illustrative and explanatory purposes only and is not intended to define the limits of the present disclosure. [Brief explanation of the drawing]

[0010]

[0010] For a more complete understanding of this disclosure, the following description will be referenced together with the attached drawings.

[0011] [Figure 1]

[0011] An exemplary implementation of a host system-on-chip (SoC) including a mixed signal waveform recognition measurement system according to a particular aspect of the present disclosure is illustrated. [Figure 2]

[0012] This is a block diagram illustrating an exemplary computing system according to various aspects of the present disclosure. [Figure 3A]

[0013] This is a block diagram illustrating peak and dip monitors (PDMs) of mixed signals according to various aspects of the present disclosure. [Figure 3B]

[0014] This graph illustrates exemplary waveforms of the power supply voltage Vdd according to various aspects of this disclosure. [Figure 3C]

[0015] This figure illustrates exemplary architectures of peak and dip monitors (PDMs) according to various aspects of the present disclosure. [Figure 4]

[0016] This block diagram illustrates an exemplary system for reducing bus traffic, including the PDM shown in Figure 3A, according to various aspects of the present disclosure. [Figure 5]

[0017] This block diagram illustrates an exemplary system for reducing bus traffic, including the PDM shown in Figure 3A, according to various aspects of the present disclosure. [Figure 6]

[0018] This block diagram illustrates an exemplary system for reducing bus traffic, including the PDM shown in Figure 3A, according to various aspects of the present disclosure. [Figure 7]

[0019] This flowchart illustrates an exemplary process, for example, one performed by a waveform recognition mixed signal measurement processor for bus traffic reduction, according to various aspects of the present disclosure. [Figure 8]

[0020] This block diagram shows an exemplary wireless communication system that may favorably adopt one configuration of the present disclosure. [Figure 9]

[0021] This is a block diagram illustrating a design workstation used for circuit design, layout design, and logic design of components according to various aspects of the present disclosure. [Modes for carrying out the invention]

[0012]

[0022] The embodiments for carrying out the invention described below with respect to the attached drawings illustrate various configurations and do not represent the only configuration in which the described concepts can be put into practice. The embodiments for carrying out the invention include specific details intended to provide a complete understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be put into practice without these specific details. In some examples, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0013]

[0023] As explained, the use of the terms “and / or” is intended to mean “inclusive or,” and the use of the term “or” is intended to mean “exclusive or.” As explained, the term “exemplary” as used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be interpreted as being preferable or advantageous to other exemplary configurations. As explained, the term “connected” as used throughout this description means “connected electrically, mechanically, or otherwise, whether direct or indirectly through intervening connections (e.g., switches),” and is not necessarily limited to physical connections. Furthermore, such connections may result in the objects being permanently connected or disconnectably connected. Such connections may be via switches. As explained, the term “proximity” as used throughout this description means “adjacent, very close, adjacent, or near.” As explained, the term “on” as used throughout this description means “directly on” in some configurations and “indirectly on” in others.

[0014]

[0024] As described, measuring and monitoring power and thermal conditions for mobile computing devices and in automotive applications is important to reduce safety issues. The power, thermal, and sensor parameters of an SoC device can be periodically monitored on-chip and off-chip for an auxiliary chipset. For example, digital power meters, current sensors, housekeeping analog-to-digital converters (ADCs), as well as other sensors and monitoring devices, can be employed with SoCs, application-specific integrated circuits (ASICs), or related power management integrated circuit (PMIC) devices.

[0015]

[0025] A single ADC can be used with a multiplexor (MUX) to periodically sample and monitor internal on-chip current and voltage sensor outputs as well as off-chip parameters. The ADC uses the MUX to periodically sample multiple inputs in different time slots. However, sporadically high activity for supply rails can be difficult for a single ADC to manage.

[0016]

[0026] In automotive applications, SoC bus traffic may further increase for safety and SoC power measurement purposes. For example, automotive integrated circuits (ICs) can have extensive testing and safety features such as error correction and triple module redundancy. Furthermore, automotive ICs may include real-time monitoring of regulator output voltage, current, and temperature, as well as built-in self-tests (BISTs) for watchdog timers, frequency monitors, and various subsystems for power-on or other safety checks.

[0017]

[0027] Conventional approaches to addressing sporadic activity may involve increasing the clock frequency. However, increasing the clock frequency significantly increases power and heat dissipation on the SoC bus and can constrain ADC specifications.

[0018]

[0028] Furthermore, when a sensor is in an idle state, periodic sampling may result in inefficiency, and may lead to great sparsity in data collection as well as additional traffic. That is, the ADC may inefficiently oversample some idle sensor parameters, creating extra or redundant traffic, and may also result in increased power dissipation for data transfer between advanced driver assistance system (ADAS) devices and edge / cloud systems.

[0019]

[0029] Accordingly, aspects of the present disclosure are directed to an intelligent data acquisition and measurement system for an SoC and associated subsystems. In various aspects, a waveform recognition mixed-signal measurement system is provided. Changes in mixed-signal waveforms can be monitored and utilized to adjust SoC bus traffic.

[0020]

[0030] Certain aspects of the subject matter described in the present disclosure can be implemented to achieve one or more of the following potential advantages. In some examples, the described techniques can enable SoC bus traffic reduction, as well as reduction of heat and power dissipation.

[0021]

[0031] Figure 1 illustrates exemplary implementations of a host system-on-chip (SoC) 100 including a mixed-signal waveform recognition and measurement system according to various aspects of the present disclosure. The host SoC 100 includes processing blocks tailored to specific functions, such as a connectivity block 110. The connectivity block 110 may include fifth-generation (5G) connectivity, fourth-generation long-term evolution (4G LTE) connectivity, Wi-Fi connectivity, universal serial bus (USB) connectivity, Bluetooth® connectivity, Secure Digital (SD) connectivity, and the like.

[0022]

[0032] In this configuration, the host SoC 100 includes various processing units that support multithreaded operation. In the configuration shown in Figure 1, the host SoC 100 includes a multicore central processing unit (CPU) 102, a graphics processor unit (GPU) 104, a digital signal processor (DSP) 106, and a neural processor unit (NPU) 108. The host SoC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, a navigation module 120 which may include a global positioning system (GPS), and memory 118. The multicore CPU 102, GPU 104, DSP 106, NPU 108, and multimedia engine 112 support various functions such as video, audio, graphics, gaming, and artificial networking. Each processor core of the multicore CPU 102 could be a reduced instruction set computing (RISC) machine, an advanced RISC machine (ARM), a microprocessor, or some other type of processor. The NPU 108 could be based on the ARM instruction set.

[0023]

[0033] Figure 2 is a block diagram illustrating an exemplary computing system 200 according to various aspects of the present disclosure. As shown in Figure 2, the exemplary computing system 200 may include a host SoC 202. The host SoC 202 may include components and functions similar to those of SoC 100 (Figure). As shown in Figure 2, the host SoC 202 includes interface circuits 204a-b and an ADC 206. The interface circuits 204a-b may provide connectivity to one or more power management integrated circuits (PMICs) 214a-b. In addition, the interface circuits may provide connectivity to one or more external chipsets 210a-z and external sensors or auxiliary integrated circuit devices 220a-z. In some embodiments, the external chipsets 210a-z may include, for example, one or more additional processors such as external GPUs 210, or one or more wireless communication devices that can facilitate communication such as 5G, 6G, vehicle-to-everything communication (V2X), and wireless local area networks (WLAN). Furthermore, in various embodiments, the external chipsets 210a-z may be related to, for example, vehicle control and safety systems.

[0024]

[0034] Sensor / auxiliary IC devices 220a~z can supply power to sensors (e.g., digital power meters), thermal sensors, current sensors, voltage sensors, and transmit power level sensors.

[0025]

[0035] The SoC202 may include a single ADC206. The ADC206 may periodically sample and monitor mixed signals, such as internal on-chip current and voltage sensor outputs. Furthermore, the ADC206 may periodically sample and monitor off-chip parameters, such as sensor output parameters associated with sensor / auxiliary IC devices 220a-z. In one example, the ADC206 may receive analog voltage signals from a power supply (e.g., PMIC214a-b) (e.g., via interface circuit 204a). The ADC206 may digitally encode the analog signals to convert the analog voltage signals into digital outputs. The ADC206 may include both analog and digital circuits and can therefore be considered a mixed-signal integrated circuit. In some embodiments, the ADC206 may also convert other analog signals supplied to the computing system 200 into digital outputs. For example, the ADC206 can convert analog signals from sensors such as temperature sensors, light sensors, sonar signals, video signals, and gyroscope sensors (e.g., 114 or sensor / auxiliary IC devices 220a-z in Figure 1).

[0026]

[0036] The ADC206 can distribute its digital output to the digital components of the computing system 200 using bus transfer protocols such as the Advanced Microcontroller Bus Architecture (AMBA) or the Advanced High-Performance Bus (AHB) protocol. Therefore, when the ADC206 performs operations to convert analog signals to digital outputs and distributes those outputs to other components of the computing system 200, it can contribute to the bus traffic for the SoC100.

[0027]

[0037] Figure 3A is a block diagram illustrating a mixed signal peak and dip monitor (PDM) 300 according to various aspects of the present disclosure. Referring to Figure 3A, the PDM 300 may be coupled to an ADC 302, a host SoC (e.g., 100 or 202), and a power supply voltage Vdd. The ADC 302 has a configuration similar to that of the ADC 206 in Figure 2 and may function in a similar manner to that of the ADC 206.

[0028]

[0038] The PDM300 can monitor the power supply voltage Vdd (or other mixed signals). For example, the PDM300 can monitor the power supply voltage for voltage drops or overshoot conditions. Periodic signaling by the ADC302 (e.g., power conversion and related signals) can burden the memory and / or result in high power consumption.

[0029]

[0039] In various aspects of this disclosure, the PDM300 may periodically or aperiodicly monitor the power supply voltage Vdd or other mixed signals. The PDM300 may monitor the polarity of the slope of the waveform of the power supply voltage Vdd. The PDM300 may send signals to the ADC302 to trigger the ADC302 to control signaling based on the timing of peaks and dips in the power supply voltage waveform, rather than allowing repetitive signaling by the ADC302 as a result of voltage transitions. For example, a PDM300 signal may trigger the ADC302 to stop analog-to-digital conversion operations associated with the monitored waveform (e.g., the power supply voltage signal). Furthermore, in various aspects, a PDM300 signal may trigger the ADC302 to reduce, and in some aspects to stop, downstream bus traffic associated with the monitored waveform.

[0030]

[0040] While the example in Figure 3A illustrates monitoring in relation to a power supply voltage Vdd, the disclosure is not limited in this way, and the PDM 300 may monitor any other mixed signal. Furthermore, although Figure 3A includes one PDM 300, it should be understood that multiple PDMs may also be included in a computing system (e.g., 200). For example, multiple PDMs (e.g., 300) may each monitor different mixed signals and / or sensor parameters of a computing system (e.g., 200) and manage the associated ADC operation or bus traffic of the monitored mixed signals.

[0031]

[0041] Figure 3B is a graph illustrating exemplary waveforms 350 of a power supply voltage Vdd according to various embodiments of the present disclosure. As shown in Figure 3B, the waveform 350 of the power supply voltage Vdd may be a non-periodic signal with numerous changes in the polarity of the slope. Points 352a-f may indicate changes in the polarity of the slope of the power supply voltage Vdd waveform 350. When the PDM 300 detects a change in the polarity of the slope, such as a peak (e.g., 352a, 352c, and 352e) or a dip (e.g., 352b, 352d, and 352f), the PDM 300 may signal the ADC 302 to enable the ADC 302 to perform power conversion and associated signaling. That is, the ADC 302 may, for example, receive the power supply voltage Vdd and perform power conversion for each device of the computing system (e.g., 200 in Figure 2). Otherwise, the PDM300 may instruct the ADC302 to skip such power conversion or associated signaling.

[0032]

[0042] Figure 3C illustrates exemplary architectures of a peak and dip monitor (PDM) 300 according to various aspects of the present disclosure. Referring to Figure 3C, the exemplary PDM 300 may include a multiplexer 372, a sample-and-hold circuit 374, a comparator 376, a D-flip-flop (DFF) 378, a delay circuit 380, and an exclusive-or (XOR) gate 382.

[0033]

[0043] The PDM300 can receive an input signal. The input signal may include a mixed signal. The mixed signal may include (but is not limited to) a power supply voltage signal (Vdd), a sensor signal (e.g., a current sensor, a temperature sensor), or other mixed signals. The sample-and-hold circuit 374 can sample the input signal, which may be a continuously fluctuating analog signal. The sample-and-hold circuit 374 may hold or fix the value of the input signal at a constant level over a predefined time period. For example, the input signal may include (but is not limited to) a power supply voltage Vdd. The sample-and-hold circuit 374 may sample the power supply voltage Vdd at times n-2 and n-1. The power supply voltage (Vdd) sampled at times n-2 and n-1 may be supplied to the comparator 376.

[0034]

[0044] Comparator 376 can compare the power supply voltages Vdd(n-2) and Vdd(n-1) at time n. Comparator 376 can generate an output indicating whether the power supply voltage Vdd(n-2) is greater than Vdd(n-1). If the power supply voltage Vdd(n-2) is less than Vdd(n-1), the peak of the power supply voltage Vdd waveform may not have been reached (for example, if both values ​​are positive). On the other hand, if the power supply voltage Vdd(n-2) is greater than Vdd(n-1), the peak of the power supply voltage Vdd waveform may have been reached (for example, if both values ​​are positive), and the polarity of the slope of the power supply voltage Vdd waveform may have changed.

[0035]

[0045] The output of comparator 376 can be supplied to DFF 378. Next, the DFF 378 delay circuit 380 and XOR gate 382 extract the peak-to-dip or dip-to-peak polarity change in the waveform of the input signal (e.g., Vdd). DFF 378 stores the output of comparator 376. The comparator output at time n can be supplied to the delay circuit 380 to generate a delayed output. The delayed comparator output (e.g., the comparator output at time n-1) and the current comparator output (e.g., the comparator output at time n) can be supplied to XOR gate 382.

[0036]

[0046] The XOR gate 382 may compare the current comparator output (e.g., the comparator output at time n) with a delayed comparator output (e.g., the comparator output at time n-1) to generate a trigger signal. For example, if the current comparator output (e.g., at time n) is different from the delayed comparator output (e.g., at time n-1), the XOR gate 382 may output 1 to indicate that the polarity of the slope of the waveform of the input signal (e.g., Vdd) has changed. On the other hand, if the current comparator output (e.g., at time n) is the same as the delayed comparator output (e.g., at time n-1), the XOR gate may output 0 to indicate that the polarity of the slope of the waveform of the input signal (e.g., Vdd) has not changed. The output of the XOR gate 382 may be a trigger signal to control the operation of an ADC (e.g., 302). For example, if the XOR gate 382 outputs 1, a trigger signal may be generated to activate the operation of the ADC (e.g., 302). Conversely, if the XOR gate 382 outputs 0, no trigger signal may be generated, and ADC (e.g., 302) operation or bus traffic related to the input signal may be disabled.

[0037]

[0047] Figure 4 is a block diagram illustrating an exemplary system 400 for bus traffic reduction, including the PDM 300 of Figure 3A, according to various aspects of the present disclosure. Referring to Figure 4, the PDM 300 may be coupled to the ADC 302 via multiplexers (MUXes) 402a and 402b. As described, the PDM 300 may monitor the power supply voltage Vdd for voltage drop or overshoot conditions, for example. However, by including MUXes 402a and 402b, the PDM 300 may be able to more narrowly adjust the restrictions on ADC conversion. That is, using MUXes 402a and 402b, the PDM 300 may selectively restrict ADC conversion and / or associated signaling to some blocks while allowing periodic signaling to other blocks. For example, the PDM 300 may beneficially allow such power conversion related to a particular automotive safety system during polarity changes, while restricting similar power conversion to other systems of a computing system (e.g., 200).

[0038]

[0048] Furthermore, as shown in the example in Figure 4, additional PDMs may be included to monitor other mixed signal inputs (e.g., sensor outputs, battery levels, temperature sensors, or current sensors). The outputs of such additional PDMs may be supplied to the MUX402b to trigger the operation of the ADC for the corresponding one of the respective mixed signal inputs.

[0039]

[0049] Figure 5 is a block diagram illustrating an exemplary system 500 for bus traffic reduction, including the PDM 300 of Figure 3A, according to various aspects of the present disclosure. The exemplary system 500 includes the elements shown in Figure 4. However, as shown in Figure 5, the exemplary system 500 for bus traffic reduction may further include delay elements 504a and 504b. The delay elements 504a and 504b may operate under the control of the PDM 300. For example, during periods between polarity changes, the PDM 300 may restrict (e.g., disable) the ADC 302 from performing certain power conversions. In addition, the PDM 300 may control the delay elements to disable the DFF 502 and driver 506 from sending relevant signals to the bus of the SoC 100, thereby reducing SoC bus traffic. Furthermore, the DFF 502 and delay elements 504 may synchronize data with the clock / enable (EN) to reduce and, in some aspects, eliminate glitches and improve ADC performance.

[0040]

[0050] Figure 6 is a block diagram illustrating an exemplary system 600 for bus traffic reduction, including the PDM 300 of Figure 3A, according to various embodiments of the present disclosure. The exemplary system 600 includes the elements shown in Figure 4. However, as shown in Figure 6, the exemplary system 600 for bus traffic reduction may further include a counter 602 and an interpolator 604. In some embodiments, the slope of the power waveform Vdd may be important for certain applications (e.g., automotive safety applications). To provide such information, the counter 602 may count the time period (e.g., clock cycles) between polarity changes. The counter 602 may be reset when a polarity change occurs. The count of the counter 602 may indicate the number of clock cycles between polarity changes (e.g., between peaks and dips). The count shown by the counter 602 may be used to calculate the slope of the waveform.

[0041]

[0051] Since an ADC can provide precise values ​​for peaks and / or subsequent dips by determining the count, the waveform between peaks and dips can be reconstructed linearly.

[0042]

[0052] Figure 7 is a flowchart illustrating an exemplary process 700 performed, for example, by a processor, according to various aspects of the present disclosure. An exemplary process 700 is an example of waveform recognition mixed signal measurement for bus traffic reduction.

[0043]

[0053] As shown in Figure 7, in block 702, the processor may receive mixed signals in a computing device including a system-on-a-chip (SoC). For example, as illustrated with reference to Figure 3C, the PDM300 may receive an input signal. The input signal may include a mixed signal. The mixed signal may include (but is not limited to) a power supply voltage signal (Vdd), a sensor signal (e.g., a current sensor, a temperature sensor), or other mixed signals.

[0044]

[0054] In block 704, the processor detects one or more polarity changes in the slope of the waveform corresponding to the mixed signal. For example, as illustrated with reference to Figure 3C, comparator 376 may compare the supply voltage Vdd(n-2) and Vdd(n-1) at time n. Comparator 376 may generate an output indicating whether the supply voltage Vdd(n-2) is greater than Vdd(n-1). The output of comparator 376 may be supplied to DFF 378. The DFF 378 delay circuit 380 and XOR gate 382 then extract polarity changes in the waveform of the input signal (e.g., Vdd), from peak to dip or from dip to peak.

[0045]

[0055] In block 706, the processor selectively disables one or more of the analog-to-digital converter (ADC) or at least a portion of the SoC bus traffic related to the operation of the ADC during one or more polarity changes in the slope of the waveform. For example, as illustrated with reference to Figure 3C, the comparator output at time n may be fed to a delay circuit 380 to generate a delayed output. The delayed comparator output (e.g., the comparator output at time n-1) and the current comparator output (e.g., the comparator output at time n) may be fed to an XOR gate 382. The XOR gate 382 may compare the current comparator output (e.g., the comparator output at time n) with the delayed comparator output (e.g., the comparator output at time n-1) to generate a trigger signal. If the XOR gate 382 outputs 1, a trigger signal may be generated to activate the operation of the ADC (e.g., 302). Conversely, if the XOR gate 382 outputs 0, no trigger signal may be generated, and ADC (e.g., 302) operation or bus traffic related to the input signal may be disabled.

[0046]

[0056] Figure 8 is a block diagram showing an exemplary wireless communication system 8 that may favorably adopt one aspect of the present disclosure. For illustrative purposes, Figure 8 shows three remote units 820, 830, and 850, and two base stations 840. It will be recognized that the wireless communication system may have more remote units and base stations. The remote units 820, 830, and 850 include integrated circuit (IC) devices 825A, 825B, and 825C, which include the disclosed bus traffic reduction system. It will be recognized that other devices, such as base stations, switching devices, and network equipment, may also include the disclosed bus traffic reduction system. Figure 8 shows a forward link signal 880 from base station 840 to remote units 820, 830, and 850, and a reverse link signal 890 from remote units 820, 830, and 850 to base station 840.

[0047]

[0057] In Figure 8, remote unit 820 is shown as a mobile phone, remote unit 830 as a portable computer, and remote unit 850 as a fixed-location remote unit in a wireless local loop system. For example, a remote unit may be a portable data unit such as a mobile phone, a handheld personal communication system (PCS) unit, or a personal information terminal; a fixed data unit such as a GPS-enabled device, a navigation device, a set-top box, a music player, a video player, an entertainment unit, or a meter reading device; or another device that stores or retrieves data or computer instructions, or a combination thereof. While Figure 8 illustrates remote units according to aspects of the present disclosure, the disclosure is not limited to these exemplary units. Aspects of the present disclosure can be suitably adopted in many devices, including the disclosed bus traffic reduction system.

[0048]

[0058] Figure 9 is a block diagram illustrating a design workstation 900 used for circuit design, layout design, and logic design of semiconductor components such as the PDM300 disclosed above. The design workstation 900 includes a hard disk 901 housing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 900 also includes a display 902 to facilitate the design of the circuit 910 or semiconductor component 912 such as the PDM300. A storage medium 904 is provided for tangibly storing the design of the circuit 910 or semiconductor component 912 (e.g., PDM300). The design of the circuit 910 or semiconductor component 912 may be stored on the storage medium 904 in a file format such as GDSII or GERBER. The storage medium 904 may be a CD-ROM, DVD, hard disk, flash memory, or other suitable device. Furthermore, the design workstation 900 includes a drive device 903 for receiving input from the storage medium 904 or writing output to the storage medium 904.

[0049]

[0059] The data recorded on the storage medium 904 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for continuous drawing tools such as electron beam lithography. The data may further include logic verification data, such as timing diagrams or net circuits associated with logic simulations. By providing data on the storage medium 904, the design of the circuit 910 or semiconductor component 912 is facilitated by reducing the number of processes required to design the semiconductor wafer.

[0050]

[0060] Implementation examples are provided in the following numbered clauses. Clause 1. A method implemented by the processor, Receiving mixed signals in a computing device including a system-on-a-chip (SoC), Detecting one or more polarity changes in the slope of the waveform corresponding to the mixed signal, A method implemented by a processor, comprising selectively disabling one or more of an analog-to-digital converter (ADC) or at least a portion of SoC bus traffic related to ADC operation during one or more polarity changes in the slope of a waveform. Clause 2. A method implemented by the processor described in Clause 1, further comprising enabling SoC bus traffic related to ADC operation when either a peak or a dip occurs in the waveform corresponding to the mixed signal. Clause 3. A method by which a mixed signal is implemented by the processor described in Clause 1 or 2, including a power signal, sensor signal, reference voltage signal, reference current signal, transmit power level, battery level, or SoC temperature. Clause 4. A method implemented by the processor described in any of Clauses 1 to 3, in which SoC bus traffic related to ADC operation is invalidated between one or more polarity changes in the waveform slope. Clause 5. A method implemented by a processor as described in any of Clauses 1 to 4, further comprising disabling analog-to-digital conversion for at least one device during one or more polarity changes in the slope of the waveform. Clause 6. A method implemented by a processor, as described in any of Clauses 1 to 5, implemented in an automotive application. Clause 7. A method implemented by a processor, as implemented in a mobile device, as described in any of Clauses 1 to 6. Clause 8. A system for mixed signal management, A detection device for detecting one or more polarity changes in the slope of a waveform corresponding to one or more mixed signals in a computing device including a system-on-a-chip (SoC), A system comprising: a mixed-signal controller for controlling SoC bus traffic or an analog-to-digital converter (ADC) based on one or more polarity changes of the slope of a waveform corresponding to one or more mixed signals. Clause 9. The system as described in Clause 8, wherein the mixed signal controller enables SoC bus traffic or ADC operation associated with one or more mixed signals when either a peak or a dip occurs in the waveform corresponding to the mixed signal. Clause 10. A system as described in Clause 8 or 9, in which the mixed signal includes a power signal, sensor signal, reference voltage signal, reference current signal, transmit power level, battery level, or SoC temperature. Clause 11. A system as described in any of Clauses 8 to 10, in which a mixed signal controller disables one or more SoC bus traffic associated with a mixed signal, or ADC operation associated with a mixed signal, during one or more polarity changes of the slope of the waveforms corresponding to one or more mixed signals. Clause 12. The system described in any of Clauses 8 to 11, further comprising disabling analog-to-digital conversion for at least one device during one or more polarity changes in the slope of the waveform. Clause 13. A system described in any of Clauses 8 to 12, implemented in an automotive application. Clause 14. A system described in any of Clauses 8-13, implemented on a mobile device. Clause 15. A device, A means for receiving mixed signals in a computing device including a system-on-a-chip (SoC), A means for determining whether the polarity of the slope of the waveform corresponding to the mixed signal has changed, An apparatus comprising means for selectively disabling one or more analog-to-digital converters (ADCs) or at least a portion of SoC bus traffic related to ADC operation during one or more changes in the polarity of the slope of a waveform. Clause 16. The apparatus according to Clause 15, further comprising means for enabling SoC bus traffic related to ADC operation when either a peak or a dip occurs in the waveform corresponding to a mixed signal. Clause 17. The apparatus described in Clause 15 or 16, in which the mixed signal includes a power signal, sensor signal, reference voltage signal, reference current signal, transmit power level, battery level, or SoC temperature. Clause 18. The apparatus according to any one of Clauses 15 to 17, further comprising means for disabling SoC bus traffic related to ADC operation during one or more changes in the polarity of the waveform slope. Clause 19. The apparatus according to any one of Clauses 15 to 18, further comprising means for disabling ADC operation for at least one device during one or more changes in the polarity of the slope of the waveform. Clause 20. Any device described in any of Clauses 15-19, which is included in automotive applications. Clause 21. A device described in any of Clauses 15-20, in which the device is included in a mobile device. Clause 22. A non-temporary computer-readable medium on which program code is recorded, wherein the program code is executed by a processor, Program code for receiving mixed signals in a computing device including a system-on-a-chip (SoC), Program code for detecting one or more polarity changes in the slope of a waveform corresponding to a mixed signal, A non-temporary computer-readable medium including program code for selectively disabling one or more analog-to-digital converters (ADCs) or at least a portion of SoC bus traffic related to ADC operation during one or more polarity changes in the slope of a waveform. Clause 23. A non-transient computer-readable medium as described in Clause 22, which includes program code for enabling SoC bus traffic related to ADC operation when either a peak or a dip occurs in the waveform corresponding to a mixed signal. Clause 24. Non-transient computer-readable media as described in Clause 22 or 23, in which the mixed signals include power signals, sensor signals, reference voltage signals, reference current signals, transmit power levels, battery levels, or SoC temperature. Clause 25. A non-transient computer-readable medium as described in any of Clauses 22 to 24, which includes program code for disabling SoC bus traffic related to ADC operation during one or more polarity changes in the slope of a waveform. Clause 26. A non-temporary computer-readable medium as described in any of Clauses 22 to 25, which includes program code for disabling analog-to-digital conversion for at least one device during one or more polarity changes in the slope of a waveform. Clause 27. A non-temporary computer-readable medium as described in any of Clauses 22-26, on which program code is implemented in an automotive application. Clause 28. Non-temporary computer-readable media as described in Clause 22, in which program code is implemented on a mobile device.

[0051]

[0061] In the case of firmware and / or software implementations, these methodologies may be implemented using modules (e.g., procedures, functions, etc.) that perform the described functions. When implementing the described methodologies, machine-readable media may be used to tangibly embody the instructions. For example, software code may be stored in memory and executed by a processor unit. Memory may be implemented inside or outside the processor unit. When used, the term “memory” refers to long-term memory, short-term memory, volatile memory, non-volatile memory, or other types of memory, and is not limited to a specific type of memory or number of memories, or the type of medium in which the memory is stored.

[0052]

[0062] When implemented in firmware and / or software, these functions may be stored as one or more instructions or codes on a computer-readable medium. Examples include computer-readable media encoded using data structures and computer-readable media encoded using computer programs. Computer-readable media include physical computer storage media. Storage media can be available media that can be accessed by a computer. Examples, but not limited to, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disc storage or other magnetic storage devices, or other media that can be used to store desired program code in the form of instructions or data structures and can be accessed by a computer. When used, "disk" and "disc" include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray® discs. A disk typically reproduces data magnetically, while a disc reproduces data optically using a laser. Any combination of these should also be included within the scope of computer-readable media.

[0053]

[0063] In addition to storage on computer-readable media, instructions and / or data may be provided as signals on a transmission medium contained within a communication device. For example, a communication device may include transceivers having signals representing instructions and data. These instructions and data are configured to cause one or more processors to implement the functions outlined in the claims.

[0054]

[0064] While the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made without departing from the technology of the present disclosure as defined by the appended claims. For example, correlated terms such as “up” and “down” are used with respect to a substrate or electronic device. Naturally, if the substrate or electronic device is inverted, up becomes down, and vice versa. Furthermore, if it is oriented sideways, up and down may refer to the sides of the substrate or electronic device. Moreover, the scope of the present disclosure is not intended to be limited to any specific configuration of the processes, machines, manufactures, compositions, means, methods, and steps described herein. It will be readily apparent to those skilled in the art that existing or subsequently developed processes, machines, manufactures, compositions, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding configurations described herein can be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include such processes, machines, manufactures, compositions, means, methods, or steps within their scope.

[0055]

[0065] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in connection with this disclosure can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this hardware-software compatibility, various illustrative components, blocks, modules, circuits, and steps have been outlined above in relation to their functions. Whether such functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functions in various ways for each specific application, but such decisions should not be construed as causing a departure from the scope of this disclosure.

[0056]

[0066] The various illustrative logic blocks, modules, and circuits described in connection with this disclosure may be implemented or carried out using general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, individual gate logic or transistor logic, individual hardware components, or any combination thereof, designed to perform the functions described. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration.

[0057]

[0067] Steps of the methods or algorithms described in this disclosure may be embodied directly in hardware, in software modules executed by a processor, or in a combination of the two. The software modules may reside in RAM, flash memory, ROM, erasable programmable read-only memory (EPROM), EEPROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. Alternatively, the processor and storage medium may reside in the user terminal as separate components.

[0058]

[0068] The preceding explanation of this disclosure is provided so that any person skilled in the art can create or use this disclosure. Various modifications to this disclosure will be readily apparent to a person skilled in the art, and the general principles defined may be applied to other variations without departing from the spirit or scope of this disclosure. Accordingly, this disclosure should be given the broadest scope that is consistent with the disclosed principles and novel features, and is not limited to the examples and designs described.

Claims

1. A method implemented by the processor, Receiving mixed signals in a computing device including a system-on-a-chip (SoC), To detect one or more polarity changes in the slope of the waveform corresponding to the mixed signal, A method implemented by a processor, comprising selectively disabling one or more of an analog-to-digital converter (ADC) or at least a portion of SoC bus traffic related to ADC operation during one or more polarity changes in the slope of the waveform.

2. A method implemented by the processor according to claim 1, further comprising enabling the SoC bus traffic related to the ADC operation when either a peak or a dip occurs in the waveform corresponding to the mixed signal.

3. A method implemented by the processor according to claim 1, wherein the mixed signal includes a power supply signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or SoC temperature.

4. A method implemented by the processor according to claim 1, wherein the SoC bus traffic related to the ADC operation is disabled between the one or more polarity changes in the slope of the waveform.

5. A method implemented by the processor according to claim 1, further comprising disabling analog-to-digital conversion for at least one device between the one or more polarity changes in the slope of the waveform.

6. The method implemented by the processor according to claim 1, wherein the method implemented by the processor is implemented in an automotive application.

7. The method implemented by the processor according to claim 1, wherein the method implemented by the processor is implemented in a mobile device.

8. A system for managing mixed signals, A detection device for detecting one or more polarity changes in the slope of a waveform corresponding to one or more mixed signals in a computing device including a system-on-a-chip (SoC), A system comprising: a mixed signal controller for controlling SoC bus traffic or an analog-to-digital converter (ADC) based on the one or more polarity changes of the slope of the waveform corresponding to one or more mixed signals.

9. The system according to claim 8, wherein the mixed signal controller enables the SoC bus traffic or ADC operation associated with one or more mixed signals when either a peak or a dip occurs in the waveform corresponding to the mixed signal.

10. The system according to claim 8, wherein the mixed signal includes a power supply signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or SoC temperature.

11. The system according to claim 8, wherein the mixed signal controller disables one or more of the SoC bus traffic or ADC operations related to the mixed signal during one or more polarity changes of the slope of the waveform corresponding to the one or more mixed signals.

12. The system according to claim 8, further comprising disabling analog-to-digital conversion for at least one device during the one or more polarity changes in the slope of the waveform.

13. The system according to claim 8, which is implemented in automotive applications.

14. The system according to claim 8, implemented in a mobile device.

15. It is a device, Means for receiving mixed signals in a computing device including a system-on-a-chip (SoC), Means for determining whether the polarity of the slope of the waveform corresponding to the mixed signal has changed, An apparatus comprising means for selectively disabling one or more analog-to-digital converters (ADCs) or at least a portion of SoC bus traffic related to ADC operation, between one or more changes in the polarity of the slope of the waveform.

16. The apparatus according to claim 15, further comprising means for activating the SoC bus traffic related to the ADC operation when either a peak or a dip occurs in the waveform corresponding to the mixed signal.

17. The apparatus according to claim 15, wherein the mixed signal includes a power supply signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or SoC temperature.

18. The apparatus according to claim 15, further comprising means for disabling the SoC bus traffic related to the ADC operation between the one or more changes in the polarity of the slope of the waveform.

19. The apparatus according to claim 15, further comprising means for disabling ADC operation for at least one device between the one or more changes in the polarity of the slope of the waveform.

20. The apparatus according to claim 15, wherein the apparatus is included in automotive applications.

21. The apparatus according to claim 15, wherein the apparatus is included in a mobile device.

22. A non-temporary computer-readable medium on which program code is recorded, wherein the program code is executed by a processor, and Program code for receiving mixed signals in a computing device including a system-on-a-chip (SoC), A program code for detecting one or more polarity changes in the slope of the waveform corresponding to the mixed signal, A non-temporary computer-readable medium including program code for selectively disabling one or more analog-to-digital converters (ADCs) or at least a portion of SoC bus traffic related to ADC operation, between one or more polarity changes in the slope of the waveform.

23. The non-temporary computer-readable medium according to claim 22, wherein the program code includes program code for enabling the SoC bus traffic related to the ADC operation when either a peak or a dip occurs in the waveform corresponding to the mixed signal.

24. The non-temporary computer-readable medium according to claim 22, wherein the mixed signal includes a power signal, a sensor signal, a reference voltage signal, a reference current signal, a transmit power level, a battery level, or SoC temperature.

25. The non-temporary computer-readable medium according to claim 22, wherein the program code includes program code for disabling the SoC bus traffic related to the ADC operation between the one or more polarity changes in the slope of the waveform.

26. The non-temporary computer-readable medium according to claim 22, wherein the program code includes program code for disabling analog-to-digital conversion for at least one device during the one or more polarity changes in the slope of the waveform.

27. The non-temporary computer-readable medium according to claim 22, wherein the program code is implemented in an automotive application.

28. The non-temporary computer-readable medium according to claim 22, wherein the program code is implemented on a mobile device.

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