High aspect ratio IN-SITU etching using redeposited helmet masks

Abstract

A method is provided for etching features in a stack beneath a patterned mask. The stack is partially etched through the patterned mask. A helmet mask is deposited on the patterned mask by providing at least one cycle of pre-treating the surface of the patterned mask and selectively depositing a metal-containing helmet layer on the surface of the patterned mask after the pre-treating surface of the patterned mask. The stack is etched through the helmet mask.

Description

[Technical Field]

[0001] Cross-Reference to Related Applications This application claims the benefit of priority from U.S. Patent Application No. 63 / 581,521, filed on September 8, 2023, which is incorporated herein by reference for all purposes.

[0002] The present disclosure relates to a method for forming semiconductor devices on a semiconductor wafer. [Background Art]

[0003] When forming semiconductor devices, etching layers may be etched to form memory holes or lines, or other semiconductor features. Some semiconductor devices may be formed, for example, by etching a single stack of silicon dioxide, also known as silicon oxide (SiO2), to form capacitors in dynamic access random memory (DRAM). Other semiconductor devices may be formed by etching a two-layer stack of alternating silicon dioxide (oxide) and silicon nitride (nitride) (ONON), or a two-layer stack of alternating silicon dioxide and polysilicon (OPOP). Other stacks of alternating layers may also be etched. Some of the alternating layer stacks may have one of several alternating layers that are silicon oxide. Some of the alternating layers may be three alternating layers. Such stacks may be used in memory applications and three-dimensional "not and" gates (3D NAND). These stacks tend to require relatively high aspect ratio (HAR) etching of the dielectric. For high aspect ratio etching, desirable etching characteristics include high etching selectivity for masks (such as amorphous carbon masks), low sidewall etching including linear profiles, and high etching rates on the etching surfaces. Some high aspect ratio etchings result in tapered features that are much wider at the top than at the bottom. Such features can increase device failure or limit device density, device performance, and device depth.

[0004] The background art descriptions provided herein are intended to provide a general context for this disclosure. The information contained in this background art section, as well as any aspects of the descriptions that may not be recognized as prior art at the time of filing, are not expressly or implicitly recognized as prior art to this disclosure. [Overview of the project]

[0005] To achieve the above, a method for etching features in a stack beneath a patterned mask is provided in accordance with the purposes of this disclosure. The stack is partially etched via the patterned mask. The helmet mask is deposited on top of the patterned mask by providing at least one cycle of pre-treating the surface of the patterned mask and selectively depositing a metal-containing helmet layer on the surface of the patterned mask after pre-treating the surface of the patterned mask. The stack is etched via the helmet mask.

[0006] In another embodiment, an apparatus for etching features in a stack is provided. A process chamber is provided. A substrate support supports a substrate in the process chamber. A power supply provides power to the process chamber. A gas source is fluidly connected to the process chamber and includes an etching gas source, a pretreatment gas source, and a deposition gas source. A controller is controllably connected to the power supply and the gas sources and is configured to etch features in the stack below a patterned mask by a process comprising: a) partially etching the stack via a patterned mask using an etching gas from an etching gas source; and depositing a helmet mask on the patterned mask, comprising at least one cycle of a) pretreatment of the surface of the patterned mask using a pretreatment gas from a pretreatment gas source, and after pretreatment of the surface of the patterned mask, selectively depositing a metal-containing helmet layer on the surface of the patterned mask using a deposition gas from a deposition gas source; and etching the stack via the helmet mask using an etching gas from an etching gas source.

[0007] These and other features of this disclosure will be described in more detail in the following detailed description, in conjunction with the following drawings.

[0008] This disclosure is shown as an example, not as an limitation, in the figures of the attached drawings, where similar reference numbers refer to similar elements. [Brief explanation of the drawing]

[0009] [Figure 1] This is a high-level flowchart of the process used in several embodiments. [Figure 2A] This is a schematic cross-sectional view of a stack processed according to several embodiments. [Figure 2B] This is a schematic cross-sectional view of a stack processed according to several embodiments. [Figure 2C] This is a schematic cross-sectional view of a stack processed according to several embodiments. [Figure 2D] This is a schematic cross-sectional view of a stack processed according to several embodiments. [Figure 2E] This is a schematic cross-sectional view of a stack processed according to several embodiments. [Figure 3] This is a schematic diagram of an etching chamber that may be used in several embodiments. [Figure 4] This is a schematic diagram of a computer system that may be used when implementing some embodiments. [Modes for carrying out the invention]

[0010] In drawings, similar reference numbers may be used to indicate similar structural elements. Please understand that the depictions in the drawings are approximate and not to scale.

[0011] This disclosure is described in detail with reference to several preferred embodiments thereof, as shown in the accompanying drawings. Numerous specific details are included in the following description to provide a complete understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be carried out without some or all of these specific details. In other examples, well-known process steps and / or structures are not described in detail so as not to unnecessarily obscure this disclosure.

[0012] Dry development of high aspect ratio contacts requires precise control of the sidewall taper angle. Various methods have been attempted to limit the difference in lateral limit dimension (CD) between the top and bottom of the etched structure. With the recent development of DRAM memory with higher aspect ratio features in smaller sizes, or 3D NAND memory with thicker structures that have an increased number of ONON or OPOP bilayer structures, the demand for precise control of the top and bottom shapes has become particularly high. If the profile (difference between top and bottom CD) increases, it poses a risk to subsequent steps in device manufacturing and affects device performance. With current technology, reactive ion etching of high aspect ratio structures relies on sidewall deposition to protect against lateral erosion of the CD. Maintaining a delicate balance between etching and sidewall deposition is particularly difficult with high aspect ratio features. As a result, high aspect ratio dry development is limited to thinner structures and requires considerably more complex development to enable etching of thicker stacks.

[0013] The embodiments described herein provide an in-situ process for providing deeper etched high aspect ratio features within a stack, where the width of the feature near the top is approximately equal to the width of the feature near the bottom. For ease of understanding, Figure 1 is a high-level flowchart which may be used in some embodiments. A stack is provided within a process chamber or etching chamber (step 104). In some embodiments, the stack is placed on a substrate support within the process chamber.

[0014] Figure 2A is a schematic cross-sectional view of a stack 204, which may be etched in some embodiments. In some embodiments, the stack 204 comprises a substrate 208 beneath a plurality of double layers 212 arranged beneath a patterning mask 216. In some embodiments, one or more layers may be arranged between the substrate 208 and the plurality of double layers 212 and / or between the plurality of double layers 212 and the patterning mask 216. In some embodiments, the patterning mask 216 is a metal or semimetallic mask. In some embodiments, plasma-enhanced physical vapor deposition (PECVD) is used to deposit a metal-containing dielectric film, which may be used as a mask. A method for depositing a tungsten carbide film using PECVD is described in U.S. Patent No. 9,875,890, published January 23, 2018, entitled “Deposition of Metal Dielectric Film for Hardmask,” which is incorporated by reference for all purposes and may be used in some embodiments. In some embodiments, the deposited tungsten carbide film is patterned to form the patterning mask 216. In some embodiments, the patterned mask 216 is a carbon-containing amorphous carbon mask. In some embodiments, the mask does not contain metals or semimetals. In some embodiments, the pattern of the patterned mask provides mask features 220 for high aspect ratio contacts. In some embodiments, the mask features 220 are formed before the stack 204 is placed in the etching chamber. In other embodiments, the mask features 220 are formed while the stack 204 is in the etching chamber. In some embodiments, each bilayer 212 includes a silicon oxide layer 224 and a silicon nitride layer 228.

[0015] The stack is partially etched (step 106). In some embodiments, an etching gas is supplied. In some embodiments, radio frequency (RF) power is supplied to convert the etching gas into a plasma containing etching ions. A voltage is applied to accelerate the etching ions from the plasma to the stack. The etching ions partially etch the stack and etch a portion of the mask. Etching of the stack may include at least one of chemical etching and physical sputtering of the stack.

[0016] Figure 2B is a schematic cross-sectional view of stack 204 after it has been partially etched and the etched feature 240 has been formed. Part of the mask 216 has been etched away. During partial etching, the patterned mask 216 is partially etched and reshaped. In the example shown in Figure 2B, the patterned mask 216 has sidewall deposition, so the patterned mask 216 becomes neck-shaped, forming a narrow section. The neck makes the feature 240 tapered. If etching continues, the feature 240 becomes even more tapered.

[0017] A helmet mask is deposited on the patterned mask 216 (step 108). In some embodiments, the deposition of the helmet mask includes one or more cycles of pre-treating the surface of the patterned mask (step 112) and depositing the metal-containing helmet layer on the surface of the patterned mask (step 116). During the pre-treating step of the patterned mask surface (step 112), a pre-treatment gas is supplied. In some embodiments, the pre-treatment gas includes a hydrogen-containing component gas. In some embodiments, the pre-treatment gas includes hydrogen gas. Hydrogen gas provides reducing chemical properties. In some embodiments, in a pre-treatment gas containing a hydrogen-containing component, the pre-treatment gas does not contain oxygen. In some embodiments, the pre-treatment gas includes a silicon-containing gas. In some embodiments, the pre-treatment gas includes at least one of silicon tetrachloride (SiCl4), silicon tetrafluoride (SiF4), and silane (SiH4). The pre-treatment gas is converted into a plasma. In some embodiments, RF power or non-RF power is used to convert the pre-treatment gas into a plasma. In some embodiments, RF power is supplied at one or more frequencies of 400 kilohertz (kHz), 60 megahertz (MHz), 2 MHz, and 27 MHz. In some embodiments, plasma is generated within the process chamber where the stack is located. In some embodiments, plasma is generated remotely and then supplied to the process chamber. In some embodiments, remote plasma is generated in a portion of the process chamber separated from where the stack is located and then supplied to the portion of the process chamber where the stack is located.

[0018] Figure 2C is a schematic cross-sectional view of a stack 204 after the mask 216 has undergone a step (step 112) of pre-treating the surface of the patterning mask, and the pre-treated surface 232 of the patterning mask 216 has been formed. In some embodiments, the step (step 112) of pre-treating the surface of the patterning mask removes part of the necking. In some embodiments, the mask forming reduces the height of the patterning mask 216. In some embodiments, the step (step 112) of pre-treating the surface of the patterning mask provides reducing chemical properties to the surface in order to provide chemical properties of chemical reduction. In some embodiments, the pre-treatment generates dangling bonds on the pre-treated surface 232.

[0019] During the step of depositing a metal-containing helmet layer on the surface of the patterned mask (step 116), a deposition gas containing at least one of a metal fluoride gas, silane (SiH4) gas, or Germanine (GeH4) gas is supplied. In some embodiments, the deposition gas contains one or more of rhenium fluorides such as tungsten hexafluoride (WF6), rhenium hexafluoride (ReF6) or rhenium heptafluoride (ReF7), molybdenum fluorides such as molybdenum hexafluoride (MoF6), tantalum fluorides such as tantalum pentafluoride (TaF5), and vanadium fluorides such as vanadium pentafluoride (VF5). The deposition gas is converted into a plasma. In some embodiments, RF power or non-RF power is used to convert the pretreatment gas into a plasma. In some embodiments, the RF power is supplied at one or more frequencies of 400 kilohertz (kHz), 60 megahertz (MHz), 2 MHz, and 27 MHz. In some embodiments, the plasma is generated within the process chamber where the stack is located. In some embodiments, the plasma is generated remotely and then supplied to the process chamber. In some embodiments, the remote plasma is generated in a portion of the process chamber separated from where the stack is located and then supplied to the portion of the process chamber where the stack is located.

[0020] FIG. 2D is a schematic cross-sectional view of the stack 204 after the step of depositing a metal-containing helmet layer on the surface of the patterned mask on which the helmet layer 244 is deposited (step 116). The drawings are not to scale so as to better illustrate the helmet layer 244. In some embodiments, the single helmet layer 244 is a single atomic layer or molecular layer. In some embodiments, the single helmet layer 244 is thicker than a single atomic layer or molecular layer.

[0021] In some embodiments, depositing the helmet mask (step 108) includes one or more cycles of a step of pretreating the surface of the patterned mask (step 112), and a step of depositing the metal-containing helmet layer on the surface of the patterned mask (step 116). In some embodiments, the deposition of the helmet mask (step 108) is provided in 2 to 10 cycles. In some embodiments, the completed helmet mask layer 244 after 2 to 10 cycles has a thickness ranging from 5 nm to 100 nm. This is because the deposition is a cyclic process that is fully or partially an atomic layer deposition process. In some embodiments, the partial atomic layer deposition process is also partially a plasma-enhanced chemical vapor deposition process.

[0022] Then, using the patterned mask 216 and the helmet mask layer 244 as a mask, the stack is further etched (step 120). In some embodiments, part of the helmet mask layer 244 and the patterned mask 216 shown in FIG. 2D is etched away. In some embodiments, etching of the stack continues until etching of the stack is completed, as shown in FIG. 2E. In some embodiments, the deposition of the helmet (step 108) and the further etching of the stack (step 120) are cyclically repeated 2 to 10 times.

[0023] After etching is completed, the stack may be further processed by performing other processes in the process chamber, such as removing any remaining patterned mask 216. After the process is completed in the process chamber, the stack is removed from the process chamber. Since etching (steps 106 and 120) and helmet deposition (step 108) are performed in the same process chamber, the etching (steps 106 and 120) and the helmet deposition (step 108) are performed in-situ. The ability to perform in-situ etching (steps 106 and 120) and deposit the helmet (step 108) eliminates the need to move the stack between process chambers during these steps, increases throughput, reduces cost, and reduces contamination caused by moving the stack between process chambers. Furthermore, in some embodiments, performing the steps in-situ eliminates the need to remove the substrate from the chamber, allowing each helmet mask layer to be thinned over more cycles. Further, the in-situ process enables less distortion of mask shape and morphology during the process.

[0024] Some embodiments may be used on an oxide / nitride (ONON) multilayer stack to form features such as contact holes or trenches when fabricating 3D NAND memory devices. Some embodiments may be used for dynamic random access memory (DRAM) capacitor etching. Some embodiments may be used for etching silicon oxide and polysilicon bilayers (OPOP). Some embodiments provide an etching depth exceeding 1 micron. In some embodiments, the etching depth exceeds 10 microns. In some embodiments, the etching depth is in the range of 0.7 microns to 1.3 microns.

[0025] An advantage of some embodiments is that device manufacturers can have more precise control over the profiling of high-aspect-ratio features. Various embodiments allow for increased bottom CD for very high-aspect-ratio features. Various embodiments enable next-generation devices that rely on deeper structures at higher aspect ratios. Various embodiments reduce the cost of device manufacturing by reducing the number of steps required to develop high-aspect-ratio contacts. Various embodiments reduce the variation in feature width along the feature depth, thereby ensuring that the difference in width at any two points along the depth of feature 240 is less than 10%. In some embodiments, the deposition of the helmet mask allows for the provision of a sidewall liner. In some embodiments, the deposition of the helmet mask layer 244 provides additional mask thickness, thereby preventing the pattern mask from being completely removed. In some embodiments, the helmet mask layer 244 increases the mask, allowing for deeper etching. Furthermore, in some embodiments, the deposition of the helmet mask may also deposit a sidewall liner.

[0026] In some embodiments, the stack may be a single silicon-containing layer, such as a single layer of silicon oxide, silicon nitride, or silicon. In some embodiments, the stack may include a single or multiple layers of other silicon-containing material. In some embodiments, the mask may further contain oxygen to etch a stack containing a silicon layer. In some embodiments, the mask may further contain silicon to etch a silicon oxide stack. Some embodiments may have a metal dopant or a metalloid dopant. In some embodiments, the metal in the metal dopant or metalloid dopant is at least one of tungsten, molybdenum, ruthenium, tantalum, titanium, platinum, and aluminum. In other embodiments, the metalloid is boron.

[0027] In some embodiments, feature 240 may be etched across the entire depth of the stack (i.e., near the substrate) before the helmet mask layer 244 is deposited. In such embodiments, the helmet mask layer 244 is used as a mask for a process that widens the bottom of feature 240 and reduces the taper. The bottom of feature 240 may be widened using aggressive etching rather than partial etching. The helmet mask layer 244 provides additional mask protection while widening the bottom of feature 240.

[0028] In some embodiments, the sidewall liner deposition may occur before, during, or after the deposition of the helmet mask layer. The sidewall liner deposition may be carbon-based or may be made of another material, such as a metallic or semimetallic material. In some embodiments, the sidewall liner deposition is part of the process of forming the helmet mask layer 244. In some embodiments, the sidewall liner is not deposited. In some embodiments, the timing and process of mask and sidewall liner deposition may be used to adjust the mask deposition to desired resulting features, such as reduced warp CD, improved bottom CD, reduced taper, reduced torsion, and reduced defect formation.

[0029] Some embodiments do not cause further distortion of the mask's shape and form. A wide variety of embodiments may exist. Embodiments have been demonstrated to work on extremely small CD features, such as CDs with circular holes in the range of 16nm to 20nm. Embodiments are expected to be applicable to nodes / processes using smaller or larger CDs on various substrate materials.

[0030] Figure 3 is a schematic diagram of an etching reactor system 300, which may be used in several embodiments. In some embodiments, the etching reactor system 300 comprises a gas distribution plate 306 providing a gas inlet and an electrostatic chuck (ESC) 308 within an etching (or process) chamber 309 enclosed by chamber walls 352. Within the etching chamber 309, a stack 304 is positioned on the ESC 308, which is used as a substrate support. The ESC 308 may be biased from an ESC source 348. An etching gas source 310 is connected to the etching chamber 309 via the gas distribution plate 306. An ESC temperature controller 350 is connected to the ESC 308. A radio frequency (RF) source 330 supplies RF power to the lower electrode and / or upper electrode, which in this embodiment are the ESC 308 and the gas distribution plate 306, respectively. In some embodiments, 400 kHz, 60 MHz, and optionally 2 MHz, and 27 MHz power supplies constitute the RF source 330 and ESC source 348. In some embodiments, the upper electrode is grounded. In some embodiments, one generator is provided for each frequency. In some embodiments, the generators may be on separate RF sources, or separate RF generators may be connected to different electrodes. For example, the upper electrode may have an inner electrode and an outer electrode connected to different RF sources. In other embodiments, other arrangements of RF sources and electrodes may be used. A controller 335 is controllably connected to the RF source 330, ESC source 348, exhaust pump 320, and etching gas source 310. An example of such an etching chamber is the Vantex® etching system manufactured by Lam Research Corporation in Fremont, California. The process chamber can be a CCP (capacitance-coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0031] Figure 4 is a high-level block diagram showing a computer system 400 suitable for implementing the controller 335 used in the embodiment. The computer system 400 may have many physical forms, ranging from integrated circuits, printed circuit boards and small handheld devices to massive supercomputers. The computer system 400 may include one or more processors 402 and further include an electronic display device 404 (for displaying graphics, text, and other data), main memory 406 (e.g., random access memory (RAM)), storage device 408 (e.g., hard disk drive), removable storage device 410 (e.g., optical disc drive), user interface device 412 (e.g., keyboard, touchscreen, keypad, mouse or other pointing device, etc.), and communication interface 414 (e.g., wireless network interface). The communication interface 414 may allow software and data to be transferred between the computer system 400 and external devices via a link. The system may also include a communication infrastructure 416 (e.g., communication bus, crossover bar, or network) to which the aforementioned devices / modules are connected.

[0032] The information transmitted via the communication interface 414 may be in the form of electronic, electromagnetic, or optical signals, or other signals that can be received by the communication interface 414, via a communication link that carries signals, and may be implemented using wired or cable, optical fiber, telephone line, mobile phone link, radio frequency link, and / or other communication channels. Using such a communication interface 414, one or more processors 402 may receive information from or output information to the network during the process of performing the method steps described above. Furthermore, embodiments of the method may be performed by a single processor or by a network such as the Internet with a remote processor that shares part of the processing.

[0033] The term “non-temporary computer-readable medium” is generally used to refer to media such as main memory, secondary memory, removable storage devices, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and should not be interpreted to cover temporary subjects such as carrier waves or signals. Examples of computer code include machine code, such as that generated by a compiler, and files containing higher-level code executed by a computer using an interpreter. Computer-readable medium may also be computer code transmitted by computer data signals, which are embodied in carrier waves and represent sequences of instructions executable by a processor.

[0034] While this disclosure describes several preferred embodiments, there are many modifications, alterations, substitutions and various equivalents that fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatus of this disclosure. Therefore, the following appended claims are intended to be interpreted as including all such modifications, alterations, substitutions and various equivalents that fall within the true spirit and scope of this disclosure. Where used herein, the phrase “A, B, or C” should be interpreted as meaning a logic using the non-exclusive logic “OR” (“A OR B OR C”) and not as meaning “only one of A, B, or C”. Each step in the process may be an optional step and is not mandatory. Different embodiments may have one or more steps omitted, or may provide steps in a different order. Furthermore, different embodiments may provide different steps simultaneously rather than sequentially. [Explanation of symbols]

[0035] 204 stacks 208 circuit boards 212 double layer 216 Patterned Masks 220 Mask Features 224 Silicon oxide layer 228 Silicon Nitride Layer 232 Surface 240 features 244 Helmet Mask Layer 300 Etching Reactor System 304 stack 306 Gas Distribution Plate 308 Electrostatic Chuck 309 Etching Chamber 310 Etching gas source 320 Exhaust pump 330 RF source 335 Controller 348 ESC source 350 ESC Temperature Controller 352 Chamber Wall 400 Computer Systems 402 Processors 404 Electronic Display Devices 406 Main Memory 408 Storage Devices 410 Removable Storage Devices 412 User Interface Devices 414 Communication Interface 416 Communication Infrastructure

Claims

1. A method for etching features in a stack under a patterned mask, a) A step of partially etching the stack through the patterned mask, b) A step of depositing a helmet mask on top of the patterned mask, The steps of pre-treating the surface of the patterned mask, and The steps include: pre-treating the surface of the patterned mask, and then selectively depositing a metal-containing helmet layer onto the surface of the patterned mask; A step including at least one cycle of, c) The step of etching the stack through the helmet mask Methods that include...

2. The pre-treated surface of the patterned mask is A step of supplying a pretreatment gas containing at least one of hydrogen gas and a silicon-containing gas, The steps of converting the aforementioned pretreatment gas into plasma and The method according to claim 1, including the method described in claim 1.

3. The silicon-containing gas is SiCl ４ , SiF ４ SiH ４ The method according to claim 2, comprising at least one of the following.

4. The method according to claim 1, wherein the step of pre-treating the surface of the patterned mask is to form the patterned mask.

5. The method according to claim 1, wherein the step of pre-treating the surface of the patterned mask and the step of selectively depositing the metal-containing helmet layer do not overlap with each other.

6. The step of selectively depositing the metal-containing helmet layer is The steps include supplying a deposit gas containing a metal fluoride gas, The steps of converting the deposited gas into plasma and The method according to claim 1, including the method described in claim 1.

7. The method according to claim 6, wherein the metal fluoride gas comprises at least one of tungsten hexafluoride, rhenium fluoride, molybdenum fluoride, tantalum fluoride, and vanadium fluoride.

8. The method according to claim 1, wherein the step of depositing the helmet mask is performed for 2 to 10 cycles.

9. The method according to claim 1, wherein the step of depositing the helmet mask is an atomic layer deposition process.

10. The method according to claim 1, wherein the helmet mask is selectively deposited, and the ratio of the thickness of the helmet mask deposition on the upper part of the mask to the thickness of the helmet mask deposition at the bottom of the feature is in the range of 50:1 to 100:

1.

11. The method according to claim 1, wherein the helmet mask is deposited on top of the mask to a thickness in the range of 5 nm to 100 nm.

12. The method according to claim 1, wherein the step of depositing the helmet mask is at least partially an atomic layer deposition process.

13. The pre-treated surface of the patterned mask is A step of supplying a pretreatment gas containing hydrogen components, The steps of converting the aforementioned pretreatment gas into plasma and The method according to claim 1, including the method described in claim 1.

14. The method according to claim 13, wherein the pretreatment gas does not contain oxygen.

15. The method according to claim 1, wherein steps a, b, and c are performed in situ.

16. The method according to claim 1, wherein steps b and c are repeated at least once.

17. A device for etching features in a stack, process chamber and A substrate support section for supporting the substrate within the process chamber, A power supply for supplying power to the process chamber, A gas source that is fluidly connected to the process chamber, Etching gas source, Pretreatment gas source, and Sedimentary gas source Includes, gas sources, A controller controllably connected to the power supply and the gas source, and configured to etch features in the stack below the patterning mask, a) A step of partially etching the stack through the patterning mask using the etching gas from the etching gas source, b) A step of depositing a helmet mask on top of the patterned mask, The steps include: pre-treating the surface of the patterned mask using a pre-treatment gas from the pre-treatment gas source, and The step involves pre-treating the surface of the patterned mask, and then selectively depositing a metal-containing helmet layer onto the surface of the patterned mask using a deposition gas from the deposition gas source. A step including at least one cycle of, c) Etching the stack through the helmet mask using the etching gas from the etching gas source. The process, which includes the controller, is configured to etch features in the stack under the patterned mask. A device equipped with the following features.

18. The apparatus according to claim 17, wherein the deposit gas source supplies metal fluoride gas.

19. The apparatus according to claim 17, wherein the pretreatment gas source supplies at least one of a hydrogen-containing component gas and a silicon-containing gas.

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