BAW resonator-based oscillator

Abstract

The circuit (100) includes a resonator (104), a pair of transistors (102), and a common-mode feedback circuit (106). The pair of transistors (102) is cross-coupled across the resonator (104). The common-mode feedback circuit (106) is coupled to the pair of transistors (102). The common-mode feedback circuit (106) includes first and second degeneration cells (132, 134). The second degeneration cell (134) is connected in parallel to the first degeneration cell (132). The second degeneration cell (134) is configured to switchably change the current flowing through the pair of transistors (102).

Description

[Background technology]

[0001] A resonator is a device or system that oscillates spontaneously at a frequency called its resonant frequency. Resonators can be, for example, crystal resonators (also known as silica resonators), inductance-capacitance (LC) resonators, or microelectromechanical system (MEMS) resonators. Generally, a resonator is a passive device combined with an active circuit element to create an oscillator. An oscillator generates a periodic signal at its resonant frequency. For example, a crystal oscillator is an electronic circuit that uses the mechanical resonance of an oscillating crystal to generate an electrical signal with a very precise frequency. Crystal oscillators can be used to generate frequencies for time tracking or to generate clock signals for digital integrated circuits. MEMS resonators can be used as an alternative to crystal resonators for time tracking and to generate stable clock signals for analog and digital integrated circuits. [Overview of the Initiative]

[0002] In one example, the circuit includes a resonator, first, second, third, fourth, fifth, and sixth transistors, first, second, third, and fourth resistors, and first and second switches. The resonator has first and second terminals. The first transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor is coupled to the first terminal of the resonator. The control terminal is coupled to the second terminal of the resonator. The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the resonator. The control terminal of the second transistor is coupled to the first terminal of the resonator. The third transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor is coupled to the second terminal of the first transistor. The control terminal of the third transistor is coupled to the first terminal of the resonator. A first resistor is coupled between the second terminal of the third transistor and the reference voltage terminal. The fourth transistor has a first terminal, a second terminal and a control terminal. The first terminal of the fourth transistor is coupled to the second terminal of the first transistor. The control terminal of the fourth transistor is coupled to the first terminal of the resonator. A second resistor and a first switch are coupled in series between the second terminal of the fourth transistor and the reference voltage terminal. The fifth transistor has a first terminal, a second terminal and a control terminal. The first terminal of the fifth transistor is coupled to the second terminal of the second transistor. The control terminal of the fifth transistor is coupled to the second terminal of the resonator. A third resistor is coupled between the second terminal of the fifth transistor and the reference voltage terminal. The sixth transistor includes a first terminal, a second terminal and a control terminal. The first terminal of the sixth transistor is coupled to the second terminal of the second transistor. The control terminal of the sixth transistor is coupled to the second terminal of the resonator. The fourth resistor and the second switch are coupled in series between the second terminal of the sixth transistor and the reference voltage terminal.

[0003] In another example, the circuit includes a resonator, a pair of transistors, and a common-mode feedback circuit. The pair of transistors is cross-coupled across the resonator. The common-mode feedback circuit is coupled to the pair of transistors. The common-mode feedback circuit includes first and second degeneration cells. The second degeneration cell is connected in parallel to the first degeneration cell. The second degeneration cell is configured to switchably change the flow of current through the pair of transistors.

[0004] In a further example, the clock generator circuit includes an oscillator circuit, a frequency divider circuit, and a driver circuit. The frequency divider circuit is coupled to the oscillator circuit. The driver circuit is coupled to the frequency divider circuit. The oscillator circuit includes a resonator, a pair of transistors, and a common-mode feedback circuit. The pair of transistors is cross-coupled across the resonator. The common-mode feedback circuit is coupled to the pair of transistors. The common-mode feedback circuit includes first and second degeneration cells. The second degeneration cell is connected in parallel to the first degeneration cell. The second degeneration cell is configured to switchably change the flow of current through the pair of transistors. [Brief explanation of the drawing]

[0005] [Figure 1] This is a schematic diagram of an exemplary oscillator circuit, including a bulk acoustic wave (BAW) resonator and variable common-mode feedback.

[0006] [Figure 2] This graph shows the small-signal loop gain and large-signal loop gain in the oscillator circuit shown in Figure 1.

[0007] [Figure 3] This is a schematic diagram of an exemplary oscillator circuit, including a BAW resonator and current ramping.

[0008] [Figure 4]It is a graph showing an example of small-signal gain for different currents in the oscillator circuit of Fig. 3.

[0009] [Figure 5] It is a graph showing an enlarged portion of the graph of Fig. 4.

[0010] [Figure 6] It is a graph showing an exemplary small-signal gain and the corresponding large-signal gain of the oscillator circuit of Fig. 3.

[0011] [Figure 7] It is a schematic diagram of an exemplary oscillator circuit including a BAW resonator and low-pass filtering for reducing high-frequency gain.

[0012] [Figure 8] It is a graph showing an example of reduction in small-signal gain at higher frequencies for the oscillator circuit of Fig. 7.

[0013] [Figure 9] It is a schematic diagram of an exemplary oscillator circuit including a BAW resonator, variable in-phase feedback, current ramping, and low-pass filtering.

[0014] [Figure 10] It is a block diagram of an exemplary clock generator circuit including an oscillator circuit as described herein. DESCRIPTION OF EMBODIMENTS FOR CARRYING OUT THE INVENTION

[0015] An oscillator circuit including a resonator such as a bulk acoustic wave (BAW) resonator can oscillate at frequencies other than the desired fundamental frequency of the resonator. In some cases, the oscillator circuit can oscillate at a parasitic frequency that is higher or lower than the fundamental frequency of the resonator. Some oscillator circuits may include an inductor-capacitor filter to prevent parasitic oscillation, but this can consume considerable circuit area. Alternatively, devices exhibiting parasitic oscillation may be discarded, which reduces yield.

[0016] Instead of using passive filters including large inductors and capacitors to reduce gain at parasitic frequencies, an oscillator circuit as described herein may include linearized common-mode feedback loop and / or current ramping in the oscillator circuit to eliminate parasitic oscillation. Some examples may include a resistor in series with a control terminal of the oscillator transistor to reduce gain at frequencies above the fundamental frequency of the resonator in order to eliminate parasitic oscillation at frequencies higher than the fundamental frequency.

[0017] Figure 1 is a schematic diagram of an example oscillator circuit 100. The oscillator circuit 100 includes a transistor pair 102, a resonator 104, a common-mode feedback circuit 106, a transistor pair 108, capacitors 118, 120, 126, and 128, resistors 122 and 124, and transistors 162 and 164. Resonator 104 may be a BAW resonator or another type of resonator. Inductor 130 and / or inductor 131 may be coupled in series with resonator 104 between a terminal of transistor pair 102 and a terminal of transistor pair 108. Inductors 130 and 131 may be components or parasitic. Capacitor 120 is coupled in parallel with resonator 104 between a terminal of transistor pair 102 and a terminal of transistor pair 108. The capacitance of capacitor 120 may be variable to provide tuning of the oscillation frequency of the oscillator circuit 100.

[0018] The transistor pair 102 includes transistors 110 and 112. Transistors 110 and 112 may be n-type field-effect transistors (NFETs) as shown in the figure. Transistors 110 and 112 are cross-coupled across the resonator 104. Thus, the first current terminal of transistor 110, or simply a terminal (e.g., drain), is coupled to the first terminal of the resonator 104, and the control terminal of transistor 110 (e.g., gate) is coupled to the second terminal of the resonator 104. Also in the cross-coupled configuration, the first current terminal of transistor 112 (e.g., drain) is coupled to the second terminal of the resonator 104, and the control terminal of transistor 112 (e.g., gate) is coupled to the first terminal of the resonator 104. The second current terminal of transistor 110 (e.g., source) is coupled to the common-mode feedback circuit 106 and the first conductor (also called a terminal) of capacitor 118. The second current terminal (e.g., source) of transistor 112 is coupled to the common-mode feedback circuit 106 and the second conductor (also called a terminal) of capacitor 118. Capacitor 118 provides control over the gain contribution of transistor pair 102 at low frequencies. Capacitor 118 may be variable to allow adjustment for process variations in capacitance.

[0019] The transistor pair 108 includes transistors 114 and 116. Transistors 114 and 116 may be p-type field-effect transistors (PFETs) as shown in the figure. Transistors 114 and 116 are cross-coupled across the resonator 104. Thus, the first current terminal (e.g., drain) of transistor 114 is coupled to the first terminal of the resonator 104, and the control terminal (e.g., gate) of transistor 114 is coupled to the second terminal of the resonator 104 via capacitor 128. Also in the cross-coupled configuration, the first current terminal (e.g., drain) of transistor 116 is coupled to the second terminal of the resonator 104, and the control terminal (e.g., gate) of transistor 116 is coupled to the first terminal of the resonator 104 via capacitor 126. The second current terminal (e.g., source) of transistor 114 is coupled to a current source, which in this example is transistor 162. The second current terminal (e.g., source) of transistor 116 is coupled to a current source, which in this example is transistor 164. Resistor 122 is coupled between the control terminal of transistor 114 and a bias voltage circuit (not shown) at the bias voltage terminal VBIAS. The bias voltage provided at VBIAS may range from 0.5 to 0.7 volts in some examples of oscillator circuit 100. Resistor 124 is coupled between the control terminal of transistor 116 and the bias voltage circuit at the bias voltage terminal VBIAS. Resistors 122 and capacitor 128 form a first high-pass filter, and resistors 124 and capacitor 126 form a second high-pass filter for controlling the gain of transistor pair 108 at low frequencies. The resistances of resistors 122 and 124 may be variable to provide control of the filter cutoff frequency with process variations.

[0020] Transistors 162 and 164 supply current to the oscillator circuit 100. The first current terminal (e.g., source) of transistor 162 is coupled to the power terminal Vdd, and the second current terminal (e.g., drain) of transistor 162 is coupled to the second current terminal of transistor 114. The control terminal (e.g., gate) of transistor 162 is coupled to the bias circuit 166. The bias circuit 166 provides a bias voltage 168 to transistors 162 and 164. Transistor 164 is coupled in parallel with transistor 162. More specifically, the first current terminal (e.g., source) of transistor 164 is coupled to the first current terminal and power terminal Vdd of transistor 162. The second current terminal (e.g., drain) of transistor 164 is coupled to the second current terminal of transistor 116. The control terminal (e.g., gate) of transistor 164 is coupled to the bias circuit 166 to receive the bias voltage 168. The bias voltage 168 can be in the range of 0.5 to 0.7 volts in some examples of the bias circuit 166. Transistors 162 and 164 can be PFETs, as shown in the figure.

[0021] The common-mode feedback circuit 106 includes degeneration cells 132, 134, 136, and 138. Degeneration cells 132 and 134 are coupled to transistor 110. Degeneration cells 136 and 138 are coupled to transistor 112. Degeneration cells 132 and 138 are coupled to a reference voltage terminal 160 (e.g., ground) by a fixed conductor. Degeneration cells 134 and 136 are switchably coupled to the reference voltage terminal 160 by a switch. An example of the common-mode feedback circuit 106 may include multiple instances of degeneration cell 134 and multiple instances of degeneration cell 136. Each instance of degeneration cell 134 and degeneration cell 136 may be controlled independently. Therefore, the resistance of the path between the transistor pair 102 and the reference voltage terminal 160 can be changed by controlling the number of degeneration cells that conduct current to the reference voltage terminal 160.

[0022] The degeneration cell 132 includes a transistor 140 and a resistor 142. The first current terminal (e.g., drain) of transistor 140 is coupled to the second current terminal of transistor 110. The resistor 142 is coupled between the second current terminal (e.g., source) of transistor 140 and the reference voltage terminal 160. The control terminal (e.g., gate) of transistor 140 is coupled to the first terminal of the resonator 104.

[0023] The degeneration cell 134 includes a transistor 144, a resistor 146, and a switch 148. The switch 148 may include a field-effect transistor or other switching device. The first current terminal (e.g., drain) of transistor 144 is coupled to the first current terminal of transistor 140. The control terminal (e.g., gate) of transistor 144 is coupled to the control terminal of transistor 140. The resistor 146 and the switch 148 are coupled in series between the second current terminal (e.g., source) of transistor 144 and the reference voltage terminal 160.

[0024] The degeneration cell 138 includes a transistor 156 and a resistor 158. The first current terminal (e.g., drain) of transistor 156 is coupled to the second current terminal of transistor 112. The resistor 158 is coupled between the second current terminal (e.g., source) of transistor 156 and the reference voltage terminal 160. The control terminal (e.g., gate) of transistor 156 is coupled to the second terminal of the resonator 104.

[0025] The degeneration cell 136 includes a transistor 150, a resistor 152, and a switch 154. The switch 154 may include a field-effect transistor or other switching device. The first current terminal (e.g., drain) of transistor 150 is coupled to the first current terminal of transistor 156. The control terminal (e.g., gate) of transistor 150 is coupled to the control terminal of transistor 156. The resistor 152 and the switch 154 are coupled in series between the second current terminal (e.g., source) of transistor 150 and the reference voltage terminal 160.

[0026] FIG. 2 is a graph showing an example of small-signal loop gain and large-signal loop gain in the oscillator circuit 100. In FIG. 2, curve 204 represents the small-signal loop gain of the oscillator circuit 100. In FIG. 2, curve 202 represents the large-signal loop gain of an oscillator circuit that does not include the variable degeneration of the in-phase feedback circuit 106. In such a circuit, the current in the in-phase feedback transistor can be modulated, thereby causing nonlinear transconductance (g m ) component to be generated, which causes an increase in large-signal impedance at low frequencies, resulting in a low-frequency peak exceeding 0 dB as shown by curve 202. The low-frequency gain peak may cause low-frequency oscillation in addition to or instead of oscillation at the fundamental frequency of the resonator.

[0027] The in-phase feedback circuit 106 has a nonlinear g of the transistors of the in-phase feedback circuit 106 m provides resistive degeneration that prevents the occurrence of the low-frequency peak of curve 202 by reducing the influence of the component. TIFF2026531679000002.tif13132Here, g m,eff is the effective transconductance of the in-phase feedback circuit 106, and g m is the transconductance of the transistor of the in-phase feedback circuit 106, and R E is the resistance of the parallel degeneration resistor of the in-phase feedback circuit 106.

[0028] Equation (1) shows that when g m R E is greater than 1, the effective transconductance (g m,eff ) of the in-phase feedback circuit 106 is a function of the resistance (RE) of the degeneration resistors (resistors 142, 146, 152, and 158) of the in-phase feedback circuit 106. Therefore, the g of the in-phase feedback circuit 106 mThis can be controlled by degeneration, and low-frequency oscillations enabled by curve 202 can be prevented. However, in order to maintain a constant amplitude across the process and voltage, the oscillator current must be changed, which in turn causes g m This changes significantly. m R E The same applies to the change. When the current value is low, g m R E <<1 and g m,eff =g m In this case, the desired degeneration may not be obtainable with fixed degeneration. The oscillator circuit 100 adjusts the number of degeneration cells 134 and 136 activated in the common-mode feedback circuit 106 (by closing switches 148 and 154) based on the current drawn by the oscillator circuit 100. m R E This problem is addressed by keeping the value constant (or nearly constant). For example, the number of degeneration cells to be activated may be selected at 100 during manufacturing / testing, and the switches of the degeneration cells can be closed during manufacturing, testing, or operation to set the desired degeneration.

[0029] In Figure 2, curve 206 represents the large-signal loop gain of the oscillator circuit 100. The common-mode feedback circuit 106 maintains the large-signal loop gain below 0 dB at low frequencies to prevent low-frequency oscillation which is enabled by curve 202.

[0030] Figure 3 is a schematic diagram of an exemplary oscillator circuit 300. Oscillator circuit 300 is similar to oscillator circuit 100. Oscillator circuit 300 includes a transistor pair 102, a resonator 104, a transistor pair 108, capacitors 118, 120, 126, and 128, and resistors 122 and 124. Oscillator circuit 300 includes a common-mode feedback circuit 314, which, as shown, includes only transistors 140 and 156, whose second terminals are directly coupled to a reference voltage terminal 160. In some examples of oscillator circuit 300, common-mode feedback circuit 106 may be used as common-mode feedback circuit 314.

[0031] The oscillator circuit 300 also incorporates a current ramp circuit 316, which includes transistors 162 and 164, ramp cells 318 and 320, and a control circuit 318. Ramp cell 318 includes transistor 304 and switch 306. Ramp cell 320 includes transistor 308 and switch 310. Transistors 304 and 308 may be PFETs as shown. Figure 3 shows two ramp cells, but the current ramp circuit 316 may include more than two ramp cells.

[0032] In lamp cell 318, transistor 304 and switch 306 are connected in series such that the first current terminal (e.g., source) of transistor 304 is connected to the first current terminals of transistors 162 and 164 via switch 306. Also, the second current terminal (e.g., drain) of transistor 304 is connected to the second current terminals of transistors 162 and 164. The control terminal (e.g., gate) of transistor 304 is connected to bias circuit 166 to receive bias voltage 168. In lamp cell 320, transistor 308 and switch 310 are connected in series such that the first current terminal (e.g., source) of transistor 308 is connected to the first current terminals of transistors 162 and 164 via switch 310. Also, the second current terminal (e.g., drain) of transistor 308 is connected to the second current terminal of transistor 162. The control terminal (e.g., gate) of transistor 308 is connected to bias circuit 166 to receive bias voltage 168.

[0033] Switches 306 and 310 are coupled to a control circuit 318 (also called a ramp control circuit) to receive control signals (C1 and CN) that control the opening and closing of switches 306 and 310. An example of a current ramp circuit 316 may include two or more ramp cells coupled in parallel to transistors 162 and 164 between Vdd and transistor pair 108. During the startup of the oscillator circuit 300, the control circuit 318 can determine the timing to close switches 306 and 310 (and any number of additional switches according to a predetermined startup timing function) to gradually increase the current flow in the oscillator circuit 300. In the oscillator circuit 300, oscillation may occur at frequencies where the loop gain is greater than 1. The loop gain is a function of transconductance, and transconductance depends on the current flow. The current ramp circuit 316 provides a reliable startup oscillation at a desired frequency (e.g., the fundamental frequency of the resonator 104) by gradually increasing the current flowing through the oscillator circuit 300 during startup. The resonator 104 has a high impedance at the fundamental frequency, which causes the gain of the oscillator circuit 300 to be higher than the higher or lower peaks at the fundamental frequency. Therefore, as the current ramp circuit 316 increases the current flowing through the oscillator circuit 300, the gain at the fundamental frequency first exceeds 0 dB, and thus oscillation begins only at the fundamental frequency.

[0034] Figures 4 and 5 are graphs illustrating an example where the small-signal gain in the oscillator circuit 300 increases as the current increases during startup (for example, when switch 310 is closed after a predetermined time following switch 306). Figure 5 is an enlarged view of curves 402, 404, and 406 at interval 408 in Figure 4. Curve 402 represents the gain of the oscillator circuit 300 at a first current. Curve 404 represents the gain of the oscillator circuit 300 at a second current higher than the first current. Curve 406 represents the gain of the oscillator circuit 300 at a third current higher than the second current. Figure 5 shows that the small-signal gain of the oscillator circuit 300 exceeds 0 dB only at the fundamental frequency of the resonator 104.

[0035] Figure 6 is a graph showing an example of the large-signal loop gain 604 and small-signal loop gain 602 in the oscillator circuit 300. The large-signal gain remains below 0 dB at all frequencies below the fundamental frequency, and therefore the oscillation stabilizes at the fundamental frequency of the resonator 104.

[0036] Figure 7 is a schematic diagram of an exemplary oscillator circuit 700. Oscillator circuit 700 is similar to oscillator circuit 100 and / or oscillator circuit 300. Oscillator circuit 700 includes a transistor pair 102, a resonator 104, a transistor pair 108, capacitors 118, 120, 126, and 128, and resistors 122 and 124. Oscillator circuit 700 includes a common-mode feedback circuit 314. In some examples of oscillator circuit 700, the common-mode feedback circuit 106 may be used as the common-mode feedback circuit 314. Some examples of oscillator circuit 700 may also include a current ramp circuit 316.

[0037] Oscillator circuit 700 provides an additional margin at frequencies above the fundamental frequency of the resonator 104 compared to oscillator circuits 100 and 300 by reducing the small-signal loop gain at high frequencies. This additional margin can improve the oscillator circuit 700's resistance to high-frequency oscillations, which are related to aging, changes in bond wire inductance, etc. The increased margin is provided by adding resistors 702, 704, 706, and 708 at the control terminals of transistors 114, 116, 110, and 112. The resistances of resistors 702, 704, 706, and 708 can be selected based on the capacitances of the control terminals of transistors 114, 116, 110, and 112 to provide a desired low-pass filter that attenuates frequencies above the fundamental frequency of the resonator 104. Resistor 702 is coupled between the control terminal of transistor 114 and the second terminal of the resonator 104. Resistor 704 is coupled between the control terminal of transistor 116 and the first terminal of resonator 104. Resistor 706 is coupled between the control terminal of transistor 110 and the second terminal of resonator 104. Resistor 708 is coupled between the control terminal of transistor 112 and the first terminal of resonator 104. Resistors 702, 704, 706, and 708, together with the control terminal capacitance (e.g., gate capacitance) of the transistors to which the resistors are coupled, provide a low-pass filter that reduces high-frequency gain to prevent high-frequency oscillation.

[0038] Figure 8 is a graph showing an example of the small-signal loop gain in oscillator circuit 700. Figure 8 shows curves 802 and 804. Curve 802 represents the small-signal loop gain of an oscillator without resistors 702, 704, 706, and 708, and curve 804 represents the small-signal loop gain of oscillator circuit 700. Comparing curves 802 and 804, oscillator circuit 700 reduces the gain at high frequencies by approximately 2 dB compared to the oscillator circuit without resistors 702, 704, 706, and 708, which helps prevent oscillation at frequencies above the fundamental frequency of the resonator 104.

[0039] Figure 9 is a schematic diagram of an exemplary oscillator circuit 900. Oscillator circuit 900 is similar to oscillator circuits 100, 300, and 700. Oscillator circuit 900 includes transistor pair 102, resonator 104, transistor pair 108, capacitors 118, 120, 126, and 128, and resistors 122 and 124. Oscillator circuit 900 also includes a common-mode feedback circuit 106, a current ramp circuit 316, and resistors 702, 704, 706, and 708, as described with respect to oscillator circuits 100, 300, and 700. Thus, oscillator circuit 900 provides all the advantages of oscillator circuits 100, 300, and 700.

[0040] Figure 10 is a block diagram of an exemplary clock generator circuit 1000. The clock generator circuit 1000 includes an oscillator circuit 1002, a frequency divider circuit 1004, an output driver circuit 1006, a temperature sensor 1008, control logic 1010, a digital-to-analog converter (DAC) 1012, and a filter 1014. The oscillator circuit 1002 may be an implementation of oscillator circuit 100, oscillator circuit 300, oscillator circuit 700, or oscillator circuit 900. The output of oscillator circuit 1002 is coupled to the input of frequency divider circuit 1004. The frequency divider circuit 1004 includes a circuit element that divides the frequency of the output signal received from oscillator circuit 1002 by an integer or non-integer divisor to generate a desired clock frequency. The output of frequency divider circuit 1004 is coupled to the input of output driver circuit 1006. The output driver circuit 1006 buffers the output of the frequency divider circuit 1004 and generates an output clock signal (CLKOUT) that is provided to an external circuit (not shown).

[0041] The temperature sensor 1008 measures the temperature of the operating environment of the oscillator circuit 1002. The temperature sensor 1008 is coupled to the control logic 1010 and provides the control logic 1010 with the temperature measurement. The control logic 1010 generates adjustment values ​​based on the temperature measurement received from the temperature sensor 1008. For example, the control logic 1010 may include a lookup table that stores adjustment values ​​for temperature values ​​or temperature ranges. The output of the control logic 1010 is coupled to the DAC 1012. The control logic 1010 provides the adjustment values ​​to the DAC 1012, which converts the adjustment values ​​into an analog signal. The output of the DAC 1012 is coupled to the filter 1014. The filter 1014 filters the analog signal received from the DAC 1012 (e.g., low-pass filtering) and provides the filtered signal to the oscillator circuit 1002. The oscillator circuit 1002 applies the filtered signal to adjust the frequency of the oscillator circuit 1002 in relation to temperature. For example, an analog signal may be applied to adjust the capacitance of capacitor 120 (Figure 9), thereby adjusting the frequency generated by the oscillator circuit 1002.

[0042] In this description, the term “to connect” may include connections, communications, or signaling paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B in order to perform a certain action, then (a) in the first example, device A is connected to device B by a direct connection, or (b) in the second example, device A is connected to device B via intermediary component C, such that device B is controlled by device A via a control signal generated by device A, provided that intermediary component C does not alter the functional relationship between device A and device B.

[0043] Furthermore, in this specification, the phrase "based on ~" means "based at least in part on ~". Therefore, if X is based on Y, X may be based on Y and any number of other factors.

[0044] A device "configured" to perform a certain task or function may be configured (e.g., programmed and / or wired) at the time of manufacture by the manufacturer to perform that function, and / or may be configurable (or reconfigurable) after manufacture by the user to perform that function and / or other additional or alternative functions. Such configuration may be via the device's firmware and / or software programming, via the configuration and / or layout of hardware components, via the interconnection of the devices, or a combination thereof.

[0045] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” are interchangeable. Unless otherwise specified, these terms are generally used to mean the interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0046] A circuit or device described herein as including certain components may instead be adapted to be coupled to those components to form the circuit element or device described. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), which may be adapted to be coupled to at least some of the passive elements and / or sources to form the structure described, either during or after manufacturing, for example, by an end user and / or a third party.

[0047] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no modification to the remaining circuit elements. For example, field-effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, e.g., NPN transistors or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used instead of or in conjunction with the devices described herein. Transistors may be depletion-mode devices, drain-extension devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Devices may also be mounted in or on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0048] In the claims, the control input and current terminals of a transistor may be referred to. In the context of an FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0049] In this specification, an FET is "on" or "enabled" to mean that a conduction channel exists in the FET and that drain current can flow through the FET. In this specification, an FET is "off" or "disabled" to mean that a conduction channel does not exist and therefore no drain current flows through the FET. However, an "off" FET may still have current flowing through the transistor's body diode.

[0050] The circuits described herein are reconfigurable to include additional or different components to provide functionality that is at least partially similar to the functionality available before component replacement. Components indicated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the indicated resistor, unless otherwise specified. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0051] In the examples described, some elements are included in the integrated circuit, while others are outside the integrated circuit, but in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being outside the integrated circuit may be included in the integrated circuit, and / or some of the features illustrated as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term “integrated circuit” means one or more circuits that are (1) incorporated in / on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated in the same module, and / or (4) incorporated in / on the same printed circuit board.

[0052] The use of the term "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suitable for the teachings herein. Unless otherwise stated herein, "about," "approximately," or "substantially" preceding a parameter means that the value is within + / - 10% of that parameter, or, if the parameter is zero, within a reasonable range of values ​​near zero.

[0053] Within the scope of the claims of the present invention, modifications may be made to the exemplary embodiments described, and other embodiments are possible.

Claims

1. It is a circuit, A resonator having a first terminal and a second terminal, A first transistor having a first terminal coupled to the first terminal of the resonator, a second terminal, and a control terminal coupled to the second terminal of the resonator, A second transistor having a first terminal coupled to the second terminal of the resonator, a second terminal, and a control terminal coupled to the first terminal of the resonator, A third transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal, and a control terminal coupled to the first terminal of the resonator, A first resistor is coupled between the second terminal of the third transistor and the reference voltage terminal, A fourth transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal, and a control terminal coupled to the first terminal of the resonator, A second resistor and a first switch are connected in series between the second terminal of the fourth transistor and the reference voltage terminal. A fifth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal, and a control terminal coupled to the second terminal of the resonator, A third resistor is coupled between the second terminal of the fifth transistor and the reference voltage terminal, A sixth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal, and a control terminal coupled to the second terminal of the resonator, A fourth resistor and a second switch are connected in series between the second terminal of the sixth transistor and the reference voltage terminal. A circuit that includes this.

2. The circuit according to claim 1, A seventh transistor having a first terminal coupled to the first terminal of the resonator, a second terminal, and a control terminal coupled to the second terminal of the resonator, An eighth transistor having a first terminal coupled to the second terminal of the resonator, a second terminal coupled to the second terminal of the seventh transistor, and a control terminal coupled to the first terminal of the resonator, A circuit that further includes the following.

3. The circuit according to claim 2, A fifth resistor is coupled between the control terminal of the first transistor and the second terminal of the resonator, A sixth resistor is coupled between the control terminal of the second transistor and the first terminal of the resonator, A seventh resistor is coupled between the control terminal of the seventh transistor and the second terminal of the resonator, An eighth resistor is coupled between the control terminal of the eighth transistor and the first terminal of the resonator, A circuit that further includes the following.

4. The circuit according to claim 3, A first capacitor is coupled between the control terminal of the first transistor and the second terminal of the resonator, A second capacitor is coupled between the control terminal of the second transistor and the first terminal of the resonator, A circuit that further includes the following.

5. The circuit according to claim 2, A ninth transistor having a first terminal, a second terminal coupled to the second terminal of the seventh transistor, and a control terminal coupled to a bias voltage circuit, A tenth transistor having a first terminal, a second terminal connected to the second terminal of the seventh transistor, and a control terminal connected to the control terminal of the ninth transistor, A third switch having a first terminal connected to the first terminal of the tenth transistor, a second terminal connected to the first terminal of the ninth transistor, and a control terminal, A circuit that further includes the following.

6. The circuit according to claim 5, further comprising a control circuit having an output coupled to the control terminal of the third switch, wherein the control circuit is configured to close the third switch based on a predetermined startup timing function.

7. The circuit according to claim 6, An eleventh transistor having a first terminal connected to the first terminal of the ninth transistor, a second terminal connected to the second terminal of the seventh transistor, and a control terminal connected to the control terminal of the ninth transistor, A twelfth transistor having a first terminal connected to the first terminal of the ninth transistor, a second terminal connected to the second terminal of the seventh transistor, and a control terminal connected to the control terminal of the ninth transistor, A fourth switch having a first terminal connected to the first terminal of the twelfth transistor, a second terminal connected to the first terminal of the ninth transistor, and a control terminal connected to the second output of the control circuit, A circuit that further includes the following.

8. The circuit according to claim 7, wherein the control circuit is configured to close the fourth switch a predetermined time after the control circuit has closed the third switch.

9. It is a circuit, Resonator and, A pair of transistors cross-coupled at both ends of the resonator, A common-mode feedback circuit coupled to the aforementioned pair of transistors, Includes, The in-phase feedback circuit includes a first degeneration cell and a second degeneration cell connected in parallel to the first degeneration cell, wherein the second degeneration cell is configured to switchably change the current flowing through the transistor pair.

10. The circuit according to claim 9, The first degeneration cell includes a first transistor and a first resistor connected in series between the transistor pair and a reference voltage terminal. The second degeneration cell includes a second transistor, a second resistor, and a switch, which are coupled in series between the pair of transistors and the reference voltage terminal. circuit.

11. The circuit according to claim 9, The aforementioned pair of transistors is the first pair of transistors, The aforementioned circuit, A second pair of transistors is cross-coupled to both ends of the resonator, A current ramp circuit coupled to the second pair of transistors, Includes, The current lamp circuit is configured to increase the current flow in the second pair of transistors as a function of time.

12. The circuit according to claim 11, wherein the current lamp circuit is A first transistor coupled between the second pair of transistors and the power terminal, A first lamp cell coupled in parallel to the first transistor between the second pair of transistors and the power terminal, the first lamp cell comprising a second transistor and a first switch coupled in series between the second pair of transistors and the power terminal, A second lamp cell coupled in parallel to the first lamp cell between the second pair of transistors and the power terminal, the second lamp cell includes a third transistor and a second switch coupled in series between the second pair of transistors and the power terminal, A circuit that includes this.

13. The circuit according to claim 12, wherein the current lamp circuit includes a lamp control circuit coupled to the first switch and the second switch, and the lamp control circuit is configured to sequentially close the first switch and the second switch.

14. The circuit according to claim 11, The first transistor pair includes a first transistor and a second transistor, The second transistor pair includes a third transistor and a fourth transistor, The aforementioned circuit, A first resistor is coupled between the control terminal of the first transistor and the first terminal of the resonator, A second resistor is coupled between the control terminal of the second transistor and the second terminal of the resonator, A third resistor is coupled between the control terminal of the third transistor and the first terminal of the resonator, A fourth resistor is coupled between the control terminal of the fourth transistor and the second terminal of the resonator, A circuit that includes this.

15. The circuit according to claim 14, wherein the resistances of the first, second, third, and fourth resistors are selected to provide a low-pass filter that attenuates frequencies above the fundamental frequency of the resonator.

16. A clock generator circuit, Oscillator circuit and, A frequency divider circuit coupled to the oscillator circuit, A driver circuit coupled to the frequency divider circuit, Includes, The oscillator circuit, Resonator and, A pair of transistors cross-coupled at both ends of the resonator, A common-mode feedback circuit coupled to the aforementioned pair of transistors, Includes, The in-phase feedback circuit includes a first degeneration cell and a second degeneration cell connected in parallel to the first degeneration cell, wherein the second degeneration cell is configured to switchably change the current flowing through the transistor pair. Clock generator circuit.

17. A clock generator circuit according to claim 16, The first degeneration cell includes a first transistor and a first resistor connected in series between the transistor pair and a reference voltage terminal. The second degeneration cell includes a second transistor, a second resistor, and a switch, which are coupled in series between the transistor pair and the reference voltage terminal. Clock generator circuit.

18. A clock generator circuit according to claim 16, The aforementioned pair of transistors is the first pair of transistors, The oscillator circuit, A second pair of transistors is cross-coupled to both ends of the resonator, A current ramp circuit coupled to the second pair of transistors, Includes, The current ramp circuit is configured to increase the current flow in the second pair of transistors as a function of time. Clock generator circuit.

19. A clock generator circuit according to claim 16, wherein the current ramp circuit is A first transistor coupled between the second pair of transistors and the power terminal, A first lamp cell coupled in parallel to the first transistor between the second pair of transistors and the power terminal, the first lamp cell comprising a second transistor and a first switch coupled in series between the second pair of transistors and the power terminal, A second lamp cell, which is coupled in parallel to the first lamp cell between the second pair of transistors and the power terminal, and which includes a third transistor and a second switch, coupled in series between the second pair of transistors and the power terminal, A lamp control circuit coupled to the first switch and the second switch, configured to sequentially close the first switch and the second switch, A clock generator circuit, including the following:

20. A clock generator circuit according to claim 18, The first transistor pair includes a first transistor and a second transistor, The second transistor pair includes a third transistor and a fourth transistor, The oscillator circuit, A first resistor is coupled between the control terminal of the first transistor and the first terminal of the resonator, A second resistor is coupled between the control terminal of the second transistor and the second terminal of the resonator, A third resistor is coupled between the control terminal of the third transistor and the first terminal of the resonator, A fourth resistor is coupled between the control terminal of the fourth transistor and the second terminal of the resonator, Includes, A clock generator circuit in which the resistances of the first, second, third, and fourth resistors are selected to provide a low-pass filter that attenuates frequencies above the fundamental frequency of the resonator.

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