Power semiconductor device having a balanced shunt structure

Abstract

The present invention provides a power semiconductor device. In one example, the power semiconductor device includes a semiconductor structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells. The power semiconductor device includes a gate structure, at least a portion of which lies on the inactive region. The power semiconductor device includes a first shunt contact structure which lies at least partially on the inactive region. The power semiconductor device includes a second shunt contact structure which lies at least partially on the inactive region. The power semiconductor device includes an equilibrium shunt structure which lies at least partially on the inactive region.

Description

Detailed description of the invention

[0001] [Cross-reference of related applications] This application is based on and claims priority to U.S. Patent Application No. 18 / 466,487, filed on 13 September 2023. This application claims priority and benefits with respect to the entirety of this cited application and incorporates it by reference in its entirety.

[0002] [Technical field] This disclosure broadly relates to semiconductor devices.

[0003] [Background technology] Power semiconductor devices are used to carry large currents and support high voltages. A wide variety of power semiconductor devices are known in the prior art, including, for example, transistors, diodes, thyristors, power modules, discrete power semiconductor packages, and other devices. For example, exemplary semiconductor devices may be transistor devices such as metal-oxide-semiconductor field-effect transistors ("MOSFETs"), bipolar junction transistors ("BJTs"), insulated-gate bipolar transistors ("IGBTs"), gate turn-off transistors ("GTOs"), junction field-effect transistors ("JFETs"), high electron-mobility transistors ("HEMTs"), and other devices. Exemplary semiconductor devices may be diodes such as Schottky diodes, or other devices. Exemplary semiconductor devices may also be power modules, which may include one or more power devices and other circuit elements and can be used to dynamically switch large amounts of power through various components such as motors, inverters, and generators. These semiconductor devices may be manufactured from wide-bandgap semiconductor materials, such as silicon carbide ("SiC")-based and / or gallium nitride ("GaN")-based semiconductor materials.

[0004] [Overview of the prefecture] The aspects and effects of each embodiment of this disclosure are, in part, described below, may be learned from the description, or may be learned through the implementation of the embodiment.

[0005] An exemplary embodiment of the present disclosure relates to a power semiconductor device. The power semiconductor device includes a semiconductor structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells. The power semiconductor device includes a gate structure, at least a portion of which lies on the inactive region. The power semiconductor device includes a first shunt contact structure which lies at least partially on the inactive region. The power semiconductor device includes a second shunt contact structure which lies at least partially on the inactive region. The power semiconductor device includes an equilibrium shunt structure which lies at least partially on the inactive region.

[0006] Another exemplary embodiment of the present disclosure relates to a power semiconductor device. The power semiconductor device includes a semiconductor structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells. The power semiconductor device includes a field insulating layer at least partially on the inactive region. The power semiconductor device includes a gate structure at least partially on the field insulating layer. The power semiconductor device includes a shunt contact structure extending at least partially through the field insulating layer. The power semiconductor device includes an equilibrium shunt structure at least partially on the inactive region.

[0007] Another exemplary embodiment of the present disclosure relates to a power semiconductor device. The power semiconductor device includes a semiconductor structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells. The power semiconductor device includes a gate structure, at least a portion of which lies on the inactive region. The power semiconductor device includes a plurality of shunt contact structures, at least partially on the inactive region. The power semiconductor device includes a balance shunt structure, at least partially on the inactive region. The balance shunt structure is operable to balance the displacement currents associated with the plurality of shunt contact structures.

[0008] Another exemplary embodiment of the present disclosure relates to a power semiconductor device. The power semiconductor device includes a semiconductor structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells. The power semiconductor device includes a gate pad located in the central portion of the power semiconductor device. The power semiconductor device includes a plurality of shunt contact structures at least partially surrounding the gate pad.

[0009] These and other features, aspects, and effects of various embodiments will be better understood by referring to the following description and the appended claims. The appended drawings incorporated into and constituting parts of this specification illustrate embodiments of the present disclosure and explain the relevant principles together with the description thereof. [Brief explanation of the drawing]

[0010] This specification provides a detailed description of each embodiment for those skilled in the art, with reference to the following accompanying drawings. [Figure 1] Figure 1 shows a plan view of a semiconductor wafer containing a plurality of semiconductor devices according to an exemplary embodiment of the present disclosure. [Figure 2A] Figure 2A shows a plan view of one of the semiconductor devices included on the semiconductor wafer of Figure 1 according to an exemplary embodiment of the present disclosure. [Figure 2B] Figure 2B shows a plan view of the semiconductor device shown in Figure 2A according to an exemplary embodiment of the present disclosure, with the metallization of the source pad and gate pad removed. [Figure 3] Figure 3 shows a plan view of a portion of a unit transistor cell of the power semiconductor device shown in Figures 2A-2B according to an exemplary embodiment of the present disclosure. [Figure 4] Figure 4 shows a cross-sectional view along line 4-4 in Figure 3 according to an exemplary embodiment of the present disclosure. [Figure 5] Figure 5 shows a plan view of an exemplary semiconductor device, including the source runner. [Figure 6]FIG. 6 is a cross-sectional view taken along line 6-6 in FIG. 5 [Figure 7] FIG. 7 is a cross-sectional view taken along line 6-6 in FIG. 5, showing a state where a body diode current flows through a source runner. [Figure 8] FIG. 8 is a plan view emphasizing a constriction region of a body diode current in the exemplary semiconductor device of FIG. 5. [Figure 9] FIG. 9 is a plan view of an exemplary semiconductor device that does not include a source runner and includes a plurality of shunt contact structures. [Figure 10] FIG. 10 is a cross-sectional view taken along line A-A' in FIG. 9. [Figure 11] FIG. 11 is a cross-sectional view taken along line B-B' in FIG. 9. [Figure 12] FIG. 12 is a plan view of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure, which does not include a source runner and includes a balanced shunt structure. [Figure 13] FIG. 13 is a cross-sectional view taken along line 13-13 in FIG. 12. [Figure 14] FIG. 14 is a plan view of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure, which does not include a source runner and includes a balanced shunt structure. [Figure 15] FIG. 15 is a plan view of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure, which does not include a source runner and includes a balanced shunt structure. [Figure 16] FIG. 16 is a plan view of an exemplary semiconductor device without a source runner according to an exemplary embodiment of the present disclosure. [Figure 17] FIG. 17 is a plan view of an exemplary semiconductor device according to an exemplary embodiment of the present disclosure, which includes a gate pad at a central portion of the power semiconductor device and has a balanced shunt structure. MODE FOR CARRYING OUT THE INVENTION

[0011] DETAILED DESCRIPTION OF THE INVENTION Details of each embodiment are referenced here, and one or more examples thereof are illustrated in each drawing. Each example is provided for the description of the embodiments, not to limit the disclosure. Indeed, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments without departing from the spirit and scope of the disclosure. For example, features illustrated or described as part of one embodiment can be used in conjunction with another embodiment to bring about yet another embodiment. Thus, aspects of the disclosure are intended to cover such modifications and variations.

[0012] A power semiconductor device has a semiconductor substrate (e.g., an n-type substrate) such as a silicon carbide substrate having a first conductivity type, and an epitaxial layer structure having a first conductivity type (e.g., n-type) may be formed on the substrate. A portion of this epitaxial layer structure (which may include one or more isolation layers) functions as a drift region of the power semiconductor device. The device typically includes an "active region," which includes one or more unit cell devices having a junction such as a pn junction. The active region may be formed on and / or within the drift region. The active region acts as a main junction, blocking voltage in the reverse bias direction and allowing current in the forward bias direction. The power semiconductor device may have a unit cell structure, in which the active region of each power semiconductor device includes a plurality of individual unit cell devices that are electrically connected in parallel and function as a single power semiconductor device as a whole.

[0013] Power semiconductor devices are often manufactured from wide-bandgap semiconductor materials, such as silicon carbide or Group III nitride semiconductor materials (e.g., gallium nitride). In this specification, wide-bandgap semiconductor materials refer to semiconductor materials with a bandgap greater than 1.40 eV. Each aspect of this disclosure is discussed with reference to a silicon carbide semiconductor structure as the wide-bandgap semiconductor structure. Those skilled in the art will understand that, using the disclosures provided herein, power semiconductor devices according to exemplary embodiments of this disclosure may be used with any semiconductor material, such as other wide-bandgap semiconductor materials, without departing from the scope of this disclosure. Examples of wide-bandgap semiconductor materials include silicon carbide (e.g., alpha-silicon carbide has a bandgap of 2.996 eV at room temperature) and Group III nitrides (e.g., gallium nitride has a bandgap of 3.36 eV at room temperature).

[0014] Power semiconductor devices can have a lateral or vertical structure. In devices with a lateral structure, the terminals of the device (e.g., the drain, gate, and source terminals of a power MOSFET device) are located on the same main surface of the semiconductor structure (e.g., the top or bottom surface). In contrast, in power semiconductor devices with a vertical structure, at least one terminal is provided on each main surface of the semiconductor structure. For example, in a vertical MOSFET device, the source may be on the top surface of the semiconductor structure and the drain on the bottom surface, or vice versa. In this specification, the term "semiconductor structure" refers to a structure comprising one or more semiconductor layers, such as a semiconductor substrate and / or a semiconductor epitaxial layer.

[0015] Vertical power semiconductor devices, including vertical MOSFETs, can have a standard gate electrode design where the transistor's gate electrode is formed on top of the semiconductor structure. Alternatively, the power semiconductor device may have the gate electrode in a gate trench within the semiconductor structure. Power semiconductor devices with trench gate electrodes are commonly referred to as trench-gate devices (e.g., trench-gate MOSFETs). In a standard gate electrode design, the channel region of each unit cell transistor is located horizontally below the gate electrode. In contrast, in a trench-gate design, the channel is located vertically.

[0016] Currently, power silicon carbide MOSFETs are used in applications requiring high voltage blocking, such as blocking voltages of 5,000 volts or more. For example, they have a current density rating of 10 A / cm² that blocks a minimum voltage of 10 kV. 2 Silicon carbide MOSFETs like the one described above are commercially available. To form such a device, multiple unit cells are formed, each unit cell containing a MOSFET transistor. For high-power applications, typically many of these unit cells (e.g., hundreds or thousands) are arranged on a single semiconductor substrate, and a gate structure (e.g., a gate electrode pattern) is formed on the upper side of the semiconductor substrate, which functions as the gate electrodes for all the unit cells. The opposite side (lower side) of the semiconductor substrate functions as the common drain for all the unit cells of the device. Multiple source contacts are formed on the source region exposed inside the opening in the gate electrode pattern of the semiconductor structure. These source contacts are electrically connected to each other and function as a common source. The resulting device has three terminals that function as terminals for hundreds or thousands of individual unit cell transistors: a common source terminal, a common drain terminal, and a common gate electrode. It should be understood that the above explanation pertains to n-type MOSFETs. In other words, in the case of p-type MOSFETs, the positions of the drain and source are reversed.

[0017] The gate structure of a power MOSFET (e.g., gate electrode pattern) may be realized by forming a patterned conductive layer on a semiconductor structure. The patterned conductive layer may include, for example, a gate pad, one or more gate runners (e.g., a gate bus), and a plurality of elongated gate fingers extending through the active region of the device. In some examples, the patterned conductive layer may include a semiconductor layer, such as a polysilicon layer. The gate pad may be located within the inert region of the device, and each gate finger may be connected directly to the gate pad or via one or more of the gate runners. The gate pad portion of the gate structure may be formed on a thick field insulating layer. The field insulating layer may include, for example, a field oxide layer (e.g., a silicon oxide layer), but other insulating materials or combinations of insulating materials may be used. A metal gate bond pad may be formed on top of a portion of the gate pad, and the gate bond pad may form an ohmic contact with the gate pad. A bond wire may be bonded to the gate bond pad to provide a mechanism for applying a bias voltage to the gate structure of the device.

[0018] As described above, the gate structure and the source, gate, and drain metal layers / bond pads are formed on a semiconductor structure. The semiconductor structure has an active region and an inactive region on which a unit cell transistor is formed. The inactive region may include the gate pad portion beneath the gate bond pad and field insulating layer, the gate runner portion beneath the gate runner and field insulating layer, and a termination portion (e.g., a termination edge portion) that may surround the active region. The gate pad portion of the inactive region of the semiconductor structure beneath the gate pad and field insulating layer may include an implanted region within the upper surface of the semiconductor structure. For example, in an n-type MOSFET, a large p-type silicon carbide region is formed on the upper surface of the semiconductor layer structure by ion implantation, constituting the inactive region. Subsequently, a field insulating layer is formed on this p-type silicon carbide region. During operation, the MOSFET can switch from a reverse-blocking state (a state in which the device blocks a very large voltage and does not allow current to flow) to an on state (a state in which the device allows a large current to flow) in a very short time. When a device switches states, a displacement current is generated (in the case of an n-type device) that flows between the drain terminal on the bottom surface of the device and the source terminal on the top surface.

[0019] In some cases, displacement current can flow within the active region or inactive region (e.g., beneath the gate structure) of the semiconductor structure. In either case, the magnitude of the displacement current (IDisp) is the product of the change in voltage per unit time across the pn junction in the semiconductor layer structure (dV / dt) and the capacitance of this pn junction (Cpn). In other words, IDisp = (dV / dt) * Cpn That is the case.

[0020] In the active region, there are many paths for displacement current (because each unit cell contains a pair of source contacts), and the pn junction is small (because the horizontal width of each p-well constituting the pn junction with the underlying n-type layer may be only about 2 to 3 micrometers). Therefore, the capacitance of the pn junction in the active region is relatively small, and the magnitude of the displacement current in the active region can be reduced. However, in the inert region beneath the gate structure, the aforementioned p-type silicon carbide region formed beneath the field insulating layer may have a length (in each horizontal direction) of, for example, about 100 to 300 micrometers. Therefore, the displacement current generated in this region must flow to the source contact of the unit cell closest to the part beneath the gate structure in the inert region of the semiconductor structure. Consequently, the capacitance of the pn junction in the inert region beneath the gate structure becomes much larger, and as a result, the displacement current can become significantly larger.

[0021] When a displacement current flows, a voltage is generated within the injection region of the semiconductor structure. Based on Ohm's law, the value of this voltage is equal to the product of the displacement current and the resistance of the semiconductor structure along the displacement current path. In silicon carbide semiconductor structures, the injection region tends to have high sheet resistance. In the inert region, the portion beneath the gate structure has high resistance because the injection region is beneath the field insulating layer, and for the reasons mentioned above, the capacitance of the pn junction can be high. Therefore, during device operation, the displacement current flowing through the inert region beneath the gate structure can generate a high voltage within the semiconductor structure. If the generated voltage is sufficiently high, it may exceed the dielectric breakdown voltage of the field insulating layer. When this happens, the field insulating layer may be damaged, potentially leading to device failure.

[0022] In some embodiments, the field insulating layer can be relatively thick. For example, the thickness of the field insulating layer may range from about 600 nanometers to about 800 nanometers, but other thicknesses may be used. However, a thin gate insulating pattern may be provided at the edge of the field insulating layer between the gate electrode pattern and the injection region of the semiconductor layer structure. This gate insulating pattern may include, for example, a silicon oxide pattern, but other insulating materials may be used. Since the gate insulating pattern may be located between the source contact and the field insulating layer, displacement currents generated in the portion beneath the gate structure in the inert region may flow beneath the gate insulating pattern. This gate insulating pattern is considerably thinner than the field insulating layer, and its thickness may be, for example, between about 35 nanometers and about 50 nanometers. In the case of silicon oxide, the dielectric breakdown voltage can be about 12 MV / cm multiplied by the thickness of the oxide. Therefore, the dielectric breakdown voltage of a silicon oxide field insulating layer with a thickness of 600 nanometers is about 720 volts. In contrast, the dielectric breakdown voltage of a silicon oxide gate insulating pattern with a thickness of 35 nanometers is only about 42 volts. As a result, if the dV / dt value received by the device is too high, dielectric breakdown may occur in the thin gate insulation pattern adjacent to the field insulation layer, potentially causing the device to fail.

[0023] The dV / dt characteristic of a semiconductor device refers to the amount of voltage change that the device can withstand over a given period of time. Silicon carbide power MOSFETs are rated to a dV / dt value of approximately 30-80 V / nanosecond; applying a higher dV / dt value may ultimately lead to device failure. To prevent the voltage generated within the thin gate insulation pattern adjacent to the field insulation layer from exceeding its breakdown voltage, the switching speed of the device may be limited (this reduces displacement current).

[0024] In some cases, a considerable amount of displacement current can be generated from the terminal edge of the inert region of a semiconductor structure. In some examples, power semiconductor devices (e.g., MOSFETs and IGBTs) may include one or more source runners located between, for example, the terminal edge of the gate structure on the power semiconductor device and the gate runner. The source runners may be located around at least a portion of the peripheral portion of the semiconductor device. The role of the source runners is to divert the displacement current by collecting it and connecting it directly to a source pad or source terminal, thereby bypassing the active cell of the power semiconductor device.

[0025] In power semiconductor devices that use a MOSFET pn junction body diode as a freewheeling diode in a circuit, the pn junction in the main active region supplies the body diode current. Since the body diode current in the active region is collected in the broad metal region of the body, the stress on the metal is very small. However, in semiconductor devices, the body diode current in the part where the source runner collects displacement current can flow through a narrow, constricted region, resulting in a high current density in the constricted region. When a body diode surge occurs, with an extremely high body diode current and a high junction temperature of the device, the constricted region may burn out, potentially causing device failure.

[0026] The problem of source runner burnout can be mitigated by replacing the source runner with multiple isolated source / drain ohmic contacts formed through (or adjacent to) the field insulating layer, providing a path for displacement currents flowing through the inert region of the device. These additional source / drain ohmic contacts may be referred to, for example, “shunt contact structures” or “dV / dt reduction structures.” The shunt contact structures may be located inside the peripheral gate runners of the gate structure. The shunt contact structures are not a single continuous contact for maintaining metallic connections (e.g., via gate fingers) between the gate runners and active unit cells of the semiconductor device.

[0027] As a result of the shunt contact structure, the voltage level applied to the thin gate insulation pattern can be significantly reduced, allowing for much higher displacement currents without the risk of device failure. Furthermore, since the field insulation layer can be 10 to 20 times thicker than the thin gate insulation pattern, the field insulation layer has a considerably higher dielectric breakdown voltage and can therefore withstand higher displacement currents and body diode surge currents.

[0028] Shunt contact structures can mitigate displacement current and body diode surge problems. However, the displacement current flowing through a semiconductor structure may depend on the size of the non-contact region within the region adjacent to the shunt contact structure, specifically the inert region (e.g., a highly doped p-region) that does not contain the shunt contact structure. Compared to gate runners, gate pads can have larger adjacent non-contact inert regions. In this regard, certain shunt contact structures (e.g., structures adjacent to gate pads) may experience larger displacement currents compared to other shunt contact structures (e.g., structures adjacent to peripheral gate runners).

[0029] According to the exemplary embodiments of this disclosure, the power semiconductor device may include a balanced shunt structure. The balanced shunt structure may be able to reduce the difference in displacement currents flowing through various shunt structures on the power semiconductor device.

[0030] For example, the first shunt contact structure may provide a first shunt path for a first displacement current flowing through a portion of an inert region adjacent to, for example, a gate pad. The second shunt contact structure may provide a second shunt path for a second displacement current flowing through a portion of an inert region adjacent to, for example, a gate runner (e.g., a peripheral gate runner). A balanced shunt structure can reduce the difference between the first and second displacement currents by reducing the difference in their respective effective resistances.

[0031] In some examples, the equilibrium shunt structure may be located at least partially on an inert region. For example, the equilibrium shunt structure may form an ohmic contact with an inert region of the semiconductor structure. The equilibrium shunt structure may be located between the gate runner and the terminal edge portion.

[0032] In some examples, multiple shunt contact structures may be located on the first side of the gate runner (e.g., the active region side of the power semiconductor device). The equilibrium shunt structure may be located on the second side of the gate runner (e.g., the peripheral region side of the power semiconductor device).

[0033] In some examples, multiple shunt contact structures may be electrically coupled to the source pad or source contact of a power semiconductor device. A balanced shunt structure is not coupled to the source pad, source contact, or any other metallic structure of the power semiconductor device. In this way, the balanced shunt structure may function to reduce the difference in effective resistance caused by displacement currents between different parts of the inert region and to balance the displacement currents among the multiple shunt contact structures.

[0034] In some embodiments, the equilibrium shunt structure may be an equilibrium annular structure surrounding at least a portion of the peripheral portion of a semiconductor device. For example, the equilibrium annular structure may at least partially surround one or more peripheral gate runners and gate pads of a power semiconductor device. In some embodiments, the equilibrium annular structure may be discontinuous with one or more breaks. However, in some embodiments, the equilibrium annular structure is a continuous structure without breaks, located around the peripheral portion of a power semiconductor device.

[0035] In some embodiments, the power semiconductor device may include a gate pad located in the central portion of the power semiconductor device. The power semiconductor device may include a pattern consisting of shunt contact structures at least partially surrounding the gate pad. The power semiconductor device may include a balance shunt structure comprising metal pieces extending away from the gate pad toward the peripheral portion of the power semiconductor device. In some examples, the balance shunt structure may include a plurality of metal piece structures forming a grid. The shunt contact structures may be arranged along the plurality of metal piece structures. The balance shunt structure may have other configurations that balance displacement currents between the plurality of shunt contact structures on an inert region without departing from the scope of the present disclosure.

[0036] Each aspect of this disclosure offers numerous technical effects and advantages. For example, a balanced shunt structure may balance displacement current between shunt contact structures used to reduce dV / dt and address surge currents in the body diode. A balanced shunt structure eliminates the source runner connected to the source contact, thereby reducing the impact of displacement current on dV / dt. A balanced shunt structure allows the gate runner to surround or enclose the entire active region of the power semiconductor device, which can lead to a reduction in internal gate resistance and mitigate gate current distribution inhomogeneity.

[0037] While various elements may be described using terms such as "first," "second," etc., in this specification, it should be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, it is possible to refer to the first element as the second element, and similarly, the second element as the first element. As used herein, the terms "and / or" include any combination of one or more of the related enumerated items.

[0038] The terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the invention. As used herein, the singular forms “a, an” and “the” are intended to include the plural unless the context explicitly indicates otherwise. It will be further understood that the terms “comprises, comprising” and / or “includes, including,” as used herein, specify the presence of the described features, numbers, processes, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, numbers, processes, operations, elements, components, and / or groups thereof.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those commonly understood by those skilled in the art in the field to which this invention pertains. Furthermore, terms used herein should be interpreted as having meanings consistent with their meanings in the context of this specification and related technologies, and should not be interpreted in an ideal or overly formal sense unless explicitly defined herein.

[0040] When referring to an element such as a layer, structure, region, or substrate as being "on" or "extending onto" another element, it will be understood that the element may be directly on or extend onto the other element, and that there may be intervening elements, or that it may be partially on the other element. In contrast, when referring to an element as being "directly on" or extending "directly onto" another element, there are no intervening elements, and the intervening elements may be partially directly on the other element. When referring to an element as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, and that there may be intervening elements. In contrast, when referring to an element as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0041] As used herein, if an axis perpendicular to the principal surface of the first structure penetrates both the first and second structures, then the first structure “at least partially overlaps” or “is in an overlapping state” with the second structure. The “peripheral portion” of a structure includes the area close to the periphery of the surface with respect to the geometric center of the surface of the structure. The “central portion” of a structure includes the area close to the geometric center of the surface with respect to the periphery of the surface of the structure. “Approximately perpendicular” means an angle of no more than 15 degrees from the perpendicular. “Approximately parallel” means an angle of no more than 15 degrees from the parallel.

[0042] In this specification, relative terms such as "below," "above," "upper," "lower," "horizontal," "lateral," or "vertical" may be used to describe the relationship between one element, layer, or region and another, as shown in each figure. It should be understood that these terms are intended to encompass different orientations of the device, in addition to the orientation of the device depicted in each figure.

[0043] This specification describes each embodiment of the present disclosure with reference to schematic cross-sectional views of ideal embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be enlarged for clarity. Furthermore, variations in the shape of each figure are to be expected, for example, as a result of manufacturing techniques and / or manufacturing tolerances. Accordingly, each embodiment of the present invention should not be construed as being limited to specific shapes of regions illustrated herein, and should include, for example, deviations in shape due to manufacturing. Similarly, it will be understood that variations in dimensions based on standard deviations in the manufacturing procedure are to be expected. As used herein, “approximately” or “about” includes values ​​within 10% of the nominal value.

[0044] Throughout the entire process, similar numbers refer to similar elements. Therefore, even if a corresponding drawing does not include a description or mention, the same or similar numbers may be explained by referring to other drawings. Similarly, elements not indicated by a reference number may be explained by referring to other drawings.

[0045] Some embodiments of the present invention are described with reference to semiconductor layers and / or semiconductor regions having a conductivity type such as n-type or p-type, which refers to the majority carrier concentration within the layer and / or region. Thus, N-type materials have a majority equilibrium concentration of negatively charged electrons, and P-type materials have a majority equilibrium concentration of positively charged holes. Some materials may be indicated by the addition of "+" or "-" (such as N+, N-, P+, P-, N++, N--, P++, P--) to indicate that the majority carrier concentration is relatively high ("+") or low ("-") compared to other layers or regions. However, such notation does not mean that a particular concentration of majority or minority carriers is present in a given layer or region.

[0046] Each aspect of this disclosure is described with reference to silicon carbide-based transistor devices for illustrative and explanatory purposes. Those skilled in the art will see that, using the disclosures provided herein, some aspects of this disclosure may be applicable to other transistor devices without departing from the scope of this disclosure.

[0047] The drawings and specification disclose representative embodiments and use specific terminology, but these are used solely in a general and descriptive sense and are not intended to limit the scope of the invention as described in the following claims.

[0048] Figure 1 is a plan view of a wafer 10 containing a plurality of power semiconductor devices according to an exemplary embodiment of the present disclosure. Referring to Figure 1, the wafer 10 may be a thin planar structure including a semiconductor structure on which other material layers, such as an insulating layer and / or a metal layer, are formed. The semiconductor structure may include a semiconductor substrate and / or a plurality of other semiconductor layers. A plurality of semiconductor devices 100 may be formed within the wafer 10. The semiconductor devices 100 may be formed in rows and columns, or they may be spaced apart from each other, so that the wafer 10 can later be subjected to a separation process (e.g., dicing) to separate the individual semiconductor devices 100 for packaging and testing. In some embodiments, the wafer 10 may comprise a silicon carbide substrate on which one or more silicon carbide layers are formed (e.g., by epitaxial growth). Power semiconductor devices 100 may be constructed by forming other semiconductor layers (e.g., polysilicon layers), insulating layers, and / or metal layers on the silicon carbide semiconductor structure. In some embodiments, the silicon carbide substrate and the silicon carbide layer formed thereon may be 4H silicon carbide.

[0049] Figure 2A is a plan view of one of the power semiconductor devices 100 contained on the semiconductor wafer 10 of Figure 1. Figure 2B is a schematic plan view of the power semiconductor device 100 of Figure 2A with the source and gate metallization removed. In the following description, the power semiconductor device 100 is assumed to be an n-type power MOSFET. However, those skilled in the art will understand that, using the disclosures provided herein, aspects of this disclosure can be realized in p-type power MOSFETs and other semiconductor devices (e.g., IGBTs, Schottky diodes, etc.) without departing from the scope of this disclosure.

[0050] As shown in Figure 2A, the protective layer 110 covers a substantial portion of the top surface of the power semiconductor device 100. The protective layer 110 may be formed of, for example, polyamide. Various bond pads may be exposed through openings 112 in the protective layer 110. The bond pads may include a gate bond pad 120 and one or more source bond pads 122. Two source bond pads 122-1 and 122-2 are shown in Figure 2A. Although not visible in Figure 2A, a drain bond pad 124 may be provided on the bottom side of the power semiconductor device 100. The bond pads 120, 122, and 124 may be formed of a metal, such as aluminum, that allows for easy bonding of bond wires using techniques such as thermal compression or soldering. The bond pads may be connected to terminals in the semiconductor package to provide the gate terminal, source terminal, and drain terminal of the semiconductor device, respectively. Source contacts are provided that contact the semiconductor structure of the power semiconductor device 100, as detailed below. The source contact may be the lower portion of the source metal pattern 123 that extends over most of the upper surface of the power semiconductor device 100 (for example, the entire upper surface of the power semiconductor device 100 other than the portion occupied by the gate bond pad 120). The source bond pads 122-1 and 122-2 may include portions of the source metal pattern 123 that are exposed by the opening 112 of the protective layer 110. Figure 2A shows bond wires 20 that may be used to connect the gate bond pad 120 and the source bond pads 122-1 and 122-2 to an external voltage source (not shown), such as the terminals of other circuit elements.

[0051] As shown in Figure 2B, the power semiconductor device 100 includes a semiconductor structure comprising an active region 102 and an inactive region 104. The active region 102 is a region of the device that includes an operable transistor (e.g., a unit cell transistor as described herein), while the inactive region 104 is a region that does not include such an operable transistor. The unit cell transistors 200 of the power semiconductor device 100 (see Figures 3-4) are formed within the active region 102. For illustrative purposes, the location of one unit cell 200 is indicated by a square 200 in Figure 2B. In some embodiments, the active region 102 may roughly correspond to the region below the source metal pattern 123. The inactive region 104 includes a gate structure portion 106 and a terminal edge portion 108. The gate structure portion 106 of the inactive region 104 may roughly correspond to a portion of the semiconductor structure below a particular portion of the gate structure of the semiconductor device. The terminal edge portion 108 of the inert region 104 may extend along the periphery of the power semiconductor device 100 and may include one or more termination structures, such as a guard ring and / or junction termination extension, which can mitigate electric field concentration that may occur around the edge of the device. The termination structure (shown as a guard ring 109) can reduce electric field concentration by dispersing the electric field along the periphery of the MOSFET. The termination edge structure functions to increase the reverse blocking voltage at which a phenomenon known as "electron avalanche breakdown" occurs. In this phenomenon, a high electric field can result in a runaway surge of charge carriers within the semiconductor device, causing a rapid increase in current that can damage and even destroy the device.

[0052] As further shown in Figure 2B, a gate structure 130 (e.g., gate electrode pattern) may be provided, including a gate pad 132, a plurality of gate fingers 134, and one or more gate runners 136 (e.g., gate buses) electrically connecting the gate fingers 134 to the gate pad 132. The gate pad 132 of the gate structure 130 may be located beneath the gate bond pad 120. The gate runners 136 may include one or more peripheral gate runners on the inert region 104. The gate runners 136 are peripheral gate runners that extend around or around at least a portion of the peripheral portion of the semiconductor device 100. The gate fingers 134 may extend horizontally across the active region 102. An insulating layer (not shown) may cover the gate fingers 134 and one or more gate runners 136. A source metal pattern 123 is provided on the gate fingers 134 and the insulating layer, and the source contacts of the source metal layer may be in contact with the corresponding source region of the semiconductor structure within the opening between the gate fingers 134.

[0053] Figure 3 is a schematic plan view of a portion of the unit cell 200 of the power semiconductor device 100 shown in Figures 2A-2B. Figure 4 is a schematic cross-sectional view along line 4-4 in Figure 3, illustrating the unit cell structure within the active region of the device. It should be understood that the specific layer structures, doping concentrations, materials, conductivity types, etc., shown in Figures 3-4 and / or described later are provided merely as examples to illustrate in detail the structure of a particular exemplary embodiment. Therefore, the specific details described later do not limit this disclosure.

[0054] Referring to Figures 2A, 2B, 3, and 4, a unit cell 200 is part of the active region 102 of the power semiconductor device 100. A unit cell 200 may be one of several unit cells 200 arranged electrically in parallel. To illustrate the situation, it will be understood that Figure 4 illustrates one complete unit cell 200 and portions of two additional unit cells 200 on either side of it.

[0055] As shown in FIGS. 3 to 4, the power semiconductor device 100, and thus the unit cell 200, includes an n-type wide bandgap semiconductor substrate 210. The substrate 210 may include, for example, a single-crystal 4H silicon carbide semiconductor substrate. The substrate 210 may be heavily doped with n-type impurities (that is, it is an n+ silicon carbide substrate). The impurities may include nitrogen or phosphorus, for example. The doping concentration of the substrate 210 is, for example, 1×10 18 atom / cm 3 to 1×10 21 atom / cm 3 , although other doping concentrations may be used. The substrate 210 may have any suitable thickness, for example, 100 to 500 micrometers.

[0056] A lightly doped n-type (n) silicon carbide drift region 220 is provided on the substrate 210. The n-type silicon carbide drift region 220 may be formed on the silicon carbide substrate 210, for example, by epitaxial growth. The n-type silicon carbide drift region 220 has a doping concentration of, for example, 1×10 16 to 5×10 17 dopant / cm 3 The n-type silicon carbide drift region 220 may be a thick region having a vertical height above the substrate 210 of, for example, 3 to 100 micrometers. In some embodiments, the upper portion of the n-type silicon carbide drift region 220 may include an n-type silicon carbide current spreading layer 230. The n-type silicon carbide current spreading layer 230 may be grown in the same process step as the remaining portion of the n-type silicon carbide drift region 220, and may be considered a part of the n-type silicon carbide drift region 220. The n-type current spreading layer 230 may be a moderately doped current spreading layer 230, and the doping concentration thereof (for example, a doping concentration of 1×10 16 to 5×10 18 dopant / cm 3 ) exceeds the doping concentration of the remaining portion of the lightly doped n-type silicon carbide drift layer 220. The n-type current spreading layer 230 may be omitted in some embodiments.

[0057] The upper part of the n-type current diffusion layer 230 may be doped to the p-type by ion implantation to form p-wells 240. The p-wells 240 may have a doping concentration of, for example, 5 × 10⁻⁶. 16 / cm 3 From 5x10 19 / cm 3 It may be between. The upper part 242 of each p well may be doped with a higher concentration of p-type dopant. The upper part 242 of each p well 240 may have a doping concentration of, for example, 2 × 10⁻⁶. 18 / cm 3 From 1 x 10 20 / cm 3 It may be between these. The p-well 240 (including the upper 242 which is more highly doped) may be formed by ion implantation. Ions such as n-type or p-type dopants may be implanted into the semiconductor layer or semiconductor region by ionizing the desired ion species in the ion implantation target chamber and accelerating the ion as an ion beam toward the surface of the semiconductor layer with a predetermined kinetic energy. Based on the predetermined kinetic energy, the desired ion species can penetrate into the semiconductor layer to a specific depth.

[0058] A highly doped (n+)n-type silicon carbide source region 250 may be formed on the upper part of the p-well 240, directly adjacent to and in contact with a more highly doped portion 242 of the p-well 240. The n-type source region 250 may also be formed by ion implantation. The highly doped (n+)n-type silicon carbide region 250 functions as the source region of a unit cell transistor. The drift region 220 / current diffusion layer 230 and the substrate 210 together function as the common drain region of the power semiconductor device 100.

[0059] The n-type silicon carbide substrate 210, the n-type silicon carbide drift region 220 / current diffusion layer 230, the p-wells 240, 242, and the n-type source region 250 formed therein may together constitute the semiconductor structure of the semiconductor device 100.

[0060] The gate insulation pattern 260 is located on the upper surface of the semiconductor layer structure, above the exposed portion of the current diffusion layer 230, and may extend over the periphery of the p-well 240 and the n-type source region 250. The gate insulation pattern 260 may include, for example, a silicon oxide layer, but other insulating materials may be used. The gate fingers 270 are located on the gate insulation pattern 260. The gate fingers 270 may correspond to one of the gate fingers 134 illustrated in Figure 2B above. Thus, it will be understood that the gate fingers 270 may be part of a continuous gate structure including a gate pad 132, one or more gate runners 136, and a plurality of gate fingers 270. In some embodiments, this gate structure may include, for example, a semiconductor pattern (e.g., polysilicon) or a metal gate pattern.

[0061] A source contact 280 may be located on a highly doped n-type source region 250 and a more highly doped portion 242 of the p-well. As described above with reference to Figures 2A-2B, the source contact 280 may be part of a continuous source pattern 123 extending across the upper surface of the silicon carbide semiconductor layer structure. For the sake of simplicity, the rest of the source pattern 123 (and the insulating layer electrically insulating the gate finger 270 from the source pattern 123) is not shown in Figures 3-4. The source contact 280 may include, for example, a metal such as nickel, titanium, tungsten, or aluminum, or an alloy or thin film laminate of these materials or similar materials. As described above, the drain contact 124 may be located on the lower surface of the substrate 210. Since the drain contact 124 forms an ohmic contact with the silicon carbide substrate, it may include, for example, a material similar to that of the source contact. The power semiconductor device 100 is an n-type device with the source contact 280 on the top surface and the drain contact 124 on the bottom surface, but it should be understood that in a p-type device, these positions are reversed.

[0062] Within the p-well 240, a horizontal channel region 272 is formed adjacent to the gate isolation pattern 260. When a voltage is applied to the gate finger 270, current can flow from the n-type source region 250 through the channel region 272 and into the portion of the drift region 220 / current diffusion layer 230 beneath the gate finger 270, as indicated by the arrows in Figure 4.

[0063] Figure 4 shows a unit cell with a gate finger 270 formed on a semiconductor structure for illustrative and explanatory purposes. Alternatively, the unit cell may have a gate finger 270 that is at least partially located within a gate trench in the semiconductor structure.

[0064] Figure 5 shows a plan view of an exemplary power semiconductor device 300. Figure 6 shows a cross-sectional view of the power semiconductor device 300 of Figure 6 along line 6-6. The power semiconductor device 300 is similar to the power semiconductor device 100 shown in Figures 1-4. For example, the power semiconductor device 300 includes an active region 302 having a plurality of unit cell devices. Each unit cell device may be a silicon carbide-based MOSFET, such as the unit cell device 200 described with reference to Figure 4. The power semiconductor device 300 includes an inert region. The inert region may be located below the gate structure 330 and may include a terminal edge region 308.

[0065] The power semiconductor device 300 includes a gate structure 330. The gate structure 330 includes a gate pad 332 and a peripheral gate runner 336. The peripheral gate runner 336 may be located around or near at least a portion of the peripheral portion of the power semiconductor device 300. As shown in Figure 6, the peripheral gate runner 336 may be on top of a field insulating layer 335. The field insulating layer 335 may be an oxide layer, such as an SiOx layer. The thickness of the field insulating layer 335 beneath the gate pad portion 332 and one or more gate runners 336 may be greater than the thickness of the gate insulating pattern 260 beneath the gate finger 270 in the active region 302. The thickness of the field insulating layer 335 may be between about 600 nanometers and about 800 nanometers, but other thicknesses may be used without departing from the scope of this disclosure.

[0066] The field insulating layer 335 may be located on the p-well region 310. The p-well region 310 may constitute part of the inert region of the semiconductor structure. The p-well region 310 may be a second conductivity type different from the first conductivity type associated with the drift region 220 and the substrate 210. The p-well region 310 may have a doping concentration of, for example, 5 × 10⁻¹⁶. 16 / cm 3 From 5x10 19 / cm 3 It may be between these points. The p-well region 310 may be formed by ion implantation.

[0067] As shown in Figures 5 and 6, the power semiconductor device 300 may include a source runner 338 located adjacent to the peripheral gate runner 336. The source runner 338 may be connected (e.g., electrically connected) to, for example, the source pad and / or source terminal associated with the power semiconductor device 300. The source runner 338 may be located between the peripheral gate runner 336 and the peripheral edge of the semiconductor device 300. The source runner 338 may be located between the peripheral gate runner and the terminal edge region 308 of the power semiconductor device 300. The source runner 338 may be in ohmic contact with the p-well region 310 of the inert region of the semiconductor structure. The source runner 338 may be nickel, titanium, tungsten, aluminum, or an alloy or thin film laminate of these materials or similar materials.

[0068] The source runner 338 may be used to protect unit cells within the active region 302 from displacement current. For example, as shown in Figure 6, when the power semiconductor device 300 is turned on, the displacement current 340 flows from the drain contact 324 to the source runner 338. In this way, the source runner 338 can provide a shunt path for the displacement current that protects unit cells in the active region 302 or other forms of the power semiconductor device 300 from the displacement current 340. More specifically, the source runner 338 bypasses unit cells within the active region 302 by collecting excess displacement current and connecting it directly to the source pad or source terminal of the semiconductor device 300.

[0069] In some applications, the pn junction of the power semiconductor device 300 may be used as a freewheeling diode in the power circuit. More specifically, as shown in Figure 7, the pn junction within a unit cell in the active region 302 can supply diode current 342 from the source contact 280. However, the source runner 338 also contributes to the diode current 342 with the same current density. Within the active region 302, the diode current 342 is collected on the main broad body metal of the source pad or source terminal of the power semiconductor device 300. However, the diode current 342 in the region of the source runner 338 may also be collected and discharged through a narrow, constricted region, such as the constricted region 345 shown in Figure 8. The current density in the constricted region 345 can be very high. In the event of a body diode surge, where the body diode current is extremely high and the junction temperature of the power semiconductor device 300 is also high, the constricted region 345 may burn out, resulting in performance degradation.

[0070] To address this problem, in some applications, power semiconductor devices may include multiple shunt contact structures or dV / dt reduction structures instead of source runners to provide a path for displacement current that passes through the inert region of the power semiconductor device and is separated from the unit cell in the active region. In some examples, the shunt contact structures may be located inside the peripheral gate runner of the gate structure. The shunt contact structures are not a single continuous contact for maintaining a metallic connection (e.g., via gate fingers) between the gate runner and the active unit cell of the semiconductor device.

[0071] For example, Figure 9 shows a plan view of an exemplary power semiconductor device 350 in which multiple shunt contact structures 355 are located inside the peripheral gate runner 336. Figure 10 shows a cross-sectional view of the power semiconductor device 350 along line A-A'. Figure 11 shows a cross-sectional view of the power semiconductor device 350 along line B-B'. The power semiconductor device 350 does not include a source runner.

[0072] Similar to the power semiconductor device 300 in Figures 4-8, the power semiconductor device 350 includes an active region 302 having a plurality of unit cell devices. Each unit cell device may be a silicon carbide-based MOSFET unit cell, such as the unit cell device 200 described with reference to Figure 4. The power semiconductor device 350 includes an inactive region. The inactive region may include a region below at least a portion of the gate structure 330 and may include a termination edge region 308.

[0073] The power semiconductor device 300 includes a gate structure 330. The gate structure 330 includes a gate pad 332 and a peripheral gate runner 336. The peripheral gate runner 336 may be located around or near at least a portion of the peripheral portion of the power semiconductor device 350. As shown in Figure 10, the peripheral gate runner 336 may be on top of a field insulating layer 335. As shown in Figure 11, the gate pad 332 may be on top of the field insulating layer 335. The field insulating layer 335 may be an oxide layer, such as a SiOx layer. The thickness of the field insulating layer 335 beneath the gate pad portion 332 and one or more gate runners 336 may be greater than the thickness of the gate insulating pattern 260 beneath the gate finger in the active region 302. The thickness of the field insulating layer 335 may be between about 600 nanometers and about 800 nanometers, but other thicknesses may be used without departing from the scope of this disclosure.

[0074] The field insulating layer 335 may be located on the p-well region 310. The p-well region 310 may constitute part of the inert region of the semiconductor structure. The p-well region 310 may be a second conductivity type different from the first conductivity type associated with the drift region 220 and the substrate 210. The p-well region 310 may have a doping concentration of, for example, 5 × 10⁻¹⁶. 16 / cm 3 From 5x10 19 / cm 3 It may be between these points. The p-well region 310 may be formed by ion implantation.

[0075] The shunt contact structure 355 may extend along the edge of the gate structure 330, which includes the gate pad 332 and the peripheral gate runner 336. For example, the shunt contact structure 355 may be located adjacent to the peripheral gate runner 336 and the gate pad 332. For example, the shunt contact structure 355 may be located between the peripheral gate runner 336 and the central portion of the semiconductor device 350. The shunt contact structure 355 may be located between the gate pad 332 and the central portion of the semiconductor device 350. As shown in Figure 9, multiple shunt contact structures 355 may be arranged at least partially annularly adjacent to the gate structure 330. The multiple shunt contact structures 355 are not a single continuous contact (e.g., separate structures) to accommodate the electrical connection between the gate runner 336 and the gate finger of the active region 302.

[0076] As shown in Figures 10 and 11, the shunt contact structure 355 may penetrate or extend through the field insulating layer 335. The shunt contact structure 355 may also be in ohmic contact with the p-well region 310 of the inert region of the semiconductor structure. Each of the multiple shunt contact structures 355 may be electrically connected to the source pad and / or source terminal of the power semiconductor device 350. The shunt contact structure 355 may be, for example, nickel, titanium, tungsten, aluminum, or an alloy or thin film laminate of these materials or similar materials.

[0077] When the power semiconductor device 350 is turned on, the displacement current 360 flows from the drain contact 324 into shunt paths within the multiple shunt contact structures 355. In this way, each of the shunt contact structures 355 can provide a shunt path for the displacement current that protects the unit cell of the active region 302 or other forms of the power semiconductor device 300 from the displacement current 360.

[0078] Multiple shunt contact structures 355 can reduce the surge problem of the body diode, but they can lead to an uneven distribution of displacement current. For example, Figure 10 shows a cross-sectional view of a power semiconductor structure 350 showing a shunt contact structure 355 adjacent to a gate runner 336. The shunt contact structure 355 in Figure 10 provides a first shunt path for a first displacement current 360. Figure 11 shows a cross-sectional view of a power semiconductor device 350 showing a shunt contact structure 355 adjacent to a gate pad 332 of a gate structure 330. The shunt contact structure 355 provides a second shunt path for a second displacement current 370.

[0079] The magnitude of the displacement current may depend on the size of the p-well region 310 that is not in contact with the shunt contact structure 355. The size of the p-well region 310 adjacent to the gate pad 332 in the semiconductor device 350 is larger than the size of the p-well region 310 adjacent to the gate runner 336 in the semiconductor device 350. In this regard, the displacement current 370 flowing through the shunt path shown in Figure 11 may be significantly larger than the displacement current 360 flowing through the shunt path shown in Figure 10.

[0080] According to exemplary embodiments of this disclosure, a power semiconductor device may include a balanced shunt structure that balances or reduces the difference in displacement currents flowing through various shunt paths through a shunt contact structure of the semiconductor device. The balanced shunt contact structure is not connected to a source terminal, source contact, gate terminal, gate structure, or other metallic structure.

[0081] For example, Figure 12 shows a power semiconductor device 400 according to an exemplary embodiment of the present disclosure. Figure 13 shows a cross-sectional view of the power semiconductor device 400 along line 13-13. The power semiconductor device 400 does not include a source runner.

[0082] Similar to the power semiconductor device 300 in Figures 4-8, the power semiconductor device 400 includes an active region 302 having a plurality of unit cell devices. Each unit cell device may be a silicon carbide-based MOSFET unit cell, such as the unit cell device 200 described with reference to Figure 4. The power semiconductor device 400 includes an inactive region. The inactive region may be located below the gate structure 430 and may include a termination edge region 408.

[0083] The power semiconductor device 400 includes a gate structure 430. The gate structure 430 includes a gate pad 432 and a peripheral gate runner 436. The peripheral gate runner 436 may be located around or near at least a portion of the peripheral portion of the power semiconductor device 400. As shown in Figure 13, the peripheral gate runner 436 may be on top of a field insulating layer 435. The field insulating layer 435 may be an oxide layer, such as a SiOx layer. The thickness of the field insulating layer 435 beneath the gate pad portion 432 and one or more gate runners 436 may be greater than the thickness of the gate insulating pattern 260 beneath the gate finger in the active region 402. The thickness of the field insulating layer 435 may be between about 600 nanometers and about 800 nanometers, but other thicknesses may be used without departing from the scope of this disclosure.

[0084] The field insulating layer 435 may be located on the p-well region 410. The p-well region 410 may constitute part of the inert region of the semiconductor structure. The p-well region 410 may be a second conductivity type different from the first conductivity type associated with the drift region 220 and the substrate 210. The p-well region 310 may have a doping concentration of, for example, 5 × 10⁻¹⁶. 16 / cm 3 From 5x10 19 / cm 3 It may be between these points. The p-well region 310 may be formed by ion implantation.

[0085] The shunt contact structure 455 may be located adjacent to the peripheral gate runner 436 and the gate pad 432. For example, the shunt contact structure 455 may be located between the peripheral gate runner 436 and the central portion of the semiconductor device 400. The shunt contact structure 455 may be located between the gate pad 432 and the central portion of the semiconductor device 400. For example, as shown in Figure 12, multiple shunt contact structures 455 may be arranged at least partially annularly adjacent to the gate structure 430. The multiple shunt contact structures 455 are not a single continuous contact (e.g., separate structures) to accommodate the electrical connection between the gate runner 436 and the gate finger of the active region 402.

[0086] As shown in Figure 13, the shunt contact structure 455 may penetrate or extend through the field insulating layer 435. The shunt contact structure 455 may also be in ohmic contact with the p-well region 410 of the inert region of the semiconductor structure. Multiple shunt contact structures 455 may each be electrically connected to the source contact of the power semiconductor device 400. The shunt contact structure 455 may be, for example, nickel, titanium, tungsten, or aluminum, or an alloy or thin film laminate of these materials or similar materials.

[0087] The multiple shunt contact structures 455 may include a first shunt contact structure 455.1 on the p-well region 410 and a second shunt contact structure 455.2 on the p-well region 410. The first shunt contact structure 455.1 may be adjacent to the gate runner 436. The second shunt contact structure 455.2 may be adjacent to the gate pad 432 of the gate structure 430. The first shunt contact structure 455.1 may provide a first shunt path for displacement current (e.g., displacement current 460 in Figure 13). The second shunt contact structure 455.2 may provide a second shunt path for displacement current.

[0088] The power semiconductor device 400 includes an equilibrium shunt structure 450 located at least partially on an inert region (for example, directly above the p-well region 410). The equilibrium shunt contact structure 450 may also be located directly above the p-well region 410. The equilibrium shunt structure 450 may provide ohmic contact with the p-well region 410. The equilibrium shunt structure 450 is made of a conductive material, such as a metal. In some examples, the equilibrium shunt structure 450 is nickel, titanium, tungsten, aluminum, copper, gold, n-type or p-type polysilicon, one or more metal silicides, or an alloy or thin film laminate of these materials or similar materials.

[0089] In some embodiments, the balanced shunt contact structure 450 is located between the peripheral gate runner 436 and the peripheral edge of the semiconductor device 400. In some embodiments, the balanced shunt contact structure 450 is located between the gate runner 436 and the terminal edge region 408.

[0090] As shown in Figure 13, the shunt contact structure 455 may be adjacent to the first side of the gate runner 436. The equilibrium shunt structure 450 may be adjacent to the second side of the gate runner 436, on the opposite side of the first side of the gate runner 436.

[0091] The balanced shunt structure 450 does not have to be electrically connected to the source pad or source terminal of the power semiconductor device 400. For example, the shunt contact structure 455 (e.g., the first shunt contact structure 455.1 and the second shunt contact structure 455.2) may be electrically connected to the source terminal or source pad of the power semiconductor device 400. However, the balanced shunt structure 450 is not connected to the source terminal, source pad, gate structure 430, or any other metallic structure.

[0092] The balanced shunt structure 450 is operable to balance the effective resistance of the shunt path for displacement currents flowing through the shunt contact structure 455. The balanced shunt structure 450 is connected to an inert region (e.g., a p-well region 410) near both the gate pad 432 and the gate runner 436, and by effectively acting as a low-value parallel resistance, it balances the effective resistance of the displacement currents flowing through the p-well region 410 in the portion of the semiconductor device 400 adjacent to the gate pad 432 and the p-well region 410 in the portion of the semiconductor device 400 adjacent to the gate runner 436. Thus, the balanced shunt structure 450 reduces the difference between the displacement currents flowing through the shunt paths in the various shunt contact structures 455 of the power semiconductor device 400. For example, the balanced shunt structure 450 reduces the difference between the first displacement current flowing through the first shunt contact structure 455.1 adjacent to the gate pad 432 and the second displacement current flowing through the second shunt contact structure 455.2 adjacent to the gate runner 436.

[0093] The equilibrium shunt structure 450 in the power semiconductor device 400 illustrated in Figures 11 and 12 is an equilibrium annular structure (e.g., a circular annular structure) located around at least a portion of the peripheral gate runner 436. The equilibrium annular structure 450 is a continuous annular structure without breaks, located on the peripheral portion of the power semiconductor device 400. The equilibrium shunt structure 450 is illustrated as having sharp edges and corners. In some examples, the equilibrium shunt structure 450 may include one or more curved portions and rounded corners. The equilibrium shunt structure 450 may have other suitable shapes or configurations without departing from the scope of the present disclosure.

[0094] For example, Figure 14 shows a plan view of an exemplary power semiconductor device 500 according to an exemplary embodiment of the present disclosure. The power semiconductor device 500 may be similar to the power semiconductor device 400 shown in Figures 12 and 13. However, the power semiconductor device 500 of Figure 14 may include a balance shunt structure 450 that is not a continuous annular structure. More specifically, the balance shunt structure 450 is a discontinuous annular structure having a plurality of cuts 452. One cut 452 represents a gap within the balance shunt structure 450. The balance shunt structure may be around at least a portion of the peripheral portion of the power semiconductor device 500. The power semiconductor device 500 does not include a source runner.

[0095] As shown in Figure 14, the balanced shunt structure may have a first portion 472 extending over a portion of the semiconductor device 100 adjacent to the gate pad 432. The first portion 472 of the balanced structure 450 may extend around the corners of the peripheral gate runner 436 and / or the semiconductor device 500. The balanced shunt structure 450 may have a second portion 474 located at a corner of the power semiconductor device 500. The balanced shunt structure may have a third portion 476 located at another corner of the power semiconductor device 500. The second portion 474 and the third portion 476 of the balanced shunt structure 450 may each extend around a corner of the gate runner 436. The balanced shunt structure 450 in Figure 14 can balance any difference in displacement currents of the shunt path flowing through the shunt structure 455 adjacent to the corner of the peripheral gate runner 436.

[0096] Figure 15 shows a plan view of an exemplary power semiconductor device 550 according to an exemplary embodiment of the present disclosure. The power semiconductor device 500 may be similar to the power semiconductor device 450 shown in Figure 14, except that the power semiconductor device 550 of Figure 15 may include a balanced shunt structure 450 that does not extend around the entire gate structure 430. The balanced shunt structure 450 may have a conductive piece 482 that extends over a portion of the semiconductor device 100 adjacent to the gate pad 432. The balanced shunt structure 450 may include a first leg 484 extending from the conductive piece 482 (for example, typically vertically). The balanced shunt structure 450 may include a second leg 486 extending from the conductive piece 482 (for example, typically vertically). The first leg 484 and / or the second leg 486 may be longer or shorter without departing from the scope of the present disclosure. The power semiconductor device 550 does not include a source runner.

[0097] Figure 16 shows a plan view of an exemplary power semiconductor device 575. For example, the power semiconductor device 575 includes an active region 602 having a plurality of unit cell devices. Each unit cell device may be a silicon carbide-based MOSFET unit cell, such as the unit cell device 200 described with reference to Figure 4. The power semiconductor device 575 includes an inert region. The inert region may be located below the gate structure and may include a termination edge region 608.

[0098] The power semiconductor device 575 includes a gate structure having a gate pad 632 in the central portion of the power semiconductor device 575. In some examples, the power semiconductor device may include one or more peripheral gate runners 636 around at least a portion of the peripheral portion of the power semiconductor device 600. However, in some examples, there are no peripheral gate runners. Similar to the embodiments described above, the gate structure including the gate pad 632 and / or peripheral gate runners 636 may be on a field insulating layer or on the p-well region of the semiconductor device 575. The power semiconductor device 575 does not include a source runner.

[0099] The power semiconductor device 575 may include a plurality of shunt contact structures 655 around at least a portion of the gate pad 632 (for example, in an annular shape surrounding the gate pad 632 in the central portion of the semiconductor device 575). The shunt contact structures 655 may be in direct contact with the p-well region of the semiconductor device 600. The shunt contact structures 655 may provide ohmic contact with the semiconductor structure of the semiconductor device 600. The shunt contact structures 655 may be located between the gate pad portion 632 and the peripheral gate runner 636. The shunt contact structures 655 may be connected to the source terminal or source pad of the power semiconductor device 650. The shunt contact structures 655 provide a shunt path for displacement current.

[0100] Figure 17 shows a plan view of an exemplary power semiconductor device 600. For example, the power semiconductor device 600 includes an active region 602 having a plurality of unit cell devices. Each unit cell device may be a silicon carbide-based MOSFET unit cell, such as the unit cell device 200 described with reference to Figure 4. The power semiconductor device 600 includes an inert region. The inert region may be located below the gate structure and may include a termination edge region 608.

[0101] The power semiconductor device 600 includes a gate structure having a gate pad 632 in the central portion of the power semiconductor device 600. In some examples, the power semiconductor device may include one or more peripheral gate runners 636 around at least a portion of the peripheral portion of the power semiconductor device 600. However, in some examples, there are no peripheral gate runners. As in the embodiments described above, the gate structure including the gate pad 632 and / or peripheral gate runners 636 may be located on a field insulating layer or on the p-well region of the semiconductor device 600.

[0102] According to an exemplary embodiment, the power semiconductor device 600 may include a plurality of shunt contact structures 655. The shunt contact structures 655 may be in direct contact with the p-well region of the semiconductor device 600. The shunt contact structures 655 may provide ohmic contact with the semiconductor structure of the semiconductor device 600. The shunt contact structures 655 may be located between the gate pad portion 632 and the peripheral gate runner 636. The shunt contact structures 655 may be connected to the source terminal or source pad of the power semiconductor device 650. The shunt contact structures 655 provide a shunt path for displacement current.

[0103] The power semiconductor device 600 includes a balanced shunt structure 650. The balanced shunt structure 650 may be located between the gate pad portion 632 and the peripheral gate runner 636. In the example in Figure 6, the balanced shunt structure 650 includes one or more metal pieces that extend at least partially from the gate pad 632 toward the peripheral portion of the semiconductor device. The balanced shunt structure 650 may balance the displacement currents flowing through a plurality of shunt contact structures 655. The balanced shunt structure 650 is a conductive material, such as a metal. In some examples, the balanced shunt structure 650 is nickel, titanium, tungsten, aluminum, copper, gold, n-type or p-type polysilicon, one or more metal silicides, or an alloy or thin film laminate of these materials or similar materials.

[0104] The equilibrium shunt structure 650 includes a plurality of intersecting metal pieces arranged in a grid pattern around the gate pad 632. For example, the equilibrium shunt structure 650 includes a first metal piece 652 extending in a direction parallel to the first side of the gate pad 632. The equilibrium shunt structure 650 includes a second metal piece 654 extending in a direction parallel to the second side of the gate pad 632. The equilibrium shunt structure 650 includes a third metal piece 656 extending in a direction parallel to the third side of the gate pad 632. The equilibrium shunt structure includes a fourth metal piece 658 extending in a direction parallel to the fourth side of the gate pad 632. The first metal piece 652 and the second metal piece 654 intersect with the third metal piece 656 at different positions. The first metal piece 652 and the second metal piece 654 intersect with the fourth metal piece 658 at different positions. The first metal piece 652 and the second metal piece 654 do not intersect and / or may be substantially parallel to each other. The third metal piece 656 and the fourth metal piece 658 do not intersect and / or may be substantially parallel to each other.

[0105] Multiple shunt contact structures 655 may be arranged along the metal pieces of the equilibrium shunt structure 650. For example, in some examples, the multiple shunt contact structures may include one or more first shunt contact structures 655.1 on the first side of one of the multiple metal pieces (e.g., metal piece 654). The multiple shunt contact structures 655 may include one or more second shunt contact structures 655.2 on the second side of one of the multiple metal pieces (e.g., metal piece 654), opposite to the first side. In some examples, at least some of the multiple shunt contact structures 650 may be arranged at different distances from the gate pad 632. For example, the first shunt contact structure 655.1 may be located at a different distance from the gate pad 632 than the second shunt contact structure 655.2.

[0106] As described above, the multiple shunt contact structures 655 may be connected to the source pad of the power semiconductor device 600. The balanced shunt structure 650 is not connected to the source pad, gate structure, or any other metallic structure of the power semiconductor device 600. The power semiconductor device 600 does not include a source runner.

[0107] An exemplary embodiment of the present disclosure relates to a power semiconductor device. The power semiconductor device includes a semiconductor structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells. The power semiconductor device includes a gate structure, at least a portion of which lies on the inactive region. The power semiconductor device includes a first shunt contact structure which lies at least partially on the inactive region. The power semiconductor device includes a second shunt contact structure which lies at least partially on the inactive region. The power semiconductor device includes an equilibrium shunt structure which lies at least partially on the inactive region.

[0108] In some embodiments, a first shunt contact structure provides a first shunt path for a first displacement current flowing through an inert region, a second shunt contact structure provides a second shunt path for a second displacement current flowing through an inert region, and a balanced shunt structure reduces the difference between the first displacement current flowing through the first shunt path and the second displacement current flowing through the second shunt path.

[0109] In some embodiments, the first shunt contact structure is adjacent to the first side of the gate structure, and the equilibrium shunt structure is adjacent to the second side of the gate structure, with the second side being opposite to the first side.

[0110] In some embodiments, the equilibrium shunt structure is located between the gate structure and the terminal edge region.

[0111] In some embodiments, at least a portion of the equilibrium shunt structure lies directly above the inert region of the semiconductor structure.

[0112] In some embodiments, the first shunt contact structure and the second shunt contact structure are connected to the source terminal of the power semiconductor device.

[0113] In some embodiments, the balanced shunt structure is not connected to the source terminal.

[0114] In some embodiments, the gate structure comprises a gate pad and a gate runner.

[0115] In some embodiments, the first shunt contact structure is adjacent to the gate pad, and the second shunt contact structure is adjacent to the gate runner.

[0116] In some embodiments, the gate runner is a peripheral gate runner located around at least a portion of the peripheral portion of the power semiconductor device.

[0117] In some embodiments, the equilibrium shunt structure comprises an equilibrium annular structure located around at least a portion of the peripheral gate runner.

[0118] In some embodiments, the equilibrium annular structure comprises a discontinuous annular structure having one or more cut sections.

[0119] In some embodiments, the balanced annular structure is a continuous structure without breaks.

[0120] In some embodiments, the gate pad is located within the peripheral portion of the power semiconductor device.

[0121] In some embodiments, the gate pad is located within the central portion of the power semiconductor device.

[0122] In some embodiments, the first shunt contact structure is located at a first distance from the gate pad, and the second shunt contact structure is located at a second distance from the gate pad, where the first distance is different from the second distance.

[0123] In some embodiments, at least a portion of the equilibrium shunt structure is located between the first shunt contact structure and the second shunt contact structure.

[0124] In some embodiments, at least a portion of the equilibrium shunt structure is located between the gate pad and the first shunt contact structure.

[0125] In some embodiments, the equilibrium shunt structure comprises multiple metal pieces that intersect with one another.

[0126] In some embodiments, the semiconductor device further comprises a field insulating layer over at least a portion of the inert region.

[0127] In some embodiments, the field insulating layer is located between at least a portion of the gate structure and the inert region.

[0128] In some embodiments, the first shunt contact structure, the second shunt contact structure, and the equilibrium shunt structure extend through the field insulating layer.

[0129] In some embodiments, the power semiconductor device does not have a source runner within the peripheral portion of the power semiconductor device.

[0130] In some embodiments, the first shunt contact structure and the second shunt contact structure are part of a plurality of shunt contact structures that are arranged at least partially annularly adjacent to the gate structure.

[0131] In some embodiments, the semiconductor structure comprises a wide-bandgap semiconductor.

[0132] In some embodiments, the semiconductor structure comprises silicon carbide.

[0133] In some embodiments, a plurality of unit cells comprises one or more silicon carbide-based MOSFET transistor cells.

[0134] Another exemplary embodiment of the present disclosure relates to a power semiconductor device. The power semiconductor device includes a semiconductor structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells. The power semiconductor device includes a field insulating layer at least partially on the inactive region. The power semiconductor device includes a gate structure at least partially on the field insulating layer. The power semiconductor device includes a shunt contact structure extending at least partially through the field insulating layer. The power semiconductor device includes an equilibrium shunt structure at least partially on the inactive region.

[0135] In some embodiments, the shunt contact structure is electrically connected to the source pad of the power semiconductor device, while the balanced shunt structure is not electrically connected to the source pad.

[0136] In some embodiments, the equilibrium shunt structure comprises an equilibrium annular structure located around at least a portion of the gate runner.

[0137] In some embodiments, the equilibrium annular structure comprises a discontinuous annular structure having one or more cut sections.

[0138] In some embodiments, the equilibrium annular structure is a continuous annular structure without a break.

[0139] In some embodiments, the equilibrium shunt structure is located between the gate structure and the terminal edge region.

[0140] In some embodiments, at least a portion of the equilibrium shunt structure is in direct contact with an inert region of the semiconductor structure.

[0141] In some embodiments, the balanced shunt structure is operable to reduce the resistance associated with the shunt contact structure.

[0142] In some embodiments, the equilibrium shunt structure is a metal piece located between the gate pad and the peripheral portion of the power semiconductor device.

[0143] In some embodiments, the semiconductor structure comprises a wide-bandgap semiconductor.

[0144] In some embodiments, the semiconductor structure comprises silicon carbide.

[0145] In some embodiments, a plurality of unit cells comprises one or more silicon carbide-based MOSFET transistor cells.

[0146] Another exemplary embodiment of the present disclosure relates to a power semiconductor device. The power semiconductor device includes a semiconductor structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells. The power semiconductor device includes a gate structure, at least a portion of which lies on the inactive region. The power semiconductor device includes a plurality of shunt contact structures, at least partially on the inactive region. The power semiconductor device includes a balance shunt structure, at least partially on the inactive region. The balance shunt structure is operable to balance the displacement currents associated with the plurality of shunt contact structures.

[0147] In some embodiments, multiple shunt contact structures are adjacent to the first side of the gate structure, and equilibrium shunt structures are adjacent to the second side of the gate structure, with the second side being on the opposite side from the first side.

[0148] In some embodiments, the equilibrium shunt structure is located between the gate structure and the terminal edge region.

[0149] In some embodiments, at least a portion of the equilibrium shunt structure lies directly above the inert region.

[0150] In some embodiments, multiple shunt contact structures are electrically connected to the source pads of a power semiconductor device, while a balanced shunt structure is not electrically connected to the source pads.

[0151] In some embodiments, the gate structure comprises a gate pad and a gate runner.

[0152] In some embodiments, the shunt contact structure comprises a first shunt contact structure adjacent to the gate pad and a second shunt contact structure adjacent to the gate runner.

[0153] In some embodiments, the gate runner is a peripheral gate runner located around at least a portion of the peripheral portion of the power semiconductor device.

[0154] In some embodiments, the equilibrium shunt structure comprises an equilibrium annular structure located around at least a portion of the peripheral gate runner.

[0155] In some embodiments, the equilibrium annular structure comprises a discontinuous annular structure having one or more cut sections.

[0156] In some embodiments, the balanced annular structure is a continuous structure without breaks.

[0157] In some embodiments, the gate pad is located within the peripheral portion of the power semiconductor device.

[0158] In some embodiments, the gate pad is located within the central portion of the power semiconductor device.

[0159] In some embodiments, the equilibrium shunt structure comprises a plurality of metal pieces arranged in a grid.

[0160] In some embodiments, the semiconductor device comprises a field insulating layer over at least a portion of the inert region.

[0161] In some embodiments, the field insulating layer is located between at least a portion of the gate structure and the inert region.

[0162] In some embodiments, multiple shunt contact structures and equilibrium shunt structures extend through a field insulating layer.

[0163] In some embodiments, the power semiconductor device does not include a source runner.

[0164] In some embodiments, multiple shunt contact structures are arranged at least partially annularly adjacent to the gate structure.

[0165] In some embodiments, the semiconductor structure comprises a wide-bandgap semiconductor.

[0166] In some embodiments, the semiconductor structure comprises silicon carbide.

[0167] In some embodiments, a plurality of unit cells comprises one or more silicon carbide-based MOSFET transistor cells.

[0168] Another exemplary embodiment of the present disclosure relates to a power semiconductor device. The power semiconductor device includes a semiconductor structure comprising an active region and an inactive region, the active region comprising a plurality of unit cells. The power semiconductor device includes a gate pad located in the central portion of the power semiconductor device. The power semiconductor device includes a plurality of shunt contact structures at least partially surrounding the gate pad.

[0169] In some embodiments, the semiconductor device includes a balanced shunt structure, which comprises a metal piece located between the gate pad and the peripheral portion of the power semiconductor device.

[0170] In some embodiments, the equilibrium shunt structure comprises multiple metal pieces between the gate pad and the peripheral portion of the power semiconductor device.

[0171] In some embodiments, the plurality of metal pieces comprises a first metal piece and a second metal piece, and the first metal piece and the second metal piece intersect each other.

[0172] In some embodiments, the power semiconductor device comprises a plurality of shunt contact structures extending along at least a portion of a metal piece.

[0173] In some embodiments, multiple shunt contact structures are electrically connected to the source terminals of a power semiconductor device, while a balanced shunt structure is not electrically connected to the source terminals.

[0174] In some embodiments, the shunt contact structure comprises a first shunt contact structure located at a first distance from the gate pad and a second shunt contact structure located at a second distance from the gate pad, wherein the first distance is different from the second distance.

[0175] In some embodiments, the shunt contact structure comprises a first shunt contact located on the first side of the metal piece and a second shunt contact structure located on the second side of the metal piece, the first side being opposite to the second side.

[0176] In some embodiments, the metal piece is one of a plurality of metal pieces, the plurality of metal pieces comprising a first metal piece extending in a direction parallel to the first side of the gate pad, a second metal piece extending in a direction parallel to the second side of the gate pad, a third metal piece extending in a direction parallel to the third side of the gate pad, and a fourth metal piece extending in a direction parallel to the fourth side of the gate pad.

[0177] In some embodiments, the first and second metal pieces intersect with the third metal piece at different positions, the first and second metal pieces intersect with the fourth metal piece at different positions, the first and second metal pieces do not intersect, and the third and fourth metal pieces do not intersect.

[0178] In some embodiments, the semiconductor structure comprises a wide-bandgap semiconductor.

[0179] In some embodiments, the semiconductor structure comprises silicon carbide.

[0180] In some embodiments, a plurality of unit cells comprises one or more silicon carbide-based MOSFET transistor cells.

[0181] While the subject matter of the present invention has been described in detail with respect to certain exemplary embodiments, those skilled in the art will understand that, having attained the foregoing understanding, modifications, variations, and equivalents of such embodiments can be readily produced. Therefore, the scope of this disclosure is illustrative and not limiting, and the disclosure of the subject matter does not preclude such modifications, variations, and / or additions to the subject matter, which would be readily apparent to those skilled in the art.

Claims

1. Power semiconductor devices, A semiconductor structure comprising an active region and an inactive region, wherein the active region comprises a plurality of unit cells, A gate structure in which at least a portion lies on the inert region, A first shunt contact structure located at least partially on the inert region, A second shunt contact structure located at least partially on the inert region, A balance shunt structure located at least partially on the inert region, A power semiconductor device equipped with these features.

2. The power semiconductor device according to claim 1, wherein the first shunt contact structure provides a first shunt path for a first displacement current flowing through the inert region, the second shunt contact structure provides a second shunt path for a second displacement current flowing through the inert region, and the balanced shunt structure reduces the difference between the first displacement current flowing through the first shunt path and the second displacement current flowing through the second shunt path.

3. The power semiconductor device according to claim 1, wherein the first shunt contact structure is adjacent to the first side of the gate structure, and the equilibrium shunt structure is adjacent to the second side of the gate structure, the second side being on the opposite side from the first side.

4. The power semiconductor device according to claim 1, wherein the equilibrium shunt structure is located between the gate structure and the terminal edge region.

5. The power semiconductor device according to claim 1, wherein at least a portion of the equilibrium shunt structure lies directly above the inert region of the semiconductor structure.

6. The power semiconductor device according to claim 1, wherein the first shunt contact structure and the second shunt contact structure are connected to the source terminal of the power semiconductor device.

7. The power semiconductor device according to claim 6, wherein the balanced shunt structure is not connected to the source terminal.

8. The power semiconductor device according to claim 1, wherein the gate structure comprises a gate pad and a gate runner.

9. The power semiconductor device according to claim 8, wherein the first shunt contact structure is adjacent to the gate pad and the second shunt contact structure is adjacent to the gate runner.

10. The power semiconductor device according to claim 8, wherein the gate runner is a peripheral gate runner located around at least a portion of the peripheral portion of the power semiconductor device.

11. The power semiconductor device according to claim 10, wherein the equilibrium shunt structure comprises an equilibrium annular structure located around at least a portion of the peripheral gate runner.

12. The power semiconductor device according to claim 11, wherein the balanced annular structure comprises a discontinuous annular structure having one or more cut portions.

13. The power semiconductor device according to claim 11, wherein the balanced annular structure is a continuous structure without a break.

14. The power semiconductor device according to claim 8, wherein the gate pad is located within the peripheral portion of the power semiconductor device.

15. The power semiconductor device according to claim 8, wherein the gate pad is located within the central portion of the power semiconductor device.

16. The power semiconductor device according to claim 15, wherein the first shunt contact structure is located at a first distance from the gate pad, and the second shunt contact structure is located at a second distance from the gate pad, and the first distance is different from the second distance.

17. The power semiconductor device according to claim 16, wherein at least a portion of the equilibrium shunt structure is located between the first shunt contact structure and the second shunt contact structure.

18. The power semiconductor device according to claim 16, wherein at least a portion of the equilibrium shunt structure is located between the gate pad and the first shunt contact structure.

19. The power semiconductor device according to claim 16, wherein the equilibrium shunt structure comprises a plurality of metal pieces, and the plurality of metal pieces intersect with one another.

20. Furthermore, the power semiconductor device according to claim 1, further comprising a field insulating layer on at least a portion of the inert region.

21. The power semiconductor device according to claim 20, wherein the field insulating layer is located between at least a portion of the gate structure and the inert region.

22. The power semiconductor device according to claim 21, wherein the first shunt contact structure, the second shunt contact structure, and the equilibrium shunt structure extend through the field insulating layer.

23. The power semiconductor device according to claim 1, wherein the power semiconductor device does not have a source runner in the peripheral portion of the power semiconductor device.

24. The power semiconductor device according to claim 1, wherein the first shunt contact structure and the second shunt contact structure are part of a plurality of shunt contact structures arranged at least partially in annularly adjacent to the gate structure.

25. The power semiconductor device according to claim 1, wherein the semiconductor structure comprises a wide-bandgap semiconductor.

26. The power semiconductor device according to claim 1, wherein the semiconductor structure comprises silicon carbide.

27. The power semiconductor device according to claim 1, wherein the plurality of unit cells each comprise one or more silicon carbide-based MOSFET transistor cells.

28. Power semiconductor devices, A semiconductor structure comprising an active region and an inactive region, wherein the active region comprises a plurality of unit cells, A field insulating layer that is at least partially located on the inert region, A gate structure that is at least partially on the field insulating layer, A shunt contact structure that extends at least partially through the field insulating layer, A balance shunt structure located at least partially on the inert region, A power semiconductor device equipped with these features.

29. The power semiconductor device according to claim 28, wherein the shunt contact structure is electrically connected to the source pad of the power semiconductor device, and the balanced shunt structure is not electrically connected to the source pad.

30. The power semiconductor device according to claim 28, wherein the equilibrium shunt structure comprises an equilibrium annular structure located around at least a portion of the gate runner.

31. The power semiconductor device according to claim 30, wherein the balanced annular structure comprises a discontinuous annular structure having one or more cut portions.

32. The power semiconductor device according to claim 30, wherein the balanced annular structure is a continuous annular structure without a break.

33. The power semiconductor device according to claim 28, wherein the equilibrium shunt structure is located between the gate structure and the terminal edge region.

34. The power semiconductor device according to claim 28, wherein at least a portion of the equilibrium shunt structure is in direct contact with the inert region of the semiconductor structure.

35. The power semiconductor device according to claim 28, wherein the balanced shunt structure is operable to reduce the resistance associated with the shunt contact structure.

36. The power semiconductor device according to claim 28, wherein the equilibrium shunt structure is a metal piece located between the gate pad and the peripheral portion of the power semiconductor device.

37. The power semiconductor device according to claim 28, wherein the semiconductor structure comprises a wide-bandgap semiconductor.

38. The power semiconductor device according to claim 28, wherein the semiconductor structure comprises silicon carbide.

39. The power semiconductor device according to claim 28, wherein the plurality of unit cells each comprise one or more silicon carbide-based MOSFET transistor cells.

40. Power semiconductor devices, A semiconductor structure comprising an active region and an inactive region, wherein the active region comprises a plurality of unit cells, A gate structure in which at least a portion lies on the inert region, Multiple shunt contact structures located at least partially on the inert region, A balance shunt structure located at least partially on the inert region, Equipped with, The balanced shunt structure is a power semiconductor device that is operable to balance the displacement currents associated with the plurality of shunt contact structures.

41. The power semiconductor device according to claim 40, wherein the plurality of shunt contact structures are adjacent to the first side of the gate structure, and the equilibrium shunt structure is adjacent to the second side of the gate structure, the second side being on the opposite side from the first side.

42. The power semiconductor device according to claim 40, wherein the equilibrium shunt structure is located between the gate structure and the terminal edge region.

43. The power semiconductor device according to claim 40, wherein at least a portion of the equilibrium shunt structure lies directly above the inert region of the semiconductor structure.

44. The power semiconductor device according to claim 40, wherein the plurality of shunt contact structures are electrically connected to the source pad of the power semiconductor device, and the balanced shunt structure is not electrically connected to the source pad.

45. The power semiconductor device according to claim 40, wherein the gate structure comprises a gate pad and a gate runner.

46. The power semiconductor device according to claim 45, wherein the plurality of shunt contact structures comprises a first shunt contact structure adjacent to the gate pad and a second shunt contact structure adjacent to the gate runner.

47. The power semiconductor device according to claim 46, wherein the gate runner is a peripheral gate runner located around at least a portion of the peripheral portion of the power semiconductor device.

48. The power semiconductor device according to claim 47, wherein the equilibrium shunt structure comprises an equilibrium annular structure located around at least a portion of the peripheral gate runner.

49. The power semiconductor device according to claim 48, wherein the balanced annular structure comprises a discontinuous annular structure having one or more cut portions.

50. The power semiconductor device according to claim 48, wherein the balanced annular structure is a continuous structure without a break.

51. The power semiconductor device according to claim 45, wherein the gate pad is located within the peripheral portion of the power semiconductor device.

52. The power semiconductor device according to claim 45, wherein the gate pad is located within the central portion of the power semiconductor device.

53. The power semiconductor device according to claim 52, wherein the equilibrium shunt structure comprises a plurality of metal pieces arranged in a grid.

54. Furthermore, the power semiconductor device according to claim 45, further comprising a field insulating layer on at least a portion of the inert region.

55. The power semiconductor device according to claim 54, wherein the field insulating layer is located between at least a portion of the gate structure and the inert region.

56. The power semiconductor device according to claim 55, wherein the plurality of shunt contact structures and the equilibrium shunt structure extend through the field insulating layer.

57. The power semiconductor device according to claim 40, wherein the power semiconductor device does not include a source runner.

58. The power semiconductor device according to claim 40, wherein the plurality of shunt contact structures are arranged at least partially in annularly adjacent to the gate structure.

59. The power semiconductor device according to claim 40, wherein the semiconductor structure comprises a wide-bandgap semiconductor.

60. The power semiconductor device according to claim 40, wherein the semiconductor structure comprises silicon carbide.

61. The power semiconductor device according to claim 40, wherein the plurality of unit cells each comprise one or more silicon carbide-based MOSFET transistor cells.

62. Power semiconductor devices, A semiconductor structure comprising an active region and an inactive region, wherein the active region comprises a plurality of unit cells, The gate pad located in the central part of the power semiconductor device, Multiple shunt contact structures located at least partially around the gate pad, A power semiconductor device equipped with these features.

63. The power semiconductor device according to claim 62, further comprising a balanced shunt structure, wherein the balanced shunt structure includes a metal piece located between the gate pad and the peripheral portion of the power semiconductor device.

64. The power semiconductor device according to claim 63, wherein the equilibrium shunt structure comprises a plurality of metal pieces between the gate pad and the peripheral portion of the power semiconductor device.

65. The power semiconductor device according to claim 64, wherein the plurality of metal pieces comprises a first metal piece and a second metal piece, and the first metal piece and the second metal piece intersect each other.

66. The power semiconductor device according to claim 63, wherein the power semiconductor device comprises a plurality of shunt contact structures extending along at least a portion of the metal piece.

67. The power semiconductor device according to claim 66, wherein the plurality of shunt contact structures are electrically connected to the source terminal of the power semiconductor device, and the balanced shunt structure is not electrically connected to the source terminal.

68. The power semiconductor device according to claim 66, wherein the plurality of shunt contact structures comprises a first shunt contact structure located at a first distance from the gate pad and a second shunt contact structure located at a second distance from the gate pad, wherein the first distance is different from the second distance.

69. The power semiconductor device according to claim 66, wherein the plurality of shunt contact structures comprises a first shunt contact located on the first side of the metal piece and a second shunt contact structure located on the second side of the metal piece, the first side being on the opposite side from the second side.

70. The aforementioned metal piece is one of a plurality of metal pieces, and the plurality of metal pieces are A first metal piece extending in a direction parallel to the first side of the gate pad, A second metal piece extending in a direction parallel to the second side of the gate pad, A third metal piece extending in a direction parallel to the third side of the gate pad, The power semiconductor device according to claim 63, further comprising a fourth metal piece extending in a direction parallel to the fourth side of the gate pad.

71. The power semiconductor device according to claim 70, wherein the first metal piece and the second metal piece intersect with the third metal piece at different positions, the first metal piece and the second metal piece intersect with the fourth metal piece at different positions, the first metal piece and the second metal piece do not intersect, and the third metal piece and the fourth metal piece do not intersect.

72. The power semiconductor device according to claim 62, wherein the semiconductor structure comprises a wide-bandgap semiconductor.

73. The power semiconductor device according to claim 62, wherein the semiconductor structure comprises silicon carbide.

74. The power semiconductor device according to claim 62, wherein the plurality of unit cells each comprise one or more silicon carbide-based MOSFET transistor cells.

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