Stepwise gate voltage control

Abstract

An electro-optical display and a driving method are disclosed. The electro-optical display includes a layer of electrophoretic material placed between a common electrode and a backplane. The backplane includes an array of pixel electrodes, each coupled to a pixel transistor. A controller provides time-dependent voltages to the gate line, source line, and common electrode of each pixel transistor. The driving method includes applying a first-stage voltage to the gate line. The first-stage voltage has a first magnitude, which is substantially half the gate-low voltage required to de-conduct the pixel transistor. The first-stage voltage is maintained across the gate line for a first period. Next, a second-stage voltage is applied across the gate line, which has a second magnitude, which is substantially the gate-low voltage required to de-conduct the pixel transistor.

Description

TECHNICAL FIELD

[0001] Cross-Reference to Related Applications This application claims priority to U.S. Provisional Application No. 63 / 588,290 filed on October 5, 2023, the entire content of which is incorporated herein by reference. Furthermore, the entire contents of any patents, published applications, or other published publications referenced herein are incorporated by reference in their entirety.

[0002] Field of the Invention The subject matter disclosed herein relates to electro-optic displays and methods for driving electro-optic displays. In particular, the subject matter disclosed herein relates to electro-optic displays that power up and power down gate voltages such that the amplitude of voltage artifacts induced across the electrophoretic medium of an active matrix display is reduced or eliminated, and methods for driving the electro-optic displays. BACKGROUND ART

[0003] Background of the Invention Electro-optic displays typically comprise a layer of electro-optic material, and the term "electro-optic material" is used herein in its conventional meaning in the imaging art to refer to a material having first and second display states differing in at least one optical property, the material being changed from its first display state to its second display state by application of an electric field to the material. The optical property is typically a color perceptible to the human eye, but may be another optical property such as light transmittance, reflectance, luminescence, or in the case of displays intended for machine reading, pseudo-color in the sense of a change in reflectance of electromagnetic wavelengths outside the visible range.

[0004] The terms “bistable” and “bistable” are used herein in their conventional sense to refer to a display having a display element having at least one first and second display state having different optical properties, wherein any given element is driven to take either its first or second display state by a finite-duration addressing pulse, and after the addressing pulse terminates, the state persists for at least several times, e.g., at least four times, the minimum duration of the addressing pulse required to change the state of the display element. U.S. Patent No. 7,170,670 shows that several particle-based electrophoretic displays capable of grayscale are stable not only in their extreme black and white states but also in their intermediate gray states, and similarly for several other types of electro-optic displays. These types of displays are appropriately called “multistable” rather than bistable, but for convenience, the term “bistable” may be used herein to cover both bistable and multistable displays.

[0005] Regardless of whether the electro-optical medium used is bistable or not, in order to obtain a high-resolution display, the individual pixels of the display must be addressable without interference from adjacent pixels. One way to achieve this objective is to provide an array of nonlinear elements, such as transistors or diodes, each associated with at least one nonlinear element, in order to generate an "active matrix" display. The addressing or pixel electrode that addresses a single pixel is connected to a suitable voltage source through the associated nonlinear element. Typically, if the nonlinear element is a transistor, the pixel electrode is connected to the drain of the transistor, and this arrangement is assumed in the following description, but this is essentially arbitrary, and the pixel electrode could be connected to the source of the transistor.

[0006] Conventionally, in high-resolution arrays, pixels are arranged in a two-dimensional array of rows and columns such that any particular pixel is uniquely defined by the intersection of one designated row and one designated column. The sources of all transistors in each column are connected to a single column electrode, while the gates of all transistors in each row are connected to a single row electrode. Here again, the assignment of sources to rows and gates to columns is conventional but essentially arbitrary and can be reversed if desired. The row electrodes are connected to a row drive circuit, which essentially ensures that at any given moment only one row is selected, i.e., a voltage is applied to the selected row electrode to ensure that all transistors in the selected row are conductive, while a voltage is applied to all other rows to ensure that all transistors in these unselected rows remain non-conductive. The column electrodes are connected to a column drive circuit, which applies selected voltages to various column electrodes to drive the pixels in the selected row into their desired optical states. (The aforementioned voltages relate to a common front electrode that is conventionally located on the opposite side of the electro-optical medium from the nonlinear array and extends as a substantially planar layer across the entire display.) After a pre-selected interval known as the “line address time,” the selected row is deselected, the next row is selected, and the voltage on the column driver is changed so that the next row of the display is written. This process is repeated until the entire display is written, line by line.

[0007] Typically, electro-optical displays are enclosed by a frame or bezel to conceal the electrical connections required for the row and column drive circuits of the display, which are generally routed along the perimeter of the display. However, in some applications, it is preferable that substantially the entire viewable area of ​​the electro-optical display is optically active. As an example, an active billboard can be fabricated by tiling multiple electro-optical displays together to create a large display. In such applications, it is preferable to minimize the space between the tiled displays. Furthermore, even with a single-panel display, it is generally preferable to minimize the dimensions of the display bezel or frame that overlaps the active area of ​​the display in order to maximize the viewable area.

[0008] To address such requirements, one strategy to reduce or eliminate the need for bezels or boundary frames extending beyond the pixels themselves is to route many of the traces or wires (e.g., "T-wires") that control the switching of pixel thin-film transistors ("TFTs") on the back of the display panel (i.e., the side opposite the display pixels on the front of the panel) toward the front of the display panel through one or more vias (sometimes referred to as "via holes" or "conductive vias"). For example, such T-wires can be routed along the back of the display panel perpendicular to the TFT gate lines routed toward the front of the display panel, providing electrical connections to row selection signals of a driver IC, and vias can be used to connect each gate line to the T-wire of its respective row selection signal.

[0009] While it is common for one separate T-wire and one separate via to be used to establish a connection to each individual gate line, multiple T-wires can be present in close proximity to each pixel of a display. Since display substrates are typically made from non-conductive materials, capacitance can be generated between the pixel electrodes and the adjacent T-wires. This capacitive coupling can result in undesirable optical defects, such as varied optical properties or responses across different areas of the display, due to certain behaviors.

[0010] For example, prior to updating an electrophoretic display, any voltage planes or data and control signals used to drive the pixels of an active matrix display must be brought down from a “pause” or power-down voltage of approximately 0 volts (e.g., ground) to some known initial voltage value. As an example, the gate line of each pixel TFT in an active matrix can be driven from the power-down voltage to a “gate-low” voltage, which is the voltage typically applied to the gate lines of “unaddressed” or deselected rows of the active matrix during a display update.

[0011] Conventional display driving techniques first continuously drive the pixel TFT gate line from the power-down voltage to a gate-low voltage that has a sufficiently negative magnitude or voltage value to place the pixel TFT in a non-conductive state. After the update to the electrophoretic display is complete, the voltage applied to the gate line is typically returned to the controller ground voltage (e.g., approximately 0 volts) in a similar manner, i.e., the pixel TFT gate line is continuously driven back from the gate-low voltage to the power-down voltage.

[0012] The gate low voltage is supplied to the gate lines of the active matrix display through the display selection driver circuit. When the gate low voltage is set from 0 volts to a negative value in preparation for a refresh, the gate lines and any associated T-wires are also used to connect to the gate lines. Because these gate lines and associated T-wire lines are capacitively coupled directly to the pixel electrodes or to the electrophoretic layer through the dielectric layer in the backplane, the electrophoretic layer receives a transient negative impulse or voltage artifact during this "power-up" event. After the refresh, when the gate low voltage is returned to 0 volts, the electrophoretic layer receives a positive voltage transient or artifact. Both of these voltage artifacts can shift and degrade the optical state of the electrophoretic medium adjacent to the artifact.

[0013] Conventional techniques have attempted to mitigate transient voltage impulses during power-down of the display voltage plane and data and control signals by using components configured to slowly dissipate impulses, such as resistors positioned within circuits that control the voltage applied to each pixel. However, such solutions are inherently passive and do not address variations in requirements due to changes in environmental conditions or differences in the electrical properties of the electrophoretic layer. Furthermore, such solutions do not address voltage artifacts induced by resetting signals such as gate lines to their initial state before updating the display. [Prior art documents] [Patent Documents]

[0014] [Patent Document 1] U.S. Patent No. 7,170,670 [Overview of the Initiative] [Means for solving the problem]

[0015] Therefore, there is a need for electro-optic displays and methods for driving electro-optic displays that power up and power down the gate low voltage in a way that reduces the amplitude of voltage artifacts induced in the electrophoretic layer of an active matrix display.

[0016] Accordingly, in one embodiment, the subject matter disclosed herein includes a method for driving an electro-optical display. The electro-optical display includes a layer of electrophoretic material placed between a common electrode and a backplane. The backplane includes an array of pixel electrodes. Each pixel electrode is coupled to a pixel transistor, which includes a source electrode, a gate electrode, and a drain electrode. The gate electrode is coupled to the gate line, the source electrode is coupled to the source line, and the drain electrode is coupled to the pixel electrode. A controller provides time-dependent voltages to the gate line, the source line, and the common electrode. The method for driving includes applying a first-stage voltage to the gate line, the first-stage voltage having a first magnitude which is substantially half the gate-low voltage required to de-conduct the pixel transistor. The method for driving also includes maintaining the first-stage voltage on the gate line over a first period of time and applying a second-stage voltage to the gate line, the second-stage voltage having a second magnitude which is substantially the gate-low voltage required to de-conduct the pixel transistor.

[0017] In another embodiment, the subject matter disclosed herein includes an electro-optical display comprising a light-transmitting common electrode and a backplane comprising an array of pixel electrodes. The electro-optical display also comprises a layer of electro-optical material placed between the common electrode and the array of pixel electrodes, and each pixel electrode is coupled to a pixel transistor comprising a source electrode, a gate electrode, and a drain electrode, wherein the gate electrode is coupled to the gate line, the source electrode is coupled to the source line, and the drain electrode is coupled to the pixel electrode. The electro-optical display also includes a controller capable of applying time-dependent voltages to the gate line, the source line, and the common electrode. The controller is configured to apply a first-stage voltage to the gate line, the first-stage voltage having a first magnitude which is substantially half the gate-low voltage required to de-conduct the pixel transistor. The controller is further configured to maintain the first-stage voltage on the gate line over a first period of time and to apply a second-stage voltage to the gate line, the second-stage voltage having a second magnitude which is substantially the gate-low voltage required to de-conduct the pixel transistor.

[0018] All embodiments disclosed herein may include additional features. In some embodiments, the gate-low voltage has a magnitude of substantially -35V. In some embodiments, the pixel transistor is an n-type transistor, and the gate-low voltage has negative polarity. In some embodiments, the pixel transistor is a p-type transistor, and the gate-low voltage has positive polarity.

[0019] In some embodiments, the first period is 30ms to 50ms. In some embodiments, the second period is 30ms to 50ms.

[0020] In some embodiments, applying a first stage voltage to a gate line causes a first voltage artifact on the layer of electrophoretic material. In some embodiments, the first period is longer than or equal to the discharge time of the first voltage artifact.

[0021] In some embodiments, applying a second stage voltage to the gate line causes a second voltage artifact on the layer of electrophoretic material. In some embodiments, the second period is longer than or equal to the discharge time of the second voltage artifact. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Various aspects and embodiments of the present application are described with reference to the following drawings. It should be understood that the drawings are not necessarily drawn to scale.

[0023] [Figure 1A] FIG. 1A is a representative cross-section of a four-particle electrophoretic display in which the electrophoretic medium is encapsulated in capsules. The structure of FIG. 1A can be used for multiparticulate electrophoretic media having both reflective and subtractive pigment particles.

[0024] [Figure 1B] FIG. 1B is a representative cross-section of a four-particle electrophoretic display in which the electrophoretic medium is encapsulated in microcells. The structure of FIG. 1B can be used for multiparticulate electrophoretic media having both reflective and subtractive pigment particles.

[0025] [Figure 2] FIG. 2 is a schematic diagram of an exemplary drive system for controlling the voltage supplied to pixel electrodes in an active matrix device. The resulting drive voltage can be used to set the optical state of the multiparticulate electrophoretic medium.

[0026] [Figure 3]Figure 3 illustrates an exemplary electrophoretic display including a display module. The electrophoretic display also includes a processor, non-temporary memory, one or more power supplies, and a controller. The electrophoretic display may also include sensors that allow the electrophoretic display to adjust its operating parameters based on the ambient environment, such as temperature and lighting.

[0027] [Figure 4A] Figure 4A is a schematic diagram showing an exemplary gate and source signal routing layout for an active matrix backplane of an electro-optical display, according to the subject matter disclosed herein.

[0028] [Figure 4B] Figure 4B is a schematic diagram of an exemplary display pixel according to the subject disclosed herein.

[0029] [Figure 5A] Figure 5A is a signal waveform diagram illustrating the voltage artifacts experienced by the electrophoretic material when the gate low voltage is powered up in a single step using a conventional driving method.

[0030] [Figure 5B] Figure 5B is a signal waveform diagram illustrating the voltage artifacts experienced by the electrophoretic material when the gate low voltage is powered up in two stages according to the driving method disclosed herein.

[0031] [Figure 5C] Figure 5C is a signal waveform diagram illustrating the voltage artifacts experienced by the electrophoretic material when the gate low voltage is powered up in three stages according to the driving method disclosed herein.

[0032] [Figure 6A] Figure 6A is a signal waveform diagram illustrating the voltage artifact experienced by the electrophoretic material when the gate low voltage is powered down in a single step using a conventional driving method.

[0033] [Figure 6B] Figure 6B is a signal waveform diagram illustrating the voltage artifacts experienced by the electrophoretic material when the gate low voltage is powered down in two stages according to the driving method disclosed herein.

[0034] [Figure 6C] Figure 6C is a signal waveform diagram illustrating the voltage artifacts experienced by the electrophoretic material when the gate low voltage is powered down in three stages according to the driving method disclosed herein. [Modes for carrying out the invention]

[0035] Detailed description of the invention The use of electro-optical display technology is expanding beyond "typical" display applications such as television screens and monitors to include display products such as ebooks, product labels, retail shelf labels, device monitoring indicators, watches, signs, and promotional or advertising displays. Typically, electro-optical displays are enclosed by a frame or bezel to conceal the electrical connections of the display, which generally run along the perimeter of the display. In some applications, particularly large-scale tiled displays, it is generally preferable that the entire viewable area of ​​the electro-optical display is optically active, for example, in active billboards created by tiling multiple electro-optical displays together to create a large display. In such applications, consumers prefer that the entire viewable surface of each individual display is optically active and that the space between tiled displays is minimized. When done correctly, tiled displays present the appearance of a single continuous display.

[0036] Electrophoretic displays ("EPDs") are a type of electro-optical display that changes color by altering the position of one or more charged colored particles on a light-transmitting viewing surface. Such electrophoretic displays are typically referred to as "electronic paper" or "ePaper" because the resulting display has high contrast and is readable in sunlight as well as ink on paper. Electrophoretic displays are widely used in e-book readers because they offer a book-like reading experience, consume little power, and allow users to carry libraries of hundreds of books in a lightweight handheld device. Such devices are increasingly being adapted to display out-of-home (OOH) digital content such as shelf labels, outdoor advertising, and traffic signs.

[0037] For many years, electrophoretic displays have contained only two types of charged colored particles: black and white. (For the record, as used herein, “color” includes black and white.) White particles are often light-scattering and include, for example, titanium dioxide, while black particles are absorbent across the visible spectrum and may include carbon black or absorbent metal oxides such as copper chromite. In its simplest sense, a monochrome electrophoretic display requires only a light-transmitting electrode on the viewing surface, a back electrode, and an electrophoretic medium containing oppositely charged white and black particles. When a voltage of one polarity is applied, the white particles move to the viewing surface, and when a voltage of the opposite polarity is applied, the black particles move to the viewing surface. If the back electrode contains controllable regions (pixels)—either segmented electrodes or an active matrix of pixel electrodes controlled by transistors—a pattern can be fabricated to appear electronically on the viewing surface. The pattern can be, for example, text on a book.

[0038] More recently, a variety of color options, including three-color displays (black, white, red; black, white, yellow) and four-color displays (black, white, red, yellow), have become commercially available for electrophoretic displays. Similar to the operation of a monochrome electrophoretic display, an electrophoretic display with three or four reflective pigments operates similarly to a simple monochrome display, as the desired color particles are driven to the visible surface. While the driving mechanism is far more complex than that of monochrome alone, ultimately, the optical function of the particles remains the same.

[0039] Advanced Color Electronic Paper (ACeP®) also contains four particles, but because the cyan, yellow, and magenta particles are subtractive rather than reflective, it allows thousands of colors to be generated at each pixel. The color process is functionally equivalent to the printing methods that have long been used in offset and inkjet printers. A given color is produced by using the correct ratio of cyan, yellow, and magenta on a bright white paper background. In the case of ACeP, the relative positions of the cyan, yellow, magenta, and white particles to the viewing surface determine the color at each pixel. While this type of electrophoretic display allows thousands of colors at each pixel, it is crucial to carefully control the position of each pigment (50-500 nanometer size) within a working space of approximately 10-20 micrometers thickness. Obviously, variations in the position of the pigments will result in the display of the wrong color at a given pixel. Therefore, sophisticated voltage control is required for such systems. Further details of this system are available in the following U.S. Patents, which are incorporated by reference in their entirety: U.S. Patents Nos. 9,361,836, 9,921,451, 10,276,109, 10,353,266, 10,467,984, 10,593,272, and 10,657,869.

[0040] The term "gray state" is used herein in its conventional sense in the field of imaging technology to refer to a state intermediate between two extreme optical states of a pixel, and does not necessarily imply a black-and-white transition between these two extreme states. For example, some of the E Ink patents and published applications referenced below describe electrophoretic displays where the extreme states are white and dark blue, so the intermediate gray state is actually light blue. In fact, as already stated, a change in optical state may not be a change in color at all. The terms black and white may be used below to refer to two extreme optical states of a display, and should be understood to typically include extreme optical states that are not strictly black and white, such as the aforementioned white and dark blue states.

[0041] When the term "impulse" is used to refer to driving an electrophoretic display, in this specification it is used to refer to the integral of the applied voltage over time during the period in which the display is driven.

[0042] Particles that absorb, scatter, or reflect light across a broadband or selected wavelength are referred to herein as colored particles or pigment particles. A variety of materials other than pigments that absorb or reflect light (in the strict sense of the term, meaning insoluble coloring materials), such as dyes or photonic crystals, may also be used in the electrophoretic media and displays of the present invention.

[0043] Particle-based electrophoretic displays have been the subject of intensive research and development for many years. In such displays, multiple charged particles (sometimes called pigment particles) move through a fluid under the influence of an electric field. Compared to liquid crystal displays, electrophoretic displays can have attributes such as good brightness and contrast, a wide viewing angle, state bistability, and low power consumption. Nevertheless, problems associated with the long-term image quality of these displays have hindered their widespread use. For example, the particles that make up electrophoretic displays tend to settle, resulting in an insufficient lifespan for these displays.

[0044] As described above, electrophoretic media require the presence of a fluid. In most prior art electrophoretic media, this fluid is a liquid, but electrophoretic media can be produced using a gaseous fluid (see, for example, Kitamura, T. et al., Electrical Toner Transfer for Electronic Paper-Like Displays, IDW Japan, 2001, Paper HCS1-1, and Yamaguchi, Y. et al., Toner Display Using Triboelectrically Charged Insulating Particles, IDW Japan, 2001, Paper AMD4-4). See also U.S. Patents 7,321,459 and 7,236,291. Such gas-based electrophoretic media appear to be susceptible to the same types of particle sedimentation problems as liquid-based electrophoretic media when the medium is used in an orientation that allows such sedimentation, for example, in labels where the medium is placed on a vertical surface. In fact, the lower viscosity of gaseous suspensions compared to liquids allows for faster sedimentation of electrophoretic particles, so particle sedimentation appears to be a more serious problem in gas-based electrophoretic media than in liquid-based electrophoretic media.

[0045] Numerous patents and applications assigned to or in the name of the Massachusetts Institute of Technology (MIT) and E Ink Corporation describe various techniques used in encapsulated electrophoretic and other electro-optical media. Such encapsulated media comprise numerous small capsules, each comprising an inner phase containing electrophoretically mobile particles in a fluid medium, and a capsule wall surrounding the inner phase. Typically, the capsules are held within a polymer binder to form a coherent layer positioned between two electrodes. The techniques described in these patents and applications include: (a) Electrophoretic particles, fluids, and fluid additives; see, for example, U.S. Patent Nos. 7,002,728 and 7,679,814; (b) Capsules, binders, and encapsulation processes; see, for example, U.S. Patent Nos. 6,922,276 and 7,411,719; (c) Microcell structures, wall materials, and methods for forming microcells; see, for example, U.S. Patent Nos. 7,072,095 and 9,279,906; (d) Methods for filling and sealing microcells; see, for example, U.S. Patent Nos. 7,144,942 and 7,715,088; (e) Films and subassemblies containing electro-optical materials; see, for example, U.S. Patent Nos. 6,982,178 and 7,839,564; (f) Backplanes, adhesive layers and other auxiliary layers and methods used in displays; see, for example, U.S. Patent Nos. 7,116,318 and 7,535,624; (g) Color formation and color adjustment; for example, U.S. Patent No. 6,017,584; No. 6,545,797; No. 6,664,944; No. 6,788,452; No. 6,864,875; No. 6,914,714; No. 6,972,893; No. 7,038,656; No. 7,038,670; No. 7,046,228; No. 7,052,571; No. 7,075,502; No. 7,167,155; No. 7,385,751; No. 7,492,505; No. 7,667,684; No. 7,684,108; No. 7,791,7 No. 89; No. 7,800,813; No. 7,821,702; No. 7,839,564; No. 7,910,175; No. 7,9 No. 52,790; No. 7,956,841; No. 7,982,941; No. 8,040,594; No. 8,054,526; No. 8,054,526; No. 8,098,418; No. 8,159,636; No. 8,213,076; No. 8,363,299; No. 8,422,116 ; Same No. 8,441,714; Same No. 8,441,716; Same No. 8,466,852; Same No. 8,503,063; Same No. 8,576,4 No. 70; No. 8,576,475; No. 8,593,721; No. 8,605,354; No. 8,649,084; No. 8,6 No. 70,174; No. 8,704,756; No. 8,717,664; No. 8,786,935; No. 8,797,634; No. 8,797,634; No. 8,810,899; No. 8,830,559; No. 8,873,129; No. 8,902,153; No. 8,902,491 ; Same No. 8,917,439; Same No. 8,964,282; Same No. 9,013,783; Same No. 9,116,412; Same No. 9,146,4 No. 39; No. 9,164,207; No. 9,170,467; No. 9,170,468; No. 9,182,646; No. 9,195,111; No. 9,199,441; No. 9,268,191; No. 9,285,649; No. 9,293,511; No. 9,341,916; No. 9,360,733; No. 9,361,836; No. 9,383,623; and No. 9,423,666; as well as U.S. Patent Application Publications 2008 / 0043318; 2008 / 0048970; and 2009 / 0225398;Same No. 2010 / 0156780; Same No. 2011 / 0043543; Same No. 2012 / 0326957; Same No. 2013 / 0242378; Same No. 2013 / 0278995; Same No. 2014 / 0055840 No. 2014 / 0078576; No. 2014 / 0340430; No. 2014 / 0340736; No. 2014 / 0362213; No. 2015 / 0103394; No. 2015 / 011839 See issues 0; 2015 / 0124345; 2015 / 0198858; 2015 / 0234250; 2015 / 0268531; 2015 / 0301246; 2016 / 0011484; 2016 / 0026062; 2016 / 0048054; 2016 / 0116816; 2016 / 0116818; and 2016 / 0140909; (h) Methods for driving a display; for example, U.S. Patent No. 5,930,026; No. 6,445,489; No. 6,504,524; No. 6,512,354; No. 6,531,997; No. 6,753,999; No. 6,825,970; No. 6,900,851; No. 6,995,550; No. 7,012,600; No. 7,023,420; No. 7,034,783; No. 7,061,166; No. 7,061,662; No. 7,116,466; No. 7,119,772; No. 7,177,066 ; Same No. 7,193,625; Same No. 7,202,847; Same No. 7,242,514; Same No. 7,259,744; Same No. 7,304, No. 787; No. 7,312,794; No. 7,327,511; No. 7,408,699; No. 7,453,445; No. 7,4 No. 92,339; No. 7,528,822; No. 7,545,358; No. 7,583,251; No. 7,602,374; No. 7,602,374; No. 7,612,760; No. 7,679,599; No. 7,679,813; No. 7,683,606; No. 7,688,297 ; Same No. 7,729,039; Same No. 7,733,311; Same No. 7,733,335; Same No. 7,787,169; Same No. 7,859, No. 742; No. 7,952,557; No. 7,956,841; No. 7,982,479; No. 7,999,787; No. 8,0 77,141; 8,125,501; 8,139,050; 8,174,490; 8,243,013; No. 8,274,472; No. 8,289,250; No. 8,300,006; No. 8,305,341; No. 8,314,784 ; Same No. 8,373,649; Same No. 8,384,658; Same No. 8,456,414; Same No. 8,462,102; Same No. 8,514,1 No. 68; No. 8,537,105; No. 8,558,783; No. 8,558,785; No. 8,558,786; No. 8,55 No. 8,855; No. 8,576,164; No. 8,576,259; No. 8,593,396; No. 8,605,032; No. 8 , 643,595; 8,665,206; 8,681,191; 8,730,153; 8,810,525;Same No. 8,928,562; Same No. 8,928,641; Same No. 8,976,444; Same No. 9,013,394; Same No. 9,019,1 No. 97; No. 9,019,198; No. 9,019,318; No. 9,082,352; No. 9,171,508; No. 9,21 No. 8,773; No. 9,224,338; No. 9,224,342; No. 9,224,344; No. 9,230,492; No. 9 , 251,736; 9,262,973; 9,269,311; 9,299,294; 9,373,289; Ibid. Nos. 9,390,066; 9,390,661; and 9,412,314; and U.S. Patent Application Publications 2003 / 0102858; 2004 / 0246562; 2005 / 0253777; 2007 / 0091418; 2007 / 0103427; 2007 / 0176912; 2008 / 0024429; 2008 / 0024482; 2008 / 0136774; 2008 / 0291129; 2008 / 0303780; 2009 / 0174651; and 2009 / 0195568; 2009 / 0322721; 2010 / 0194733; 2010 / 0194789 ; Same No. 2010 / 0220121; Same No. 2010 / 0265561; Same No. 2010 / 0283804; Same No. 2011 / 006331 No. 4; Same No. 2011 / 0175875; Same No. 2011 / 0193840; Same No. 2011 / 0193841; Same No. 2011 / 0199 No. 671; No. 2011 / 0221740; No. 2012 / 0001957; No. 2012 / 0098740; No. 2013 / 00 No. 63333; No. 2013 / 0194250; No. 2013 / 0249782; No. 2013 / 0321278; No. 2014 / 0009817; Same No. 2014 / 0085355; Same No. 2014 / 0204012; Same No. 2014 / 0218277; Same No. 20 14 / 0240210; 2014 / 0240373; 2014 / 0253425; 2014 / 0292830; 2014 / 0293398; 2014 / 0333685; 2014 / 0340734; 2015 / 0070744;See also Patent Nos. 2015 / 0097877; 2015 / 0109283; 2015 / 0213749; 2015 / 0213765; 2015 / 0221257; 2015 / 0262255; 2015 / 0262551; 2016 / 0071465; 2016 / 0078820; 2016 / 0093253; 2016 / 0140910; and 2016 / 0180777 (these patents and applications may hereafter be referred to as MEDEOD (Methods for Driving Electro-optic Displays) applications); (i) Uses of the display; see, for example, U.S. Patent Nos. 7,312,784 and 8,009,348; (j) Non-electrophoretic displays as described in U.S. Patent No. 6,241,921; and U.S. Patent Publication No. 2015 / 0277160; and U.S. Patent Publication Nos. 2015 / 0005720 and 2016 / 0012710.

[0046] Many of the aforementioned patents and applications recognize that the walls surrounding individual microcapsules in an encapsulated electrophoretic medium are replaced by a continuous phase, and therefore the electrophoretic medium can produce a so-called polymer-dispersed electrophoretic display comprising multiple individual droplets of electrophoretic fluid and a continuous phase of polymer material, and that individual droplets of electrophoretic fluid within such a polymer-dispersed electrophoretic display can be considered capsules or microcapsules even if individual capsule membranes are not associated with each individual droplet, see, for example, U.S. Patent No. 6,866,760. For the purposes of this application, such a polymer-dispersed electrophoretic medium is considered a type of encapsulated electrophoretic medium.

[0047] A related type of electrophoretic display is the so-called microcell electrophoretic display. In a microcell electrophoretic display, charged particles and fluids are not encapsulated within microcapsules, but instead are held within multiple cavities formed in a carrier medium, typically a polymer film. See, for example, U.S. Patent Nos. 6,672,921 and 6,788,449.

[0048] Electrophoretic media are often opaque (for example, in many electrophoretic media, the particles substantially block the transmission of visible light through the display) and operate in reflective mode; however, many electrophoretic displays can be manufactured to operate in a so-called shutter mode, where one display state is substantially opaque and the other is light-transmitting. See, for example, U.S. Patents 5,872,552, 6,130,774; 6,144,361; 6,172,798; 6,271,823; 6,225,971; and 6,184,856. Dielectrophoretic displays are similar to electrophoretic displays but depend on variations in electric field strength and can operate in a similar mode; see U.S. Patent 4,418,346 for this. Other types of electro-optical displays may also be capable of operating in shutter mode. An electro-optical medium operating in shutter mode can be used in a multilayer structure for a full-color display, in which at least one layer adjacent to the viewing surface of the display operates in shutter mode to expose or conceal a second layer further away from the viewing surface.

[0049] Encapsulated electrophoretic displays typically do not suffer from the clustering and sedimentation failure modes of conventional electrophoretic devices and offer further advantages, such as the ability to print or coat the display on a wide variety of flexible and rigid substrates. (The use of the term "printing" is not limited to but is intended to include all forms of printing and coating, including, but is not limited to, pre-measured coatings such as patch-die coating, slot or extrusion coating, slide or cascade coating, curtain coating; roll coatings such as knife-over-roll coating, forward and reverse roll coating; gravure coating; immersion coating; spray coating; meniscus coating; spin coating; brush coating; air knife coating; silkscreen printing process; electrostatic printing process; thermal printing process; inkjet printing process; electrophoretic deposition (see U.S. Patent No. 7,339,715); and other similar techniques.) Therefore, the resulting display can be flexible. Furthermore, since the display medium can be printed (using various methods), the display itself can be manufactured inexpensively.

[0050] As shown above, the simplest conventional electrophoretic media essentially display only two colors. Such electrophoretic media use either a single type of electrophoretic particle having a first color in a colored fluid having a second distinct color (in which case the first color is displayed when the particle is adjacent to the visible surface of the display, and the second color is displayed when the particle is separated from the visible surface), or a first and second type of electrophoretic particle having different first and second colors in an uncolored fluid (in which case the first color is displayed when the first type of particle is adjacent to the visible surface of the display, and the second color is displayed when the second type of particle is adjacent to the visible surface). Typically, the two colors are black and white. If a full-color display is desired, a color filter array can be deposited over the visible surface of a monochrome (black and white) display. Displays with a color filter array rely on area sharing and color blending to create color stimuli. The available display area is shared among three or four primary colors, such as red / green / blue (RGB) or red / green / blue / white (RGBW), and the filters can be arranged in a one-dimensional (striped) or two-dimensional (2x2) repeating pattern. Other choices of primary colors or more than three primary colors are also known in the art. The three (for RGB displays) or four (for RGBW displays) subpixels are selected to be small enough that they visually blend together into a single pixel with a uniform color stimulus ("color blend") at the intended viewing distance. The inherent drawbacks of area sharing are that a colorant is always present, and that color can only be modulated by switching the corresponding pixels of the underlying monochrome display to white or black (switching the corresponding primary color on or off). For example, in an ideal RGBW display, each of the primary colors—red, green, blue, and white—occupies 1 / 4 of the display area (one subpixel out of four), the white subpixel is as bright as the white on the underlying monochrome display, and each of the colored subpixels is no brighter than 1 / 3 of the white on the monochrome display.The brightness of white as a whole displayed by the display cannot exceed half the brightness of a single white subpixel (the white area of ​​the display is generated by displaying one of four white subpixels, and in addition, each colored subpixel in its colored form is equivalent to one-third of a white subpixel, so the combined three colored subpixels contribute to only one white subpixel). The brightness and saturation of a color are reduced by area sharing when the color pixels are switched to black. Area sharing is particularly problematic when mixing yellow, because yellow is brighter than any other color of equal brightness, and saturated yellow is almost as bright as white. Switching the blue pixels (one-quarter of the display area) to black will make the yellow too dark.

[0051] U.S. Patents 8,576,476 and 8,797,634 describe a multicolor electrophoretic display having a single backplane with independently addressable pixel electrodes and a common light-transmitting front electrode. Multiple electrophoretic layers are positioned between the backplane and the front electrode. The displays described in these applications are capable of rendering any of the primary colors (red, green, blue, cyan, magenta, yellow, white, and black) at any pixel location. However, there are drawbacks to using multiple electrophoretic layers positioned between a single set of addressable electrodes. The electric field experienced by particles in a particular layer is lower than that of a single electrophoretic layer treated with the same voltage. In addition, optical losses in the electrophoretic layer closest to the viewing surface (e.g., caused by light scattering or undesirable absorption) can affect the appearance of the image formed in the underlying electrophoretic layer.

[0052] Attempts have been made to provide full-color electrophoretic displays using a single electrophoretic layer. For example, U.S. Patent No. 8,917,439 describes a color display comprising an electrophoretic fluid containing one or two types of pigment particles dispersed in a colorless or colored solvent, the electrophoretic fluid being placed between a common electrode and a number of pixels or driving electrodes. The driving electrodes are arranged to expose the background layer. U.S. Patent No. 9,116,412 describes a method for driving a display cell filled with an electrophoretic fluid containing two types of charged particles having opposite charge polarities and two contrasting colors. The two types of pigment particles are dispersed in a colored solvent, or in a solvent in which uncharged or slightly charged colored particles are dispersed. The method comprises driving the display cell by applying a driving voltage which is about 1 to about 20% of the total driving voltage to display the color of the solvent or the color of the uncharged or slightly charged colored particles. U.S. Patents No. 8,717,664 and 8,964,282 describe electrophoretic fluids and methods for driving electrophoretic displays. The fluids contain first, second, and third types of pigment particles, all dispersed in a solvent or solvent mixture. The first and second types of pigment particles have opposite charge polarities, and the third type of pigment particles have a charge level less than 50% of the charge level of the first or second type. The three types of pigment particles have different levels of threshold voltage, or different levels of mobility, or both.

[0053] Electrophoretic displays capable of rendering any color at any pixel location are described in U.S. Patents 10,475,399 and 10,678,111. Patent 399 describes a display in which a white (light-scattering) pigment moves in a first direction when treated with a low applied voltage and in the opposite direction when treated with a higher voltage. Patent 111 describes a full-color electrophoretic display in which four pigments are present: white, cyan, magenta, and yellow, with two of the pigments being positively charged and two being negatively charged. U.S. Patent Publication 2022 / 0082896 describes a full-color electrophoretic display in which four pigments are present: white, cyan, magenta, and yellow, with three colored pigments being positively charged and the white pigment being negatively charged. Embodiments of this type of invention are referred to as CMYW embodiments.

[0054] In addition, there are multi-particle display designs in which color pigments scatter light (i.e., reflective color particles). U.S. Patent No. 10,339,876 describes this type of display having black, white, and red particles capable of rendering three states. A similar display design containing four pigments can render four different colors (see, for example, U.S. Patent No. 9,922,603), or by using translucent colored particles, such a display can render six colors (see, for example, U.S. Patent No. 11,640,803).

[0055] The electrophoretic media used herein include charged particles whose color, reflectance or absorption properties, charge density, and mobility in an electric field (measured as zeta potential) vary. Particles that absorb, scatter, or reflect light in a broadband or selected wavelength are referred to herein as colored particles or pigment particles. A variety of materials other than pigments (in the strict sense of the term, meaning insoluble coloring materials) that absorb or reflect light, such as dyes, photonic crystals, and quantum dots, may also be used in the electrophoretic media and displays of the present invention. For example, the electrophoretic medium may include a fluid and a plurality of first particles and a plurality of second particles dispersed in the fluid, wherein the first and second particles have charges of opposite polarity, the first particles are light-scattering particles, and the second particles have one of the subtractive primary colors, and a plurality of third particles and a plurality of fourth particles dispersed in the fluid, wherein the third and fourth particles have charges of opposite polarity, the third and fourth particles each have a subtractive primary color that is different from the second particle, and the electric field required to separate aggregates formed by the third and fourth particles is greater than the electric field required to separate aggregates formed by any two other types of particles.

[0056] The electrophoretic media of the present invention may contain, for example, any of the additives used in prior art electrophoretic media, such as those described in the E Ink and MIT patents and applications mentioned above. For example, the electrophoretic media of the present invention typically comprises at least one charge control agent for controlling the charge on various particles, and the fluid may dissolve or disperse therein a polymer having a number-average molecular weight greater than about 20,000 and being essentially non-absorbent to particles in order to improve the bistability of the display, as described in U.S. Patent No. 7,170,670 above.

[0057] In one embodiment, the present invention uses light-scattering particles, typically white, and three substantially non-scattering particles. Naturally, there are no such things as perfectly light-scattering or perfectly non-scattering particles, and the minimum degree of light scattering of the light-scattering particles used in the electrophoresis of the present invention, and the maximum acceptable degree of light scattering in substantially non-scattering particles, can vary somewhat depending on factors such as the exact pigments used, their colors, and the user's or application's ability to tolerate some deviation from the ideal desired color. The scattering and absorption properties of the pigments can be evaluated by measuring the diffuse reflectance of samples of the pigment dispersed in a suitable matrix or liquid against white and dark backgrounds. Results from such measurements can be interpreted according to several models well known in the art, e.g., the one-dimensional Kubelka-Munk treatment. In the present invention, the white pigment preferably exhibits a diffuse reflectance of at least 5% at 550 nm, measured across a black background, when the pigment is distributed approximately isotropically at 15 volume% in a 1 μm thick layer containing the pigment and a liquid with a refractive index of less than 1.55. Yellow, magenta, and cyan pigments preferably exhibit a diffuse reflectance of less than 2.5% at 650, 650, and 450 nm, respectively, measured across a black background under the same conditions. (The wavelengths selected above for the measurement of yellow, magenta, and cyan pigments correspond to the spectral regions of minimum absorption by these pigments.) Coloring pigments that meet these criteria are hereafter referred to as “non-scattering” or “substantially non-light-scattering.” Specific examples of suitable particles are disclosed in U.S. Patent No. 9,921,451, which is incorporated herein by reference.

[0058] Alternative particle sets may be used, which include four sets of reflective particles, or one absorbent particle with three or four sets of different reflective particles, such as those described in U.S. Patents 9,922,603 ​​and 10,032,419, which are incorporated herein by reference. For example, white particles may be formed from inorganic pigments such as TiO2, ZrO2, ZnO, Al2O3, Sb2O3, BaSO4, and PbSO4, while black particles may be formed from CI Pigment Black 26 or 28 (e.g., manganese ferrite black spinel or copper chromite black spinel) or carbon black. Third / fourth / fifth types of particles may be of colors such as red, green, blue, magenta, cyan, or yellow. Pigments of this type of particle may include, but are not limited to, CI pigments PR254, PR122, PR149, PG36, PG58, PG7, PB28, PB15:3, PY138, PY150, PY155, or PY20. Specific examples include Clariant Hostaperm Red D3G 70-EDS, Hostaperm Pink E-EDS, PV fast red D3G, Hostaperm red D3G 70, Hostaperm Blue B2G-EDS, Hostaperm Yellow H4G-EDS, Hostaperm Green GNX, BASF Irgazine red L 3630, Cinquasia Red L 4100 HD, and Irgazin Red L 3660 HD; Sun Chemical phthalocyanine blue, phthalocyanine green, diarylide yellow, or diarylide AAOT yellow.

[0059] As shown in Figures 1A and 1B, an electrophoretic display (101, 102) typically comprises an upper transparent electrode 110, an electrophoretic medium 120, and a bottom electrode 130, the bottom electrode 130 being a pixel electrode of an active matrix of pixels controlled by thin-film transistors (TFTs). While four different types of particles 121, 122, 123, and 124 are present in the electrophoretic medium 120 described herein, more (or fewer) particle sets can be used with the method and display described herein. For example, the technique of the present invention can be used with a set of three types of particles, for example, white, black, and red, where one of the three different types of particles has a lower charge magnitude than the other two types of particles. In some cases, two of the particles are positively charged and one (or two) of the particles are negatively charged. In some cases, one of the particles is positively charged and three of the particles are negatively charged. In some cases, one of the particles is negatively charged and three particles are positively charged. The electrophoretic medium 120 is typically partitioned by the walls of microcapsules 126 or microcells 127, etc. Any adhesive layer 140 can be placed adjacent to any of the layers, but typically it is adjacent to the electrode layer (110 or 130). A given electrophoretic display (105, 106) may have two or more adhesive layers 140, but one layer is more common. The entire display stack is typically mounted on a substrate 150, which may be rigid or flexible. The displays (101, 102) also typically include a protective layer 160, which may simply protect the upper electrode 110 from damage or wrap the entire display (101, 102) to prevent the ingress of water, etc. The electrophoretic displays (101, 102) may also include a sealing layer 180 if necessary. In some embodiments, the adhesive layer 140 may contain a primer component to improve adhesion to the electrode layer 110, or a separate primer layer (not shown in Figure 1B) may be used.The structure of electrophoretic displays, as well as their components, pigments, adhesives, electrode materials, etc., are described in numerous patents and patent applications published by E Ink Corporation, including U.S. Patent Nos. 6,922,276; 7,002,728; 7,072,095; 7,116,318; 7,715,088; and 7,839,564, all of which are incorporated herein by reference in their entirety.

[0060] In some embodiments, as shown in Figure 1A, for example, the electrophoretic display may include a light-transmitting electrode, an electrophoretic medium, and a plurality of rear pixel electrodes. For example, to produce a high-resolution display for displaying an image, each pixel electrode 130 is individually addressable without interference from adjacent pixels so that the image file is faithfully reproduced on the display. One way to achieve this objective is to provide an array of nonlinear elements, such as transistors or diodes, each associated with at least one nonlinear element, to produce an "active matrix" display. (See Figure 2.) The addressing or pixel electrode 130 that addresses a single pixel is connected to a suitable voltage source through the associated nonlinear element. Typically, if the nonlinear element is a transistor, the pixel electrode is connected to the drain of the transistor, and this arrangement is assumed in the following description, but is essentially arbitrary, and the pixel electrode may be connected to the source of the transistor.

[0061] It should be noted that the magnitude of the voltage that can be provided in such row-column driving can be limited by the material from which the nonlinear element, such as a thin-film transistor, is fabricated. In many embodiments, the semiconductor material is silicon, particularly amorphous silicon, which allows the driving voltage to be controlled to about ±15V. In other embodiments, the semiconductor of the thin-film transistor may be a metal oxide such as indium gallium zinc oxide (IGZO), which allows for a wider range of driving voltages, such as up to ±30V, as described, for example, in U.S. Patent Publication No. 2022-0084473. This design feature is particularly suitable when driving a waveform to sort multi-particle pigments. In such systems, it is beneficial to provide at least five voltage levels (high positive, low positive, 0, low negative, high negative), and at higher total voltages, it is easier to separate the particles. For more details, see U.S. Patent Publication No. 2021-0132459. In some embodiments, voltages greater than ±30V (e.g., ±35V, ±45V) can be applied during row-column driving by applying a voltage substantially other than ground (e.g., 0V) to a common voltage reference power supply when driving the display.

[0062] In conventional electrophoretic displays using an active matrix backplane, each pixel electrode is associated with a capacitor electrode (energy storage capacitor) such that the pixel electrode and the capacitor electrode form a capacitor; see, for example, International Patent Application Publication No. 01 / 07961. In some embodiments, an N-type semiconductor (e.g., amorphous silicon) may be used to form transistors, and the “selective” and “deselective” voltages applied to the gate electrode may be positive and negative, respectively.

[0063] Additional details of row-column addressing used in “active matrix” displays are shown in Figure 2. Addressing or pixel electrodes for addressing a single pixel are fabricated on substrate 202 and connected to appropriate voltages via lines 204 and 206 through associated nonlinear elements. It is understood that the voltages supplied on lines 204 and 206 may originate from separate circuit elements, or the voltages may be delivered with the help of a single power supply and power management integrated circuit (“PMIC”). In some cases, intervening source controllers 220 and gate controllers 230 are used to control the supply voltages to the source and gate lines, while in other embodiments, controller 260 is configured to control the entire addressing process, including tuning the gate and source lines.

[0064] Those skilled in the art will understand that the controller 260 of the present invention can be implemented in several different physical forms and can utilize a variety of analog and digital components. For example, the controller 260 may include a general-purpose microprocessor in conjunction with appropriate peripheral components (e.g., one or more digital-to-analog converters, “DAC”) to convert the digital output from the microprocessor into a suitable voltage for application to the pixels. Alternatively, the display controller circuit may be implemented in an application-specific integrated circuit (“ASIC”) or a field-programmable gate array (“FPGA”). Those skilled in the art will understand that the display controller circuit may include both processing components and power management circuits such as the PMIC described above.

[0065] Figure 2 is a diagram of an exemplary layout of the active matrix backplane 200, but it should be understood that in reality the active matrix has depth, and some elements, such as TFTs, may actually be below the pixel electrodes, and vias may provide electrical connections from the drain to the upper pixel electrodes. Furthermore, electrical traces routing signals from the gate and / or source controllers to the respective row and column selection signals of the active matrix backplane 200 can be T-wires extending perpendicularly to the signals they connect.

[0066] Conventionally, in high-resolution arrays, pixels are arranged in a two-dimensional array of rows and columns such that any particular pixel is uniquely defined by the intersection of one designated row and one designated column. The sources of all transistors in each column are connected to a single column (scan) line 206, while the gates of all transistors in each row are connected to a single row (gate) line 208. Here again, the assignment of sources to rows and gates to columns is conventional but essentially arbitrary and can be reversed if desired. The gate line 208 is optionally connected to a gate line driver 212, which essentially ensures that at any given moment only one row is selected, i.e., a selection voltage is applied to the selected row electrodes to ensure that all transistors in the selected row are conductive, while a deselection voltage is applied to all other rows to ensure that all transistors in these unselected rows remain nonconductive. The column scanning lines 206 are optionally connected to a scanning line driver 210 that applies a selected voltage to various scanning lines 206 to drive the pixels in the selected row to their desired optical state. (The aforementioned voltage is applied to a common upper electrode not shown in Figure 2 (e.g., V) COM This is in response to...

[0067] In conventional driving, after a pre-selected interval known as the "line address time," the selected row is deselected, the next row is selected, and the column driver voltage is changed so that the next row of the display is written. This process is repeated linearly, so that the entire display is written line by line. As shown in Figure 2, the time interval between gate voltage pulses in each frame is typically constant, representing the rhythm of the lines due to line addressing. In particular, the present invention does not implement a uniform interval between each gate voltage pulse for a given address row of the pixel electrodes.

[0068] The active matrix backplane, described with respect to Figure 2, is coupled to an electro-optical medium, for example, as shown in Figures 1A and 1B, and is typically sealed, as shown in Figure 3, to create a display module 55. Such a display module 55 forms the core of the electrophoretic display 40. The electrophoretic display 40 typically includes a processor 50 configured to coordinate many functions related to displaying content on the display module 55 and to convert a “standard” image, such as an sRGB image, to a color regime that best replicates the image on the display module 55. Naturally, if the electrophoretic display is used as a sensor or counter, the content may be related to other inputs. The processor is typically a mobile processor chip, such as those from Freescale or Qualcomm, but other manufacturers are also known. The processor frequently communicates with non-temporary memory 70, from which it retrieves image files and / or lookup tables and performs color image conversions, as described later. The non-temporary memory 70 may also contain gate drive instructions to the extent that certain color transitions may require different gate drive patterns. The electrophoretic display 40 may have two or more non-temporary memory chips. The non-temporary memory 70 may be flash memory. In many embodiments, the non-temporary memory 70 is directly integrated into the end consumer device by integrating all the elements of Figure 3 into a circuit board or package. However, in some cases, the driver circuit is not directly integrated into the display, such as when the display is external to an object such as a car.

[0069] Waveforms (described below) are typically stored in non-temporary memory 70, but they can also be incorporated into the controller 60 or processor 50, or they can be stored in the cloud and downloaded via communication 85. Several lookup tables can be used to facilitate the method of the present invention, in particular to provide time-shifted waveforms to the controller 60 as appropriate. In particular, for a given transition from a first color to a second color in an electrophoretic medium having eight primary colors, the lookup table may include instructions to update from color 1 to a later color (without time offset) in lookup slots 1 to 8, instructions to update from color 1 to a later color (with a first time offset) in lookup slots 9 to 16, and instructions to update from color 1 to a later color (with a second time offset) in lookup slots 17 to 24, and so on. Naturally, this type of lookup table can also be indexed for improved performance, taking into account operating conditions such as device temperature, battery health, front light color, and front light intensity.

[0070] Once the desired image is converted for display on the display module 55, a specific image command is sent to the controller 60, which facilitates the transmission of a voltage sequence to each thin-film transistor (described above). Such voltages typically originate from one or more power supplies 80, which may include, for example, a power management integrated chip or PMIC. The electrophoretic display 40 may additionally include communication 85, which may be, for example, the WIFI protocol or BLUETOOTH®, enabling the electrophoretic display 40 to receive images and commands that may be stored in memory 70. The electrophoretic display 40 may additionally include one or more sensors 90, which may include a temperature sensor and / or a photosensor, and such information may be supplied to the processor 50, enabling the processor to select the optimal lookup table when such a lookup table is indexed against ambient temperature or incident illumination intensity or spectrum. In some cases, multiple components of the electrophoretic display 40 can be embedded in a single integrated circuit. For example, a dedicated integrated circuit may perform the functions of the processor 50 and the controller 60.

[0071] The layout of the active matrix backplane 200 shown in Figure 2, and the various components of the electrophoretic display 40 shown in Figure 3, are provided as examples to facilitate the reader's understanding of possible configurations of these structures. Figures 2 and 3 do not necessarily include all elements and components that may be present in an actual electrophoretic display incorporating an active matrix backplane, or all electrical traces and connections between different elements of the backplane.

[0072] Figure 4A is a schematic diagram showing an exemplary gate and source signal routing layout for an active matrix backplane of an electro-optical display. As shown in Figure 4A, a series of T-wires 16 extend from a driver chip or IC 12 along the back of the display panel 14 and are then electrically coupled to specific gate lines 18 on the front of the display panel 14 through individual conductive vias 22 that penetrate the display panel 14. In some embodiments, the T-wires 16 are used to route connections to source lines 20 in addition to, or instead of, the gate lines 18. In some embodiments, the IC 12 shown in Figure 4A is located on the front or back of the display panel substrate.

[0073] As shown in Figure 4A, it is typical that one separate T-wire 16 and one separate via 22 are used to establish connections with each individual gate line 18. In the arrangement shown in Figure 4A, the majority of the rows of pixels (i.e., the long-dimensioned lines of pixels shown as arranged vertically in Figure 4A) are associated with three separate T-wires 16, and in various embodiments, other numbers of T-wires 16 (e.g., two, four, or more) may be associated with each row of pixels. The grouping of vertically extending T-wires 16 typically corresponds to adjacent source lines 20, as shown in Figure 4A.

[0074] Figure 4B is a schematic diagram of an exemplary display pixel including a TFT 24 for applying a voltage waveform from the source line 20 to the pixel electrode 30 when the gate line 18 is set to a voltage sufficient to make the TFT 24 conduct. Furthermore, a capacitor 26 is connected to the pixel electrode 32 at a common voltage or V COMA voltage supply or plane is formed between the TFT 24 and the TFT 24. In some embodiments, direct or indirect coupling between the gate electrode of the TFT 24 and the pixel electrode 32 forms a parasitic capacitance (not shown in Figure 4B). Three T-wires 16 (e.g., T1, T2, and T3) are routed perpendicularly in close proximity to the display pixels to provide connection points between row selection signals driven by the driver IC 12 and the gate lines 18 of the display.

[0075] When using the configurations illustrated in Figures 4A and 4B, the display substrate is typically made from a non-conductive material, so capacitance is generated between the pixel electrodes 32 and the multiple T-wires 16. For example, as shown in Figure 4B, three parasitic capacitances 28 (e.g., C pT1 , C pT2 , and C pT3 A capacitive coupling is formed between the T-wire 16 and the pixel electrode 30. Because the T-wires 16 are typically arranged regularly, multiple adjacent T-wires 16 are often energized simultaneously because they are used to drive transitions between nearby neighboring pixels in the pixel array. This capacitive coupling can result in undesirable optical defects, such as optical properties or responses that vary across different areas of the display, due to certain behaviors.

[0076] As described above, when using conventional methods for driving electrophoretic displays, portions of the electrophoretic layer located above the gate line, above the pixel electrodes positioned above the gate line, and above the T-wire routing lines connected to the gate and / or source lines may be subject to voltage artifacts caused by powering up and down the gate low voltage prior to updating the display. The present invention described herein reduces or minimizes the adverse effects of voltage artifacts induced on the electrophoretic layer by conventional driving methods. In particular, the present invention provides a method for powering up and powering down the gate low voltage in a stepwise manner that divides the received voltage artifacts into a plurality of lower amplitude voltage artifacts. It has been observed that the electrophoretic layer is far less responsive to a series of smaller voltage impulses that are consecutively spaced in time than to a single higher amplitude voltage impulse. Therefore, the stepwise method for powering up and powering down the gate low voltage described herein results in less optical artifacts on the display.

[0077] According to the present invention, the power-up of the gate-low voltage of an active matrix display is performed in two or more stages to bring the gate line voltage from 0 volts to a negative value in preparation for a display refresh cycle. The voltage applied to the gate line of the pixel TFT increases in amplitude in each stage, and the stages are temporally separated for a time of at least a significant proportion of the natural relaxation time of the voltage artifact induced on the electrophoretic layer. In this way, most or all of the voltage associated with the voltage artifact can decay or discharge during the time between stages. Preferably, the time between stages is about the same as this natural relaxation time, and more preferably significantly greater than this natural relaxation time with respect to the relaxation time value exhibited throughout at least a portion of the operating temperature range of the electro-optical display device. This allows all of the voltage associated with the voltage artifact to discharge during the time between stages.

[0078] The power-down of the gate-low voltage in an active-matrix display is also performed in two or more stages to return the gate line voltage from the gate-low voltage value to 0 volts after the display refresh cycle is complete. The voltage applied to the gate line of the pixel TFT decreases in amplitude in each stage, and the stages for powering down the gate-low voltage are temporally separated, similar to the power-up stage described above.

[0079] Figure 5A is a signal waveform diagram 500a illustrating the voltage artifact experienced by the electrophoretic material when the gate-low voltage is powered up in a single step using a conventional driving method. Signal trace 510 illustrates the voltage at the gate line, and signal trace 515 illustrates the voltage measured across the electrophoretic material of the display. Referring to signal trace 510, at time t1, the gate line is driven to the gate-low voltage in a single step. Referring to signal trace 515, it can be seen that powering up the gate-low voltage in this way induces a voltage artifact on the electrophoretic material, which has a magnitude approximately half that of the gate-low voltage applied to the gate line.

[0080] In some embodiments, the gate-low voltage applied to the gate line is -35V. However, as described above, the voltages applied to the row (e.g., gate) and column (e.g., source) signals can vary depending on the material from which the TFT is fabricated (e.g., ±15V, ±30V, ±35V, ±45V).

[0081] Figure 5B is a signal waveform diagram 500b illustrating the voltage artifacts experienced by the electrophoretic material when the gate-low voltage is powered up in two stages according to the driving method disclosed herein. Referring to signal trace 515, at time t1, the gate line is driven to a first-stage voltage that induces a voltage artifact (e.g., a first voltage artifact) on the electrophoretic material. In some embodiments, the first-stage voltage has substantially half the magnitude of the gate-low voltage. The gate line voltage is maintained at the first-stage voltage for a first period, and then driven to the gate-low voltage at time t2, which induces a voltage artifact (e.g., a second voltage artifact) on the electrophoretic material. The gate line is then maintained at the gate-low voltage for a second period, in this case for the remainder of the driving cycle, although in some embodiments this can be shorter. As shown in Figure 5B, the first period is longer than or equal to the time it takes for the first voltage artifact to dissipate or discharge (e.g., to decay to approximately 0V or the reference voltage of the display). Similarly, the second period is longer than or equal to the time it takes for the second voltage artifact to decay or discharge.

[0082] Referring to signal trace 515 in Figure 5B, it can be seen that powering up the gate low voltage in two stages induces first and second voltage artifacts on the electrophoretic material at the start of each stage, with each voltage artifact having approximately half the magnitude of the voltage difference applied to the gate line in each stage. For example, using a gate low voltage of -45V, when the gate line is driven from 0V to -22.5V at the start of the first stage, the voltage difference is 22.5V, and the magnitude of the voltage artifact induced on the electrophoretic material is less than half of -22.5V. Then, when the gate line is driven from -22.5V to -45V at the start of the second stage, the voltage difference between the first and second stages is again 22.5V, and the magnitude of the voltage artifact induced on the electrophoretic material is again less than half of -22.5V. Furthermore, in signal trace 515, it can be seen that the voltage artifact induced at time t1 discharges or decays to approximately 0V by time t2, and the voltage artifact induced at time t2 discharges or decays to approximately 0V within a similar time after time t2.

[0083] Figure 5C is a signal waveform diagram 500c illustrating the voltage artifacts experienced by the electrophoretic material when the gate-low voltage is powered up in three stages according to the driving method disclosed herein. Referring to signal trace 515, at time t1, the gate line is driven to a first-stage voltage that induces a voltage artifact (e.g., a first voltage artifact) on the electrophoretic material. In some embodiments, the first-stage voltage has a magnitude of substantially 1 / 3 of the gate-low voltage. The gate line voltage is maintained at the first-stage voltage for a first period and then driven to a second-stage voltage at time t2, which induces a voltage artifact (e.g., a second voltage artifact) on the electrophoretic material. In some embodiments, the second-stage voltage has a magnitude of substantially 2 / 3 of the gate-low voltage. The gate line voltage is maintained at the second stage voltage for a second period, and then driven down to the gate low voltage at time t3, which induces a voltage artifact (e.g., a third voltage artifact) on the electrophoretic material. The gate line is then maintained at the gate low voltage for a third period, in this case for the remainder of the drive cycle, although in some embodiments this can be shorter.

[0084] As shown in Figure 5C, the first period is longer than or equal to the time it takes for the first voltage artifact to decay or discharge. Similarly, the second period is longer than or equal to the time it takes for the second voltage artifact to decay or discharge, and the third period is longer than or equal to the time it takes for the third voltage artifact to decay or discharge.

[0085] Referring to signal trace 515 in Figure 5C, it can be seen that powering up the gate low voltage in three stages induces first, second, and third voltage artifacts in the electrophoretic material at the start of each respective stage, with each voltage artifact having approximately half the magnitude of the voltage difference applied to the gate line in each stage. For example, when the gate line is driven from 0V to -15V at the start of the first stage, the voltage difference is 15V, and the magnitude of the voltage artifact induced on the electrophoretic material is less than half of -15V. Then, when the gate line is driven from -15V to -30V at the start of the second stage, the voltage difference between the first and second stages is again 15V, and the magnitude of the voltage artifact induced on the electrophoretic material is again less than half of -15V. Finally, when the gate line is driven from -30V to -55V at the start of the third stage, the voltage difference is again 15V, and the magnitude of the voltage artifact induced on the electrophoretic material is again less than half of -15V.

[0086] In signal trace 515, it can be seen that the voltage artifact induced at time t1 discharges or decays back to approximately 0V by time t2, the voltage artifact induced at time t2 discharges or decays back to approximately 0V by time t3, and the voltage artifact induced at time t3 discharges or decays back to approximately 0V within a similar timeframe to the other two stages after time t3.

[0087] As described above, the voltage applied to the gate line at each stage is maintained over the period before the voltage for the next stage is applied. In some embodiments, the stages are temporally separated by at least a substantial amount of the decay time of the voltage artifacts they induce. For example, the voltage artifact decay time after each stage (and thus the minimum time delay between stages) can be around 30-50 ms, depending on factors such as the backplane structure and the conductivity of the electrophoretic material. Thus, in some embodiments, the time delay added to a conventional one-stage routine by powering up the gate-low voltage in two stages is approximately 30-50 ms. In some embodiments, the time delay added to a conventional one-stage routine by powering up the gate-low voltage in three stages is approximately 60-100 ms. In some embodiments, the time delay added to a conventional one-stage routine to power up the gate-low voltage in four stages is approximately 90-150 ms. The present invention is not limited to using only two or three stages. Those skilled in the art will understand that, depending on the system requirements of the display, more delays in powering up the gate-low voltage may be acceptable, and any number of stages can be used.

[0088] Figures 6A to 6C are signal waveform diagrams illustrating the voltage artifacts experienced by the electrophoretic material when the gate-low voltage is powered down in a single step (Figure 6A), in two steps (Figure 6B), and in three steps (Figure 6C) using a conventional drive method. In Figures 6A to 6C, signal trace 610 illustrates the voltage at the gate line, and signal trace 615 illustrates the voltage measured across the electrophoretic material of the display. Referring to the signal trace 615 in each figure, it can be seen that the voltage artifacts induced on the electrophoretic material by powering down the gate-low voltage in one, two, or three steps are substantially similar to the voltage artifacts induced in Figures 5A to 5C above for each method of powering up the gate-low voltage, but the magnitude of the voltage artifact induced by powering down the gate-low voltage is positive, not negative.

[0089] It should be noted that this disclosure primarily concerns active matrix displays that use n-type thin-film transistors in their pixel array. However, those skilled in the art will understand that the electro-optic displays and methods for driving electro-optic displays disclosed herein are equally applicable to active matrix displays based on p-type TFTs and a “gate high” voltage applied to the gate line of each pixel TFT to achieve an unaddressed or deselected state for each row.

[0090] Accordingly, the present invention as described herein reduces or minimizes undesirable optical artifacts arising from capacitive coupling between gate lines and their associated T-wire lines, having a pixel electrode or electrophoretic material on top. Stepwise powering up and down the gate low voltage divides the resulting voltage artifact into a series of lower amplitude voltage artifacts, in contrast to which the electrophoretic layer is far less responsive to a single higher amplitude voltage impulse.

[0091] It will be apparent to those skilled in the art that numerous changes and modifications can be made to the specific embodiments of the present invention described above without departing from the scope of the invention. Therefore, the entire above description should be interpreted illustratively and not restrictively.

[0092] This disclosure provides the aspects and embodiments described in the following clauses.

[0093] Clause 1: A method for driving an electro-optical display comprising a layer of electrophoretic material placed between a common electrode and a backplane, the backplane comprising an array of pixel electrodes, each pixel electrode coupled to a pixel transistor comprising a source electrode, a gate electrode, and a drain electrode, the gate electrode being coupled to a gate line, the source electrode being coupled to a source line, and the drain electrode being coupled to a pixel electrode, the controller providing a time-dependent voltage to the gate line, the source line, and the common electrode, the method for driving comprising: applying a first stage voltage to the gate line, the first stage voltage having a first magnitude which is substantially half the gate low voltage required to de-conduct the pixel transistor; maintaining the first stage voltage on the gate line for a first period of time; and applying a second stage voltage to the gate line, the second stage voltage having a second magnitude which is substantially the gate low voltage required to de-conduct the pixel transistor.

[0094] Clause 2: The method according to Clause 1, wherein the gate low voltage is substantially of -35V or -45V.

[0095] Clause 3: The pixel transistor is an n-type transistor, and the gate low voltage has negative polarity, as described in Clause 1 or 2.

[0096] Clause 4: The pixel transistor is a p-type transistor, and the gate low voltage has positive polarity, as described in Clause 1.

[0097] Clause 5: The first period is 30ms to 50ms, as described in any one of Clauses 1 to 4.

[0098] Clause 6: The second period is 30ms to 50ms, as described in any one of Clauses 1 to 5.

[0099] Clause 7: The method according to any one of Clauses 1 to 6, wherein applying a first-stage voltage to the gate line causes a first voltage artifact on the layer of electrophoretic material.

[0100] Clause 8: The method described in any one of Clauses 1 to 7, wherein the first period is longer than or equal to the discharge time of the first voltage artifact.

[0101] Clause 9: The method according to any one of Clauses 1 to 8, wherein applying a second stage voltage to the gate line causes a second voltage artifact on the layer of electrophoretic material.

[0102] Clause 10: The method described in any one of Clauses 1 to 9, wherein the second period is longer than or equal to the discharge time of the second voltage artifact.

[0103] Clause 11: An electro-optical display comprising: a light-transmitting common electrode; a backplane including an array of pixel electrodes; a layer of electro-optical material placed between the common electrode and the array of pixel electrodes, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode, the gate electrode being coupled to a gate line, the source electrode being coupled to a source line, and the drain electrode being coupled to a pixel electrode; and a controller capable of applying a time-dependent voltage to the gate line, source line, and common electrode, wherein the controller is configured to: apply a first-stage voltage to the gate line having a first magnitude which is substantially half the gate-low voltage required to de-conduct the pixel transistor; maintain the first-stage voltage on the gate line for a first period of time; and apply a second-stage voltage to the gate line having a second magnitude which is substantially the gate-low voltage required to de-conduct the pixel transistor.

[0104] Clause 12: The electro-optical display described in Clause 11 has a gate-low voltage of substantially -35V.

[0105] Clause 13: The pixel transistor is an n-type transistor, and the gate-low voltage has negative polarity, as described in Clause 11 or 12 of the electro-optical display.

[0106] Clause 14: The pixel transistor is a p-type transistor, and the gate low voltage has positive polarity, as described in Clause 11 of the electro-optical display.

[0107] Clause 15: An electro-optical display as described in any one of Clauses 11 to 14, wherein the first period is 30 ms to 50 ms.

[0108] Clause 16: An electro-optical display as described in any one of Clauses 11 to 15, wherein the second period is 30 ms to 50 ms.

[0109] Clause 17: Applying a first-stage voltage to the gate line causes a first-stage voltage artifact in the layer of electrophoretic material, as described in any one of Clauses 11-16 of the electro-optical display.

[0110] Clause 18: An electro-optical display as described in any one of Clauses 11 to 17, wherein the first period is longer than or equal to the discharge time of the first voltage artifact.

[0111] Clause 19: Applying a second-stage voltage to the gate line causes a second voltage artifact in the layer of electrophoretic material, as described in any one of Clauses 11-18 of the electro-optical display.

[0112] Clause 20: An electro-optical display as described in any one of Clauses 11 to 19, wherein the second period is longer than or equal to the discharge time of the second voltage artifact.

[0113] Clause 21: A method for driving an electro-optical display comprising a layer of electrophoretic material placed between a common electrode and a backplane, wherein the backplane comprises an array of pixel electrodes, each pixel electrode being coupled to a pixel transistor comprising a source electrode, a gate electrode, and a drain electrode, the gate electrode being coupled to a gate line, the source electrode being coupled to a source line, and the drain electrode being coupled to a pixel electrode, and a controller providing time-dependent voltages to the gate line, source line, and common electrode, the method for driving is to apply a first-stage voltage to the gate line, the first-stage voltage de-inducting the pixel transistor. A method comprising: having a first magnitude which is substantially 1 / 3 of the gate low voltage required to bring the pixel transistor into a conduction state; maintaining a first stage voltage on the gate line for a first period of time; and applying a second stage voltage to the gate line, wherein the second stage voltage has a second magnitude which is substantially 2 / 3 of the gate low voltage required to bring the pixel transistor into a non-conduction state; maintaining a second stage voltage on the gate line for a second period of time; and applying a third stage voltage to the gate line, wherein the third stage voltage has a third magnitude which is substantially the gate low voltage required to bring the pixel transistor into a non-conduction state.

[0114] Clause 22: The method according to Clause 21, wherein the gate low voltage is substantially of -35V or -45V.

[0115] Clause 23: The method according to Clause 21 or 22, wherein the pixel transistor is an n-type transistor and has a gate-low voltage with negative polarity.

[0116] Clause 24: The method according to Clause 21, wherein the pixel transistor is a p-type transistor and the gate low voltage has positive polarity.

[0117] Clause 25: The first period is 30 ms to 50 ms, as described in any one of Clauses 21 to 24.

[0118] Clause 26: The method described in any one of Clauses 21 to 25, wherein the second period is 30 ms to 50 ms.

[0119] Clause 27: The third period is 30ms to 50ms, as described in any one of Clauses 21 to 26.

[0120] Clause 28: The method according to any one of Clauses 21 to 27, wherein applying a first-stage voltage to the gate line causes a first-stage voltage artifact on the layer of electrophoretic material.

[0121] Clause 29: The method described in any one of Clauses 21 to 28, wherein the first period is longer than or equal to the discharge time of the first voltage artifact.

[0122] Clause 30: The method according to any one of Clauses 21 to 29, wherein applying a second stage voltage to the gate line causes a second voltage artifact on the layer of electrophoretic material.

[0123] Clause 31: The method described in any one of Clauses 21 to 30, wherein the second period is longer than or equal to the discharge time of the second voltage artifact.

[0124] Clause 32: The method according to any one of Clauses 21 to 31, wherein applying a third stage voltage to the gate line causes a third voltage artifact on the layer of electrophoretic material.

[0125] Clause 33: The method described in any one of Clauses 21 to 32, wherein the third period is longer than or equal to the discharge time of the third voltage artifact.

[0126] Cause 34: An electro-optical display comprising: a light-transmitting common electrode; a backplane including an array of pixel electrodes; a layer of electro-optical material placed between the common electrode and the array of pixel electrodes, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode, the gate electrode being coupled to the gate line, the source electrode being coupled to the source line, and the drain electrode being coupled to the pixel electrode; and a controller capable of applying a time-dependent voltage to the gate line, the source line, and the common electrode, the controller being configured to perform the method described in any one of the clauses 21 to 33.

Claims

1. A method for driving an electro-optical display comprising a layer of electrophoretic material placed between a common electrode and a backplane, wherein the backplane comprises an array of pixel electrodes, each pixel electrode being coupled to a pixel transistor comprising a source electrode, a gate electrode, and a drain electrode, the gate electrode being coupled to a gate line, the source electrode being coupled to a source line, and the drain electrode being coupled to the pixel electrode, and a controller providing a time-dependent voltage to the gate line, the source line, and the common electrode, the driving method is Applying a first-stage voltage to the gate line, wherein the first-stage voltage has a first magnitude that is substantially half the gate low voltage required to deconduct the pixel transistor, Maintaining the voltage of the first stage on the gate line over a first period, Applying a second stage voltage to the gate line, wherein the second stage voltage has a second magnitude that is substantially the gate low voltage for causing the pixel transistor to become non-conductive. Methods that include...

2. The method according to claim 1, wherein the gate low voltage has a magnitude of substantially -35V.

3. The method according to claim 1, wherein the pixel transistor is an n-type transistor and the gate low voltage has negative polarity.

4. The method according to claim 1, wherein the pixel transistor is a p-type transistor and the gate low voltage has positive polarity.

5. The method according to claim 1, wherein the first period is 30 ms to 50 ms.

6. The method according to claim 1, wherein the second period is 30 ms to 50 ms.

7. The method according to claim 1, wherein applying the first stage voltage to the gate line causes a first voltage artifact on the layer of electrophoretic material.

8. The method according to claim 7, wherein the first period is longer than or equal to the discharge time of the first voltage artifact.

9. The method according to claim 1, wherein applying the second voltage to the gate line causes a second voltage artifact on the layer of electrophoretic material.

10. The method according to claim 9, wherein the second period is longer than or equal to the discharge time of the second voltage artifact.

11. Electro-optical display, A light-transmitting common electrode, A backplane containing an array of pixel electrodes, A layer of electro-optic material is placed between the common electrode and the array of pixel electrodes, wherein each pixel electrode is coupled to a pixel transistor including a source electrode, a gate electrode, and a drain electrode, the gate electrode is coupled to the gate line, the source electrode is coupled to the source line, and the drain electrode is coupled to the pixel electrode. A controller capable of applying a time-dependent voltage to the gate line, the source line, and the common electrode, wherein the controller Applying a first-stage voltage to the gate line, wherein the first-stage voltage has a first magnitude that is substantially half the gate low voltage required to deconduct the pixel transistor, Maintaining the voltage of the first stage on the gate line over a first period, Applying a second stage voltage to the gate line, wherein the second stage voltage has a second magnitude that is substantially the gate low voltage for causing the pixel transistor to become non-conductive. A controller and An electro-optical display equipped with the following features.

12. The electro-optical display according to claim 11, wherein the gate low voltage has a magnitude of substantially -35V.

13. The electro-optical display according to claim 11, wherein the pixel transistor is an n-type transistor and the gate low voltage has negative polarity.

14. The electro-optical display according to claim 11, wherein the pixel transistor is a p-type transistor and the gate low voltage has positive polarity.

15. The electro-optical display according to claim 11, wherein the first period is 30 ms to 50 ms.

16. The electro-optical display according to claim 11, wherein the second period is 30 ms to 50 ms.

17. The electro-optical display according to claim 11, wherein applying the first stage voltage to the gate line causes a first voltage artifact in the layer of electrophoretic material.

18. The electro-optical display according to claim 17, wherein the first period is longer than or equal to the discharge time of the first voltage artifact.

19. The electro-optical display according to claim 11, wherein applying the second voltage to the gate line causes a second voltage artifact in the layer of electrophoretic material.

20. The electro-optical display according to claim 19, wherein the second period is longer than or equal to the discharge time of the second voltage artifact.

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