Semiconductor structure and method for manufacturing the same

Abstract

The disclosed semiconductor device includes first and second semiconductor stacks stacked vertically. The first semiconductor stack includes a first memory array layer comprising a first array of memory cells, a first peripheral circuit layer comprising a first transistor formed on the first semiconductor layer, and a layer extending vertically through the first semiconductor stack, located between adjacent first arrays of memory cells, and penetrating the first semiconductor layer. pass through The second semiconductor stack includes a first interconnection structure, a second memory array layer including a second array of memory cells, a second peripheral circuit layer formed on the second semiconductor layer and comprising a second transistor, and extending vertically through the second semiconductor stack, and memory cells. Next to It is located between the touching arrays, and the 1 Penetrating the semiconductor layer pass through The first interconnection structure is in contact with the second interconnection structure, and the first semiconductor layer faces the second semiconductor layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor technology, and more specifically, to semiconductor devices and methods of manufacturing the same.

BACKGROUND ART

[0002] Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and manufacturing technologies become difficult and costly. As a result, the memory density of planar memory cells approaches the upper limit.

[0003] Three-dimensional (3D) memory architectures can address the density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral circuits for facilitating operation of the memory array.

SUMMARY OF THE INVENTION

[0004] Some aspects of the present invention provide a semiconductor structure, the semiconductor structure comprising a first semiconductor stack, the first semiconductor stack comprising a first memory array layer having a first array of memory cells, and a first peripheral circuit layer on the first memory array layer, the first peripheral circuit layer comprising a first transistor formed on a first semiconductor layer, A first junction layer on a first semiconductor layer, a first interconnect structure extending vertically through the first semiconductor stack, positioned between adjacent first arrays of memory cells, and extending through the first semiconductor layer and the first bonding layer and a second semiconductor stack, the second semiconductor stack comprising a second memory array layer having a second array of memory cells no A and a second peripheral circuit layer on the second memory array layer, the second peripheral circuit layer comprising a second transistor formed on a second semiconductor layer, A second junction layer on a second semiconductor layer, extending vertically through the second semiconductor stack, adjacent to the memory cells RuA positioned between the arrays, First semiconductor layer and second junction layera second interconnect structure extending therethrough, and a second semiconductor stack comprising the second interconnect structure A first junction layer is joined to a second junction layer, a first interconnection structure is in contact with a second interconnection structure, a first semiconductor layer is located between the first junction layer and a first peripheral circuit layer, and a second semiconductor layer is located between the second junction layer and a second peripheral circuit layer. .

[0005] In some implementations, each of the first array and the second array of memory cells comprises an array of vertical transistors, and each vertical transistor comprises a transistor layer having a vertically extending channel structure, and a storage layer stacked vertically over the transistor layer and comprising an array of capacitors each coupled to a corresponding one of the array of vertical transistors.

[0006] In some implementations, the first semiconductor stack and the second semiconductor stack are hybrid bonded to each other, and the first conductive portion of the first interconnect structure pad is in contact with the second conductive portion of the second interconnect structure pad .

[0007] In some implementations, The first bonding layer is the first conductive portion pad is embedded The first bonding layer comprises a carbon nitride layer, and the second bonding layer comprises a second carbon nitride layer into which a second conductive pad is embedded. .

[0008] In some implementations, The first bonding layer is the first conductive portion pad is embedded The first silicon oxide layer comprises a second bonding layer, the second silicon oxide layer into which the second conductive pad is embedded. .

[0009] In some implementations, the thickness of the first semiconductor stack or the second semiconductor stack is less than 12 μm.

[0010] In some implementations, the first memory array layer is bonded to the first peripheral circuit layer, and the second memory array layer is bonded to the second peripheral circuit layer.

[0011] In several implementation configurations, the first semiconductor stack further comprises a first bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically by passing through the first semiconductor layer twice to interconnect two of the first transistors, and the second semiconductor stack further comprises a second bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically by passing through the second semiconductor layer twice to interconnect two of the second transistors.

[0012] In some implementations, the capacitor array comprises a plurality of first electrodes coupled to an array of vertical transistors and a plurality of second electrodes coupled to a common conductive layer.

[0013] In several implementation configurations, a common conductive layer comprises a main lateral plate in contact with a plurality of second electrodes, a vertical plate in contact with the edge of the main lateral plate, and a lateral landing portion in contact with the vertical plate and a capacitor interconnect structure coupled to a first or second transistor.

[0014] This disclosure Another aspectThe present invention provides a semiconductor structure comprising: a first memory array layer comprising a first memory array layer comprising a first array of memory cells and a first through-array interconnect structure located between the first arrays of memory cells; a first peripheral circuit layer bonded to the first memory array layer comprising a first transistor formed on the first semiconductor layer and a first through-circuit interconnect structure extending through the first semiconductor layer and in contact with the first through-array interconnect structure; and a second memory array layer comprising a second memory cell The first semiconductor stack comprises a second memory array layer comprising an array and a second through-array interconnect structure located between a second array of memory cells, and a second peripheral circuit layer joined to the second memory array layer, the second peripheral circuit layer comprising a second transistor formed on the second semiconductor layer and a second through-circuit interconnect structure extending through the second semiconductor layer and in contact with the second through-array interconnect structure, wherein the first semiconductor stack is joined to the second semiconductor stack such that the first through-circuit interconnect structure is in contact with the second through-circuit interconnect structure.

[0015] In several implementation configurations, each of the first and second arrays of memory cells comprises a transistor layer having an array of vertical transistors, each vertical transistor having a channel structure extending vertically, and a storage layer having an array of capacitors stacked vertically on the transistor layer, each capacitor being coupled to a corresponding one of the arrays of vertical transistors.

[0016] In some implementations, the first semiconductor stack and the second semiconductor are hybrid-junctioned with each other, and the first conductive material of the first through-circuit interconnection structure pad The second conductive of the second through-circuit interconnection structure pad They are in contact with each other.

[0017] In some implementations, the first conductive pad and second conductive pad It is embedded in a bonding layer containing carbon nitride.

[0018] In some implementations, the first conductive pad and second conductive pad It is embedded in a bonding layer containing silicon oxide.

[0019] In some implementation configurations, the thickness of the first or second semiconductor stack is less than 12 μm.

[0020] In some implementation configurations, the first semiconductor layer and the second semiconductor layer are located between the first memory array layer and the second memory array layer.

[0021] In several implementation configurations, the first semiconductor stack further comprises a first bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically by passing through the first semiconductor layer twice to interconnect two of the first transistors, and the second semiconductor stack further comprises a second bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically by passing through the second semiconductor layer twice to interconnect two of the second transistors.

[0022] In some implementations, the capacitor array comprises a plurality of first electrodes coupled to an array of vertical transistors and a plurality of second electrodes coupled to a common conductive layer.

[0023] In several implementation configurations, a common conductive layer comprises a main lateral plate in contact with a plurality of second electrodes, a vertical plate in contact with the edge of the main lateral plate, and a lateral landing portion in contact with the vertical plate and a capacitor interconnect structure coupled to a first or second transistor.

[0024] This disclosure Another aspectThe present invention provides a method for forming a semiconductor structure, the method comprising the steps of forming a first wafer, the first of which a first memory array layer comprising a first array of memory cells, the first of which a first peripheral circuit layer comprising a first transistor formed on a first semiconductor layer, the first of which which comprises a first memory array layer comprising a first memory array layer comprising a first memory array layer comprising a first memory array layer comprising a first peripheral circuit layer comprising a first memory array layer comprising a first interconnection structure extending perpendicularly through the first wafer, located between adjacent first arrays of memory cells, and extending through the first semiconductor layer, and the second of which which comprises a second wafer, the memory cells no A The steps include forming a second memory array layer having rays, forming a second peripheral circuit layer on the second memory array layer having a second transistor formed on a second semiconductor layer, and extending vertically through the second wafer and adjacent to memory cells. RuA It is located between the rays, and the 1 The method includes the steps of forming a second interconnection structure that extends through the semiconductor layer of a first wafer, and joining a first wafer and a second wafer to form a bond structure such that the first interconnection structure is in contact with the second interconnection structure and the first semiconductor layer faces the second semiconductor layer.

[0025] In some implementations, the method further includes the step of cutting the junction structure into multiple semiconductor structures after bonding.

[0026] In some implementations, the step of forming a first memory array layer or a second memory array layer includes the step of forming a transistor layer comprising an array of vertical transistors, wherein each vertical transistor comprises a channel structure extending vertically, and the step of forming a storage layer comprising an array of capacitors stacked vertically on the transistor layer, each of which is coupled to a corresponding one of the array of vertical transistors.

[0027] In several implementation configurations, the step of joining the first wafer and the second semiconductor is performed by the first conductive of the first interconnection structure pad to the second conductive of the second interconnection structure pad This includes the step of joining to it.

[0028] The step of joining the first wafer and the second semiconductor involves bonding the dielectric layer and the first conductive pad A first bonding layer containing carbon nitride and a second conductive pad The process further includes the step of bonding to a second bonding layer which includes the above.

[0029] In several implementation forms , the Steps for forming one wafer or a second wafer Pu is The method further includes the step of thinning the first semiconductor layer or the second semiconductor layer so that the thickness of the first wafer or the second wafer is less than 12 μm.

[0030] In several implementation configurations, the step of forming a first wafer further includes the step of joining a first memory array layer and a first peripheral circuit layer, and the step of forming a second wafer further includes the step of joining a second memory array layer and a second peripheral circuit layer.

[0031] In several implementation configurations, the step of forming a first wafer further includes forming a first bridge contact structure that extends laterally between a first semiconductor layer and a second semiconductor layer and extends vertically by penetrating the first semiconductor layer twice to interconnect two of the first transistors, and the step of forming a second wafer further includes forming a second bridge contact structure that extends laterally between a first semiconductor layer and a second semiconductor layer and extends vertically by penetrating the second semiconductor layer twice to interconnect two of the second transistors.

[0032] In some implementations, the step of forming a memory layer includes the steps of forming a plurality of first electrodes coupled to an array of vertical transistors, forming a plurality of second electrodes insulated from the plurality of first electrodes by a dielectric layer, and forming a common conductive layer coupled to the plurality of second electrodes.

[0033] In several implementation configurations, the step of forming a common conductive layer includes the steps of forming a main lateral plate that contacts a plurality of second electrodes, forming a vertical plate that contacts the edge of the main lateral plate, and forming a lateral landing portion that contacts the vertical plate and also contacts the capacitor interconnect structure.

[0034] Another aspect of the present disclosure provides a method for forming a semiconductor structure, the method comprising the steps of forming at least two DRAM wafers, each DRAM wafer forming step comprising: forming a memory array layer on a first semiconductor layer; forming a peripheral circuit layer on a second semiconductor layer; thinning the second semiconductor layer; and forming a first interconnection structure extending through the second semiconductor layer; and bonding the first DRAM wafer to the second DRAM wafer such that the first interconnection structure of the first DRAM wafer is in contact with the first interconnection structure of the second DRAM wafer.

[0035] In some implementations, the method further includes the steps of: bonding a third DRAM wafer to a fourth DRAM wafer such that a first interconnection structure of the third DRAM wafer is in contact with a first interconnection structure of the fourth DRAM wafer; thinning the first semiconductor layers of the second and third DRAM wafers; forming a second interconnection structure that extends through the first semiconductor layer of the second DRAM wafer and is in contact with the first interconnection structure of the second DRAM wafer, or that extends through the first semiconductor layer of the third DRAM wafer and is in contact with the first interconnection structure of the third DRAM wafer; and bonding a second DRAM wafer to a third DRAM wafer such that a second interconnection structure of the second DRAM wafer is in contact with the first interconnection structure of the fourth DRAM wafer.

[0036] In some implementation configurations, the method further includes the step of bonding a second DRAM wafer to a third DRAM wafer, and then cutting the bonded structure into a plurality of semiconductor structures.

[0037] In some implementations, the step of forming a memory array layer includes the step of forming a transistor layer comprising an array of vertical transistors, wherein each vertical transistor comprises a channel structure extending vertically, and the step of forming a storage layer comprising an array of capacitors stacked vertically on the transistor layer, each of which is coupled to a corresponding one of the array of vertical transistors.

[0038] In several implementation configurations, the step of forming each DRAM wafer includes the step of forming a first bonding layer including a first conductive pad within a first dielectric layer, and the step of bonding the first DRAM wafer to a second DRAM wafer includes the step of hybrid bonding the first bonding layer of the first DRAM wafer to the first bonding layer of the second DRAM wafer such that the first conductive pad in the first bonding layer of the first DRAM wafer is in contact with the first conductive pad in the first bonding layer of the second DRAM wafer.

[0039] In several implementation configurations, the method further includes the step of thinning the first semiconductor layers of a second DRAM wafer and a third DRAM wafer, and then forming a second bonding layer on the first semiconductor layers of the second DRAM wafer and the third DRAM wafer, respectively, wherein each second bonding layer comprises a second conductive pad within a second dielectric layer, and the step of bonding the second DRAM wafer to the third DRAM wafer includes hybrid bonding the second bonding layer of the second DRAM wafer to the second bonding layer of the third DRAM wafer such that the second conductive pad in the second bonding layer of the second DRAM wafer contacts the second conductive pad in the second bonding layer of the third DRAM wafer.

[0040] In some implementation configurations, the step of forming each DRAM wafer further includes the step of bonding the memory array layer and the peripheral circuit layer such that the memory array layer and the peripheral circuit layer are located between a first semiconductor layer and a second semiconductor layer.

[0041] In some implementation configurations, the step of forming each DRAM wafer further includes thinning a second semiconductor layer and then forming a bridge contact structure that extends vertically through the second semiconductor layer twice in order to interconnect two of the transistors in the peripheral circuit layer.

[0042] In some implementations, the step of forming a memory layer includes the steps of forming a plurality of first electrodes coupled to an array of vertical transistors, forming a plurality of second electrodes insulated from the plurality of first electrodes by a dielectric layer, and forming a common conductive layer coupled to the plurality of second electrodes.

[0043] In several implementation configurations, the step of forming a common conductive layer includes the steps of forming a main lateral plate that contacts a plurality of second electrodes, forming a vertical plate that contacts the edge of the main lateral plate, and forming a lateral landing portion that contacts the vertical plate and also contacts the capacitor interconnect structure. [Brief explanation of the drawing]

[0044] The accompanying drawings incorporated herein and forming part thereof illustrate implementations of the disclosure and, together with the descriptions, further assist in explaining the principles of the disclosure and enabling those skilled in the art to implement and use the disclosure. [Figure 1] A schematic circuit diagram of a semiconductor device including a memory cell array according to several implementation forms of this disclosure is shown. [Figure 2A] A schematic block diagram of a cross-section of a first semiconductor device relating to several implementation forms of this disclosure is shown. [Figure 2B]A schematic block diagram of a cross-section of a second semiconductor device relating to several implementation forms of the present disclosure is shown. [Figure 2C] This shows a block diagram of a cross-section of a third semiconductor device relating to several implementation forms of the present disclosure. [Figure 3A] A schematic cross-sectional view of a first semiconductor device relating to several implementation forms of this disclosure is shown. [Figure 3B] A schematic cross-sectional view of a second semiconductor device relating to several implementation forms of this disclosure is shown. [Figure 3C] A schematic cross-sectional view of a third semiconductor device relating to several implementation forms of this disclosure is shown. [Figure 4] This diagram shows a schematic, enlarged cross-sectional view of a portion of a semiconductor device relating to several implementation forms of the present disclosure. [Figure 5] This shows schematic side views of the cross-section of a semiconductor device relating to several implementation forms of this disclosure. [Figure 6] A flowchart of a manufacturing method for forming a semiconductor device relating to several implementation forms of this disclosure is shown. [Figure 7A] Figure 6 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 7B] Figure 6 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 7C] Figure 6 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 7D] Figure 6 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 7E] Figure 6 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 7F] Figure 6 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 7G]Figure 6 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 7H] Figure 6 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 8] A flowchart of a manufacturing method for forming a semiconductor device relating to several implementation forms of this disclosure is shown. [Figure 9A] Figure 8 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 9B] Figure 8 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 10] A flowchart of a manufacturing method for forming a semiconductor device relating to several implementation forms of this disclosure is shown. [Figure 11A] Figure 8 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure. [Figure 11B] Figure 8 shows a schematic diagram of a semiconductor device at a specific manufacturing stage of the method relating to various implementation forms of this disclosure.

[0045] This disclosure will be explained with reference to the attached drawings. [Modes for carrying out the invention]

[0046] While specific configurations and arrangements are described, it should be understood that these are for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used for a variety of other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified with respect to each other and in ways not specifically shown in the drawings, so that these combinations, adjustments, and modifications remain within the scope of this disclosure.

[0047] In general, terms can be understood at least partially from their use in context. For example, the term “one or more” as used herein may, at least partially depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may, at least partially depending on the context, be understood to convey either a singular or plural usage. Furthermore, the term “based on” may be understood not necessarily to convey an exclusive set of factors, but instead, at least partially depending on the context, may allow for the presence of additional factors that are not necessarily explicitly described.

[0048] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted most broadly, so that “on” not only means “directly on” something, but also “on” something with an intermediate feature or layer in between, and “above” or “over” means “above” or “over” something, but also “above” or “over” something without an intermediate feature or layer in between (i.e., directly on something).

[0049] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate descriptions of the relationship between one element or feature and other elements or features, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or in other directions), and the spatially relative descriptors used herein may be interpreted accordingly.

[0050] As used herein, the term “substrate” refers to the material upon which subsequent material layers are added. The substrate itself can be patterned. The material added to the substrate may be patterned or left unpatterned. Furthermore, the substrate may include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate may be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0051] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer may extend over the entirety of a structure below or above it, or may have a smaller extent than the extent of the structure below or above it. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the upper and lower end faces of a continuous structure, or between any pair of horizontal planes between the upper and lower end faces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may contain one or more layers, and / or have one or more layers above, above, and / or below it. A layer may contain multiple layers. For example, an interconnection layer may include one or more conductor and contact layers (on which interconnection lines and / or vertical interconnection access (via) contacts are formed) and one or more dielectric layers.

[0052] Transistors are used as switches or selectors within memory cells in several semiconductor devices, such as dynamic radon-access memory (DRAM). In 1-transistor-1-capacitor (1T1C) DRAM structures or 1-transistor-N-capacitor (1TNC) DRAM structures, data is stored in the capacitor. Conventional DRAM devices employ a 6F2 architecture with logic circuits positioned laterally adjacent to the memory array, which presents challenges in low density and miniaturization. On the other hand, vertical channel DRAM devices employ a 4F2 architecture, where logic circuits overlap vertically with the memory array, thereby saving space and improving density. However, reducing the size of the memory unit remains difficult, along with high manufacturing costs.

[0053] Furthermore, while high-bandwidth memory (HBM) chips are crucial for AI computing capabilities, conventional HBM implementations face significant challenges due to the use of through-silicon vias (TSVs) combined with u-bump technology for stacking DRAM dies. The die-to-die packaging industry faces common but challenging issues. The manufacturing process involves stacking dies, each with a thickness of 50–70 μm. However, the total package thickness limits the number of layers that can be stacked, making it difficult to exceed 16 layers. Additionally, there are limitations to the size of the u-bumps, and TSVs occupy a considerable amount of die area, increasing costs. Moreover, mechanical strength requirements prevent reductions in die thickness, and further reductions in u-bump pitch pose reliability risks. These constraints present significant challenges to scaling HBM technology to meet the growing demand for higher bandwidth in AI applications.

[0054] To address one or more of the aforementioned problems, this disclosure introduces a multi-deck stacked DRAM architecture having logic circuits positioned vertically stacked with a memory array. A corresponding manufacturing process for the multi-deck stacked DRAM architecture. By utilizing inter-wafer hybrid bonding for DRAM stacking, the die thickness can be significantly reduced to approximately 10 μm by holding only the functional memory structure without having to consider mechanical strength. This manufacturing method enables the creation of a 2DRAM die stack that can be stacked in a 2+2 configuration to form a 4-layer DRAM die stack, ultimately resulting in a multi-layer stacked HBM structure.

[0055] By utilizing a new multi-deck stacked DRAM architecture and corresponding new manufacturing methods, the disclosed semiconductor devices can achieve even smaller size and higher memory density. This approach to HBM development using wafer-to-wafer hybrid bonding offers advantages such as reduced overall thickness and higher interconnect density for the same number of stacks. Compared to die-to-die hybrid bonding, wafer-to-wafer hybrid bonding offers significant advantages in terms of thickness reduction, interconnect density, and cost efficiency. For example, the overall thickness of the HBM stack can be reduced by more than 80%, while the interconnect density increases by more than 100 times. This not only makes wafer-to-wafer hybrid bonding more compact but also better addresses the high interconnection requirements of advanced HBM designs, reducing overall process costs. It should also be noted that as the wafer stacking process is repeated multiple times, die yield decreases rapidly, especially at higher stack levels. As a result, the disclosed method imposes stringent requirements on DRAM die yield, making it crucial to maintain high-quality dies throughout the process to achieve a reliable and efficient multilayer HBM structure.

[0056] In accordance with the scope of this disclosure, according to some implementations of this disclosure, the disclosed semiconductor device includes vertical transistors and vertical capacitors. Each vertical transistor includes a vertically extending semiconductor layer and a gate structure located laterally beside the semiconductor layer. In some implementations, word lines and bit lines connected to the vertical transistor are arranged along a first transverse direction and a second transverse direction, respectively. Each vertical capacitor includes a vertically extending first electrode, a second electrode, and a capacitor dielectric between the first and second electrodes. Such an arrangement can increase memory area efficiency. Furthermore, the memory cell array and peripheral circuits can be formed separately on different wafers, thereby preventing the manufacturing processes of the memory cell array and peripheral circuits from affecting each other, and thereby further increasing memory area efficiency.

[0057] Figure 1 shows a schematic diagram of a semiconductor device 100 relating to several aspects of the present disclosure, including an array of memory cells and peripheral circuits, each having a vertical transistor. The semiconductor device 100 may include a memory cell array 110 and peripheral circuits 120 coupled to the memory cell array 110. The memory cell array 110 can be any suitable memory cell array in which each memory cell 130 includes a vertical transistor 132 and a storage unit 134 coupled to the vertical transistor 132. In some implementations, the memory cell array 110 is a DRAM cell array, and the storage unit 134 is a capacitor for storing charge as binary information stored by each DRAM cell. As shown in Figure 1, the memory cells 130 may be arranged in a two-dimensional (2D) array having rows and columns. The peripheral circuits 120 may include any suitable digital, analog, and / or mixed-signal circuits used to facilitate the operation of the memory cell array. For example, the peripheral circuit may include one or more of the following: a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the aforementioned functional circuit (e.g., a sub-circuit), or any active or passive component of the circuit (e.g., a transistor, diode, resistor, or capacitor). The peripheral circuit 120 may, according to several implementation forms, use complementary metal-oxide-semiconductor (CMOS) technology, which can be implemented in, for example, logic processes (e.g., technology nodes such as 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). The semiconductor device 100 may include a word line 140 connecting a peripheral circuit 120 to a memory cell array 110 for controlling the switching of vertical transistors 132 in a row of memory cells 130, and a bit line 150 connecting the peripheral circuit 120 to the memory cell array 110 for transmitting and / or receiving data to and from the row of memory cells 130.In other words, each word line 140 is connected to each row of the memory cell 130, and each bit line 150 is connected to each column of the memory cell 130.

[0058] In accordance with the scope of this disclosure, as described in detail below, vertical transistors 132, such as vertical metal-oxide-semiconductor field-effect transistors (MOSFETs), can replace conventional planar transistors as pass transistors for memory cells 130, reducing the area occupied by pass transistors, coupled capacitance, and interconnect routing complexity. Unlike planar transistors, in which the active region is formed within the substrate, as shown in Figure 1, in some implementations, the vertical transistor 132 includes a semiconductor body extending perpendicularly (in the z-direction) above the substrate (not shown). That is, the semiconductor body extends above the upper surface of the substrate, exposing not only the top surface of the semiconductor body but also one or more of its sides. The semiconductor body can be a rectangular parallelepiped with four exposed faces, for example, as shown in Figure 1. It is understood that the semiconductor body may have any suitable shape, such as a polyhedral or cylindrical shape. That is, the cross-section of the semiconductor body in plan view (e.g., in the xy-plane) can be a square, rectangular (or trapezoidal), circular (or elliptical), or any other suitable shape. In accordance with the scope of this disclosure, with respect to semiconductor bodies having a circular or elliptical cross-section in a plan view, it is understood that the semiconductor body may still be considered to have multiple sides such that the gate structure is coupled to two or more sides of the semiconductor body.

[0059] In some packaging configurations, the semiconductor body can be formed from a substrate (e.g., by etching or epitaxy) and therefore can have the same semiconductor material (e.g., silicon crystalline silicon) as the substrate (e.g., silicon substrate). In some packaging configurations, the semiconductor body can include low-temperature polysilicon (LTPS) and metal oxides such as indium gallium zinc oxide and semiconductor materials. Specifically, the semiconductor body may include indium gallium zinc oxide (In x Ga y Znz O), indium gallium silicon oxide (In x Ga y Si z O), indium tin zinc oxide (In x Sn y Zn z O), indium zinc oxide (In x Zn y O), zinc oxide (Zn x O), zinc tin oxide (Zn x Sn y O), zinc oxynitride (Zn x O y N), zirconium zinc tin oxide (Zr x Zn y Sn z O), tin oxide (Sn x O), hafnium indium zinc oxide (Hf x In y Zn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), aluminum zinc tin oxide (Al x Zn y Sn z O), ytterbium gallium zinc oxide (Yb x Ga y Zn z O), indium gallium oxide (In x Ga y O), and the like, one or more of these can be included.

[0060] As shown in Figure 1, the vertical transistor 132 may also include a gate structure coupled to one or more sides of the semiconductor body. In other words, the active region of the vertical transistor 132, i.e., the semiconductor body, may be at least partially surrounded by the gate structure. The gate structure may also include a gate dielectric coupled to one or more sides of the semiconductor body, for example, to the four sides of the semiconductor body as shown in Figure 1. The gate structure may also include a gate electrode coupled to the gate dielectric across the gate dielectric. The gate dielectric may include any suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. The gate electrode may include any suitable conductive material such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metallic compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides.

[0061] As shown in Figure 1, the vertical transistor 132 may further include a pair of source and drain (S / D, doped regions, also known as source electrode and drain electrode) formed at both ends of the semiconductor body in the vertical direction (z direction). The source and drain can be doped with any suitable P-type dopant such as boron (B) or gallium (Ga), or any suitable N-type dopant such as phosphorus (P) or arsenic (As). The source and drain can be separated in the vertical direction (z-direction) by a gate structure. This allows one or more channels (not shown) of the vertical transistor 132 to be formed vertically between the source and drain of the semiconductor body when the gate voltage applied to the gate electrode of the gate structure exceeds the threshold voltage of the vertical transistor 132.

[0062] In some implementations, the vertical transistor 132 can be a single-gate transistor, for example, to increase transistor and memory cell density, where the gate structure can be located on a single side of the semiconductor body. In some other implementations, the vertical transistor 132 can be a multi-gate transistor. That is, the gate structure can be located laterally on two or more sides of the semiconductor body to form two or more gates, so that two or more channels can be formed between the source and drain during operation. In other words, unlike a planar transistor which contains only a single planar gate (resulting in a single planar channel), the vertical transistor 132 shown in Figure 1 can contain multiple vertical gates on multiple sides of the semiconductor body, due to the semiconductor structure of the semiconductor body and the gate structure located on multiple sides of the semiconductor body. Compared to a planar transistor, the vertical transistor 132 shown in Figure 1 can have a larger gate control region to achieve better channel control with smaller subthreshold fluctuations. Since the channel is completely depleted while in the off state, the leakage current of the vertical transistor 132 can also be significantly reduced. As will be described in detail below, multi-gate vertical transistors can include double-gate vertical transistors (e.g., double-sided gate vertical transistors), triple-gate vertical transistors (e.g., triple-sided gate vertical transistors), and full-circumference gate (GAA) vertical transistors.

[0063] As shown in Figure 1, the storage unit 134 can be coupled to the source or drain of the vertical transistor 132. The storage unit 134 may include any device capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and FRAM® cells, and PCM elements for PCM cells. The peripheral circuit 120 can be coupled to the memory cell array 110 via bit lines 150, word lines 140, and any other suitable metal wiring. As previously mentioned, the peripheral circuit 120 may include any suitable circuitry to facilitate the operation of the memory cell array 110 by applying and sensing voltage and / or current signals to and from each memory cell 130 via the word lines 140 and bit lines 150. The peripheral circuit 120 may include various types of peripheral circuits formed using CMOS technology.

[0064] In some implementations, the memory unit 134 can be a pillar capacitor formed after the vertical transistor 132 is formed. Both the outer and inner surfaces of the pillar capacitor can be used as effective capacitor regions. This structure can be used to achieve a higher packing density in the semiconductor device. In some other implementations, the memory unit 134 can be a cup capacitor formed before the vertical transistor 132 is formed. In such implementations, the high-temperature process for forming the cup capacitor does not affect the formation of the vertical transistor 132. This allows a metal oxide semiconductor to be used as the channel structure of the vertical transistor 132.

[0065] Figure 2A shows a cross-sectional side view of a semiconductor device 200A according to several embodiments of the present disclosure. It should be understood that Figure 2A is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnections) in practice. The semiconductor device 200A may include a memory array layer 210 comprising a plurality of memory cell arrays 212, with a first wiring region 214 between adjacent memory cell arrays 212. The semiconductor device 200A may further include a peripheral circuit layer 220 comprising peripheral circuits 222 of the memory cell arrays 212, with a second wiring region 224 between adjacent peripheral circuits 222.

[0066] In some implementation configurations, the semiconductor device 200A represents an example of a bonded chip. That is, the two layers of the semiconductor device 200A, namely the memory array layer 210 and the peripheral circuit layer 220, can be formed separately on different substrates and then joined at the bonding interface 215 to form a bonded chip. In some other implementation configurations, the semiconductor device 200A represents an example of a single chip. That is, the two layers of the semiconductor device 200A, namely the memory array layer 210 and the peripheral circuit layer 220, can be formed on the same substrate. In some implementation configurations, the thickness of the semiconductor device 200A is less than 12 μm.

[0067] Figure 2B shows a cross-sectional side view of a semiconductor device 200B according to several embodiments of the present disclosure. It should be understood that Figure 2B is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnects) in practice. The semiconductor device 200B may include two vertically stacked semiconductor stacks 230 and 230', each of which may be the same as the semiconductor device 200A described above in relation to Figure 2A. That is, the first semiconductor stack 230 may include a first memory array layer 210 and a first peripheral circuit layer 220, and the second semiconductor stack 230' may include a second memory array layer 210' and a second peripheral circuit layer 220'. In some implementations, the thickness of the first semiconductor stack 230 or the second semiconductor stack 230' is less than 12 μm.

[0068] In some implementation configurations, the semiconductor device 200B is a bonded structure 240 formed by using an inter-wafer hybrid bonding process to bond the first and second semiconductor stacks 230 and 230'. That is, the two entire wafers are hybrid-bonded in a face-to-face manner before the wafers 230 / 230' are cut into dies. Thus, as shown in Figure 2B, the first and second peripheral circuit layers 220 and 220' are bonded to each other at the bonding interface 235, and the first and second memory array layers 210 and 210' sandwich the first and second peripheral circuit layers 220 and 220'. The first interconnection region 214 / 214' and the second interconnection region 224 / 224' are aligned with each other along the vertical direction to form a through-interconnection region 299, realizing signal interconnection between memory cell arrays and peripheral circuits on different wafers.

[0069] Figure 2C shows a cross-sectional side view of a semiconductor device 200C according to several embodiments of the present disclosure. It should be understood that Figure 2C is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnects) in practice. The semiconductor device 200C may include two vertically stacked junction structures 240 and 240', each of which may be the same as the semiconductor device 200B described above in relation to Figure 2B. That is, the first junction structure 240 may include two semiconductor stacks, each including a memory array layer and a peripheral circuit layer, and the second junction structure 240' may also include two semiconductor stacks, each including a memory array layer and a peripheral circuit layer.

[0070] In some implementations, the semiconductor device 200C is a bonded chip formed by using an interwafer hybrid bonding process to bond a first bonding structure 240 and a second bonding structure 240'. That is, the two entire bonded chips are hybrid-bonded face-to-face at the bonding interface 245 before the bonding structures 240 / 240' are cut into a die. Thus, the formed semiconductor device 200C can contain four semiconductor stacks, each including a memory array layer and peripheral circuit layers. In some implementations, each of the four semiconductor stacks has a thickness of less than 12 μm. Note that two semiconductor devices 200C can be further bonded to each other to form an 8-layer DRAM die stack, etc., ultimately resulting in a multilayer stacked HBM structure.

[0071] Figure 3A shows a cross-sectional side view of a semiconductor device 300A, such as the semiconductor device 200A shown in Figure 2A, according to several embodiments of this disclosure.

[0072] In some implementations, the memory array layer 310 includes a plurality of memory cell arrays 313 provided on a substrate 311 in the form of an array of DRAM cells. Each memory cell array 313 can be an array of 1T1C cells, each consisting of one transistor and one capacitor. In some implementations, each memory cell array 313 can include a transistor layer including an array of vertical transistors and a storage layer including an array of vertical capacitors. That is, each DRAM cell includes a vertical capacitor and a vertical transistor coupled to the vertical capacitor. Each vertical capacitor can include a first electrode, a second electrode, and a dielectric layer formed between the first and second electrodes. The first and second electrodes and the dielectric layer can extend vertically (in the z-direction), and the dielectric layer can be sandwiched between the first and second electrodes. In some implementations, the second electrodes can be connected to each other and function as a common electrode 316, and each first electrode can be coupled to the source of each vertical transistor in the same DRAM cell via a source node contact (SNC).

[0073] In some configurations, the first electrode and / or the second electrode may include conductive materials including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some configurations, the first electrode and / or the second electrode may include a multilayer structure, where each layer of the multilayer structure includes one of TiN, TaN, carbon, polysilicon, metals, metal compounds, and silicides. In some configurations, the dielectric layer may include dielectric materials such as silicon oxide, silicon nitride, or high-k dielectrics including, but not limited to, aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), titanium oxide (TiO2), or any combination thereof.

[0074] In some implementations, each vertical transistor (e.g., MOSFET) is configured to switch each DRAM cell. In some implementations, each first transistor includes a semiconductor body extending vertically (in the z-direction) (i.e., an active region where multiple channels may be formed) and a gate structure located on one or more sides of the semiconductor body. In some implementations, the semiconductor body may include any suitable semiconductor material such as single-crystal silicon, polycrystalline silicon, or silicon germanium. In some other implementations, the semiconductor body is In x Ga y Zn z O,In x Ga y Si z O,In x Sn y Zn z O,In x Zn y O,Zn x O,Zn x Sn y O,Zn x O y N,Zr x Zn y Sn z O,Sn x O, Hf x In y Zn zO,Ga x Zn y Sn z O,Al x Zn y Sn z O,Yb x Ga y Zn z O,In x Ga y It may include metal oxide semiconductor materials such as O.

[0075] In some implementations, the semiconductor body extends vertically (z-direction) and includes a source and a drain located at two ends (upper and lower ends) of the semiconductor body, respectively. The source and drain can be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level. In some implementations, the source is coupled to the corresponding vertical capacitor via an SNC, and the drain is coupled to a bit line extending laterally (y-direction). In some implementations, the SNC may contain highly doped polysilicon to form ohmic contact with the source end of the vertical transistor to reduce contact resistance.

[0076] In some implementations, the gate structure of each vertical transistor (not shown in Figure 3A) includes a gate dielectric and a gate electrode. In some implementations, the gate dielectric includes dielectric materials such as silicon oxide, silicon nitride, or high-k dielectrics including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some implementations, the gate electrode includes conductive materials including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some implementations, the gate electrode includes multiple conductive layers, such as a W layer on top of a TiN layer. In one example, the gate structure may be a “gate oxide / gate poly” gate, where the gate dielectric includes silicon oxide and the gate electrode includes doped polysilicon. In another example, the gate structure may be a high-k metal gate (HKMG), where the gate dielectric includes a high-k dielectric and the gate electrode includes a metal.

[0077] In some implementations, the gate electrode may be part of a word line, or it may extend as a word line in the word line direction (x-direction). Each word line can extend in the word line direction (x-direction) and be coupled to a row of DRAM cells. That is, the bit lines and word lines can extend in two perpendicular transverse directions, and the semiconductor body of each vertical transistor can extend in a vertical direction perpendicular to the two transverse directions in which the bit lines and word lines extend.

[0078] In some implementations, the memory array layer 310 may further include one or more interconnection layers, which include interconnection structures for electrically connecting word lines, bit lines, capacitor electrodes, etc., to transfer electrical signals. In some implementations, one or more interconnection layers may include lateral interconnection lines and vertical interconnection access (VIA) contacts. In some implementations, as shown in Figure 3A, one or more first interconnection structures 319 may be located between adjacent memory cell arrays 313 and extend through the memory array layer 310. In some implementations, one or more interconnection layers may also include local interconnections such as bit line contacts, word line contacts, and capacitor contacts.

[0079] As used herein, the term “interconnection” can broadly include any suitable type of interconnection, such as middle-end-of-line (MEOL) interconnections and back-end-of-line (BEOL) interconnections. One or more interconnection layers may further include one or more interlayer dielectric (ILD) layers (also known as “intermetallic dielectric (IMD) layers”) on which interconnection lines and via contacts can be formed. That is, one or more interconnection layers may contain interconnection lines and via contacts within a plurality of ILD layers. The interconnections within one or more interconnection layers may include, but are not limited to, conductive materials such as W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed of dielectric materials including, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0080] In some implementations, the peripheral circuit layer 320 may include a plurality of transistors 323 (e.g., planar transistors and / or semiconductor transistors (not shown)) formed on or within the semiconductor layer 321. Trench isolation (e.g., shallow trench isolation (STI) not shown) and doped regions (e.g., wells, sources, and drains of transistors not shown) may be formed on or within the semiconductor layer 321. In some implementations, the peripheral circuit layer 320 may include one or more interconnection layers containing interconnection structures for electrically connecting the transistors 323 to transfer electrical signals. In some implementations, one or more interconnection layers may include lateral interconnection lines and via contacts. In some implementations, as shown in Figure 3A, one or more second interconnection structures 329 may extend through the semiconductor layer 321. In some implementations, one or more bridge contact structures 326 may extend laterally on the semiconductor layer 321 opposite to the transistors 323 and extend twice vertically through the semiconductor layer 321 to interconnect two of the transistors 323. In some implementations, the peripheral circuit layer 320 may further include a pad-out layer 325 containing pad contacts 327.

[0081] In some implementation configurations, the memory array layer 310 and the peripheral circuit layer 320 can be joined to each other at a bonding interface 315 to form a semiconductor stack 330. The bonding interface 315 can be the interface between the memory array layer 310 and the peripheral circuit layer 320 formed by any suitable bonding technique, such as hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, or eutectic bonding. The first interconnection structure 319 can be joined to the second interconnection structure 329 at the bonding interface 315 to form a through-interconnection portion within the through-interconnection region 399.

[0082] Figure 4 shows schematic enlarged cross-sectional views of the joints of the first and second interconnection structures 319 and 329 in some implementations of the present disclosure. In some implementations, the first interconnection structure 319 includes a first conductive pad 433 in a first bonding layer 410 and a first VIA structure 435 extending through the memory array layer 310. The second interconnection structure 329 includes a second conductive pad 443 in a second bonding layer 420 and a second VIA structure 445 extending through the peripheral circuit layer 320. The first conductive pad 433 is in contact with the second conductive pad 443 by a hybrid bonding between the first bonding layer 410 and the second bonding layer 420. In some implementations, the first bonding layer 410 comprises a first carbon nitride layer into which the first conductive pad 433 is embedded, and the second bonding layer 420 comprises a second carbon nitride layer into which the second conductive pad 443 is embedded. In some implementations, the first bonding layer 410 comprises a first silicon oxide layer into which the first conductive pad 433 is embedded, and the second bonding layer 420 comprises a second silicon oxide layer into which the second conductive pad 443 is embedded.

[0083] Figure 3B shows a cross-sectional side view of a semiconductor device 300B, such as the 200B shown in Figure 2B, according to some aspects of this disclosure.

[0084] In some implementations, the semiconductor device 300B may include two semiconductor stacks 330 and 330', each having the same structure as the semiconductor device 300A described above in relation to Figure 3A. In some implementations, the first semiconductor stack 330 and the second semiconductor stack 330' may be joined to each other in a face-to-face manner to form a junction structure 350. The through-connection portions of the first and second semiconductor stacks 330 and 330' within the through-connection region 399 may be connected at the junction interface 335. The junction portion of the through-connection may be similar to the structure shown in Figure 4 and the corresponding description above.

[0085] In some implementations, as shown in Figure 3B, the original substrate of the second semiconductor stack 330' can be removed, and the pad-out layer 340 can be bonded to the back surface of the second semiconductor stack 330' at the junction interface 345. In some implementations, the pad-out layer 340 may include a substrate 347 and through-contacts 384 extending through the substrate 347. The pad-out layer 340 may further include one or more interconnection layers, which include interconnection structures for electrically connecting the through-contacts 384 to transfer electrical signals. In some implementations, the one or more interconnection layers may include lateral interconnection lines, via contacts, and contact pads 388. In some implementations, as shown in Figure 3B, the through-contacts 384 are located within a through-interconnection region 399 and can be coupled to the interconnection of the second semiconductor stack 330' via the junction interface 345. The junction of the through-interconnection region and the through-contacts 384 may be similar to the structures shown in Figure 4 and the corresponding descriptions above.

[0086] Figure 3C shows a cross-sectional side view of a semiconductor device 300C, such as the 200C shown in Figure 2C, according to several embodiments of this disclosure.

[0087] In some implementations, the semiconductor device 300C may include two junction structures 350 and 350', each having the same structure as the semiconductor device 300B described above in relation to Figure 3B. In some implementations, the first junction structure 350 and the second junction structure 350' can be joined to each other in a face-to-face manner. The through-connection portions of the first and second junction structures 350 and 350' within the through-connection region 399 can be connected at the junction interface 355. The junction portion of the through-connection may be similar to the structure shown in Figure 4 and the corresponding description above.

[0088] In some implementations, as shown in Figure 3C, the original substrate of the second bond structure 350' can be removed, and the pad-out layer 360 can be bonded to the back surface of the second bond structure 350' at the bond interface 365. In some implementations, the pad-out layer 360 may include a substrate 367 and through-contacts 394 extending through the substrate 367. The pad-out layer 360 may further include one or more interconnection layers, which include interconnection structures for electrically connecting the through-contacts 394 to transfer electrical signals. In some implementations, one or more interconnection layers may include lateral interconnection lines, via contacts, and contact pads 398. In some implementations, as shown in Figure 3C, the through-contacts 394 are located within a through-interconnection region 399 and can be coupled to the interconnection of the second bond structure 350' via the bond interface 365. The bond portion of the through-interconnection and the through-contact 394 may be similar to the structure shown in Figure 4 and the corresponding description above.

[0089] Figure 5 shows a cross-sectional side view of a memory device 500 according to several implementation configurations of the present disclosure. The memory device 500 may be a DRAM device. As shown in Figure 5, the memory device 500 may be a chip packing structure including a base substrate 510, one or more die stacks 520 and memory control circuits 530 on a first side of the base substrate 510, a molded compound layer 540 that completely covers one or more die stacks 520 and memory control circuits 530, and a ball grid array (BGA) 550 on a second side opposite to the first side of the base substrate 510.

[0090] The base substrate 510 can be any suitable semiconductor substrate having any suitable structure, such as a single-crystal monolayer substrate, a polycrystalline silicon (polysilicon) monolayer substrate, or a polysilicon and metal multilayer substrate. The base substrate 510 may include a conductive wiring structure 512 embedded therein. The conductive wiring structure 512 may include any suitable conductive interconnect structure, such as conductive vias and patterned conductive layers. The base substrate 510 may further include an array of ball pads 514 on its bottom surface to receive the BGA 550 for both electrical and / or mechanical fastening connections. The array of conductive wiring structures 512 and ball pads 514 may include any suitable conductive material such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art.

[0091] In some implementations, one or more die stacks 520 may include one or more of each of the semiconductor devices 300A / 300B / 300C shown in Figures 3A-3C, as described in detail above. In some implementations, the entire wafer of the semiconductor device 300A / 300B / 300C can be cut to form multiple functional dies, and one or more of these functional dies can be stacked to form a die stack 520. One or more die stacks 520 may be attached to the base substrate 510 by an adhesive film (not shown). The adhesive film may be any suitable die attach film (DAF). In some implementations, the contact pads (also called bond pads, redistribution pads, or similar structures known to those skilled in the art) of the pad-out layer of the semiconductor device 300A / 300B / 300C may be coupled to the conductive interconnect structures of the conductive wiring structure 512 of the base substrate 510.

[0092] In some implementations, the memory control circuit 530 is coupled to one or more die stacks 520 and configured to control and adjust one or more die stacks 520. The memory control circuit 530 can be configured to adjust one or more die stacks 520 and to control the operation of multiple memory cell arrays within one or more die stacks 520. In some implementations, the memory control circuit 530 can also be configured to manage various functions relating to data stored or to be stored in one or more die stacks 520, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some implementations, the memory control circuit 530 is further configured to determine the maximum memory capacity and speed, memory particle data depth and data width, and other important parameters.

[0093] In some implementations, multiple signal wires (not shown) can be electrically connected between multiple bond pads of one or more die stacks 520, a memory control circuit 530, and a conductive wiring structure 512. Thus, one or more die stacks 520 and / or memory control circuits 530 can be coupled with a BGA 550 to connect to an external device such as a printed circuit board (PCB). In some implementations, the BGA 550 may include multiple solder balls located on the bottom surface of the base substrate 510 and mechanically connected to ball pads 514. That is, the solder balls are configured to electrically connect the memory device 500 to the PCB in order to provide electrical signal transmission between the circuit on the PCB and one or more die stacks 520 and / or memory control circuits 530 of the memory device 500. In some configurations, solder balls may include any suitable metallic material such as aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), cobalt (Co), copper (Cu), nickel (Ni), gold (Au), silver (Ag), indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), and any suitable alloy thereof.

[0094] As shown in Figure 5, the memory device 500 may further include a molded compound layer 540 on the base substrate 510 to completely cover one or more die stacks 520 and memory control circuits 530. In some implementations, the molded compound layer 540 may be a thermosetting epoxy molding compound or a thermosetting epoxy molding resin. For example, the molded compound layer 540 may include an inorganic filler (e.g., silica), an epoxy resin, a curing agent, a flame retardant, a curing accelerator, a release agent, and any other suitable components known to those skilled in the art.

[0095] Figure 6 shows a flowchart of a manufacturing method 600 for forming a semiconductor structure, relating to several implementations of the present disclosure. Figures 7A to 7H show schematic diagrams of a semiconductor device at a specific manufacturing stage of the method 600 shown in Figure 6, relating to various implementations of the present disclosure. The steps shown in method 600 are not exhaustive, and it should be understood that other steps may be performed before, after, or between any of the illustrated steps. Furthermore, some of the steps may be performed simultaneously or in an order different from that shown in Figure 6.

[0096] As shown in Figure 6, Method 600 can begin with step 602, which allows for the provision of peripheral circuit layers and memory array layers. Figure 7A shows a schematic side cross-sectional view of the semiconductor structure in the yz plane after step 602 of Method 600.

[0097] In some implementations, as shown in Figure 7A, forming a peripheral circuit layer 720 involves forming a peripheral circuit containing multiple transistors 723 on a semiconductor layer 721. In some implementations, an interconnection layer 728 is formed above the peripheral circuit. The interconnection layer 728 may contain multiple interconnections on one or more ILD layers.

[0098] In some implementations, multiple transistors 723 are formed on the semiconductor layer 721. The transistors can be formed by a number of processes including, but not limited to, photolithography, dry / wet etching, thin-film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes. In some implementations, doped regions are formed within the semiconductor layer 721 by ion implantation and / or thermal diffusion, for example, to function as the source and drain of the transistors 723. In some implementations, isolated regions (e.g., STI) are also formed within the semiconductor layer 721 by wet / dry etching and thin-film deposition. One or more peripheral circuits can be formed on the semiconductor layer 721 of the transistors 723.

[0099] In some implementations, an interconnection layer 728 can be formed above the peripheral circuit having the transistor 723. The interconnection layer 728 may include MEOL and / or BEOL interconnections within multiple ILD layers to provide electrical connections with the transistor 723. In some implementations, the interconnection layer 728 may include multiple ILD layers and interconnections formed by multiple processes. For example, interconnections within the interconnection layer 728 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the interconnection may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layers may include dielectric materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The ILD layers and interconnections shown in Figure 7A can be collectively referred to as the interconnection layer 728.

[0100] In some implementations, a junction layer 726 containing multiple junction contacts is formed above the peripheral circuit (and interconnection layer 728). As shown in Figure 7A, the junction layer 726 is formed above the interconnection layer 728 and the peripheral circuit having the transistor 723. The junction layer 726 may include multiple junction contacts surrounded by a dielectric. In some implementations, a dielectric layer (e.g., an ILD layer) is deposited on the upper surface of the interconnection layer 728 by one or more thin-film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof. The junction contacts can then be formed by first patterning contact holes penetrating the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer) so that they penetrate the dielectric layer and contact the interconnection in the interconnection layer 728. The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling contact holes involves depositing a barrier layer, an adhesive layer, and / or a seed layer before depositing the conductor.

[0101] In some implementations, forming a memory array layer 710 may include forming an array of DRAM cells 713, each containing vertical transistors and memory units on a substrate 711. The substrate 711 may include a carrier substrate. The memory units may include capacitors or PCM elements. In some implementations, capacitors are formed to be coupled to the vertical transistors in each memory cell. In some implementations, forming an array of memory cells may include forming a transistor layer and forming a memory layer. In some implementations, forming a transistor layer may include forming an array of semiconductor bodies, each extending vertically. In some implementations, the manufacturing process for forming the array of semiconductor bodies may include one or more of the following: deposition processes, lithography processes, epitaxial growth processes, dry etching and / or wet etching processes, and / or any other suitable processes. In some implementations, each semiconductor body may function as a channel for a vertical transistor. In some implementations, both ends of each semiconductor body may be doped to form the source / drain for a vertical transistor. In some implementations, an injection process and / or thermal diffusion process is performed to dop a P-type dopant or an N-type dopant into one or more ends of the semiconductor body to form a source / drain.

[0102] In some implementations, forming a transistor layer further includes forming a gate structure on the side surface of the semiconductor body. In some implementations, to form a gate structure, a gate dielectric is formed on the exposed portion of the semiconductor body, a conductive layer is deposited on the gate dielectric, and the conductive layer is patterned to form a gate electrode on the gate dielectric. Note that each formed gate structure lies on one or more sides of the corresponding semiconductor body and can form any suitable type of transistor, such as a single-gate transistor, a double-gate transistor, a gate-all-around (GAA) transistor, or a gate-partial-around (GPA) transistor. In some implementations, the patterned conductive layer can be a word line, each extending in the word line direction (x-direction) and separated by adjacent trenches, and the portion of the patterned conductive layer on the gate dielectric can be the gate electrode.

[0103] In some implementations, forming a memory layer may involve forming an array of memory units in contact with a semiconductor body, for example, one of its doped ends. The memory units may include capacitors or PCM elements. In some implementations, to form a memory unit that is a capacitor, a first electrode is formed on one doped end of the semiconductor body, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric. In some implementations, the manufacturing process for forming the first electrode, the capacitor dielectric, and the second electrode may include one or more thin-film deposition processes (e.g., CVD, PVD, ALD, etc.), patterning and etching processes, and / or any other suitable processes. In some implementations, the second electrode of the capacitor may be coupled to a common conductive layer 712 to function as a common electrode. In some implementations, the common conductive layer 712 includes a main lateral plate in contact with a plurality of second electrodes, a vertical plate in contact with the edge of the main lateral plate, and a lateral landing portion in contact with the vertical plate and the capacitor contacts.

[0104] In some implementations, an interconnection layer 718 containing bit lines is formed above the array of memory cells. As shown in Figure 7A, the interconnection layer 718 can be formed above the DRAM cells 713. The interconnection layer 718 may include MEOL and / or BEOL interconnections within a plurality of ILD layers to provide electrical connections with the DRAM cells 713. In some implementations, the interconnection layer 718 includes a plurality of ILD layers and interconnections formed by a plurality of processes. In some implementations, one or more through-interconnection portions 719 extending through the memory array layer 710 can be formed within a through-interconnection region 799 between adjacent arrays of DRAM cells 713. In some implementations, the through-interconnection 719 and the interconnections within the interconnection layer 718 may include conductive materials deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the interconnects may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer and interconnects shown in Figure 7A can be collectively referred to as the interconnection layer 718.

[0105] In some implementations, forming the interconnection layer 718 involves forming bit lines on the doped source ends of the DRAM cell 713. As shown in Figure 7A, bit lines 714 can be formed on the source ends by patterning and etching trenches aligned with the row of source ends along the bit line direction (y-direction) using lithography and etching processes, and then filling the trenches by depositing conductive material using a thin-film deposition process. This allows bit lines 714 and capacitors, each having a first electrode, a second electrode, and a capacitor dielectric, to be formed on both sides of the semiconductor body and coupled to both ends of the semiconductor body. It is understood that through-interconnections 719 and additional local interconnections such as word line contacts, capacitor contacts, and bit line contacts can also be formed.

[0106] In some implementations, a bonding layer 716 can be formed above the DRAM cell array 713 and the interconnection layer 718, which may include bonding contacts. As shown in Figure 7A, the bonding layer 716 is formed above the interconnection layer 718 and the DRAM cells 713. The bonding layer 716 may include multiple bonding contacts surrounded by dielectrics. In some implementations, a dielectric layer (e.g., an ILD layer) is deposited on the upper surface of the interconnection layer 718 by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Bonding contacts that penetrate the dielectric layer and contact the interconnection in the interconnection layer 718 can then be formed by first patterning contact holes that penetrate the dielectric layer using a patterning process (e.g., photolithography and dry / wet etching of the dielectric material in the dielectric layer). The contact holes can be filled with a conductor (e.g., Cu). In some implementations, filling the contact holes includes depositing a barrier layer, an adhesive layer, and / or a seed layer before depositing the conductor.

[0107] Referring back to Figure 6, Method 600 proceeds to step 604, where the memory array layer and the peripheral circuit layer are joined in a face-to-face manner so that the first array of memory cells is coupled to the peripheral circuit via the junction interface. Figure 7B shows a schematic side cross-sectional view of the semiconductor structure in the yz plane after step 604 of Method 600.

[0108] In some implementations, the junction between the memory array layer 710 and the peripheral circuit layer 720 may include a hybrid junction. In some implementations, the junction contacts in the junction layer 716 of the memory array layer 710 contact the junction contacts in the junction layer 726 of the peripheral circuit layer 720 at the junction interface 715 after junction. In some implementations, the peripheral circuit layer 720 is located on top of the memory array layer 710 after junction.

[0109] As shown in Figure 7A, the semiconductor layer 721 and the components (e.g., peripheral circuits) formed thereon are inverted. As shown in Figure 7A, the bonding interface 715 shown in Figure 7B is formed by bonding with the bonding layer 726 facing downwards and the bonding layer 716 facing upwards, i.e., in a face-to-face configuration. In some mounting configurations, processing steps, such as plasma treatment, wet treatment, and / or heat treatment, are applied to the bonding surface before bonding. After bonding, the bonding contacts within bonding layers 716 and 726 are aligned and in contact with each other, thereby allowing the DRAM cell 713 to be electrically connected to peripheral circuits, including transistors 723, via the bonding interface 715.

[0110] Method 600 proceeds to step 606, where through-connectors can be formed to penetrate the semiconductor layers of the peripheral circuit layer, and a pad-out layer is formed on the back surface of the semiconductor layers of the peripheral circuit layer. Figures 7C to 7G show schematic side cross-sectional views of the semiconductor structure in the yz plane at a specific stage of step 606 of Method 600. Figure 7H shows a schematic side cross-sectional view of the semiconductor stack 750 in the yz plane after step 606 of Method 600.

[0111] As shown in Figure 7C, a patterned mask layer 722 can be formed on the semiconductor layer 721. Using the patterned mask layer 722, multiple openings 729 can be formed that penetrate the semiconductor layer 721 and expose a portion of the interconnection of the interconnection layer 728 of the peripheral circuit layer 720. As shown in Figure 7D, multiple through-interconnections 739 can be formed in the openings 729. In some implementations, some through-interconnections 739 within the through-interconnection region 799 can be coupled to through-interconnections 719 in the memory array layer 710. Some other interconnections 739 can be coupled to interconnections in the interconnection layer 728 of the peripheral circuit layer 720. In some implementations, a patterned conductive layer 737 including a bridge contact structure and / or contact pads can be formed on the patterned mask layer 722 so as to contact the through-interconnections 739. In some implementation configurations, the through-connector 739 and the patterned conductive layer 737 may include, but are not limited to, conductive materials such as W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The patterned mask layer 722 may include, but are not limited to, dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0112] As shown in Figure 7E, an etching stop layer 725 can be formed on the patterned conductive layer 737, and an insulating layer 732 can be formed on the etching stop layer 725. In some configurations, the etching stop layer 725 and the insulating layer 732 may have different dielectric materials with different etching rates in the same etching process. In some configurations, the etching rate of the dielectric material of the etching stop layer 725 may be lower than the etching rate of the dielectric material of the insulating layer 732. For example, the etching stop layer 725 may contain silicon nitride, and the insulating layer 732 may contain silicon oxide. As shown in Figure 7F, the insulating layer 732 can be patterned by forming an opening 731 that exposes a portion of the etching stop layer 725 using a wet etching process. As shown in Figure 7G, a dry etching process such as punch etching can be performed on the exposed portion of the etching stop layer 725 at the bottom of the opening 731 so that the contact pads of the patterned conductive layer 737 are exposed by the opening 731. As shown in Figure 7H, a conductive material can be filled into the opening 731 by a deposition process to form a pad contact 738. In this way, a pad-out layer 735, including pad contacts 738 embedded in the insulating layer 732, is formed on the etching stop layer 725. In some mounting configurations, the pad contacts 738 may include, but are not limited to, conductive materials such as W, Co, Cu, Al, doped silicon, silicides, or any combination thereof.

[0113] Figure 8 shows a flowchart of a manufacturing method 800 for forming a semiconductor structure, relating to several implementations of the present disclosure. Figures 9A and 9B show schematic diagrams of a semiconductor device at a specific manufacturing stage of the method 800 shown in Figure 8, relating to various implementations of the present disclosure. The steps shown in method 800 are not exhaustive, and it should be understood that other steps may be performed before, after, or between any of the illustrated steps. Furthermore, some of the steps may be performed simultaneously or in an order different from that shown in Figure 8.

[0114] As shown in Figure 8, Method 600 can be started in step 802, where two semiconductor stacks are joined in a face-to-face configuration. Figure 9A shows a schematic side cross-sectional view of the semiconductor structure in the yz plane after step 802 of Method 800.

[0115] As shown in Figure 9A, two semiconductor stacks 750 and 750' can be joined in a face-to-face manner. In some implementations, each of the two semiconductor stacks 750 and 750' can be formed by the method described above in relation to Figures 6 and 7A-7H. In some implementations, the joining of the two semiconductor stacks 750 and 750' can include a hybrid joining. In some implementations, the pad contacts 738 and 738' in the pad-out layers 735 and 735' of the two semiconductor stacks 750 and 750' can contact each other at the joining interface 740 after joining.

[0116] As shown in Figure 9A, one semiconductor stack 750' is inverted. The downward-facing pad-out layer 735' is bonded to the upward-facing pad-out layer 735, i.e., in a face-to-face manner, thereby forming the bonding interface 740 shown in Figure 9A. In some implementations, processing steps, such as plasma treatment, wet treatment, and / or heat treatment, are applied to the bonding surface before bonding. After bonding, the pad contacts 738 and 738' within the pad-out layers 735 and 735' are aligned and in contact with each other, thereby allowing the through-interconnections within the through-interconnection region 799 to be electrically connected to each other via the bonding interface 740. In this way, the bonded structure 770 is formed.

[0117] Referring back to Figure 8, Method 800 proceeds to step 804, where the pad-out interconnect layer can be bonded to the junction structure. Figure 9B shows a schematic side cross-sectional view of the semiconductor structure in the yz plane after step 804 of Method 800.

[0118] As shown in Figure 9B, the original substrate 711' of the semiconductor stack 750' can be removed, and a bonding layer 741 including bonding pads can be formed. The bonding layer 741 may include multiple bonding pads surrounded by dielectrics. The manufacturing process for forming the bonding layer 741 can be referenced in the above description and will not be repeated here.

[0119] In some implementations, the pad-out interconnect layer 760 can be bonded to the bonding layer 741 at the bonding interface 745. As shown in Figure 9B, the pad-out interconnect layer 760 may include a substrate 762, a plurality of through-substrate contacts 764, a plurality of interconnect layers 766 bonded to both ends of the through-substrate contacts 764, a plurality of pad contacts 768 bonded to the interconnect layer 766 on one side of the substrate 762, and a bonding layer 761 containing bonding pads on the other side of the substrate 762. In some implementations, the bonding layer 761 of the pad-out interconnect layer 760 is bonded to the bonding layer 741 of the semiconductor stack 750'. In some implementations, the bonding of bonding layers 741 and 761 may include a hybrid bonding. In some implementations, the bonding contacts within bonding layers 741 and 761 are aligned and in contact with each other after bonding.

[0120] Figure 10 shows a flowchart of a manufacturing method 900 for forming a semiconductor structure, relating to several implementations of the present disclosure. Figures 11A and 11B show schematic diagrams of a semiconductor device at a specific manufacturing stage of the method 900 shown in Figure 10, relating to various implementations of the present disclosure. The steps shown in method 900 are not exhaustive, and it should be understood that other steps may be performed before, after, or between any of the illustrated steps. Furthermore, some of the steps may be performed simultaneously or in an order different from that shown in Figure 10.

[0121] As shown in Figure 10, method 900 can be started in step 902, where two junction structures are joined in a face-to-face manner. Figure 11A shows a schematic side cross-sectional view of the semiconductor structure in the yz plane after step 902 of method 900.

[0122] As shown in Figure 11A, the two joint structures 770 and 770' can be joined in a face-to-face manner. In some implementations, each of the two joint structures 770 and 770' can be formed by the method 800 described above in relation to Figures 8 and 9A-9Bni. In some implementations, the joining of the two joint structures 770 and 770' can include a hybrid joining. In some implementations, the joining contacts within the joining layers 741 and 741' of the two joint structures 770 and 770' can come into contact with each other at the joining interface 775 after joining.

[0123] As shown in Figure 11A, one of the bonding structures 770' is inverted. The downward bonding layer 741' is bonded to the upward bonding layer 741, i.e., in a face-to-face manner, thereby forming the bonding interface 775 shown in Figure 11A. In some implementations, processing steps, such as plasma treatment, wet treatment, and / or heat treatment, are applied to the bonding surface before bonding. After bonding, the bonding contacts within bonding layers 741 and 741' are aligned and in contact with each other, thereby allowing the through-connection portions within the through-connection region 799 to be electrically connected to each other via the bonding interface 775.

[0124] Referring back to Figure 10, Method 900 proceeds to step 904, where the pad-out interconnect layer can be bonded to one of the junction structures. Figure 11B shows a schematic side cross-sectional view of the semiconductor structure in the yz plane after step 904 of Method 900.

[0125] As shown in Figure 11B, the original substrate 771' of the bond structure 770' can be removed, and a bond layer 781 including bond pads can be formed. The bond layer 781 may include multiple bond pads surrounded by a dielectric. The manufacturing process for forming the bond layer 781 can be referenced in the above description and will not be repeated here.

[0126] In some implementations, the pad-out interconnect layer 780 can be bonded to the bonding layer 781 at the bonding interface 785. As shown in Figure 11B, the pad-out interconnect layer 780 may include a substrate 782, a plurality of through-substrate contacts 784, a plurality of interconnect layers 786 bonded to both ends of the through-substrate contacts 784, a plurality of pad contacts 788 bonded to the interconnect layer 786 on one side of the substrate 782, and a bonding layer 783 containing bonding pads on the other side of the substrate 782. In some implementations, the bonding layer 783 of the pad-out interconnect layer 780 is bonded to the bonding layer 781 of the bonding structure 770'. In some implementations, the bonding of bonding layers 783 and 781 may include a hybrid bonding. In some implementations, the bonding contacts in bonding layers 783 and 781 are aligned and in contact with each other after bonding.

[0127] The foregoing descriptions of specific implementations may be readily modified and / or adapted for various uses. Such adaptations and modifications are therefore intended to be within the meaning and scope of the equivalents of the disclosed implementations, based on the teachings and guidance presented herein.

[0128] The scope and width of this disclosure should not be limited by any of the aforementioned implementations, but should be defined solely in accordance with the following claims and their equivalents.

Claims

1. A first semiconductor stack, A first memory array layer comprising a first array of memory cells, A first peripheral circuit layer on the first memory array layer, comprising a first transistor formed on the first semiconductor layer, A first interconnection structure extends vertically through the first semiconductor stack, is located between adjacent first arrays of memory cells, and extends through the first semiconductor layer, The first semiconductor stack comprises, A second semiconductor stack, A second memory array layer comprising a second array of memory cells, A second peripheral circuit layer on the second memory array layer, comprising a second transistor formed on the second semiconductor layer, A second interconnection structure extends vertically through the second semiconductor stack, is located between adjacent second arrays of memory cells, and extends through the second semiconductor layer, The second semiconductor stack comprises, Equipped with, The first semiconductor stack is joined to the second semiconductor stack such that the first interconnection structure is in contact with the second interconnection structure and the first semiconductor layer faces the second semiconductor layer. Semiconductor structure.

2. Each of the first and second arrays of memory cells is: A transistor layer comprising an array of vertical transistors, each vertical transistor having a channel structure in which it extends vertically, A memory layer comprising an array of capacitors stacked vertically on the transistor layer, each of which is coupled to a corresponding one of the vertical transistor arrays, The semiconductor structure according to claim 1, comprising:

3. The first semiconductor stack and the second semiconductor stack are hybrid-junctioned with each other. The semiconductor structure according to claim 1, wherein the first conductive plate of the first interconnection structure is in contact with the second conductive plate of the second interconnection structure.

4. The semiconductor structure according to claim 3, wherein the first conductive plate and the second conductive plate are embedded in a junction layer containing carbon nitride.

5. The semiconductor structure according to claim 3, wherein the first conductive plate and the second conductive plate are embedded in a bonding layer containing silicon oxide.

6. The semiconductor structure according to claim 1, wherein the thickness of the first semiconductor stack or the second semiconductor stack is less than 12 μm.

7. The first memory array layer is joined to the first peripheral circuit layer, The semiconductor structure according to claim 1, wherein the second memory array layer is joined to the second peripheral circuit layer.

8. The first semiconductor stack further comprises a first bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically through the first semiconductor layer twice to interconnect two of the first transistors. The second semiconductor stack further comprises a second bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically through the second semiconductor layer twice to interconnect two of the second transistors. The semiconductor structure according to claim 1.

9. The aforementioned capacitor array is A plurality of first electrodes coupled to the array of vertical transistors, Multiple second electrodes coupled to a common conductive layer, The semiconductor structure according to claim 2, comprising:

10. The aforementioned common conductive layer is A main lateral plate that contacts the plurality of second electrodes, A vertical plate that contacts the edge of the main lateral plate, A lateral landing portion that contacts the vertical plate and a capacitor interconnection structure coupled to the first transistor or the second transistor, The semiconductor structure according to claim 9, comprising:

11. The system comprises a first semiconductor stack, and the first semiconductor stack is The first memory array layer, The first array of memory cells, A first through-array interconnect structure located between the first arrays of the memory cells, The first memory array layer comprises, A first peripheral circuit layer joined to the first memory array layer, A first transistor formed on a first semiconductor layer, A first through-circuit interconnection structure extends through the first semiconductor layer and is in contact with the first through-array interconnection structure, The first peripheral circuit layer comprises, Equipped with, The system comprises a second semiconductor stack, the second semiconductor stack being A second memory array layer, The second array of memory cells, A second through-array interconnect structure located between the second arrays of the memory cells, The second memory array layer comprises, A second peripheral circuit layer joined to the second memory array layer, A second transistor formed on a second semiconductor layer, A second through-circuit interconnection structure extends through the second semiconductor layer and is in contact with the second through-array interconnection structure, The second peripheral circuit layer comprises, Equipped with, The first semiconductor stack is joined to the second semiconductor stack such that the first through-circuit interconnection structure is in contact with the second through-circuit interconnection structure. Semiconductor structure.

12. Each of the first and second arrays of memory cells is: A transistor layer comprising an array of vertical transistors, each vertical transistor having a channel structure in which it extends vertically, A memory layer comprising an array of capacitors stacked vertically on the transistor layer, each of which is coupled to a corresponding one of the vertical transistor arrays, The semiconductor structure according to claim 11, comprising:

13. The first semiconductor stack and the second semiconductor stack are hybrid-junctioned with each other. The semiconductor structure according to claim 11, wherein the first conductive plate of the first through-circuit interconnection structure is in contact with the second conductive plate of the second through-circuit interconnection structure.

14. The semiconductor structure according to claim 13, wherein the first conductive plate and the second conductive plate are embedded in a junction layer containing carbon nitride.

15. The semiconductor structure according to claim 13, wherein the first conductive plate and the second conductive plate are embedded in a bonding layer containing silicon oxide.

16. The semiconductor structure according to claim 11, wherein the thickness of the first semiconductor stack or the second semiconductor stack is less than 12 μm.

17. The semiconductor structure according to claim 11, wherein the first semiconductor layer and the second semiconductor layer are located between the first memory array layer and the second memory array layer.

18. The first semiconductor stack further comprises a first bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically through the first semiconductor layer twice to interconnect two of the first transistors. The second semiconductor stack further comprises a second bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically through the second semiconductor layer twice to interconnect two of the second transistors. The semiconductor structure according to claim 11.

19. The aforementioned capacitor array is A plurality of first electrodes coupled to the array of vertical transistors, Multiple second electrodes coupled to a common conductive layer, The semiconductor structure according to claim 12, comprising:

20. The aforementioned common conductive layer is A main lateral plate that contacts the plurality of second electrodes, A vertical plate that contacts the edge of the main lateral plate, A lateral landing portion that contacts the vertical plate and a capacitor interconnection structure coupled to the first transistor or the second transistor, The semiconductor structure according to claim 19, comprising:

21. In a method for forming a semiconductor structure, The step of forming a first wafer, The steps include forming a first memory array layer comprising a first array of memory cells, The steps include forming a first peripheral circuit layer on the first memory array layer, which includes a first transistor formed on the first semiconductor layer, The steps include forming a first interconnection structure that extends vertically through the first wafer, is located between adjacent first arrays of memory cells, and extends through the first semiconductor layer, Steps including, The step of forming a second wafer, The steps include forming a second memory array layer comprising a second array of memory cells, The steps include forming a second peripheral circuit layer on the second memory array layer, which includes a second transistor formed on the second semiconductor layer, The steps include forming a second interconnection structure that extends vertically through the second wafer, is located between adjacent second arrays of memory cells, and extends through the second semiconductor layer, Steps including, The steps of forming a bond structure by joining the first wafer and the second wafer such that the first interconnection structure is in contact with the second interconnection structure and the first semiconductor layer faces the second semiconductor layer, A method that includes this.

22. After bonding, the bonding structure is cut into a plurality of semiconductor structures. The method according to claim 21, further comprising:

23. The step of forming the first memory array layer or the second memory array layer is: A step of forming a transistor layer comprising an array of vertical transistors, wherein each vertical transistor comprises a channel structure extending vertically, The steps include forming a memory layer comprising an array of capacitors stacked vertically on the transistor layer, each of which is coupled to a corresponding one of the vertical transistor arrays, The method according to claim 21, including the method described in claim 21.

24. The step of joining the first wafer and the second wafer is: The method according to claim 21, further comprising the step of joining the first conductive plate of the first interconnection structure to the second conductive plate of the second interconnection structure.

25. The step of joining the first wafer and the second wafer is to join a first bonding layer, which includes a dielectric layer and a first conductive plate, to a second bonding layer, which includes carbon nitride and a second conductive plate. The method according to claim 24, further comprising:

26. The step of forming the first wafer or the second wafer is: A step of thinning the first semiconductor layer or the second semiconductor layer so that the thickness of the first wafer or the second wafer is less than 12 μm. The method according to claim 21, further comprising:

27. The step of forming the first wafer further includes the step of bonding the first memory array layer and the first peripheral circuit layer, The step of forming the second wafer further includes the step of bonding the second memory array layer and the second peripheral circuit layer. The method according to claim 21.

28. The step of forming the first wafer further includes forming a first bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically through the first semiconductor layer twice to interconnect two of the first transistors, The step of forming the second wafer further includes forming a second bridge contact structure that extends laterally between the first semiconductor layer and the second semiconductor layer and extends vertically through the second semiconductor layer twice to interconnect two of the second transistors. The method according to claim 21.

29. The step of forming the memory layer is: The steps include forming a plurality of first electrodes coupled to the array of vertical transistors, The steps include forming a plurality of second electrodes that are insulated from the plurality of first electrodes by a dielectric layer, The steps include forming a common conductive layer that is coupled to the plurality of second electrodes, The method according to claim 23, including the method described in claim 23.

30. The step of forming the common conductive layer is, The steps include forming a main lateral plate that contacts the plurality of second electrodes, The steps include forming a vertical plate that contacts the edge of the main lateral plate, The steps include forming a lateral landing portion that contacts the vertical plate and the capacitor interconnection structure, The method according to claim 29, including the method described in claim 29.

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