Semiconductor power devices

Abstract

A semiconductor power device with low resistance and high breakdown voltage is disclosed. A method for operating the semiconductor power device is disclosed. The semiconductor power device comprises a drain region, a first region in contact with the drain region and having the same conductivity as the drain region, and being doped to a lower concentration than the doping of the drain region, a source region, a second region in contact with the first region and the source region, a gate region, a gate insulating layer in which at least a portion is positioned between the gate region and the second region, a body electrode configured to supply a bias to the second region, and a source electrode configured to supply a bias to the source region, and the second region and the source region can be controlled independently.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor power device.

BACKGROUND ART

[0002] Semiconductor power devices are widely used in many applications.

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0003] A low-resistance and high-withstand-voltage semiconductor power device is disclosed. A method of operating a semiconductor power device is also disclosed.

MEANS FOR SOLVING THE PROBLEMS

[0004] According to one aspect of the present invention, there is provided a semiconductor power device comprising: a drain region; a first region in contact with the drain region, having the same conductivity type as the drain region, and doped at a lower concentration than the doping of the drain region; a source region; a second region in contact with the first region and the source region; a gate region; a gate insulating layer at least partially positioned between the gate region and the second region; a body electrode configured to supply a bias to the second region; and a source electrode configured to supply a bias to the source region, wherein independent control of the second region and the source region is possible.

[0005] In at least one embodiment, in the conduction mode, when a positive voltage is applied to the second region while a substantially zero voltage is applied to the source region, a larger current flows from the drain region to the source region compared to a configuration in which the second region is short-circuited to the source region.

[0006] In at least one embodiment, in the conduction mode, a positive voltage is applied to the gate region, a positive voltage is applied to the drain region, a substantially zero voltage is applied to the source region, and a positive voltage is applied to the second region.

[0007] In at least one embodiment, an intrinsic lateral bipolar transistor is turned on by applying a positive bias to the second region, the source region functions as the emitter region of the lateral bipolar transistor, the second region functions as the base region of the lateral bipolar transistor, and the first region and the drain region function as the collector region of the lateral bipolar transistor.

[0008] In at least one embodiment, when the device is turned off, a negative bias is applied to the second region, increasing the energy barrier between the drain region and the source region, thereby suppressing punch-through and improving the device's breakdown voltage compared to when the second region is grounded.

[0009] In at least one embodiment, the device includes an LDMOS device.

[0010] In at least one embodiment, the second region includes a body region, and the device further comprises a substrate and a third region in contact with the substrate and the second region between the substrate and the second region.

[0011] In at least one embodiment, the semiconductor power device further comprises a body contact region that electrically contacts a body electrode with a body region, the body contact region being doped to a higher concentration than the body region.

[0012] In at least one embodiment, the body contact region extends into the device to a depth greater than the depth of the body region.

[0013] In at least one embodiment, the device includes a VMOS device.

[0014] In at least one embodiment, the drain region includes a substrate, the first region includes a drift region, and the gate region and gate insulating layer are formed in a V-shaped groove that cuts the source region and the second region and extends to the drift region.

[0015] In at least one embodiment, the device includes a UMOS device.

[0016] In at least one embodiment, the drain region includes a substrate, the first region includes a drift region, and the gate region and gate insulating layer are formed within a U-shaped trench.

[0017] In at least one embodiment, the device includes a DVMOS device.

[0018] In at least one embodiment, the drain region includes a substrate, the first region includes a drift region, and current flows from the drain region to the source region in a conductive state.

[0019] In at least one embodiment, the device includes a superjunction vertical channel semiconductor power device.

[0020] In at least one embodiment, the drain region includes a substrate, the first region includes a drift region having the same conductivity type as the substrate and being doped to a lower concentration than the substrate, and the semiconductor power device further includes a second region and a longitudinal region in contact with the drift region, the longitudinal region having a conductivity type different from that of the drift region.

[0021] According to another aspect of the present invention, an insulated-gate bipolar transistor (IGBT) semiconductor power device comprises a substrate having a first conductivity type, a drift region in contact with the substrate and having a second conductivity type different from the first conductivity type, a base region having the first conductivity type and in contact with the drift region, an emitter region in contact with the base region and having a second conductivity type, a gate insulating layer and gate region positioned above the drift region and overlapping a part of the base region, a body electrode electrically connected to the base region, and an emitter electrode electrically connected to the emitter region, wherein the base region and the emitter region can be controlled independently.

[0022] In at least one embodiment, the IGBT semiconductor power device further comprises a collector electrode electrically connected to the substrate, the IGBT semiconductor power device is a vertical channel device, in an on state, a current flows from the collector electrode to the emitter electrode, the power device is turned on by applying a positive voltage to the gate region, and the base region under the gate insulating layer is inverted to form a channel region connecting the emitter region and the drift region.

[0023] In at least one embodiment, when the power device is in a conduction mode, a substantially zero voltage is applied to the emitter region and a positive voltage is applied to the base region, so that a larger current flows from the substrate to the emitter region than in a case where the base region is grounded.

[0024] In at least one embodiment, when the IGBT semiconductor power device is turned off, a negative bias is applied to the body electrode, which increases the energy barrier between the drift region and the emitter region, so that punch-through is suppressed and the withstand voltage of the IGBT semiconductor power device is improved, compared with the case where the base region is grounded.

[0025] In at least one embodiment, by applying a negative bias to the base region, the potential of the base region can be limited to be lower than the latch-up condition of the thyristor element formed by the substrate, the drift region, the base region, and the emitter region, so that the latch-up resistance of the IGBT semiconductor power device is improved.

[0026] According to one aspect of the present invention, a method of operating a semiconductor power device is provided, the semiconductor power device comprising: a drain region; a first region in contact with the drain region, having the same conductivity type as the drain region, and doped at a lower concentration than the drain region; a source region; a second region in contact with the first region and the source region; a gate region; a gate insulating layer at least partially positioned between the gate region and the second region; a body electrode configured to supply a bias to the second region; and a source electrode configured to supply a bias to the source region, the method comprising the steps of: applying a first bias from the body electrode to the second region; and applying a second bias from the source electrode to the source region, wherein the first bias and the second bias are independently controlled.

[0027] In at least one embodiment, in a conduction mode, a positive voltage is applied to the gate region, a positive voltage is applied to the drain region, the second bias is a substantially zero voltage applied to the source region, the first bias is a positive voltage applied to a body contact region electrically connected to the second region, and a larger current flows from the drain region to the source region than in a case where the body contact region is grounded.

[0028] In at least one embodiment, the positive bias applied to the second region via the body contact region also turns on an inherent lateral bipolar transistor, the source region functions as an emitter region, the second region functions as a base region, and the first region and the drain region function as a collector region of the bipolar transistor.

[0029] According to one aspect of the present invention, a method for operating a semiconductor power device is provided, comprising: a drain region; a first region in contact with the drain region and having the same conductivity as the drain region, and being doped to a lower concentration than the drain region; a source region; a second region in contact with the first region and the source region; a gate region; a gate insulating layer, at least a portion of which is positioned between the gate region and the second region; a body electrode configured to supply a bias to the second region; and a source electrode configured to supply a bias to the source region, the method comprising the step of applying a negative bias to the second region when the semiconductor power device is turned off, thereby increasing the energy barrier between the drain region and the source region, suppressing punch-through and improving the withstand voltage of the device compared to the case where the second region is grounded when the semiconductor power device is turned off.

[0030] In at least one embodiment, when the semiconductor power device is off, that is, when the gate region is turned off by applying a bias of approximately 0V, the leakage current between the drain region and the source region is also reduced by applying a negative bias to the second region.

[0031] In at least one embodiment, applying a negative bias to the second region removes charge within the second region, thereby improving the turn-off time of the semiconductor power device.

[0032] In at least one embodiment, the method further includes the step of applying a negative bias to a gate region along with the step of applying a negative bias to a second region.

[0033] In at least one embodiment, the bias is a voltage bias.

[0034] In at least one embodiment, the bias is a current bias.

[0035] According to one aspect of the present invention, a method is provided for operating an insulated-gate bipolar transistor (IGBT) semiconductor power, comprising a substrate having a first conductivity type, a drift region in contact with the substrate and having a second conductivity type different from the first conductivity type, a base region having the first conductivity type and in contact with the drift region, an emitter region in contact with the base region and having a second conductivity type, a gate insulating layer and gate region positioned above the drift region and overlapping a portion of the base region, a body electrode electrically connected to the base region, and an emitter electrode electrically connected to the emitter region, the method comprising the steps of applying a first bias from the body electrode to the base region and applying a second bias from the emitter electrode to the emitter region, wherein the first bias and the second bias are controlled independently.

[0036] In at least one embodiment, the IGBT semiconductor power device further includes a collector electrode electrically connected to a substrate, the IGBT semiconductor power device is a vertical channel device in which current flows from the collector electrode to the emitter electrode when conductive, the method further includes the step of turning on the power device by applying a positive voltage to the gate region, thereby inverting the base region beneath the gate insulating layer to form a channel region connecting the emitter region and the drift region.

[0037] In at least one embodiment, when the power device is in conduction mode, the method includes the step of applying a substantially zero voltage to the emitter region and a positive voltage to the base region, thereby causing a larger current to flow from the substrate to the emitter region than when the base region is grounded.

[0038] In at least one embodiment, the method further includes the step of turning off an IGBT semiconductor power device, which includes applying a negative bias to the body electrodes, thereby increasing the energy barrier between the drain region and the emitter region, thereby suppressing punch-through and improving the breakdown voltage of the IGBT semiconductor power device compared to the case where the base region is grounded.

[0039] In at least one embodiment, by applying a negative bias to the base region, the potential of the base region can be limited to a level lower than the latch-up condition of the thyristor element formed by the substrate, drift region, base region, and emitter region, thereby improving the latch-up immunity of the IGBT semiconductor power device.

[0040] In at least one embodiment, the first bias and the second bias are voltage biases.

[0041] In at least one embodiment, the first bias and the second bias are current biases.

[0042] According to one aspect of the present invention, a driver circuit is provided that generates signals for operating at least one semiconductor power device, the driver circuit generates two signals for each of the at least one semiconductor power device.

[0043] In at least one embodiment, the semiconductor power device includes a gate electrode and a body electrode.

[0044] In at least one embodiment, the two signals include a signal for controlling the gate electrode of a semiconductor power device and a signal for controlling the body electrode of a semiconductor power device.

[0045] In at least one embodiment, signals to the gate electrode and the body electrode can be controlled independently.

[0046] In at least one embodiment, one of the signals has a higher driver current capability than the other signal.

[0047] In at least one embodiment, the polarity of the signal may be positive or negative.

[0048] According to one aspect of the present invention, the power system includes a driver circuit and at least one semiconductor power device, the driver circuit generates two signals for each of the at least one semiconductor power device.

[0049] In at least one embodiment, each semiconductor power device includes a gate electrode and a body electrode.

[0050] In at least one embodiment, the two signals include a signal for controlling the gate electrode and a signal for controlling the body electrode.

[0051] In at least one embodiment, signals to the gate electrode and the body electrode can be controlled independently.

[0052] In at least one embodiment, one of the signals has a higher driver current capability than the other signal.

[0053] In at least one embodiment, the polarity of the signal may be positive or negative.

[0054] According to one aspect of the present invention, a method for reducing variations in a semiconductor power device includes the step of applying a bias to the body electrodes of the semiconductor power device.

[0055] According to one aspect of the present invention, a method for adjusting the characteristics of a semiconductor power device includes the step of applying a bias to the body electrodes of the semiconductor power device.

[0056] These and other advantages of the present invention will become apparent to those skilled in the art upon reading the details of the embodiments described below in more detail. [Brief explanation of the drawing]

[0057] [Figure 1A] This shows a cross-sectional view of a lateral double-diffusion metal-oxide-semiconductor field-effect transistor (lateral double-diffusion MOSFET, or LDMOS) device, as described in the conventional technology. [Figure 1B] This shows a cross-sectional view of a lateral double-diffusion metal-oxide-semiconductor field-effect transistor (lateral double-diffusion MOSFET, or LDMOS) device, as described in the conventional technology. [Figure 1C] This is a cross-sectional view of an LDMOS device according to one embodiment of the present invention. [Figure 1D] Figures 1A-1C and 1E show an intrinsic lateral bipolar transistor in one of the LDMOS devices. [Figure 1E] This is a cross-sectional view of an LDMOS device according to one embodiment of the present invention. [Figure 2] This shows a cross-sectional view of a vertical channel semiconductor power (VMOS) device, as described in the conventional technology. [Figure 3] This shows a cross-sectional view of a vertical channel semiconductor power (UMOS) device, as described in the conventional technology. [Figure 4] A cross-sectional view of a VMOS device according to another embodiment of the present invention is shown. [Figure 5] A cross-sectional view of a UMOS device according to another embodiment of the present invention is shown. [Figure 6] This shows a cross-sectional view of a vertical diffusion metal-oxide-semiconductor (vertical diffusion MOS or VDMOS) device, as described in the conventional technology. [Figure 7] A cross-sectional view of a VDMOS device according to another embodiment of the present invention is shown. [Figure 8] This shows a cross-sectional view of a superjunction vertical power device, as explained using conventional technology. [Figure 9] A cross-sectional view of a superjunction vertical power device according to another embodiment of the present invention is shown. [Figure 10] This shows a cross-sectional view of an insulated-gate bipolar transistor (IGBT) device, as described using conventional technology. [Figure 11] A cross-sectional view of an IGBT device according to another embodiment of the present invention is shown. [Figure 12] A schematic diagram of a system equipped with semiconductor power devices is shown. [Figure 13]A schematic block diagram of the driver circuit according to one embodiment of the present invention is shown. [Figure 14] Figures 14A and 14B schematically show the output signals generated to turn on a semiconductor power device according to one embodiment of the present invention. [Figure 15] Figures 15A and 15B schematically show the output signals generated to turn off a semiconductor power device according to one embodiment of the present invention. [Figure 16] Figure 16A shows a conventional power device schematically represented as a MOSFET device in parallel with a diode. Figure 16B shows power devices schematically represented as MOSFET devices and bipolar transistors according to various embodiments of the present invention. [Figure 17] Figure 17A shows an exemplary distribution of device parameters, such as on-resistance, of a conventional power device. Figure 17B shows an exemplary distribution of device parameters, such as on-resistance, of a power device according to an embodiment of the present invention, in which a positive bias is applied to the body electrodes of a power device with high initial on-resistance in order to reduce the on-resistance. [Modes for carrying out the invention]

[0058] To illustrate the semiconductor power device and the method described herein, it should be understood that the present invention is not limited to the specific embodiments described and is naturally subject to change. The terms used herein are for the sole purpose of describing specific embodiments and are not intended to be limiting, and the scope of the present invention is limited only to the appended claims.

[0059] Where a range of values ​​is indicated, unless otherwise explicitly indicated in the context, each intermediate value between the upper and lower limits of that range is also understood to be specifically disclosed to one-tenth of the unit of the lower limit. Any subrange between any stated value or intermediate value within the range and any other stated value or intermediate value within that range is also included in the present invention. The upper and lower limits of these subranges may be independently included in or excluded from the range, and subranges that include one or neither of these limits, or both, depending on the specifically excluded limits within the range, are also included in the present invention. Where the range includes one or both of the limits, the range excluding one or both of these included limits is also included in the present invention.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention pertains. Any methods and materials similar to or equivalent to those described herein may be used in carrying out or testing the present invention, but preferred methods and materials are described below. All references used herein are incorporated herein by reference to disclose and explain the methods and / or materials related to their citations.

[0061] When used in this specification and the appended claims, it should be noted that, unless explicitly indicated otherwise in the context, singular forms such as "one" and "it" refer to multiple objects. For example, "one cell" refers to multiple such cells, and "its float" refers to one or more floats and their equivalents known to those skilled in the art.

[0062] The documents described herein are provided only for disclosures prior to the filing date of this application. The publication dates provided may differ from the actual publication dates and may need to be verified independently.

[0063] Semiconductor power devices are semiconductor devices that enable operation at high currents and high voltages. Semiconductor power devices can interrupt high voltages, such as 600V or 1200V, when off, and therefore have high junction withstand voltage. The withstand voltage of a power device is much higher than the voltage required to turn the device on. For example, a 1200V device may require a 20V bias to turn on. When a power device is on, a large current can flow through it.

[0064] Figure 1A shows a semiconductor power device 100, often referred to as a lateral double-diffusion MOSFET (LDMOS). The power device 100 includes a substrate 12 of a first conductivity type, such as p-type. Examples of semiconductor materials used in the manufacture of the power device 100 include silicon, silicon carbide, and gallium oxide, but other semiconductor materials may also be included. A region 14 of the first conductivity type is embedded in the substrate 12. The region 14 is usually doped to a lower concentration than the substrate 12. The region 14 can be epitaxially grown on the substrate 12.

[0065] The power device 100 also includes a body region 22 having a first conductivity type. The body region 22 is located between the source region 16 and the drain region, and the drain region includes a low-concentration doped region 24 and a drain region 18. The source region 16, the low-concentration doped region 24, and the drain region 18 have a second conductivity type, such as n-type. The low-concentration doped region 24 is designed so that the power device 100 has high voltage resistance and can operate at high voltage levels, for example, up to 100V. The power device 100 also includes a gate insulating layer 62 and a gate region 60.

[0066] The power device 100 also includes a body contact region 20 having a first conductivity type. The body contact region 20 is typically doped more densely than the body region 22 to reduce contact resistance. To further reduce contact resistance, the body contact region 20 may be deeper, for example, as shown in Figure 1B. In prior art semiconductor power devices, it is known that the body region 22 and the source region 16 are electrically short-circuited, as described, for example, in U.S. Patent Application Publication 2011 / 0294289, "Method for Producing a Connection Electrode for Two Semiconductor Zones Arranged One Above Another," the entire application of which is incorporated herein by reference. This is achieved by a source electrode 40 that electrically short-circuits the body contact region 20 and the source region 16. The power device 100 also includes a drain electrode 42 for electrically connecting to a drain region 18 and a gate electrode (not shown in Figures 1A and 1B) connected to a gate region 60.

[0067] Figure 1C shows an LDMOS device 120 according to one embodiment of the present invention. Similar to LDMOS 100, LDMOS 120 includes a substrate 12 of a first conductivity type, such as p-type; a region 14 of the first conductivity type that is doped to a lower concentration than the substrate 12; a body region 22 having the first conductivity type; a body contact region 20 having the first conductivity type; a source region 16 having a second conductivity type; a drain region 18 having a second conductivity type; a low-concentration doped region 24 having a second conductivity type; a gate insulating layer 62; and a gate region 60.

[0068] The LDMOS device 120 includes a drain electrode 42 electrically connected to the drain region 18, a source electrode 40 electrically connected to the source region 16, and a body electrode 41 electrically connected to the body contact region 20. The source electrode 40 and the body electrode 41 enable independent control of the body region 22 and the source region 16.

[0069] When the LDMOS120 is in conduction mode, a positive voltage is applied to the gate region 60, a positive voltage is applied to the drain region 18, a near-zero voltage is applied to the source region 16, and a positive voltage is applied to the body contact region 20. When a positive voltage is applied to the body contact region 20, a larger current flows (from the drain region 18 to the source region 16) compared to when the body contact region 20 is grounded (as in the LDMOS100, for example).

[0070] This large current is a result of the threshold voltage (Vt) decreasing when the body region 22 is positively biased (through the body contact region 20). The effect of biasing the body region 22 is expressed by the following equation.

number

[0071] During the ceremony, v t This is the threshold voltage when a body bias is present. V t0 This is the threshold voltage when no bias is applied. γ is the body effect coefficient, 2 φp This is the surface potential, V SB This is the bias applied to the body region 22.

[0072] By applying a positive bias to the body region 22 (via the body contact region 20), the intrinsic lateral bipolar transistor 50 (see Figure 1D) is also turned on. In this case, the source region 16 functions as the emitter region, the body region 22 functions as the base region, and the low-concentration doped region 24 and the drain region 18 function as the collector region of the bipolar transistor 50. When the body contact region 20 is positively biased, the lateral bipolar transistor 50 also contributes to a larger current flow (from the drain region 18 to the source region 16).

[0073] When the LDMOS device 120 is turned off, a negative bias can be applied to the body electrode 41. Applying a negative bias to the body region 22 (via the body contact region 20) increases the energy barrier between the drain region 18 and the source region 16, suppressing punch-through and improving the breakdown voltage of the LDMOS device 120 compared to when the body region 22 is grounded (as in LDMOS devices 100 and 102, for example). Applying a negative bias to the body region 22 also reduces the leakage current between the drain region 18 and the source region 16 when the LDMOS device 120 is turned off (when the gate region 60 is turned off by applying a bias of approximately 0V). Furthermore, applying a zero or negative bias to the body region 22 can also remove charge within the body region 22, thus improving the turn-off time of the LDMOS device 120. A negative bias can be applied to the gate region 60 in addition to the body region 22.

[0074] The bias applied to the body region 22 has been described as a voltage bias, i.e., a positive voltage bias when the LDMOS device 120 is ON, and a zero or negative voltage bias when it is OFF. However, a current bias, i.e., a positive current bias when the LDMOS device 120 is ON, and a zero or negative current bias when the LDMOS device 120 is OFF, may also be applied to the body region 22.

[0075] Figure 1E shows an LDMOS device 122, in which case the contact resistance to the body region 22 of the LDMOS device can be reduced by making the body contact region 20 deeper.

[0076] Figure 2 shows a vertical channel semiconductor power device 200, often referred to as a VMOS. The power device 200 includes a substrate 18 having a second conductivity type, such as n-type. Examples of semiconductor materials used in the manufacture of the power device 200 include silicon, silicon carbide, and gallium oxide, but other semiconductor materials may also be included. A drift region 18A of the second conductivity type is embedded in the substrate 18. The drift region 18A is usually doped to a lower concentration than the substrate 18.

[0077] The power device 200 also includes a base region 20 having a first conductivity type, such as p-type. The power device 200 further includes a source region 16 having a second conductivity type. The power device 200 also includes a gate insulating layer 62 and a gate region 60 formed in a V-shaped groove that cuts into the source region 16 and the base region 20 and extends to the drift region 18A. The source electrode 40 electrically short-circuits the base region 20 and the source region 16, while the drain electrode 42 is electrically connected to the bottom of the substrate 18. The power device 200 is a vertical channel device, and in the conductive state, current flows from the drain electrode 42 to the source electrode 40. When the power device is turned on by applying a positive voltage to the gate region 60, the base region 20 below the gate insulating layer 62 inverts, forming a channel region connecting the source region 16 and the drift region 18A.

[0078] Figure 3 shows a vertical channel semiconductor power device 300, often referred to as a UMOS or trench MOS. In the power device 300, the gate insulating layer 62 and the gate region 60 are formed within a U-shaped trench, and the bottom corners of this trench are more rounded than the sharp corners of the V-shaped groove of the VMOS 200. The power device 300 is a vertical channel device, and in the conductive state, current flows from the drain electrode 42 to the source electrode 40. When the power device 300 is turned on by applying a positive voltage to the gate region 60, the base region 20 beneath the gate insulating layer 62 inverts, forming a channel region connecting the source region 16 and the drift region 18A.

[0079] Figure 4 shows a VMOS device 220, in which the body region 20 and the source region 16 can be controlled independently via the body electrode 41 and the source electrode 40, respectively. The body electrode 41 is electrically connected to the body region 20, and the source electrode 40 is electrically connected to the source region 16.

[0080] When the VMOS220 is in conduction mode, a positive voltage is applied to the gate region 60, a positive voltage is applied to the drain region 18, a near-zero voltage is applied to the source region 16, and a positive voltage is applied to the body contact region 20. When a positive voltage is applied to the body contact region 20, a larger current flows (from the drain region 18 to the source region 16) compared to when the body contact region 20 is grounded (as in the VMOS200, for example).

[0081] When the VMOS device 220 is turned off, a negative bias can be applied to the body electrode 41. Applying a negative bias to the body region 22 (via the body electrode 41) increases the energy barrier between the drain region 18 and the source region 16, suppressing punch-through and improving the breakdown voltage of the VMOS device 220 compared to when the body region 20 is grounded (as in the VMOS device 200, for example). Applying a negative bias to the body region 20 also reduces the leakage current (between the drain region 18 and the source region 16) when the VMOS device 120 is off (when the gate region 60 is turned off by applying a bias of approximately 0V). Furthermore, applying a zero or negative bias to the body region 20 can also remove charge within the body region 20, thus improving the turn-off time of the VMOS device 120. A negative bias can be applied to the gate region 60 in addition to the body region 20.

[0082] The bias applied to the body region 20 is described as a voltage bias. However, a current bias may also be applied to the body region 20, i.e., a positive current bias when the VMOS device 220 is ON, and a zero or negative current bias when the VMOS device 220 is OFF.

[0083] Figure 5 shows the UMOS device 320, where the body region 20 and the source region 16 can be controlled independently via the body electrode 41 and the source electrode 40, respectively. The body electrode 41 is electrically connected to the body region 20, and the source electrode 40 is electrically connected to the source region 16.

[0084] When the UMOS220 is in conduction mode, a positive voltage is applied to the gate region 60, a positive voltage is applied to the drain region 18, a near-zero voltage is applied to the source region 16, and a positive voltage is applied to the body contact region 20. When a positive voltage is applied to the body contact region 20, a larger current flows (from the drain region 18 to the source region 16) compared to when the body contact region 20 is grounded (for example, as in the UMOS300).

[0085] When the UMOS device 320 is turned off, a negative bias can be applied to the body electrode 41. Applying a negative bias to the body region 20 (via the body electrode 41) increases the energy barrier between the drain region 18 and the source region 16, suppressing punch-through and improving the breakdown voltage of the UMOS device 320 compared to when the body region 20 is grounded (as in the UMOS device 300, for example). Applying a negative bias to the body region 20 also reduces the leakage current (between the drain region 18 and the source region 16) when the UMOS device 320 is off (when the gate region 60 is turned off by applying a bias of approximately 0V). Furthermore, applying a zero or negative bias to the body region 20 removes charge within the body region 20, and therefore the turn-off time of the UMOS device 320 may be improved. A negative bias can be applied to the gate region 60 in addition to the body region 20.

[0086] The bias applied to the body region 20 is described as a voltage bias. However, a current bias may also be applied to the body region 20, i.e., a positive current bias when the UMOS device 320 is ON, and a zero or negative current bias when the UMOS device 320 is OFF.

[0087] Figure 6 shows a vertical channel semiconductor power device 400, often referred to as a vertical diffuse MOS (VDMOS). The power device 400 includes a substrate 18 of a second conductivity type, such as n-type. Examples of semiconductor materials used in the manufacture of the power device 400 include silicon, silicon carbide, and gallium oxide, but other semiconductor materials may also be included. A drift region 18A of the second conductivity type is embedded in the substrate 18. The drift region 18A is usually doped to a lower concentration than the substrate 18.

[0088] The power device 400 also includes a base region 20 having a first conductivity type, such as p-type. The power device 400 further includes a source region 16 having a second conductivity type. The power device 400 also includes a gate insulating layer 62 and a gate region 60 located above the drift region 18A and overlapping a portion of the body region 20. The source electrode 40 electrically short-circuits the base region 20 and the source region 16, while the drain electrode 42 is electrically connected to the bottom of the substrate 18. The power device 400 is a vertical channel device, and in the conductive state, current flows from the drain electrode 42 to the source electrode 40. When the power device is turned on by applying a positive voltage to the gate region 60, the base region 20 below the gate insulating layer 62 inverts, forming a channel region connecting the source region 16 and the drift region 18A.

[0089] Figure 7 shows a DVMOS device 420, in which the body region 20 and the source region 16 can be controlled independently via the body electrode 41 and the source electrode 40, respectively. The body electrode 41 is electrically connected to the body region 20, and the source electrode 40 is electrically connected to the source region 16.

[0090] When the VDMOS 420 is in conduction mode, a positive voltage is applied to the gate region 60, a positive voltage is applied to the drain region 18, a near-zero voltage is applied to the source region 16, and a positive voltage is applied to the body contact region 20. When a positive voltage is applied to the body contact region 20, a larger current flows (from the drain region 18 to the source region 16) compared to when the body contact region 20 is grounded (as in the VDMOS 400, for example).

[0091] When the VDMOS device 420 is turned off, a negative bias can be applied to the body electrode 41. Applying a negative bias to the body region 20 (via the body electrode 41) increases the energy barrier between the drain region 18 and the source region 16, suppressing punch-through and improving the breakdown voltage of the VDMOS device 420 compared to when the body region 20 is grounded (as in the VDMOS device 400, for example). Applying a negative bias to the body region 20 also reduces the leakage current (between the drain region 18 and the source region 16) when the VDMOS device 420 is off (when the gate region 60 is turned off by applying a bias of approximately 0V). Furthermore, applying a zero or negative bias to the body region 20 removes charge within the body region 20, and therefore the turn-off time of the VDMOS device 420 may be improved. A negative bias can be applied to the gate region 60 in addition to the body region 20.

[0092] The bias applied to the body region 20 is described as a voltage bias. However, a current bias may also be applied to the body region 20, i.e., a positive current bias when the VDMOS device 420 is ON, and a zero or negative current bias when the VDMOS device 420 is OFF.

[0093] Figure 8 shows a superjunction vertical channel semiconductor power device 500. The power device 500 includes a substrate 18 of a second conductivity type, such as n-type. Examples of semiconductor materials used in the manufacture of the power device 500 include silicon, silicon carbide, and gallium oxide, but other semiconductor materials may also be included. A drift region 18A of the second conductivity type is embedded in the substrate 18. The drift region 18A is usually doped to a lower concentration than the substrate 18. The power device 500 also includes a vertical region having a first conductivity type, such as p-type. This results in alternating columns having the first conductivity type 19B and columns having the second conductivity type 18A.

[0094] The power device 500 also includes a base region 20 having a first conductivity type, located above a vertical region 19B having a first conductivity type. The power device 500 further includes a source region 16 having a second conductivity type. The power device 500 also includes a gate insulating layer 62 and a gate region 60 located above a drift region 18A and overlapping a portion of the body region 20. The source electrode 40 electrically short-circuits the base region 20 and the source region 16, while the drain electrode 42 is electrically connected to the bottom of the substrate region 18. The power device 500 is a vertical channel device, and in the conductive state, current flows from the drain electrode 42 to the source electrode 40. When the power device 500 is turned on by applying a positive voltage to the gate region 60, the base region 20 below the gate insulating layer 62 inverts, forming a channel region connecting the source region 16 and the drift region 18A.

[0095] Figure 9 shows a superjunction vertical channel semiconductor power device 520, where the body region 20 and the source region 16 can be controlled independently via the body electrode 41 and the source electrode 40, respectively. The body electrode 41 is electrically connected to the body region 20, and the source electrode 40 is electrically connected to the source region 16.

[0096] When the superjunction power device 520 is in conduction mode, a positive voltage is applied to the gate region 60, a positive voltage is applied to the drain region 18, a near-zero voltage is applied to the source region 16, and a positive voltage is applied to the body contact region 20. When a positive voltage is applied to the body contact region 20, a larger current flows (from the drain region 18 to the source region 16) compared to when the body region 20 is grounded (for example, as in the superjunction power device 500).

[0097] When the superjunction power device 520 is turned off, a negative bias can be applied to the body electrode 41. Applying a negative bias to the body region 20 (via the body electrode 41) increases the energy barrier between the drain region 18 and the source region 16, suppressing punch-through and improving the breakdown voltage of the superjunction power device 420 compared to when the body region 20 is grounded (e.g., as in the superjunction power device 500). Applying a negative bias to the body region 20 also reduces the leakage current (between the drain region 18 and the source region 16) when the superjunction power device 520 is turned off (when the gate region 60 is turned off by applying a bias of approximately 0V). Furthermore, applying a zero or negative bias to the body region 20 removes charge within the body region 20, and therefore the turn-off time of the superjunction power device 520 may be improved. In addition to applying a negative bias to the body region 20, a negative bias can also be applied to the gate region 60.

[0098] The bias applied to the body region 20 is described as a voltage bias. However, a current bias may also be applied to the body region 20, i.e., a positive current bias when the superjunction power device 520 is ON, and a zero or negative current bias when the superjunction power device 520 is OFF.

[0099] Superjunction power devices can also be manufactured laterally by alternating rows of first conductivity type regions 18B and second conductivity type regions 18A. Independent control of the body region 20 and source region 16 can also be implemented in such laterally superjunction power devices, which enables reduced on-resistance and improved breakdown voltage.

[0100] Figure 10 shows a semiconductor power device 600, often referred to as an insulated-gate bipolar transistor (IGBT). The power device 600 includes a substrate 19 of a first conductivity type, such as p-type. Examples of semiconductor materials used in the manufacture of the power device 600 include silicon, silicon carbide, and gallium oxide, but other semiconductor materials may also be included. For example, a drift region 18A of a second conductivity type, such as n-type, is embedded in the substrate 19.

[0101] The power device 600 also includes a base region 20 having a first conductivity type, such as p-type. The power device 600 further includes an emitter region 16 having a second conductivity type. The power device 600 also includes a gate insulating layer 62 and a gate region 60 located above the drift region 18A and overlapping a portion of the base region 20. The emitter electrode 40 electrically short-circuits the base region 20 and the emitter region 16, while the collector electrode 42 is electrically connected to the bottom of the substrate region 19. The power device 600 is a vertical channel device, and in the conductive state, current flows from the collector electrode 42 to the emitter electrode 40. When the power device is turned on by applying a positive voltage to the gate region 60, the base region 20 below the gate insulating layer 62 inverts, forming a channel region connecting the source region 16 and the drift region 18A.

[0102] Figure 11 shows the IGBT620, in which the base region 20 and the emitter region 16 can be controlled independently via the body electrode 41 and the emitter electrode 40, respectively. The body electrode 41 is electrically connected to the base region 20, and the emitter electrode 40 is electrically connected to the emitter region 16.

[0103] When the IGBT620 is in conduction mode, a positive voltage is applied to the gate region 60, a positive voltage is applied to the substrate 19, a near-zero voltage is applied to the emitter region 16, and a positive voltage is applied to the base region 20. When a positive voltage is applied to the base region 20, a larger current flows (from the substrate 19 to the emitter region 16) compared to when the base region 20 is grounded (as in the IGBT600, for example).

[0104] When the IGBT620 is turned off, a negative bias can be applied to the body electrode 41. Applying a negative bias to the base region 20 (via the body electrode 41) increases the energy barrier between the drift region 18A and the emitter region 16, suppressing punch-through and improving the breakdown voltage of the IGBT620 compared to when the base region 20 is grounded (as in the IGBT600, for example). Applying a negative bias to the base region 20 also reduces the leakage current (between the substrate 19 and the emitter region 16) when the IGBT620 is off (when the gate region 60 is turned off by applying a bias of approximately 0V). Furthermore, applying a zero or negative bias to the base region 20 removes charge within the base region 20, and therefore the turn-off time of the IGBT device 620 may be improved. A negative bias can be applied to the gate region 60 in addition to the base region 20.

[0105] By applying a negative bias to the base region 20 of the IGBT620, the potential of the base region 20 can be limited to a level lower than the latch-up condition of the thyristor element formed by the substrate 19, drift region 18A, base region 20, and emitter region 16, thereby improving the latch-up immunity of the IGBT620 device.

[0106] The bias applied to the base region 20 is described as a voltage bias. However, a current bias may also be applied to the base region 20, i.e., a positive current bias when the IGBT device 620 is ON, and a zero or negative current bias when the IGBT device 620 is OFF.

[0107] Figure 12 shows a schematic diagram of system 800 with power device 840. Power device 840 may be any of the following power devices, including but not limited to LDMOS devices 120 and 122, VMOS device 220, UMOS device 320, VDMOS device 420, superjunction device 520, and IGBT 620. Power system 800 also includes a control circuit 820 that supplies input to a driver circuit 830. The driver circuit 830 generates the voltage or current signals necessary to operate power device 840, including but not limited to signals, voltage levels, and current levels for gate electrode / region, source electrode, drain electrode, and body electrode. The control circuit 820, driver circuit 830, and power device 840 may be in the form of separate components and then integrated to form the power system 800 module. Power system 800 may also include other components, such as passive components such as resistors, capacitors, and inductors, and / or additional circuits for energy harvesting. In another embodiment of the present invention, the control circuit 820, the driver circuit 830, and the power device 840 may be integrated into a single package as separate semiconductor dies. Alternatively, the control circuit 820, the driver circuit 830, and the power device 840 may be an integrated chip.

[0108] Figure 13 shows an exemplary block diagram of the driver circuit 830. VDD and GND supply the power supply voltage to the driver circuit 830. The INPUT signal instructs the power device 840 to be turned on or off by supplying output signals VG and VP. The CE signal can be used to control the timing of the power device 840 or adjust its duty cycle. The driver circuit 830 may also have additional control signals to control the timing of the VG and VP output signals, such as pulse width, delay time, and slew rate. Alternatively, the driver circuit 830 may include programmable bits that can be used for timing control. The driver circuit 830 can also sense the current flowing through the power device 840 (or the voltage drop across it) or the current flowing through the driver circuit 830. This can be used to adjust the output signals VG and VP. Current sensing can also be used to detect fault conditions. For example, if the current flowing through the power device 840 or the driver circuit 830 exceeds a fault indication threshold, the driver circuit 830 adjusts the VG and VP output signals to turn off the power device 840.

[0109] The driver circuit 830 generates independently controllable output signals VG and VP. Output signal VP has a higher drive current capability than output signal VG. Output signals VG and VP can be used to drive the gate region 60 and body electrode 41 of any power device, including but not limited to LDMOS devices 120 and 122, VMOS device 220, UMOS device 320, VDMOS device 420, superjunction device 520, and IGBT 620. In another alternative embodiment of the present invention, the VG signal can be used to drive the gate region 60 of power devices without a body electrode 41, such as LDMOS devices 100 and 102, VMOS device 200, UMOS device 300, VDMOS device 400, superjunction device 500, and IGBT 600, while the VP signal can be used to drive the base terminal of a bipolar device, such as those described in "Modern Semiconductor Devices for Integrated Circuits" by C. Hu, which is incorporated herein by reference in its entirety.

[0110] The signal polarity of the output signals VG and VP can be positive or negative. As described above, applying a positive VG and / or VP bias can improve the conductivity of the power device 840. Similarly, applying a negative VG and / or VP bias can improve the breakdown voltage and turn-off time of the power device 840. The waveforms of the VG and VP signals can be controlled to optimize the switching time and switching energy of the power device 840.

[0111] Figures 14A and 14B show exemplary VG and VP waveforms that may be applied to turn on the power device 840. The VG and VP signals can turn on the power device 840 by starting from zero or a negative voltage and rising to a positive voltage. The driver circuit 830 can adjust the delay time tdelay between the rising edges of the VG and VP signals. Although the delay time tdelay is illustrated as positive, tdelay may also be negative, meaning the VP signal may rise earlier than the VG signal. Furthermore, the slew rates of the VG and VP signals can be controlled independently, as shown in Figure 14A as ramp rate 1 and ramp rate 2, respectively.

[0112] In one exemplary embodiment, the VG voltage rises from -5 volts to 10 volts, and the VP voltage rises from -5 volts to 0.7 volts. In another exemplary embodiment, the VG voltage rises from 0 volts to 10 volts, and the VP voltage rises from 0 volts to 0.7 volts. Different output voltages VG and VP may be generated by the control circuit 830, and the exemplary voltages described are not limiting.

[0113] Figure 14B shows another example of the VG and VP waveforms, where the VP signal can first stabilize at the first level VP1 before rising to the second level VP2. The slew rates, ramp rates 3 and 4, and the hold time thold determine the delay time tdelay between the stabilization points of the VG and VP signals, and these can be controlled independently.

[0114] In one exemplary embodiment, the VP voltage rises from -5 volts to a first level VP1 of 0 volts, and then rises to a second level of 0.7 volts.

[0115] Figures 15A and 15B show exemplary VG and VP waveforms that may be applied to turn off the power device 840. The VG and VP signals start as a positive voltage and end as zero or a negative voltage. The driver circuit 830 can adjust the delay time tdelay between the falling edges of the VG and VP signals. Although the delay time tdelay is illustrated as positive, tdelay may also be negative, i.e., the VG signal may fall earlier than the VP signal. Furthermore, the slew rates of the VG and VP signals can be controlled independently, shown as slew rate 1 and slew rate 2 in Figure 15A, respectively.

[0116] In one exemplary embodiment, the VG voltage drops from 10 volts to -5 volts, and the VP voltage drops from 0.7 volts to -5 volts. In another exemplary embodiment, the VG voltage drops from 10 volts to 0 volts, and the VP voltage drops from 0.7 volts to 0 volts. Different output voltages VG and VP may be generated by the control circuit 830, and the exemplary voltages described are not limiting.

[0117] Figure 15B shows another example of the VG and VP waveforms, where the VP signal can first stabilize at a first level VP1 and then drop to a second level VP2. The slew rates 3 and 4 and the hold time thold determine the delay time tdelay between the stabilization points of the VG and VP signals, and these can be controlled independently.

[0118] In one exemplary embodiment, the VP voltage first drops to a first level VP1 of 0 volts, and then stabilizes at a second level of -5 volts.

[0119] Power devices 100, 102, 200, 300, 400, and 500 include an intrinsic diode. For example, in LDMOS 100, the diode is formed by a body region 22 and a source region 16, and the body region 22 and a drain region (including a low-concentration doped region 24 and a drain region 18). Similarly, in VMOS 200, UMOS 300, VDMOS 400, and power device 500, the diode is formed by a base region 20 and a source region 16, and the base region 20 and a drift region 18A (and substrate region 18). Since the source electrode 40 electrically short-circuits the body region 22 or base region 20 with the source region 16, the LDMOS 100, VMOS 200, UMOS 300, VDMOS 400, and power devices 500 are often schematically represented as MOSFET devices 900 in parallel with a diode 920, which is connected between the source electrode 40 and the drain electrode 42 (see Figure 16A). These diodes 920 can be used as conduction paths when devices 100, 200, 300, 400, and 500 are off (for example, when a near-zero voltage is applied to the gate 60).

[0120] In LDMOS120, 122, VMOS220, UMOS320, VDMOS420, and power device 520, a bias can be applied to the body region 22 or the base region 20 by the body electrode 41. As a result, the current flowing through devices 120, 122, 220, 320, 420, and 520 can be modulated by the bias applied to the body electrode 41. For example, a larger current can be obtained by applying a positive bias to the body electrode 41. Similarly, a smaller current can be obtained by applying a negative bias to the body electrode. Therefore, devices 120, 122, 220, 320, 420, and 520 can also be schematically represented as MOSFET device 900 and bipolar transistor 930, as shown in Figure 16B.

[0121] Inter-device variability can also be reduced by applying a bias to the body electrode 41. Figure 17A shows an exemplary distribution of on-resistances of device parameters, e.g., power devices 100, 102, 200, 300, 400, 500, or 600. By applying a bias to the body electrode, the uniformity of on-resistances of power devices 120, 122, 220, 320, 420, 520, or 620 can be improved. For example, to reduce on-resistance, a positive bias can be applied to the body electrode 41 of a power device with a high initial on-resistance. As a result, higher inter-device uniformity can be achieved, for example, as shown in Figure 17B.

[0122] The characteristics of power devices may shift over time due to operation or aging. The device parameters can be adjusted and returned to the desired state by applying a bias to the body electrode 41.

[0123] From the foregoing, it is clear that a power device having low on-resistance and high voltage resistance is disclosed. The above description of the present invention enables those skilled in the art to implement and use embodiments that are considered to be the best currently available, but those skilled in the art will understand and recognize the existence of specific embodiments, methods, and examples, variations, combinations, and equivalents. Accordingly, the present invention should be limited not by the embodiments, methods, and examples described above, but by all embodiments and methods that fall within the spirit and scope of the invention as described in the claims.

Claims

1. It is a semiconductor power device, drain region and, A first region that is in contact with the drain region, has the same conductivity as the drain region, and is doped at a lower concentration than the doping of the drain region, Source area and, The first region and the second region which is in contact with the source region, Gate region and A gate insulating layer, at least a portion of which is positioned between the gate region and the second region, A body electrode configured to supply bias to the second region, A source electrode configured to supply bias to the source region A semiconductor power device comprising the above, wherein the second region and the source region can be independently controlled.

2. A semiconductor power device according to claim 1, wherein, in the conduction mode, when a positive voltage is applied to the second region and a substantially zero voltage is applied to the source region, a larger current flows from the drain region to the source region compared to a configuration in which the second region is short-circuited to the source region.

3. A semiconductor power device according to claim 1 or 2, wherein in conduction mode, a positive voltage is applied to the gate region, a positive voltage is applied to the drain region, a substantially zero voltage is applied to the source region, and a positive voltage is applied to the second region.

4. A semiconductor power device according to claim 1, wherein an intrinsic lateral bipolar transistor is turned on by applying a positive bias to the second region, the source region functions as the emitter region of the lateral bipolar transistor, the second region functions as the base region of the lateral bipolar transistor, and the first region and the drain region function as the collector region of the lateral bipolar transistor.

5. A semiconductor power device according to claim 1, wherein when the device is turned off, a negative bias is applied to the second region, increasing the energy barrier between the drain region and the source region, thereby suppressing punch-through and improving the breakdown voltage of the device compared to when the second region is grounded.

6. A semiconductor power device according to any one of claims 1, 2, 4, and 5, wherein the device includes an LDMOS device.

7. In the semiconductor power device according to claim 6, the second region includes a body region, and the device is circuit board and Between the substrate and the second region, the third region is in contact with the substrate and the second region. A semiconductor power device that further incorporates these features.

8. The semiconductor power device according to claim 7 further comprises a body contact region that electrically contacts the body electrode and the body region, A semiconductor power device in which the body contact region is doped to a higher concentration than the doping of the body region.

9. A semiconductor power device according to claim 8, wherein the body contact region extends into the device to a depth greater than the depth of the body region.

10. A semiconductor power device according to any one of claims 1, 2, 4, and 5, wherein the device includes a VMOS device.

11. In the semiconductor power device according to claim 10, The drain region includes the substrate, The first region includes a drift region, A semiconductor power device in which the gate region and the gate insulating layer are formed within a V-shaped groove that cuts through the source region and the second region and reaches the drift region.

12. A semiconductor power device according to any one of claims 1, 2, 4, and 5, wherein the device includes a UMOS device.

13. In the semiconductor power device according to claim 12, The drain region includes the substrate, The first region includes a drift region, A semiconductor power device in which the gate region and the gate insulating layer are formed within a U-shaped trench.

14. A semiconductor power device according to any one of claims 1, 2, 4, and 5, wherein the device includes a DVMOS device.

15. In the semiconductor power device according to claim 14, The drain region includes the substrate, The first region includes a drift region, A semiconductor power device in which current flows from the drain region to the source region when conducting.

16. A semiconductor power device according to any one of claims 1, 2, 4, and 5, wherein the device includes a superjunction vertical channel semiconductor power device.

17. In the semiconductor power device according to claim 16, The drain region includes the substrate, The first region includes a drift region having the same conductivity type as the substrate and being doped to a lower concentration than the substrate. The semiconductor power device further includes a longitudinal region in contact with the second region and the drift region, wherein the longitudinal region has a conductivity type different from that of the drift region.

18. An insulated-gate bipolar transistor (IGBT) semiconductor power device, A substrate having a first conductivity type, A drift region that contacts the substrate and has a second conductivity type different from the first conductivity type, A base region having the first conductivity type and in contact with the drift region, An emitter region having the second conductivity type and in contact with the base region, A gate insulating layer and a gate region are located above the drift region and overlap a part of the base region, A body electrode electrically connected to the base region, The emitter electrode electrically connected to the emitter region and An insulated-gate bipolar transistor (IGBT) semiconductor power device comprising the above, wherein the base region and the emitter region can be independently controlled.

19. The IGBT semiconductor power device according to claim 18 further comprises a collector electrode electrically connected to the substrate, An IGBT semiconductor power device is a vertical channel device in which current flows from the collector electrode to the emitter electrode when it is conducting. An IGBT semiconductor power device, wherein the power device is turned on by applying a positive voltage to the gate region, causing the base region beneath the gate insulating layer to invert and form a channel region connecting the emitter region and the drift region.

20. An IGBT semiconductor power device according to claim 18, wherein when the power device is in conduction mode, a substantially zero voltage is applied to the emitter region and a positive voltage is applied to the base region, so that a larger current flows from the substrate to the emitter region compared to when the base region is grounded.

21. An IGBT semiconductor power device according to any one of claims 18 to 20, wherein when the IGBT semiconductor power device is turned off, a negative bias is applied to the body electrode, thereby increasing the energy barrier between the drift region and the emitter region, suppressing punch-through compared to when the base region is grounded, and improving the breakdown voltage of the IGBT semiconductor power device.

22. An IGBT semiconductor power device according to any one of claims 18 to 20, wherein by applying a negative bias to the base region, the potential of the base region can be limited to a level lower than the latch-up condition of the thyristor element formed by the substrate, the drift region, the base region, and the emitter region, thereby improving the latch-up resistance of the IGBT semiconductor power device.

23. A method for operating a semiconductor power device comprising: a drain region; a first region in contact with the drain region and having the same conductivity as the drain region, and being doped to a lower concentration than the drain region; a source region; a second region in contact with the first region and the source region; a gate region; a gate insulating layer, at least a portion of which is positioned between the gate region and the second region; a body electrode configured to supply a bias to the second region; and a source electrode configured to supply a bias to the source region; The steps include applying a first bias from the body electrode to the second region, The steps include applying a second bias from the source electrode to the source region, and A method comprising the first bias and the second bias being controlled independently.

24. In the method according to claim 23, in conduction mode, a positive voltage is applied to the gate region, a positive voltage is applied to the drain region, the second bias is a substantially zero voltage applied to the source region, and the first bias is a positive voltage applied to a body contact region electrically connected to the second region. A method wherein a larger current flows from the drain region to the source region compared to when the body contact region is grounded.

25. The method according to claim 24, wherein the positive bias applied to the second region via the body contact region also turns on an intrinsic lateral bipolar transistor, the source region functions as an emitter region, the second region functions as a base region, and the first region and the drain region function as collector regions of a bipolar transistor.

26. A method for operating a semiconductor power device comprising: a drain region; a first region in contact with the drain region and having the same conductivity as the drain region, and being doped to a lower concentration than the drain region; a source region; a second region in contact with the first region and the source region; a gate region; a gate insulating layer, at least a portion of which is positioned between the gate region and the second region; a body electrode configured to supply a bias to the second region; and a source electrode configured to supply a bias to the source region; The step of applying a negative bias to the second region when the semiconductor power device is turned off, thereby increasing the energy barrier between the drain region and the source region, suppressing punch-through and improving the device's breakdown voltage compared to when the second region is grounded when the semiconductor power device is turned off. Methods that include...

27. The method according to claim 26, wherein when the semiconductor power device is off, that is, when the gate region is turned off by applying a bias of about 0V, the leakage current between the drain region and the source region is also reduced by the step of applying a negative bias to the second region.

28. A method according to claim 26, wherein the step of applying a negative bias to the second region removes charge in the second region, thereby improving the turn-off time of the semiconductor power device.

29. A method according to claim 26, further comprising the step of applying a negative bias to the gate region along with the step of applying a negative bias to the second region.

30. The method according to claim 26, wherein the bias is a voltage bias.

31. A method according to claim 26, wherein the bias is a current bias.

32. A method for operating an insulated-gate bipolar transistor (IGBT) semiconductor power, comprising: a substrate having a first conductivity type; a drift region in contact with the substrate and having a second conductivity type different from the first conductivity type; a base region having the first conductivity type and in contact with the drift region; an emitter region in contact with the base region and having the second conductivity type; a gate insulating layer and gate region positioned above the drift region and overlapping a part of the base region; a body electrode electrically connected to the base region; and an emitter electrode electrically connected to the emitter region, wherein The steps include applying a first bias from the body electrode to the base region, The steps include applying a second bias from the emitter electrode to the emitter region, and A method comprising the first bias and the second bias being controlled independently.

33. The method according to claim 32, wherein the IGBT semiconductor power device further includes a collector electrode electrically connected to the substrate, the IGBT semiconductor power device is a vertical channel device, and in a conductive state, current flows from the collector electrode to the emitter electrode, and the method is The step of turning on the power device by applying a positive voltage to the gate region, thereby inverting the base region beneath the gate insulating layer to form a channel region connecting the emitter region and the drift region. Methods that further include this.

34. A method according to claim 32 or 33, further comprising the step of applying a substantially zero voltage to the emitter region and a positive voltage to the base region when the power device is in conduction mode, thereby causing a larger current to flow from the substrate to the emitter region than when the base region is grounded.

35. A method according to claim 32 or 33, further comprising the step of turning off the IGBT semiconductor power device, the step of applying a negative bias to the body electrode, thereby increasing the energy barrier between the drain region and the emitter region, thereby suppressing punch-through and improving the breakdown voltage of the IGBT semiconductor power device compared to when the base region is grounded.

36. A method according to claim 35, wherein by applying a negative bias to the base region, the potential of the base region can be limited to a level lower than the latch-up condition of the thyristor element formed by the substrate, the drift region, the base region, and the emitter region, thereby improving the latch-up resistance of the IGBT semiconductor power device.

37. The method according to claim 32, wherein the first bias and the second bias are voltage biases.

38. The method according to claim 32, wherein the first bias and the second bias are current biases.

39. A driver circuit for generating signals to operate at least one semiconductor power device, wherein the driver circuit generates two signals for each of the at least one semiconductor power device.

40. The driver circuit according to claim 39, wherein the semiconductor power device includes a gate electrode and a body electrode.

41. The driver circuit according to claim 40, wherein the two signals include a signal for controlling the gate electrode of the semiconductor power device and a signal for controlling the body electrode of the semiconductor power device.

42. A driver circuit according to claim 41, wherein the signals to the gate electrode and the body electrode can be controlled independently.

43. A driver circuit according to any one of claims 39 to 42, wherein one of the signals has a higher driver current capability than the other of the signals.

44. A driver circuit according to any one of claims 39 to 42, wherein the polarity of the signal may be positive or negative.

45. It is a power system, Driver circuit and At least one semiconductor power device and A power system comprising the driver circuit which generates two signals for each of the at least one semiconductor power devices.

46. A power system according to claim 45, wherein each semiconductor power device includes the gate electrode and the body electrode.

47. The power system according to claim 46, wherein the two signals include a signal for controlling the gate electrode and a signal for controlling the body electrode.

48. A power system according to claim 47, wherein the signals to the gate electrode and the body electrode can be controlled independently.

49. A power system according to any one of claims 45 to 48, wherein one of the signals has a higher driver current capability than the other of the signals.

50. A power system according to any one of claims 45 to 48, wherein the polarity of the signal may be positive or negative.

51. A method for reducing variability in a semiconductor power device, comprising the step of applying a bias to the body electrodes of the semiconductor power device.

52. A method for adjusting the characteristics of a semiconductor power device, comprising the step of applying a bias to the body electrodes of the semiconductor power device.

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