Sizing of nanosheets for power delivery

Abstract

Various structures for implementing nanosheet transistors are disclosed. These structures include nanosheet transistors with different widths inside a transistor device. Changing the width of nanosheet transistors within a transistor device allows for different designs of the input and output stages of the transistor device, which can improve the power utilization and performance of the transistor device. In some examples, the input stage has nanosheet transistors with narrower nanosheet fins than the nanosheet transistors in the output stage. Changing the nanosheet transistor width may be achieved within the input or output stage by merging nanosheet fins.

Description

Technical Field

[0001] Embodiments described in the present specification relate to transistor structures of semiconductor devices. More specifically, the embodiments described in the present specification relate to structures for nanosheet transistors in integrated circuit devices.

Background Art

[0002] Nanosheet (e.g., gate-all-around) transistors are increasingly being utilized in integrated circuits. Nanosheet transistors can have more effective characteristics for turning transistors on / off relative to planar FETs or FinFETs due to increased gate control of the channel provided by the geometry of the nanosheet transistor design. The increased effectiveness in turning transistors on or off can provide reduced leakage and better power utilization (e.g., reduced voltage) for integrated circuits that utilize nanosheet transistors. Nanosheet transistors can have more complex designs than planar FETs or FinFETs. As integrated circuit designs evolve, more approaches for utilizing the more complex designs of nanosheet transistors may be contemplated.

[0003] The features and advantages of the methods and apparatuses of the embodiments described in the present disclosure will be more fully understood with reference to the following detailed description of the presently preferred, yet nonetheless exemplary, embodiments according to the embodiments described in the present disclosure, taken in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0004] [Figure 1] FIG. 3 illustrates a perspective view of a nanosheet transistor, in accordance with some embodiments.

[0005] [Figure 2] FIG. 4 illustrates an end view of a channel region, in accordance with some embodiments.

[0006] [Figure 3]A top view of a standard cell layout having nanosheet transistors, according to several embodiments, is shown.

[0007] [Figure 4] The diagram shows a top view of the layout of a transistor device having nanosheet transistors according to several embodiments.

[0008] [Figure 5] The diagram shows a top view of a transistor device layout comprising a nanosheet transistor having nanosheet fins merged in the output stage, according to several embodiments.

[0009] [Figure 6] The diagram shows a top view of a transistor device layout comprising a nanosheet transistor having merged nanosheet fins in both the input and output stages, according to several embodiments.

[0010] [Figure 7] This is a block diagram of one embodiment of an exemplary system.

[0011] The embodiments disclosed herein are open to various modifications and alternative forms, but specific embodiments are shown in the drawings and described in detail herein for illustrative purposes. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed in the claims. On the contrary, this application is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the disclosure of this application, as set forth in the appended claims. [Modes for carrying out the invention]

[0012] As used herein, the term “standard cell” refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions that are standard for various implementation forms. For example, an individual standard cell may be one cell in a library of multiple cells from which various suitable cells may be selected to implement a particular cell design. As a further example, a standard cell may also be a created (e.g., designed) cell design, which is then performed multiple times to produce an integrated circuit device, for example, through a synthesis or automated flow. Integrated circuit cells may also include custom circuit design cells that are individually designed for a particular implementation form. Embodiments of circuit design cells described herein may be implemented in various implementation forms of logic integrated circuits or memory integrated circuits.

[0013] Figure 1 shows perspective views of nanosheet transistors according to several embodiments. In the illustrated embodiments, the nanosheet transistor 100 is formed on a substrate 150. In certain embodiments, the transistor 100 includes a gate 110 and a channel region 120. The gate 110 may be a polysilicon gate or a metallic gate. The channel region 120 includes nanosheet fins 130 and a substrate channel 140. The nanosheet fins 130 are fins made of silicon, another semiconductor, or a combination of semiconductors that pass through the structure (e.g., material) of the gate 110. In various embodiments, the nanosheet fins 130 are relatively thin (in vertical dimensions) rectangular sheets of semiconductor material aligned parallel to the substrate 150 (e.g., the horizontal plane of the nanosheet fins 130 is parallel to the horizontal plane of the substrate 150). The transistor 100 typically includes multiple nanosheet fins 130 passing through the gate 110. For example, as shown in Figure 1, the transistor 100 includes three nanosheet fins 130 passing through the gate 110.

[0014] In various embodiments, the substrate channel 140 is formed within the substrate 150 beneath the nanosheet fin 130. The substrate channel 140 may be formed by forming shallow trench isolation (STI) 145 on both sides of the substrate channel within the substrate 150. Thus, the substrate channel 140 is part of the substrate 150 between the STI 145. In certain embodiments, the substrate channel 140 is aligned with the nanosheet fin 130 and has similar horizontal dimensions (e.g., length or width) to the nanosheet fin 130. In some embodiments, the substrate channel 140 is made of the same semiconductor material as the nanosheet fin 130. For example, both the nanosheet fin 130 and the substrate channel 140 may be silicon.

[0015] Figure 2 shows an end view of the channel region 120 according to several embodiments. In the illustrated embodiments, the channel region 120 includes a nanosheet fin 130 inside the gate 110 above the substrate channel 140. In certain embodiments, the gate 110 substantially surrounds the nanosheet fin 130 (e.g., "all around"). Note that at least some gate dielectric material (not shown) may be present between the nanosheet fin 130 and the gate 110. Surrounding the nanosheet fin 130 with the gate 110 provides better control over the gate's operation, reduces current leakage from the gate, and results in more effective properties for turning the gate on and off.

[0016] Figure 3 shows a top view of a standard cell layout having a nanosheet transistor according to several embodiments. In the illustrated embodiments, the standard cell 300 includes active gate structures 310A-C and dummy (e.g., inactive) gate structures 320A-B. In various embodiments, the active gate structures 310A-C and the dummy gate structures 320A-B are formed from the same material and are structurally similar. In such embodiments, the determination of whether a gate structure is "active" or "dummy" may be made by whether or not a connection to the gate is made in the layout and design of the cell 300.

[0017] In some embodiments, the dummy gate structures 320A-B are implemented to delineate (e.g., separate) the structure within the cell or the cell layout from other structures. For example, as shown in Figure 3, the dummy gate structure 320A is located at the left end of cell 300 in the gate pitch direction 302 (e.g., the horizontal direction of the cell), and the dummy gate structure 320B is located at the right end of cell 300. Thus, the dummy gate structures 320A-B separate the active gate structures 310A-C from the left and right cells or other structures of cell 300 in the gate pitch direction 302.

[0018] In various embodiments, the active gate structures 310A-C and dummy gate structures 320A-B are fingers or lines of gate material that extend (e.g., persist) across the cell 300 in the cell height direction 304 (e.g., vertically to the cell). Examples of gate materials include, but are not limited to, polysilicon or metal. In some embodiments, the gate material of the gate structures 310A-C may extend beyond the boundaries of the cell 300. For example, the gate structures 310A-C may include gate material that extends into adjacent cells above or below the cell 300 in the cell height direction 304.

[0019] In various embodiments, cell 300 includes channel regions 330A-B. In certain embodiments, channel regions 330A-B include nanosheet fins 340A-B. Nanosheet fins 340A-B may include multiple stacked nanosheet fins, such as nanosheet fin 130 shown in Figures 1 and 2. Therefore, in the top view of Figure 3, only the upper nanosheet fins are shown as nanosheet fins 340A and nanosheet 340B. In various embodiments, as shown in Figure 3, nanosheet fins 340A-B extend across the width of cell 300 in the gate pitch direction 302. For example, nanosheet fins 340A-B extend between dummy gate structures 320A and 320B.

[0020] In certain embodiments, the active gates 350 (dotted boxes) are formed in the region where nanosheet fins 340A-B (oriented in the gate pitch direction 302) intersect with the active gate structures 310A-C (oriented in the cell height direction 304). For example, in the exemplary embodiment of Figure 3, the active gates 350A-C are formed in the region where nanosheet fin 340A intersects with the active gate structures 310A-C, and the active gates 350D-F are formed in the region where nanosheet fin 340B intersects with the active gate structures 310A-C. Thus, the cell 300 contains six active gates (gates 350A-F) within the boundaries of a standard cell. The active gates 350A-F may have a structure similar to that of gate 110 shown in Figures 1 and 2.

[0021] In the current implementation of standard cells such as cell 300, the nanosheet fins 340A and 340B have the same horizontal width (e.g., a fixed width determined by the cell design and dimensions). For example, the width 342A of nanosheet fin 340A is approximately the same as the width 342B of nanosheet fin 340B. Note that widths 342A and 342B, although shown vertically in the diagram in Figure 3, are the horizontal widths of the nanosheet fins (e.g., the horizontal widths of nanosheet fin 130 shown in Figures 1 and 2). In various embodiments, the transistor device based on cell 300 may have an input stage and an output stage. For example, as shown in Figure 3, cell 300 may include an input stage 360 ​​and an output stage 370 (dashed box).

[0022] In cell 300, since nanosheet fins 340A to 340B have the same width, gates 350A to 350F all have substantially the same operating characteristics (e.g., drive current capacity, capacitance, and power), so the different operating characteristics desired for input stage 360 and output stage 370 can be implemented by selecting the number of gates used in the input stage relative to the output stage. For example, in the illustrated embodiment of cell 300, input stage 360 includes two active gates (active gate 350A and active gate 350D), and output stage 370 includes four active gates (active gate 350B, active gate 350C, active gate 350E, and active gate 350F). Output stage 370 has more active gates to enable a larger drive output, and input stage 360 has fewer active gates to have a lower capacitance at the input. Since the widths of nanosheet fins 340 within cell 300 are substantially the same, the flexibility in designing the input stage and output stage of the transistor devices of cell 300 may be limited. For example, modifications to the stage design can generally only be implemented by changing the selection of the number of active gates in each stage.

[0023] The present disclosure recognizes that additional flexibility in the design of transistor devices can be enabled by providing variations in the widths of nanosheet fins across transistors within a transistor device, to provide greater flexibility in the design of the input and output stages of the transistor device. The increased flexibility may provide improved power utilization and improved performance over transistor devices having nanosheet transistors that have the same width across the transistors. For example, flexibility in input / output stage design may allow the transistor device to have a lower capacitance (as viewed from other devices) at the input stage, while having greater current drive capability from the output stage to other devices.

[0024] Certain embodiments disclosed in the present specification have four broad elements, namely: 1) a plurality of gate structures oriented along a first direction, 2) a plurality of elongated channel regions oriented along a second direction, the elongated channel regions including two or more stacked nanosheet fins, 3) an input stage including the elongated channel regions having the nanosheet fins with a first width along the first direction, and 4) an output stage including the elongated channel regions having the nanosheet fins with a second width along the first direction that is greater than the first width. In certain embodiments, the elongated channel regions pass through the gate structures, and an active gate is located at the intersection of the nanosheet fins and the gate structures. In some embodiments, the input stage and the output stage are in separate cells separated in the cell height direction, and the gate structures extend across both stages.

[0025] Various illustrations of embodiments having these broad elements are described herein in the present disclosure. It should be noted that the illustrated embodiments of the present disclosure show design templates for cells having various nanosheet transistors that may be implemented in the input stage and the output stage of a transistor device. These design templates provide basic building blocks from which many different types of devices can be constructed based on the connection schemes to the transistors within the design templates. For example, simple devices (inverters, NAND devices, multiplexers (MUX), etc.), as well as more complex devices (e.g., complex FETs) may be constructed based on the basic building blocks of the present disclosure.

[0026] Figure 4 shows a top view of the layout of a transistor device having nanosheet transistors according to several embodiments. In the illustrated embodiments, the transistor device 400 is a device having a cell width in the gate pitch direction 402 which is the standard cell width, and a cell height in the cell height direction 404 which is twice the standard cell height (e.g., 2 × standard cell height 406A~B). In some embodiments, the standard cell height is the cell height that accommodates two rows of channel regions and nanosheet transistor fins (e.g., two channel regions 430 having nanosheet fins 440).

[0027] In certain embodiments, device 400 includes active gate structures 410A-B and dummy (e.g., inactive) gate structures 420A-B. The dummy gate structures 420A-B define the ends of device 400 in the gate pitch direction 402, separating device 400 from other devices in the gate pitch direction, with dummy gate structure 420A defining the left end and dummy gate structure 420B defining the right end. In various embodiments, the active gate structures 410A-B and dummy gate structures 420A-B are fingers or lines of gate material that extend (e.g., protrude) across device 400 in the cell height direction 404 (e.g., vertically to the device in the figure). The gate material may be, for example, polysilicon or metal. In some embodiments, the gate material of gate structures 410A-B or dummy gate structures 420A-B may extend beyond the boundaries of device 400.

[0028] In certain embodiments, the device 400 is separated into an input stage 460 at the top of the device (defined by a standard cell height 406A) and an output stage 470 at the bottom of the device (defined by a standard cell height 406B). Various routings in the upper layers of the structure shown in Figure 4 may be implemented to define the connection between the input stage 460 and the output stage 470.

[0029] In certain embodiments, the input stage 460 includes channel regions 430A-B, and the output stage 470 includes channel regions 430C-D. In various embodiments, the channel regions 430A-B include nanosheet fins 440A-B, and the channel regions 430C-D include nanosheet fins 440C-D. Each of the nanosheet fins 440A-D may include a stacked nanosheet fin such as the nanosheet fin 130 shown in Figures 1 and 2. The nanosheet fins 440A-D extend across the width of the device 400 in the gate pitch direction 402. For example, the nanosheet fins 440A-D may extend between dummy gate structures 420A and 420B.

[0030] In various embodiments, the input stage 460 includes active gates 450A to D. Active gates 450A to D (dotted boxes) may be formed in regions where nanosheet fins 440A to B (oriented in the gate pitch direction 402) intersect with active gate structures 410A to B (oriented in the cell height direction 404). For example, active gates 450A to B are formed in regions where nanosheet fin 440A intersects with active gate structures 410A to B, and active gates 450C to D are formed in regions where nanosheet fin 440B intersects with active gate structures 410A to B.

[0031] In various embodiments, the output stage 470 includes active gates 450E-H. Active gates 450E-H (dotted boxes) may be formed in regions where nanosheet fins 440C-D (oriented in the gate pitch direction 402) intersect with active gate structures 410A-B (oriented in the cell height direction 404). For example, active gates 450E-F are formed in regions where nanosheet fins 440C intersect with active gate structures 410A-B, and active gates 450G-H are formed in regions where nanosheet fins 440D intersect with active gate structures 410A-B. Thus, both the input stage 460 and the output stage 470 may include the same number of active gates (e.g., four each within device 400).

[0032] In the illustrated embodiment of Figure 4, nanosheet fins 440A-B in the input stage 460 have a width 442A, and nanosheet fins 440C-D in the output stage 470 have a width 442B. In certain embodiments, width 442A is different from width 442B. For example, width 442A may be smaller than width 442B, and nanosheet fins 440A-B are heterogeneous with respect to nanosheet fins 440C-D. Changing the width of the nanosheet fins 440 between the input stage 460 and the output stage 470 may be done to provide varying properties of the active gates 450 associated with the nanosheet fins. For example, in device 400, the input stage 460 includes active gates 450A-D having nanosheet fins 440A-B having a smaller width (width 442A) than the active gates 450E-H having nanosheet fins 440C-D in the output stage 470. Smaller nanosheet fins can be implemented in the input stage 460 to reduce the capacitance that may be experienced by other devices around device 400. Furthermore, larger nanosheet fins implemented in the output stage 470 increase the drive current capacity of device 400 so that as much drive power as possible is provided to other devices outside of device 400. By reducing the capacitance of device 400 as seen by other devices, while providing as much drive power as possible, the performance and power utilization of device 400 (together with other devices associated with device 400) are improved.

[0033] An example of a transistor device that can benefit from reducing capacitance in the input stage and increasing the drive output to other devices is a clock implemented in a flop circuit. Having a clock with reduced capacitance in the input stage reduces the capacitance impact on other devices connected to the clock, while providing a high signal output from the clock that can be easily received by those other devices. Such a clock device can also be implemented in a smaller area within a flop circuit, reducing the area penalty of the clock within the flop circuit.

[0034] Additional embodiments of the device may be conceived, in which the width of the device is increased and the input and output stages are arranged side by side within the device (for example, side by side in the gate pitch direction). By arranging the input and output stages side by side in the gate pitch direction, the design of the channel region and the gates formed by the channel region can be further modified. For example, the width of the channel region may be changed between the gates of the input or output stage, or the channel region may be merged to form a wider channel region. Various exemplary embodiments are described with the understanding that the elements in each example may be applicable to other embodiments, including those explicitly shown herein.

[0035] Figure 5 shows a top view of a transistor device layout comprising a nanosheet transistor having merged nanosheet fins in the output stage, according to several embodiments. In the illustrated embodiments, the transistor device 500 is a device having a cell width in the gate pitch direction 502 that is wider than the cell width in Figures 3 and 4. The device 500 has a cell height in the cell height direction 504 that is twice the standard cell height (e.g., 2 × standard cell heights 506A-B) and is similar in height to the device 400 shown in Figure 4.

[0036] In certain embodiments, the device 500 includes active gate structures 510A-C and dummy (e.g., inactive) gate structures 520A-C. In various embodiments, the active gate structures 510A-C and dummy gate structures 520A-C are fingers or lines of gate material that extend (e.g., protrude) across the device 500 in the cell height direction 504 (e.g., the vertical direction of the device in the figure). The gate material may be, for example, polysilicon or metal. In some embodiments, the gate material of the gate structures 510A-C or dummy gate structures 520A-C may extend beyond the boundary of the device 500.

[0037] In various embodiments, dummy gate structures 520A-B define the ends of device 500 in the gate pitch direction 502, separating device 500 from other devices in the gate pitch direction, with dummy gate structure 520A defining the left end and dummy gate structure 520B defining the right end. In a particular embodiment, dummy gate structure 520C separates device 500 into an input stage 560 and an output stage 570. For example, device 500 is separated by dummy gate structure 520C into an input stage 560 on the left side of the device (gate pitch direction 502) and an output stage 570 on the right side of the device. Various routings in the upper layers of the structure shown in Figure 5 can be implemented to define the connection between the input stage 560 and the output stage 570.

[0038] In certain embodiments, the input stage 560 includes channel regions 530A-D, and the output stage 570 includes channel regions 530E-G. Channel regions 530A-G may include corresponding nanosheet fins 540A-G. Each of the nanosheet fins 540A-G may include a laminated nanosheet fin such as the nanosheet fin 130 shown in Figures 1 and 2. In various embodiments, the nanosheet fins 540A-D extend across the width of the input stage 560 in the gate pitch direction 502. For example, the nanosheet fins 540A-D may extend between dummy gate structures 520A and 520C. The nanosheet fins 540E-G extend across the width of the output stage 570 in the gate pitch direction 502 between dummy gate structures 520C and 520B.

[0039] In various embodiments, the input stage 560 includes active gates 550A to H. Active gates 550A to D (dotted boxes) may be formed in the region where nanosheet fins 540A to B (oriented in the gate pitch direction 502) intersect with active gate structures 510A to B (oriented in the cell height direction 504). Furthermore, active gates 550E to H (dotted boxes) may be formed in the region where nanosheet fins 540C to D (oriented in the gate pitch direction 502) intersect with active gate structures 510A to B (oriented in the cell height direction 504). For example, active gates 550A to B are formed in the region where nanosheet fins 540A intersect with active gate structures 510A to B, active gates 550C to D are formed in the region where nanosheet fins 540B intersect with active gate structures 510A to B, active gates 550E to F are formed in the region where nanosheet fins 540C intersect with active gate structures 510A to B, and active gates 550G to H are formed in the region where nanosheet fins 540D intersect with active gate structures 510A to B.

[0040] In the illustrated embodiment of Figure 5, nanosheet fins 540A-B in the input stage 560 have a width 542A, and nanosheet fins 540C-D in the input stage have a width 542B. In certain embodiments, width 542A is different from width 542B. For example, width 542A may be smaller than width 542B, and nanosheet fins 540A-B are heterogeneous with respect to nanosheet fins 540C-D. Changing the width of the nanosheet fins 540 in the input stage 560 makes it possible to use connections to gates of different sizes within the input stage. Thus, the input stage 560 increases the flexibility in the design of the device 500 by providing gate characteristics and corresponding gate connectivity that can be implemented in various different types of transistor devices.

[0041] In a particular embodiment, the output stage 570 includes active gates 550I to K formed in a region where nanosheet fins 540E to G (oriented in the gate pitch direction 502) intersect with the active gate structure 510C (oriented in the cell height direction 504) between the dummy gate structure 520C and the dummy gate structure 520B. For example, active gate 550I (dotted box) is formed in a region where nanosheet fins 540E intersect with the active gate structure 510C, active gate 550J (dotted box) is formed in a region where nanosheet fins 540F intersect with the active gate structure 510C, and active gate 550K (dotted box) is formed in a region where nanosheet fins 540G intersect with the active gate structure 510C.

[0042] In various embodiments, the output stage 570 is based on a layout including four nanosheets of similar size (e.g., similar width), two of which are merged to form a single nanosheet. For example, in the embodiment illustrated in Figure 5, nanosheet fins 540E (in channel region 530E) and 540G (in channel region 530G) are individual nanosheet fins, and nanosheet fin 540F (in channel region 530F) is formed by merging two individual nanosheet fins. The merging of nanosheet fins to form nanosheet fin 540F can be carried out by designing the formation of two individual nanosheet fins to be substantially adjacent or have some overlap within the layout.

[0043] Therefore, in the illustrated embodiment of Figure 5, both nanosheet fins 540E and 540G have a width 542C, and nanosheet fin 540F has a width 542D, which is about twice the width 542C. Thus, the nanosheet fin 540F in the output stage 570 is larger than either nanosheet fin 540E or nanosheet fin 540G, and the active gate 550J (corresponding to nanosheet fin 540F) has a higher drive current capacity than either the active gate 550I (corresponding to nanosheet fin 540E) or the active gate 550K (corresponding to nanosheet fin 540G). In a particular embodiment, the width 542D is about twice the width 542C, and therefore the active gate 550J has about twice the drive current capacity of the active gate 550I or the active gate 550K. Although nanosheet fins 540E and 540G are shown in Figure 5 having the same width, several embodiments in which nanosheet fins 540E and 540G have different widths may be considered.

[0044] By changing the width (and drive current capacity) of the active gates 550I~K of the output stage 570, different outputs can be achieved based on providing different connections to the active gates, thus increasing the design flexibility of the device 500. For example, in one intended embodiment, the active gate 550J (having the largest drive current capacity) may be connected to another device that needs to receive a higher drive output from device 500, while the active gates 550I and 550K may be connected to other devices that have less need for drive output from device 500.

[0045] Device 500 also has design advantages over the output stage 570 provided by device 400 shown in Figure 4. For example, the smaller nanosheet fins of the input stage 560 may be used to reduce the capacitance that other devices around device 500 may experience, while the larger nanosheet fins of the output stage 570 may be used to increase the drive current capacity of device 500 and provide as much drive power as possible to other devices outside of device 500.

[0046] Figure 6 shows a top view of a transistor device layout with a nanosheet transistor having merged nanosheet fins in both the input and output stages, according to several embodiments. In the illustrated embodiments, the transistor device 600 is substantially the same as the device 500 shown in Figure 5, except for a change in the input stage. For example, the input stage 560' shown in Figure 6 is substantially the same as the input stage 560 shown in Figure 5, except that the channel region in the vertical central portion of the input stage is merged (together with the nanosheet fins).

[0047] In various embodiments, the input stage 560' includes a merged channel region 630BC having merged nanosheet fins 640BC. Channel region 630BC can be formed, for example, by moving the individual channel regions 530B and individual channel regions 530C, as shown in Figure 5, adjacent to each other (or with some overlap) at or near the boundary between standard cell heights 506A and 506B, thereby merging the individual channel regions to form a single channel region which is channel region 630BC. Nanosheet fins 640BC are formed in correspondence with the merging of the channel region as a merging between individual nanosheet fins 530B and individual nanosheet fins 530C.

[0048] Using the merged channel region 630BC and merged nanosheet fin 640BC formed in the input stage 560', the active gate 650CE (dotted box) and active gate 650DF (dotted box) can be formed as merged active gates in relation to the active gates 550C~F shown in Figure 5. For example, the active gate 650CE may be formed in the region where the merged nanosheet fin 640BC (oriented in the gate pitch direction 502) intersects with the active gate structure 510A (oriented in the cell height direction 504), and the merged active gate 650DF (dotted box) may be formed in the region where the merged nanosheet fin 640BC intersects with the active gate structure 510B (oriented in the cell height direction 504).

[0049] In the illustrated embodiment, the merged nanosheet fin 640BC has a width 642AB. The width 642AB may be, for example, the sum of widths 542A and 542B (shown in both Figures 5 and 6). Thus, the formation of the merged nanosheet fin 640BC results in a third sizing of the nanosheet fin width in the input stage (input stage 560'). For example, the width 642AB is a third available width added to the first available width 542A and the second available width 542B, which are widths of different sizes, as described above.

[0050] The different widths of the nanosheet fins in the input stage 560' provide active gates with different capabilities within the input stage. Furthermore, the merging of the channel region and the nanosheet fins reduces the total number of active gates in the input stage 560' while maintaining the total area of ​​active gates in the input stage (e.g., current driving capability). For example, the input stage 560' shown in Figure 6 has 6 active gates, while the input stage 560 shown in Figure 5 has 8 active gates, but the total active gate area (and therefore current driving capability) is almost the same. Having additional variations in the width of the nanosheet fins in the input stage 560' provides additional flexibility in the design of the device 600 by offering three options for gate characteristics and corresponding gate connectivity that can be implemented in various different types of transistor devices. Exemplary computer system

[0051] Referring next to Figure 7, a block diagram of one embodiment of system 700 is shown, which can incorporate and / or utilize the methods and mechanisms described herein. In the illustrated embodiment, system 700 includes at least one instance of system on chip (SoC) 706, which may include multiple types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other methods, a communication fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors within the SoC 706 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 706 is coupled to external memory 702, peripherals 704, and a power supply 708.

[0052] A power supply 708 is also provided, which supplies a supply voltage to the SoC 706 and one or more supply voltages to the memory 702 and / or peripheral devices 704. In various embodiments, the power supply 708 represents a battery (e.g., a rechargeable battery for a smartphone, laptop or tablet computer, or other device). In some embodiments, two or more instances of the SoC 706 are included (and two or more external memories 702 are also included).

[0053] Memory 702 is any type of memory, including dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3 and / or low-power versions such as LPDDR2), Rambus DRAM (RDRAM), and static RAM (SRAM). One or more memory devices are coupled to a circuit board to form memory modules such as single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). Alternatively, the devices are mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0054] The peripheral device 704 includes any desired circuit configuration depending on the type of system 700. For example, in one embodiment, the peripheral device 704 includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, and global positioning systems. In some embodiments, the peripheral device 704 also includes additional storage, such as RAM storage, solid-state storage, or disk storage. The peripheral device 704 includes user interface devices such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker.

[0055] As illustrated, System 700 is shown to be applicable to a wide area. For example, System 700 may be used as part of a chip, circuit, or component in a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a television 750 (or a set-top box coupled to a television). A smartwatch and a health monitoring device 760 are also illustrated. In some embodiments, the smartwatch may include a variety of general-purpose computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any of the health monitoring-related functions. Other wearable devices, such as devices worn around the neck, implantable devices in the human body, and glasses designed to provide augmented and / or virtual reality experiences, are also intended.

[0056] System 700 may be further used as part of a cloud-based service(s) 770. For example, the aforementioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 700 may be used in one or more devices of a home 780 other than those described above. For example, appliances in a home may monitor and detect conditions of note. For example, various devices in a home (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and alert the homeowner (or repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in the home and automate the adjustment of the heating / cooling system based on the homeowner's response history to various conditions. Figure 7 also shows the application of System 700 to various modes of transport 790. For example, System 700 may be used in control and / or entertainment systems for aircraft, trains, buses, rental cars, private cars, ships ranging from privately owned boats to cruise ships, and scooters (rented or owned). In various cases, System 700 may be used to provide automatic guidance (e.g., autonomous vehicles), general system control, and other methods. Many other embodiments of these are possible and contemplated. Note that the devices and applications shown in Figure 7 are illustrative and not intended to be limiting. Other devices are possible and contemplated. ***

[0057] This disclosure includes references to “one embodiment” or a group of “embodiments” (e.g., “several embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concept. References to “one embodiment,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, and modifications or substitutions within the spirit or scope of this disclosure are intended.

[0058] This disclosure may discuss the potential benefits that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily demonstrate any or all of the potential benefits. Whether a benefit is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the claims may not exhibit some or all of any disclosed benefits. For example, a particular implementation may include other circuits outside the scope of this disclosure that, together with one of the disclosed embodiments, negate or reduce one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation technique or tool) may also negate or reduce the disclosed benefits. Even assuming skilled execution, the realization of benefits may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, the inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on certain occasions, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations on claims that must be satisfied to demonstrate infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvements available to designers who have an interest in this disclosure. The acceptable description of such benefits (e.g., the statement that a particular benefit "may occur") is not intended to convey any doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0059] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single embodiment describes a particular feature, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure. The disclosed embodiments are intended to be illustrative, not limiting, unless there is a statement to the contrary in this disclosure. The foregoing is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that would be obvious to a person skilled in the art who would benefit from this disclosure.

[0060] For example, the features of this application can be combined in any preferred manner. Therefore, new claims can be formulated for any such combination of features during the examination of this application (or an application claiming priority to this application). In particular, referring to the attached claims, features from dependent claims can be combined with features from other dependent claims, including claims dependent on other independent claims, as appropriate. Similarly, features from each independent claim can be combined as appropriate.

[0061] Accordingly, each of the attached dependent claims may be constructed to depend on a single other claim, but additional dependencies are also contemplated. Any combination of features in the dependent claims that are consistent with the present disclosure is contemplated and may be claimed in this application or another application. In summary, the combinations are not limited to those specifically enumerated in the attached claims.

[0062] Where appropriate, claims prepared in one format or legal type (e.g., apparatus) are intended to also support corresponding claims in another format or legal type (e.g., method). ***

[0063] As this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, and the definitions provided through this disclosure, are hereby publicly noted as being used in interpreting the claims made pursuant to this disclosure.

[0064] References to singular items (i.e., nouns or noun phrases preceded by "a," "an," or "the") are intended to mean "one or more" unless explicitly stated in the context. Therefore, references to "items" in the claims do not, without context, preclude additional instances of an item. "Multiple" items refer to a set of two or more items.

[0065] In this specification, the word "may" is used in an allowable sense (i.e., possible, feasible) and not in an obligatory sense (i.e., not required).

[0066] The terms and forms "comprising" and "including" are open-ended and mean "to include, but not to limit."

[0067] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless otherwise explicitly stated in the context. Thus, the enumeration of “x or y” is equivalent to “x or y, or both,” and therefore includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase “either x or y, but not both” clarifies that “or” is used in an exclusive sense.

[0068] The enumerations "w, x, y, z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities, including single elements, up to the total number of elements in the set. For example, in the set [w, x, y, z], these expressions cover any single element in the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0069] In this disclosure, various “labels” may precede nouns or noun phrases. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different examples of the feature. Furthermore, when applied to features, the labels “first,” “second,” and “third” do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0070] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision; that is, the decision may be based on the specified factor alone, or on the specified factor plus other unspecified factors. Consider the phrase "determine A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover even one embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0071] The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not preclude the possibility that additional factors may influence, or otherwise trigger, the effect, either in conjunction with or independently of a specific factor. That is, the effect may depend on these factors alone, or on the specified factor and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase means that B is a factor that triggers the performance of A, or a specific outcome with respect to A. This phrase does not preclude the performance of A from also being in response to other factors, such as C. This phrase also does not preclude the performance of A from being in response to both B and C. This phrase is intended to include embodiments in which A is performed solely in response to B. As used herein, the phrase “in response to” is synonymous with the phrase “in response to at least partially.” Similarly, the phrase “in response to” is synonymous with the phrase “in at least partially.” ***

[0072] Within this disclosure, various entities (which may be referred to as “units,” “circuits,” or other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “configured to perform one or more tasks” is used herein to refer to structures (i.e., physical things). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when the structure is not currently in operation. Thus, entities described or explained as “configured” to perform some task refer to physical things such as devices, circuits, and systems having a processor unit and memory storing program instructions that can be executed to perform the task. This phrase is not used herein to refer to intangible things.

[0073] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. Even if not specifically stated, it is understood that those entities are "configured" to perform those tasks / operations.

[0074] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After proper programming, the FPGA can then be said to be "configured" to perform a particular function.

[0075] For the purposes of a U.S. patent application based on this disclosure, to state in the claims that the structure is “configured” to perform one or more tasks is not intended to expressly invoke Section 112(f) of the U.S. Patent Act with respect to that claim. not present If the applicant wishes to invoke Section 112(f) of the U.S. Patent Application under this Disclosure during the examination process, it would use “means for” to perform the function to describe the elements of the claim.

[0076] This disclosure may describe various “circuits.” These circuits or “circuit configurations” constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), and programmable logic arrays. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuit configurations may include digital components, analog components, or a combination of both, as needed. Certain types of circuits may generally be referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), function units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit configurations.

[0077] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoder unit” may be described as performing the function of “processing the opcode of an instruction and routing the instruction to one or more of several functional units,” meaning that the decoder unit is “configured” to perform this function. The detail of this function is sufficient to imply to a person skilled in the art of computer technology a set of possible structures of the circuit.

[0078] In various embodiments, as described in the previous paragraph, circuits, units, and other elements defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to each other, and the way they interact, form the microarchitecture definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation form of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementation forms can be derived, and all of its implementation forms belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with the microarchitecture definition provided pursuant to this disclosure can implement the structure by coding the circuit / unit / component description in a hardware description language (HDL), such as Verilog or VHDL, using ordinary art without excessive experimentation. The HDL description is often expressed in a form that appears to be functional. However, to those skilled in the art, this HDL description is a method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions can take the form of operation-level code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, in contrast to operation-level code), or structure code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry, generating a mask, and ultimately manufacturing the integrated circuit. Some hardware circuits, or parts thereof, can also be custom-designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuits.An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected integrally to realize a hardware circuit, and / or, in some embodiments, separate elements may be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented on an FPGA. This decoupling between the design of this group of circuits and the subsequent low-level implementation of these circuits generally leads to scenarios where the circuit or logic designer does not specify any particular set of structures for low-level implementation forms other than a description of how the circuit is configured, because this process is performed at different stages of the circuit implementation process.

[0079] The fact that the same specifications of a circuit can be implemented using many different low-level combinations of circuit elements results in a multitude of equivalent structures for that circuit. As mentioned above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. Often, the choice made by different design tools or methods to generate these different implementation forms can be arbitrary.

[0080] Furthermore, in a given embodiment, a single implementation of a specific functional specification of a circuit typically involves a large number of devices (e.g., millions of transistors). Therefore, given this sheer volume of information, it is impractical to fully enumerate the low-level structures used to implement a single embodiment, let alone a vast number of equivalent possible implementations. For this reason, this disclosure describes the circuit structure using functional omissions commonly used in the industry.

Claims

1. An integrated circuit device, circuit board and A plurality of gate structures oriented along a first direction in the horizontal dimension above the substrate, A plurality of elongated channel regions oriented along a second direction in the horizontal dimension, wherein the second direction is perpendicular to the first direction, the elongated channel regions passing through at least one of the gate structures, and the elongated channel regions include two or more nanosheet fins stacked in the vertical dimension above the substrate, An input stage comprising at least one of the elongated channel regions, wherein the nanosheet fin in the at least one elongated channel region of the input stage has a first width along the first direction in the horizontal dimension, An output stage comprising at least one other elongated channel region of the elongated channel region, wherein the nanosheet fin in the at least one other elongated channel region of the output stage has a second width in the horizontal dimension along the first direction, and the second width is greater than the first width. An integrated circuit device comprising the above features.

2. The device according to claim 1, wherein the nanosheet fins are aligned parallel to the substrate in the vertical dimension.

3. The device according to claim 1, wherein an active gate is formed at the intersection of at least one of the elongated channel regions and at least one of the gate structures.

4. The device according to claim 1, wherein the elongated channel region extends between a first dummy gate structure on the first side of the device in the horizontal dimension and a second dummy gate structure on the second side of the device in the horizontal dimension.

5. The device according to claim 1, wherein the nanosheet fin is substantially surrounded by a portion of the at least one gate structure through which the nanosheet fin passes.

6. The device according to claim 1, wherein the input stage includes at least two of the elongated channel regions, and the nanosheet fins within the at least two elongated channel regions of the input stage have the first width.

7. The device according to claim 6, wherein the input stage further comprises at least two additional elongated channel regions of the elongated channel region, and the nanosheet fins in the at least two additional elongated channel regions of the input stage have a third width along the first direction in the horizontal dimension, the third width being greater than the first width.

8. The device according to claim 1, wherein the output stage includes at least two of the elongated channel regions, and the nanosheet fins within the at least two elongated channel regions of the output stage have the second width.

9. The device according to claim 1, wherein the output stage includes at least two of the elongated channel regions, and the nanosheet fins within the at least two elongated channel regions of the output stage are merged.

10. The device according to claim 1, wherein the device includes one or more integrated circuit cells, the first direction in the horizontal dimension is the cell height direction, and the second direction in the horizontal dimension is the gate pitch direction.

11. The device according to claim 10, wherein at least one of the gate structures extends across both the input stage and the output stage in the cell height direction.

12. The device according to claim 10, wherein the output stage is separated from the input stage in the gate pitch direction by at least one dummy gate structure oriented in the cell height direction.

13. An integrated circuit device, A plurality of gate structures oriented along a first direction in the horizontal dimension above the substrate, wherein the plurality of gate structures are A first dummy gate structure positioned on the first side of the device along a second direction in the horizontal dimension, wherein the second direction is perpendicular to the first direction, A second dummy gate structure positioned on the second side of the device along the second direction, A plurality of gate structures, including at least one active gate structure positioned between the first dummy gate structure and the second dummy gate structure, A plurality of elongated channel regions oriented along the second direction and extending between the first dummy gate structure and the second dummy gate structure, wherein the elongated channel regions pass through the at least one active gate structure, and the elongated channel regions include two or more nanosheet fins stacked vertically above the substrate, An input stage comprising at least one of the elongated channel regions, wherein the nanosheet fin in the at least one elongated channel region of the input stage has a first width along the first direction in the horizontal dimension, An output stage comprising at least one other elongated channel region of the elongated channel region, wherein the nanosheet fin in the at least one other elongated channel region of the output stage has a second width in the horizontal dimension along the first direction, and the second width is greater than the first width. An integrated circuit device comprising the above features.

14. The device according to claim 13, wherein the output stage is separated from the input stage in the first direction.

15. The device according to claim 13, wherein the gate structure extends across both the input stage and the output stage.

16. The device according to claim 13, wherein the input stage includes at least two of the elongated channel regions, and the nanosheet fins in the at least two elongated channel regions of the input stage have a first width, and the output stage includes at least two of the elongated channel regions, and the nanosheet fins in the at least two elongated channel regions of the output stage have a second width.

17. An integrated circuit device, A plurality of gate structures oriented along a first direction in the horizontal dimension above the substrate, wherein the plurality of gate structures are A first dummy gate structure positioned on the first side of the device along a second direction in the horizontal dimension, wherein the second direction is perpendicular to the first direction, A second dummy gate structure positioned on the second side of the device along the second direction, Two or more active gate structures positioned between the first dummy gate and the second dummy gate, A plurality of gate structures, including a third dummy gate structure positioned between at least two of the active gate structures, The input stage, An input stage comprising a plurality of first elongated channel regions oriented along the second direction and extending between the first dummy gate structure and the third dummy gate structure, wherein each first elongated channel region passes through at least one of the active gate structures, and each first elongated channel region comprises two or more first nanosheet fins stacked vertically above the substrate, wherein each first nanosheet fin in at least one of the first elongated channel regions of the input stage comprises two or more first nanosheet fins having a first width along the first direction in the horizontal dimension, It is the output stage, An output stage comprising a plurality of second elongated channel regions oriented along the second direction and extending between the third dummy gate structure and the second dummy gate structure, wherein the second elongated channel regions pass through at least one of the active gate structures, and the second elongated channel regions comprise two or more second nanosheet fins stacked on the substrate in the vertical dimension, wherein the second nanosheet fins in at least one of the second elongated channel regions of the input stage comprise two or more second nanosheet fins having a second width along the first direction in the horizontal dimension, the second width being greater than the first width, and the output stage comprising a plurality of second elongated channel regions, An integrated circuit device comprising the above features.

18. The device according to claim 17, wherein the output stage is separated from the input stage by the third dummy gate structure.

19. The device according to claim 17, wherein the second nanosheet fins in at least two of the second elongated channel regions are merged.

20. The device according to claim 17, wherein the input stage further comprises at least one first nanosheet fin in at least one other of the first elongated channel regions of the input stage having the second width.

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