Buffer and inverter transistors embedded in interconnection metal layer

Abstract

The present invention provides buffer and inverter transistors embedded in an interconnection metal layer. [Solution] An integrated circuit device having a buffer transistor or inverter transistor formed between upper BEOL (back-end of line) metal layers is described. The buffer or inverter transistor includes an active region and a source / drain which may be formed in the space between the upper metal layers. In certain cases, the transistor is formed between the metal layers furthest from the substrate. The transistor is connected to a routing either above or below the transistor to buffer and / or invert signals passing through the routing. For example, the transistor may include an active region located between a power routing and a ground routing, and be connected to a signal routing between the power routing and the ground routing to boost and / or invert signals propagating along the signal routing. In various cases, the active region of the transistor is formed by a thin channel material.

Description

TECHNICAL FIELD

[0001] The embodiments described in the present specification relate to signal routing for semiconductor devices. More specifically, the implementations described in the present specification relate to the implementation of buffers or inverter transistors in an interconnect layer for buffering signals.

BACKGROUND ART

[0002] Large-scale integrated circuits of integrated circuits (such as very large-scale integrated circuits (VLSI)) may have signals that travel globally between a large number of circuits or blocks of circuits. In some cases, these signals can travel long distances across a large number of circuits or blocks of circuits. In such cases, the signals may need to be boosted (e.g., amplified or buffered) at one or more points along their paths to maintain signal strength and an acceptable signal-to-noise ratio of the signals. In current implementations, buffering or inverting is typically implemented by placing buffer or inverter circuits in the transistor region of the device (e.g., the silicon / CMOS level of the device). However, placing buffer or inverter circuits in the transistor region requires the signal to travel along vias between the transistor region and the global signal routing layer, which is typically located in the upper metal layers of the device.

[0003] Having buffer or inverter circuits in the transistor region occupies valuable silicon footprint in that region and still generates longer travel paths due to signals moving up and down between the transistor region and the upper metal layer. Furthermore, buffer or inverter circuits and their associated vias to the upper metal layer create path interruptions that must be adapted to the device design. For example, complex or undesirable routes may be required to route signals around path interruptions caused by buffer or inverter circuits and their associated vias. Thus, there are both electrical (e.g., high resistance over long travel paths) and mechanical (e.g., footprint and path interruption) problems associated with buffer or inverter circuits located in the transistor region.

[0004] The features and advantages of the methods and apparatus of the embodiments described herein will be better understood by referring to the following detailed description of the currently preferred but nevertheless exemplary embodiments according to the embodiments described herein, in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0005] [Figure 1] The image shows a top view of a planned device having buffer transistors between upper metal layers, according to several embodiments.

[0006] [Figure 2] This is a cross-sectional side view of a device showing a buffer transistor along line 2-2 in Figure 1, according to several embodiments.

[0007] [Figure 3] This is a cross-sectional side view of a device showing a buffer transistor along line 3-3 in Figure 1, according to several embodiments.

[0008] [Figure 4] Three-dimensional perspective views of buffer transistors according to several embodiments are shown.

[0009] [Figure 5] Schematic diagrams of buffer transistors according to several embodiments are shown.

[0010] [Figure 6] Three-dimensional perspective views of another buffer transistor according to several embodiments are shown.

[0011] [Figure 7] A schematic diagram of another buffer transistor, according to several embodiments, is shown.

[0012] [Figure 8] A top view of the intended device is shown, illustrating various layouts of the buffer transistor according to several embodiments.

[0013] [Figure 9] This is a block diagram of one embodiment of an exemplary system.

[0014] The embodiments disclosed herein are open to various modifications and alternative forms, but specific embodiments are shown in the drawings and described in detail herein for illustrative purposes. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed in the claims. On the contrary, this application is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the disclosure of this application, as set forth in the appended claims. [Modes for carrying out the invention]

[0015] This disclosure relates to the mounting of transistors (such as buffer transistors) between metal layers above the transistor region of an integrated circuit device (e.g., upper metal layers). In various embodiments, these upper metal layers may be referred to as BEOL ("back-end of line") metal layers. The upper metal layers may provide routing (e.g., paths) for control signals and / or power signals. Many current cell designs provide connections and routing for power or signals to transistors or other structures in the area above the transistor. For example, connections and routing for power or signals may be provided in the upper layers of the device. As used herein, the term “upper” refers to an area within the device that lies vertically above the active layer of the device (e.g., above the transistor region of the device when viewed in a typical cross-sectional view). For example, “upper” may refer to components such as contacts or layers that are vertically above the transistor region, as shown in the drawings and described herein. In some cases, the term “front” may be used interchangeably with the term “upper.”

[0016] As used herein, the term “routing” refers to any combination of metal vias, metal wires, metal traces, etc., that provide a path / route between two structures. Additional embodiments may be contemplated in which the metal in the “routing” is replaced with an alternative conductive material. For example, the metal in the “routing” may be replaced with a superconducting material, a semiconductor material, or a nonmetallic conductor.

[0017] As described above, placing buffer or inverter transistors in the transistor region of an integrated circuit device in a large-scale integrated circuit can cause electrical (e.g., high resistance) and mechanical (e.g., footprint / area utilization and path disruption) problems. This disclosure recognizes that these problems can be mitigated by placing buffer or inverter transistors not in the transistor region of the integrated circuit device, but in locations between upper routing layers (e.g., upper metal routing layers). Placing buffer or inverter transistors in these locations allows for connections between the buffer or inverter transistors and their associated signal routes over short distances. For example, a buffer or inverter transistor may be coupled to a signal route in the upper metal layer directly above or below the buffer or inverter transistor. These shorter connection distances reduce resistance in the connection between the buffer or inverter transistor and the signal route, which improves the electrical characteristics for signal transmission. In some cases, the number of buffer or inverter transistors required for global signal transmission across the device may be reduced by implementing these shorter connection paths. Reducing the number of buffer or inverter transistors can increase the flexibility in the design or manufacture of these devices.

[0018] Relocating buffer or inverter transistors from the transistor region of a device by placing them between upper metal layers frees up footprints in that region. These freed footprints can be used, for example, to increase the number of other types of transistors or circuit elements, enabling more complex or powerful devices. Furthermore, relocating buffer or inverter transistors from the transistor region of a device eliminates potential blockages caused by the transistors. Freeing up footprints and eliminating blockages increases flexibility in the design or manufacture of integrated circuit devices. For example, the design of an integrated circuit may include more optimized routing strategies for signals within the device, involving footprint freeing and blockage elimination. Manufacturing may also be more efficient in certain cases using optimized design strategies.

[0019] Specific embodiments disclosed herein have three broad elements: 1) a transistor region; 2) a first metal layer and a second metal layer in the upper metal layer above the transistor region, wherein one or more of the metal layers include signal routing, power routing, and ground supply routing; and 3) a transistor circuit positioned between the first and second metal layers. In various embodiments, the transistor circuit is a buffer transistor or inverter transistor including an active region, a gate, a signal input coupled to the gate, a portion of the signal routing, a voltage supply input coupled to the power routing, a ground supply input coupled to the ground supply routing, and a signal output coupled to another portion of the signal routing. In certain embodiments, the signal routing, power routing, and ground supply routing are located in the same upper metal layer (e.g., either the first or second metal layer). In some intended embodiments, the transistor circuit is a two-stage or one-stage inverter circuit in which the active region includes a p-type active region and an n-type active region.

[0020] Various examples of embodiments having these broad elements are described herein in the present disclosure. It should be noted that the illustrated embodiments of the present disclosure show a design template for a device having a buffer transistor positioned between upper metal layers. Those skilled in the art will recognize that the illustrated embodiments in the present disclosure may be a design template for an inverter transistor positioned between upper metal layers, or a combination of a buffer transistor and an inverter transistor. Accordingly, the design template presented in the present disclosure provides a basic building block from which many different types of routing schemes and logic functions (such as NAND and NOR) for devices can be constructed based on the connection scheme to the transistors within the design template. Additional embodiments that use more metal tracks in either the first metal layer or the second metal layer, along with variations in the size and / or width of the active region, may be contemplated.

[0021] Figure 1 shows a top view of a contemplated device having a buffer transistor between upper metal layers, in accordance with some embodiments. In the illustrated embodiment, two upper metal layers 110 and 120 of the device 100 are shown. The upper metal layers 110 and 120 may be, for example, BEOL metal layers vertically above the transistor region of the device 100. In certain embodiments, metal layer 110 is the metal layer that is vertically closer to the transistor region of device 100 (e.g., as shown in Figures 2 and 3, metal layer 110 is a lower metal layer, and metal layer 120 is an upper metal layer).

[0022] In various embodiments, the metal layer 110 includes routings 112A to F, and the metal layer 120 includes routings 122A to F. Since the metal layer 110 and the metal layer 120 are adjacent metal layers in the upper metal layers, the routings 112A to F and the routings 122A to F may extend perpendicular to each other, as shown in FIG. 3. The routings 112A to F and the routings 122A to F may include signal routing, power supply routing, or ground supply routing. In certain embodiments, one or more of the routings 112 and the routings 122 are global routings. A global routing may be, for example, a routing that carries signals over long distances and attempts to avoid detours in its path when passing over transistor regions to which it is not connected.

[0023] In certain embodiments, the device 100 includes one or more buffer transistors positioned in the vertical space between the metal layer 110 and the metal layer 120. In the illustrated embodiment, the device 100 includes a buffer transistor 130 and a buffer transistor 140. The dashed lines represent the horizontal area occupied by the buffer transistor 130 and the buffer transistor 140. The buffer transistor 130 includes an active region 132 positioned parallel to the routing 112 and perpendicular to the routing 122. The buffer transistor 140 includes an active region 142 positioned parallel to the routing 122 and perpendicular to the routing 112. The active region 132 may traverse under the routing 122, while the active region 142 traverses over the routing 112. In various embodiments, the active region 132A and the active region 132B are complementary active regions (for example, one is a PMOS active region and the other is an NMOS active region). The active region 142A and the active region 142B may likewise be complementary active regions.

[0024] Figure 2 is a cross-sectional side view of device 100 showing a buffer transistor 130 along line 2-2 in Figure 1, according to several embodiments. Note that Figure 2 shows only a portion of device 100, including the buffer transistor 130 along line 2-2. Furthermore, elements within device 100 (including, but not limited to, the substrate 200, the transistor region 210, and the dielectric 220) are shown representatively for illustrative purposes, along with their dimensions and spacing from one another. In the illustrated embodiments, device 100 includes a substrate 200 having a transistor region 210 above the substrate.

[0025] In various embodiments, metal layers 110 and 120 (e.g., upper / BEOL metal layers) are located above the transistor region 210. In certain embodiments, metal layers 110 and 120 are higher metal layers. For example, metal layers 110 and 120 may be metal layers that are further vertically away from the transistor region 210 than other metal layers (e.g., an additional metal layer exists between the transistor region 210 and metal layer 110). However, metal layers 110 and 120 may be any pair of adjacent (e.g., vertically adjacent) metal layers located above the transistor region 210. For example, an embodiment may be considered in which metal layers 110 and 120 are the two metal layers closest vertically to the transistor region 210.

[0026] In certain embodiments, the dielectric layer 220 is positioned between the metal layer 110 and the metal layer 120. The dielectric 220 may include any suitable dielectric material to provide electrical insulation and mechanical support between the metal layer 110 and the metal layer 120. For example, the dielectric 220 may include silicon oxide. The buffer transistor 130, including the active regions 132A / 132B, is formed between the metal layer 110 and the metal layer 120 and may be at least partially surrounded by the dielectric 220. In various embodiments, as shown in Figure 2, the active regions 132A, 132B and routings 112C-E are parallel and extend in / out of the page, while routing 122B extends horizontally along the page.

[0027] Figure 3 is a cross-sectional side view of device 100 showing a buffer transistor 140 along line 3-3 in Figure 1, according to several embodiments. Note that Figure 3 shows only a portion of device 100, including the buffer transistor 140 along line 3-3. Furthermore, as with Figure 2, elements within device 100 (including, but not limited to, the substrate 200, transistor region 210, and dielectric 220) are shown representatively for illustrative purposes, along with their dimensions and spacing from one another.

[0028] In various embodiments, the buffer transistor 140, which includes active regions 142A / 142B, is formed between metal layer 110 and metal layer 120 and is at least partially surrounded by dielectric 220. In some embodiments, as shown in Figure 3, the active regions 142A, 142B and routings 122D-F are parallel and extend in / out of the page, while routing 112B extends horizontally along the page. As shown in Figures 2 and 3, the buffer transistor (e.g., buffer transistor 130 or buffer transistor 140) may be formed in the vertical space between two adjacent metal layers (e.g., metal layer 110 and metal layer 120) above the transistor region 210 of the device 100 (e.g., on the upper side of the transistor region).

[0029] In certain embodiments, the active region 132 of buffer transistor 130 and the active region 142 of buffer transistor 140 are active regions made of a thin channel material. For example, the channel material may be on the order of tens of atomic layers or less. Thin channel materials may include, but are not limited to, 2D (two-dimensional) materials, CNTs (carbon nanotubes), and oxide semiconductors (e.g., indium gallium zinc oxide and tungsten-doped indium oxide). Examples of 2D materials include, but are not limited to, graphene, silicene, BNNS (boron nitride nanosheets), TMDC (transition metal dichalcogenides), phospholenes, and metal oxide nanosheets. By utilizing these types of materials, it may be possible to achieve silicon-like active region characteristics in a few layers that can be positioned between existing upper metal layers in the device layout. Buffer transistors having these types of active regions and positioned between upper metal layers can be implemented in various designs of devices having buffer transistors positioned at various locations within the device (such as device 100) to provide buffering for signals propagating across the device, as described herein.

[0030] Figures 4 to 7 illustrate representations of intended embodiments for the design of a buffer transistor that can be mounted in the space between the upper metal layers as described herein. Figure 4 shows a three-dimensional perspective view of a buffer transistor 130 according to several embodiments. In the illustrated embodiments, the buffer transistor 130 is a two-stage inverter circuit in which active regions 132A and 132B are complementary active regions. In certain embodiments, active region 132A is a p-type active region and active region 132B is an n-type active region.

[0031] In various embodiments, the buffer transistor 130 increases the strength of the signal input to the buffer transistor by utilizing connections to routings 112C-E within the metal layer 110. In the illustrated embodiment, routing 112D is the signal routing, routing 112C is the power routing, and routing 112E is the ground supply routing. The voltage supply input 430 for the buffer transistor 130 is provided by using via 434 to connect routing 112C (e.g., the power routing) to source wire 432 (above the metal layer 110). Source wire 432 then extends above the source region of the active region 132A and connects to it, providing the voltage supply input for the buffer transistor 130. The ground supply input 440 for the buffer transistor 130 is provided by using via 444 to connect routing 112E (e.g., the ground supply routing) to source wire 442 (above the metal layer 110). The source wire 442 then extends over the source region of the active region 132B, connects to it, and provides a ground supply input for the buffer transistor 130. The power routing (e.g., routing 112C) and ground supply routing (e.g., routing 112E) may also provide electrical shielding for the buffer transistor 130, as the routing (e.g., rails) is positioned along the outer circumference of the buffer transistor.

[0032] In certain embodiments, routing 112D includes an input routing 112D' connected to the signal input 410 of the buffer transistor 130 and an output routing 112D'' connected to the signal output 420 of the buffer transistor. Input routing 112D' and output routing 112D'' may be physically separated (e.g., disconnected) portions of routing 112D in the area of ​​the buffer transistor 130. Embodiments may be contemplated in which input routing 112D' and output routing 112D'' are created by inserting electrical isolation into routing 112D.

[0033] In certain embodiments, the signal input 410 to the buffer transistor 130 is made by connecting the input routing 112D' to the gate wire 412 (above the metal layer 110) using a via 414. The gate wire 412 then extends over both the active region 132A and the active region 132B to form the gate for the first stage of the buffer transistor 130 (e.g., the first stage of a two-stage inverter circuit). The gate wire 412 may extend over both the channel regions of the active region 132A and the active region 132B, for example. The gate wire 412 may be connected to both the channel regions of the active region 132A and the active region 132B to provide the input for the first stage.

[0034] The output from the first stage is provided via a stage output wire 416, which extends over and connects to the drain regions of both the active region 132A and the active region 132B. A local interconnect wire 418 may be connected to the stage output wire 416 to route the output of the first stage on the stage output wire 416 to the input of the second stage of the buffer transistor 130. In various embodiments, the local interconnect wire 418 may be a C-shaped wire that connects to the end of the stage output wire 416 and then routes over and connects to the channel regions of both the active region 132A and the active region 132B to provide the input for the second stage of the buffer transistor 130. Thus, the local interconnect wire 418 provides the same layer connection for routing the signal from the output of the first stage to the input of the second stage of the buffer transistor 130.

[0035] In various embodiments, the local interconnect wire 418 can have its routing if there is sufficient space between the metal layer 110 and the metal layer 120. For example, in higher metal layers (e.g., metal layers further away from the transistor region), the metal layers and the dielectric between them may be larger and therefore have more space to accommodate the local interconnect wire 418. Accommodation of the local interconnect wire 418 may include enabling the routing of the local interconnect wire without causing it to electrically interfere with other wires or components, or without the local interconnect wire violating any design rules or guidelines. In lower metal layers (e.g., metal layers closer to the transistor region), the height of the local interconnect wire 418 may have to be constrained. In some embodiments, the local interconnect wire 418 can be formed by using a portion of the metal layer above the buffer transistor 130 (e.g., a portion of metal layer 120). For example, vias may be added to connect the stage output wire 416 to a local interconnect wire 418 located within the metal layer 120 above the buffer transistor 130.

[0036] After the local interconnect wire 418 routes the signal to the input of the second stage of the buffer circuit 130, the output of the second stage (e.g., the final signal output stage) is provided by the stage output wire 422. The stage output wire 422 is positioned above the drain regions of both the active region 132A and the active region 132B and can be connected to them. The stage output wire 422 (above the metal layer 110) is then connected to routing 112D'' using via 424, providing the buffer transistor 130 with a signal output 420. The output signal on signal output 420 is stronger than the input signal on signal input 410 after passing through the two-stage inverter circuit of the buffer transistor 130 described above.

[0037] Figure 5 shows schematic diagrams of buffer transistors 130 according to several embodiments. In the illustrated embodiments, buffer transistors 130 include a first-stage inverter 510 and a second-stage inverter 520. In various embodiments, routing 112C carries VDD 506 (e.g., voltage supply input). Routing 112C is connected by source wire 432 to the source of the p-type region (e.g., active region 132A) in the first-stage inverter 510 and the second-stage inverter 520. Routing 112E carries VSS 508 (e.g., ground supply input) and is connected by source wire 442 to the source of the n-type region (e.g., active region 132B) in the first-stage inverter 510 and the second-stage inverter 520. These connections to VDD 506 and VSS 508 supply operating power to the first-stage inverter 510 and the second-stage inverter 520.

[0038] In a particular embodiment, the first stage inverter 510 receives an input signal 502 provided on routing 112D'. The output of the first stage inverter 510 is then connected to the input of the second stage inverter 520 by a combination of stage output wire 416 and local interconnect wire 418. The output signal 504 is then output from the second stage inverter 520 onto routing 112D''.

[0039] Figure 6 shows three-dimensional perspective views of the buffer transistor 140 according to several embodiments. In the illustrated embodiments, the buffer transistor 140 is a two-stage inverter circuit in which active regions 132A and 132B are complementary active regions. In a particular embodiment, active region 142A is a p-type active region, and active region 142B is an n-type active region.

[0040] In various embodiments, the buffer transistor 140 is similar to the buffer transistor 130 in a structure where the connection is made to the metal layer 120 instead of the metal layer 110. For example, the buffer transistor 140 may utilize connections to routings 122D-F in the metal layer 120 to increase the strength of the signal input to the buffer transistor. In the illustrated embodiment, routing 122D is a power supply routing and routing 122F is a ground supply routing. The voltage supply input 630 for the buffer transistor 140 is provided by using via 634 to connect routing 122D (e.g., power supply routing) to source wire 632 (below the metal layer 120). Source wire 632 then extends over the source region of the active region 142A and connects to it, providing the voltage supply input for the buffer transistor 140. The ground supply input 640 for the buffer transistor 140 is provided by using via 644 to connect routing 122F (e.g., ground supply routing) to source wire 642 (below the metal layer 120). Source wire 642 then extends over the source region of the active region 142B, connects to it, and provides a ground supply input for buffer transistor 140. Power routing (e.g., routing 122D) and ground supply routing (e.g., routing 122F) can also provide electrical shielding for buffer transistor 140, as the routing (e.g., rails) is positioned along the outer circumference of the buffer transistor.

[0041] In certain embodiments, routing 122E is signal routing. Routing 122E may include input routing 122E' connected to the signal input 610 of buffer transistor 140 and output routing 122E'' connected to the signal output 620 of buffer transistor. Input routing 122E' and output routing 122E'' may be physically separated (e.g., disconnected) portions of routing 122E in the area of ​​buffer transistor 140. Embodiments may be contemplated in which input routing 122E' and output routing 122E'' are created by inserting electrical isolation within routing 122E.

[0042] In certain embodiments, the signal input 610 to the buffer transistor 140 is made by using via 614 to connect the input routing 122E' to the gate wire 612 (below the metal layer 120). The gate wire 612 extends over the channel regions of both the active region 142A and the active region 142B to form the gate for the first stage of the buffer transistor 140 (e.g., the first stage of a two-stage inverter circuit). The gate wire 612 may be connected to the channel regions in both the active region 142A and the active region 142B to provide the input for the first stage of the buffer transistor 140.

[0043] The output from the first stage is provided via a stage output wire 616, which extends over and connects to the drain regions of both the active region 142A and the active region 142B. The output of the first stage on the stage output wire 616 is routed to the input of the second stage of the buffer transistor 140 by connecting a local interconnect wire 618 to the stage output wire 616. In various embodiments, the local interconnect wire 618 may be a C-shaped wire that connects to the end of the stage output wire 616 and then routes over and connects to the channel regions of both the active region 142A and the active region 142B to provide the input for the second stage of the buffer transistor 140. Thus, the local interconnect wire 618 may provide the same layer connection for routing the signal from the output of the first stage to the input of the second stage of the buffer transistor 140.

[0044] In various embodiments, the local interconnect wire 618, like the local interconnect wire 418, may have its routing if there is sufficient space between the metal layer 110 and the metal layer 120. Furthermore, accommodating the local interconnect wire 618 may include enabling the routing of the local interconnect wire without causing it to electrically interfere with other wires or components, or without the local interconnect wire violating any design rules or guidelines. In the lower metal layers (e.g., the metal layer closer to the transistor region), the height of the local interconnect wire 618 may have to be constrained. Due to this constraint, in some embodiments, the local interconnect wire 618 may be formed by using a portion of the metal layer below the buffer transistor 140 (e.g., a portion of metal layer 110). For example, vias may be added to connect the stage output wire 616 to the local interconnect wire 618 located in the metal layer 110 below the buffer transistor 140.

[0045] After the local interconnect wire 618 routes the signal to the input of the second stage of the buffer circuit 140, the output of the second stage (e.g., the final signal output stage) is provided by the stage output wire 622. The stage output wire 622 is positioned above and can be connected to the drain regions of both the active region 142A and the active region 142B. The stage output wire 622 (below the metal layer 120) is connected to routing 122E'' using via 624 to provide the signal output 620 for the buffer transistor 140. The output signal on the signal output 620 has increased intensity compared to the input signal on the signal input 610 after passing through the two-stage inverter circuit of the buffer transistor 140 as described herein.

[0046] Figure 7 shows schematic diagrams of buffer transistors 140 according to several embodiments. In the illustrated embodiments, buffer transistors 140 include a first-stage inverter 710 and a second-stage inverter 720. In various embodiments, routing 122D carries VDD 706 (e.g., voltage supply input). Routing 122D is connected by source wire 632 to the source of the p-type region (e.g., active region 142A) in the first-stage inverter 710 and the second-stage inverter 720. Routing 122F carries VSS 708 (e.g., ground supply input) and is connected by source wire 642 to the source of the n-type region (e.g., active region 142B) in the first-stage inverter 710 and the second-stage inverter 720. These connections to VDD 706 and VSS 708 supply operating power to the first-stage inverter 710 and the second-stage inverter 720.

[0047] In a particular embodiment, the first stage inverter 710 receives an input signal 702 provided on routing 122E'. The output of the first stage inverter 710 is then connected to the input of the second stage inverter 720 by a combination of stage output wire 616 and local interconnect wire 618. The output signal 704 is then output from the second stage inverter 720 onto routing 122E''. As described above, both buffer transistors 130 and 140 constitute a two-stage inverter circuit capable of providing output signals (e.g., output signals 504 and 704) with increased intensity compared to the input signals (e.g., input signals 502 and 702). By positioning the buffer transistors between two metal layers (e.g., metal layer 110 and metal layer 120, as shown in Figures 2 and 3), the buffer transistors can provide this buffering (e.g., amplification) of signals propagating through device 100 without increasing the device footprint or area, since the buffer transistors are positioned in existing space within the device.

[0048] The number and layout (e.g., arrangement) of the buffer transistors described herein (e.g., buffer transistor 130 or buffer transistor 140) may vary based on the design or operational requirements of the device on which the buffer transistors are mounted. For example, embodiments may be contemplated in which multiple buffer transistors are stacked together across multiple columns or rows of routing within the device (e.g., across multiple routings within metal layer 110 or metal layer 120). In some embodiments, the stacked buffer transistors may share a common ground supply routing among them. In such embodiments, the stacked buffer transistors may be stacked in alignment (e.g., when the width of the active region is constrained) or in a staggered pattern to allow for a larger active region width.

[0049] Figure 8 shows a top view of a planned device illustrating various layouts of buffer transistors according to several embodiments. In the illustrated embodiments, the device 800 includes a metal layer 110 having routings 112A-112J and a metal layer 120 having routings 122A-122K. Routings 112B and 112F may be power routings (e.g., VDD), and routing 112D is ground supply routing. Routings 112C and 112E may be signal routings.

[0050] The pair of buffer transistors 130A (having active regions 132A and 132B) and 130B (having active regions 132A' and 132B') represents a pair of buffer transistors stacked in alignment. Note that the complementary pair of active regions is inverted between buffer transistors 130A and 130B, allowing the buffer transistors to share a ground supply routing (routing 112D). Thus, the active region 132B of buffer transistor 130A is adjacent to the active region 132B' of buffer transistor 130B. Although buffer transistors 130A and 130B share a common ground supply routing, the buffer transistors have separate power supply routings (e.g., routing 112B and routing 112F, respectively) and operate to buffer (e.g., amplify) different signals on different signal routings (e.g., routing 112C and routing 112E, respectively).

[0051] Since buffer transistors 130A and 130B are aligned (for example, the left and right ends of the buffer transistors are aligned in the figure), the width of the active region 132 is constrained and cannot be increased (note that the width of the active region is vertical in the figure). Arranging the buffer transistors in a staggered pattern, as shown by buffer transistors 130C and 130D in Figure 8, may allow the width of the active region 132 to be increased. In the illustrated embodiment, buffer transistor 130C includes active region 132A'' and active region 132B'', and buffer transistor 130D includes active region 13A'' and active region 132B''''.

[0052] Similar to the pairing of buffer transistors 130A and 130B, the complementary active regions are inverted between buffer transistors 130C and 130D, allowing the ground supply routing (routing 112D) to be shared by the buffer transistors. However, by arranging buffer transistors 130C and 130D in a staggered pattern, there are no size constraints from adjacent buffer transistors, thus allowing for an increase in the width of active regions 132A'', 132B'', 13A'''', and 132B''''. For example, the size of active regions 132A'' and 132B'' in buffer transistor 130C is not constrained by the arrangement of buffer transistor 130D, and vice versa. Therefore, by arranging buffer transistors 130C and 130D in a staggered pattern, it becomes possible to implement wider active regions within device 800. These wider active regions can be used to increase the amplification strength of the buffer transistors. For example, the signal strength increase provided by buffer transistors 130C / 130D may be greater than the signal strength increase provided by buffer transistors 130A / 130B. Using active regions rotated 90 degrees in the horizontal direction parallel to the substrate, the stacked buffer transistors may be stacked in an aligned manner (e.g., when the width of the active regions is constrained) or in a staggered pattern using metal layers 120 as routing (e.g., 122A-122K).

[0053] While buffer transistors have been described above, it is logical and easy for those skilled in the art to construct other logic functions and logic gates using the concepts and constructions described above. For example, an inverter can be constructed by employing only the second stage of the buffer. In another example, other logic gates (such as NAND and NOR) can be constructed by using more routing metal tracks in either metal layer 110 or metal layer 120, which provides the freedom to adjust the size and width of the active region. Exemplary computer system

[0054] Referring next to Figure 9, a block diagram of one embodiment of system 900 is shown, which can incorporate and / or utilize the methods and mechanisms described herein. In the illustrated embodiment, system 900 includes at least one instance of system on chip (SoC) 906, which may include multiple types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other methods, a communication fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors within the SoC 906 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 906 is coupled to external memory 902, peripherals 904, and a power supply 908.

[0055] A power supply 908 is also provided, which supplies a supply voltage to the SoC 906 and one or more supply voltages to the memory 902 and / or peripheral devices 904. In various embodiments, the power supply 908 represents a battery (e.g., a rechargeable battery for a smartphone, laptop or tablet computer, or other device). In some embodiments, two or more instances of the SoC 906 are included (and two or more external memories 902 are also included).

[0056] Memory 902 is any type of memory, including dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3 and / or low-power versions such as LPDDR2), Rambus DRAM (RDRAM), and static RAM (SRAM). One or more memory devices are coupled to a circuit board to form memory modules such as single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). Alternatively, the devices are mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0057] The peripheral device 904 includes any desired circuit configuration depending on the type of system 900. For example, in one embodiment, the peripheral device 904 includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, and global positioning systems. In some embodiments, the peripheral device 904 also includes additional storage, such as RAM storage, solid-state storage, or disk storage. The peripheral device 904 includes user interface devices such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker.

[0058] As illustrated, system 900 is shown to be applicable to a wide area. For example, system 900 may be used as part of the chip, circuit configuration, components, etc., of a desktop computer 910, a laptop computer 920, a tablet computer 930, a cellular or mobile phone 940, or a television 950 (or a set-top box coupled to a television). A smartwatch and a health monitoring device 960 are also illustrated. In some embodiments, the smartwatch may include a variety of general-purpose computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any of the health monitoring-related functions. Other wearable devices, such as devices worn around the neck, implantable devices in the human body, and glasses designed to provide augmented and / or virtual reality experiences, are also intended.

[0059] System 900 may be further used as part of a cloud-based service(s) 970. For example, the aforementioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 900 may be used in one or more devices of a home 980 other than those described above. For example, appliances in a home may monitor and detect conditions of note. For example, various devices in a home (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and alert the homeowner (or repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in the home and automate the adjustment of the heating / cooling system based on the homeowner's response history to various conditions. Figure 9 also shows the application of System 900 to various modes of transport 990. For example, System 900 may be used in control and / or entertainment systems for aircraft, trains, buses, rental cars, private cars, ships ranging from privately owned boats to cruise ships, and scooters (rented or owned). In various cases, system 900 may be used to provide automatic guidance (e.g., autonomous vehicles), general system control, and other methods. Many other embodiments of these are possible and contemplated. Note that the devices and applications shown in Figure 9 are illustrative and not intended to be limiting. Other devices are possible and contemplated. ***

[0060] This disclosure includes references to “one embodiment” or a group of “embodiments” (e.g., “several embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concept. References to “one embodiment,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, and modifications or substitutions within the spirit or scope of this disclosure are intended.

[0061] This disclosure may discuss the potential benefits that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily demonstrate any or all of the potential benefits. Whether a benefit is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the claims may not exhibit some or all of any disclosed benefits. For example, a particular implementation may include other circuits outside the scope of this disclosure that, together with one of the disclosed embodiments, negate or reduce one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation technique or tool) may also negate or reduce the disclosed benefits. Even assuming skilled execution, the realization of benefits may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, the inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on certain occasions, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations on claims that must be satisfied to demonstrate infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvements available to designers who have an interest in this disclosure. The acceptable description of such benefits (e.g., the statement that a particular benefit "may occur") is not intended to convey any doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0062] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single embodiment describes a particular feature, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure. The disclosed embodiments are intended to be illustrative, not limiting, unless there is a statement to the contrary in this disclosure. The foregoing is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that would be obvious to a person skilled in the art who would benefit from this disclosure.

[0063] For example, the features of this application can be combined in any preferred manner. Therefore, new claims can be formulated for any such combination of features during the examination of this application (or an application claiming priority to this application). In particular, referring to the attached claims, features from dependent claims can be combined with features from other dependent claims, including claims dependent on other independent claims, as appropriate. Similarly, features from each independent claim can be combined as appropriate.

[0064] Accordingly, each of the attached dependent claims may be constructed to depend on a single other claim, but additional dependencies are also contemplated. Any combination of features in the dependent claims that are consistent with the present disclosure is contemplated and may be claimed in this application or another application. In summary, the combinations are not limited to those specifically enumerated in the attached claims.

[0065] Where appropriate, claims prepared in one format or legal type (e.g., apparatus) are intended to also support corresponding claims in another format or legal type (e.g., method). ***

[0066] As this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, and the definitions provided through this disclosure, are hereby publicly noted as being used in interpreting the claims made pursuant to this disclosure.

[0067] References to singular items (i.e., nouns or noun phrases preceded by "a," "an," or "the") are intended to mean "one or more" unless explicitly stated in the context. Therefore, references to "items" in the claims do not, without context, preclude additional instances of an item. "Multiple" items refer to a set of two or more items.

[0068] In this specification, the word "may" is used in an allowable sense (i.e., possible, feasible) and not in an obligatory sense (i.e., not required).

[0069] The terms and forms "comprising" and "including" are open-ended and mean "to include, but not to limit."

[0070] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless otherwise explicitly stated in the context. Thus, the enumeration of “x or y” is equivalent to “x or y, or both,” and therefore includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase “either x or y, but not both” clarifies that “or” is used in an exclusive sense.

[0071] The enumerations "w, x, y, z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities, including single elements, up to the total number of elements in the set. For example, in the set [w, x, y, z], these expressions cover any single element in the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0072] In this disclosure, various “labels” may precede nouns or noun phrases. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different examples of the feature. Furthermore, when applied to features, the labels “first,” “second,” and “third” do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0073] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision; that is, the decision may be based on the specified factor alone, or on the specified factor plus other unspecified factors. Consider the phrase "determine A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover even one embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0074] The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not preclude the possibility that additional factors may influence, or otherwise trigger, the effect, either in conjunction with or independently of a specific factor. That is, the effect may depend on these factors alone, or on the specified factor and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase means that B is a factor that triggers the performance of A, or a specific outcome with respect to A. This phrase does not preclude the performance of A from also being in response to other factors, such as C. This phrase also does not preclude the performance of A from being in response to both B and C. This phrase is intended to include embodiments in which A is performed solely in response to B. As used herein, the phrase “in response to” is synonymous with the phrase “in response to at least partially.” Similarly, the phrase “in response to” is synonymous with the phrase “in at least partially.” ***

[0075] Within this disclosure, various entities (which may be referred to as “units,” “circuits,” or other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “configured to perform one or more tasks” is used herein to refer to structures (i.e., physical things). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when the structure is not currently in operation. Thus, entities described or explained as “configured” to perform some task refer to physical things such as devices, circuits, and systems having a processor unit and memory storing program instructions that can be executed to perform the task. This phrase is not used herein to refer to intangible things.

[0076] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. Even if not specifically stated, it is understood that those entities are "configured" to perform those tasks / operations.

[0077] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After proper programming, the FPGA can then be said to be "configured" to perform a particular function.

[0078] For the purposes of a U.S. patent application based on this disclosure, any claim that states a structure is “configured” to perform one or more tasks is not expressly intended to invoke Section 112(f) of the U.S. Patent Act with respect to that claim element. If an applicant wishes to invoke Section 112(f) during the examination process of a U.S. patent application based on this disclosure, it would use “means for” performing the function to describe the claim element.

[0079] This disclosure may describe various “circuits.” These circuits or “circuit configurations” constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), and programmable logic arrays. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuit configurations may include digital components, analog components, or a combination of both, as needed. Certain types of circuits may generally be referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), function units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit configurations.

[0080] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoder unit” may be described as performing the function of “processing the opcode of an instruction and routing the instruction to one or more of several functional units,” meaning that the decoder unit is “configured” to perform this function. The detail of this function is sufficient to imply to a person skilled in the art of computer technology a set of possible structures of the circuit.

[0081] In various embodiments, as described in the previous paragraph, circuits, units, and other elements defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to each other, and the way they interact, form the microarchitecture definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation form of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementation forms can be derived, and all of its implementation forms belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with the microarchitecture definition provided pursuant to this disclosure can implement the structure by coding the circuit / unit / component description in a hardware description language (HDL), such as Verilog or VHDL, using ordinary art without excessive experimentation. The HDL description is often expressed in a form that appears to be functional. However, to those skilled in the art, this HDL description is a method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions can take the form of operation-level code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, in contrast to operation-level code), or structure code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry, generating a mask, and ultimately manufacturing the integrated circuit. Some hardware circuits, or parts thereof, can also be custom-designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuits.An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected integrally to realize a hardware circuit, and / or, in some embodiments, separate elements may be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented on an FPGA. This decoupling between the design of this group of circuits and the subsequent low-level implementation of these circuits generally leads to scenarios where the circuit or logic designer does not specify any particular set of structures for low-level implementation forms other than a description of how the circuit is configured, because this process is performed at different stages of the circuit implementation process.

[0082] The fact that the same specifications of a circuit can be implemented using many different low-level combinations of circuit elements results in a multitude of equivalent structures for that circuit. As mentioned above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. Often, the choice made by different design tools or methods to generate these different implementation forms can be arbitrary.

[0083] Furthermore, in a given embodiment, a single implementation of a specific functional specification of a circuit typically involves a large number of devices (e.g., millions of transistors). Therefore, given this sheer volume of information, it is impractical to fully enumerate the low-level structures used to implement a single embodiment, let alone a vast number of equivalent possible implementations. For this reason, this disclosure describes the circuit structure using functional omissions commonly used in the industry.

Claims

1. It is a device, A transistor region of an integrated circuit, wherein the transistor region is located above the substrate in a vertical direction perpendicular to the substrate, A first metal layer located vertically above the transistor region, A second metal layer located above the first metal layer in the vertical direction, At least one of the first metal layer and the second metal layer includes a second metal layer which includes power routing, ground supply routing, and signal routing, The system comprises a transistor circuit positioned between the first metal layer and the second metal layer in the vertical direction, wherein the transistor circuit Active area and, The gate, A signal input coupled to the gate and a part of the signal routing, A voltage supply input for the active region coupled to the power routing, A grounding supply input for the active region coupled to the grounding supply routing, A device including a signal output coupled to an additional portion of the signal routing.

2. The apparatus according to claim 1, wherein the transistor circuit is a buffer transistor circuit configured to increase the intensity of the signal received at the signal input.

3. The apparatus according to claim 1, wherein the transistor circuit is an inverter transistor circuit, and the active region includes a p-type active region and an n-type active region.

4. The apparatus according to claim 3, wherein the transistor circuit further includes local vias between one or more of the gate, the voltage supply input, the ground supply input, and the signal output, and one or both of the first metal layer and the second metal layer.

5. The apparatus according to claim 3, wherein the transistor circuit further includes a local interconnection wire between the drain region and the gate region of the active region.

6. The apparatus according to claim 1, wherein the power routing, the ground supply routing, and the signal routing are oriented parallel to each other in a horizontal direction parallel to the substrate, and the active region is located between the power routing and the ground routing in the horizontal direction.

7. The apparatus according to claim 1, further comprising an additional transistor circuit positioned between the first metal layer and the second metal layer in the vertical direction, wherein the additional transistor circuit includes an additional active region.

8. The apparatus according to claim 7, wherein the additional active region is oriented orthogonally to the active region in a horizontal direction parallel to the substrate.

9. The apparatus according to claim 1, wherein the transistor circuit is located in a dielectric layer between the first metal layer and the second metal layer.

10. The apparatus according to claim 1, wherein the active region is formed by a thin channel material positioned between the first metal layer and the second metal layer.

11. It is a device, A transistor circuit located within the transistor region of an integrated circuit, wherein the transistor is located above the substrate in a vertical direction perpendicular to the substrate, A first metal layer located vertically above the transistor region, A second metal layer located vertically above the transistor region, The first metal layer and at least one of the second metal layers include power routing, ground supply routing, and signal routing, and a portion of the signal routing is coupled to the transistor circuit, The system comprises a transistor circuit positioned between the first metal layer and the second metal layer in the vertical direction, wherein the transistor circuit p-type active region, n-type active region and A gate input coupled to the portion of the signal routing coupled to the transistor circuit, The source region within the p-type active region and the voltage supply input coupled to the power routing, The source region within the n-type active region and the ground supply input coupled to the ground supply routing, A device including a gate output coupled to an additional portion of the signal routing.

12. The apparatus according to claim 11, wherein the power routing, the ground supply routing, and the signal routing are oriented parallel to a first direction in a horizontal direction parallel to the substrate.

13. The apparatus according to claim 12, wherein the p-type active region and the n-type active region are oriented parallel to the first direction in the horizontal direction.

14. The apparatus according to claim 12, wherein the transistor circuit includes a gate wire oriented along a second direction in the horizontal direction, the second direction being perpendicular to the first direction, and the gate wire extends over both the p-type active region and the n-type active region in the vertical direction.

15. The aforementioned voltage supply input is A metal wire positioned at least partially above the source region in the p-type active region, The apparatus according to claim 11, further comprising a via coupled between the metal wire and the power routing.

16. The aforementioned grounding supply input is A metal wire positioned at least partially above the source region in the n-type active region, The apparatus according to claim 11, further comprising a via coupled between the metal wire and the ground supply routing.

17. The aforementioned transistor circuit is A first gate wire oriented along a horizontal direction, wherein the first gate wire is at least partially positioned above both the p-type active region and the n-type active region channel regions in the vertical direction, A first stage output wire oriented along the aforementioned direction, wherein the first stage output wire is at least partially positioned above the drain regions of both the p-type active region and the n-type active region in the vertical direction, The apparatus according to claim 11, comprising a local interconnect wire connected to both ends of the first stage output wire, wherein at least a portion of the local interconnect wire is positioned above the channel regions of both the p-type active region and the n-type active region in the vertical direction.

18. The apparatus according to claim 17, wherein the gate output includes a second stage output wire oriented along the second direction, the second stage output wire being at least partially positioned above the drain regions of both the p-type active region and the n-type active region in the vertical direction.

19. The apparatus according to claim 11, wherein the transistor circuit is located in a dielectric layer between the first metal layer and the second metal layer.

20. It is a device, A transistor region of an integrated circuit, wherein the transistor region is located above the substrate in a vertical direction perpendicular to the substrate, A first metal layer located vertically above the transistor region, the first metal layer includes a first power routing, a first ground supply routing, and a first signal routing, A second metal layer located vertically above the first metal layer, the second metal layer includes a second power routing, a second ground supply routing, and a second signal routing, The system comprises a first buffer transistor circuit positioned between the first metal layer and the second metal layer in the vertical direction, wherein the first buffer transistor circuit The first p-type active region, The first n-type active region, A first gate input coupled to a part of the first signal routing, A first source region and a first voltage supply input coupled to the first power routing within the first p-type active region, A first source region and a first ground supply input coupled to the first ground supply routing within the first n-type active region, A first gate output coupled to the additional portion of the first signal routing, The system includes a second buffer transistor circuit positioned between the first metal layer and the second metal layer in the vertical direction, wherein the second buffer transistor circuit is The second p-type active region, The second n-type active region, A second gate input coupled to a part of the second signal routing, A second source region within the second p-type active region and a second voltage supply input coupled to the second power supply routing, A second source region within the second n-type active region and a second ground supply input coupled to the second ground supply routing, A device including a second gate output coupled to an additional portion of the second signal routing.

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