Device structure for inducing layout-dependent threshold voltage shift

Abstract

This provides a device structure for inducing a layout-dependent threshold voltage shift. [Solution] A device layout for an integrated circuit device is disclosed, which includes a threshold voltage shift induced by the arrangement of alternating work function metals adjacent to active gates. The device layout includes a single epitaxy for the active regions in the device, having common source / drain regions between the active region rows in the layout. The metal gate sections above the active regions of one or more rows may be replaced with metals of different work functions in the inactive regions of the layout. The metals of different work functions in the inactive regions induce a threshold voltage shift in adjacent (neighboring) active transistors in the device layout.

Description

TECHNICAL FIELD

[0001] Embodiments described in the present specification relate to transistor structures and layouts for semiconductor devices. More specifically, the embodiments described in the present specification relate to transistor structures and layouts including transistors that induce threshold voltage shifts in adjacent transistors. BACKGROUND ART

[0002] In advanced metal gate CMOS technologies, work function metals are often utilized as gate materials to adjust the threshold voltage of NMOS or PMOS transistors. For example, selection of the work function metal for the gate material can be used to set an appropriate threshold voltage for an NMOS or PMOS transistor. However, NMOS transistors and PMOS transistors have significantly different work function metals. Therefore, in CMOS logic circuits or devices having physically connected NMOS gates and PMOS gates, the merge / junction of the NMOS work function gate material and the PMOS work function gate material may result in an additional threshold voltage shift in one or both of the NMOS gate and the PMOS gate. This threshold voltage shift induced by the physical connection of different work function metals may be referred to as the metal boundary effect. Examples of devices in which the metal boundary effect may occur include, but are not limited to, inverters, NAND devices, and NOR devices.

[0003] In some cases, it is desirable to induce a threshold voltage shift due to the metal boundary effect. Current methods for adding an induced threshold voltage shift involve adding dummy NMOS / PMOS devices next to each active (e.g., device under test) PMOS / NMOS device. For example, a dummy NMOS device may be placed next to an active PMOS device to induce a threshold voltage shift in the PMOS device. However, placing dummy devices requires at least two minimum number of dummy NMOS / PMOS rows due to current process constraints. Having at least two dummy rows generates the threshold voltage shift at the expense of circuit or device area. Therefore, it is necessary to generate the desired threshold voltage shift without the current sacrifice of increasing circuit or device area.

[0004] The features and advantages of the methods and apparatus of the embodiments described herein will be better understood by referring to the following detailed description of the currently preferred but nevertheless exemplary embodiments according to the embodiments described herein, in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0005] [Figure 1] The image shows an exemplary top plan view of a device layout having a metal for an active PMOS transistor and a metal for a dummy NMOS transistor adjacent to a metal for an active PMOS transistor, according to several embodiments.

[0006] [Figure 2] The image shows a top plan view of a planned device having a row of NMOS metal sections adjacent to an active PMOS metal section, according to several embodiments, where both metal sections are located above the PMOS active region.

[0007] [Figure 3]The image shows a top plan view of a planned device layout in which, according to several embodiments, there is a cut between the row of NMOS metal sections and the row of active PMOS metal sections to suppress threshold voltage shift in the row of active transistors.

[0008] [Figure 4] The image shows a top plan view of a planned device layout in which, according to several embodiments, there are two rows of NMOS metal sections adjacent to an active PMOS metal section, and both types of metal sections are located above the PMOS active region.

[0009] [Figure 5] The image shows a top plan view of a planned device layout in which, according to several embodiments, there are three rows of NMOS metal sections adjacent to an active PMOS metal section, and both types of metal sections are located above the PMOS active region.

[0010] [Figure 6] The image shows a top plan view of a planned device layout, which has rows along the x-direction and alternating NMOS metal sections between adjacent active PMOS metal sections, according to several embodiments, with both types of metal sections above the PMOS active region.

[0011] [Figure 7] The image shows a top plan view of a planned device layout, according to several embodiments, having two columns of NMOS metal sections along the x-row and an adjacent active PMOS metal section, with both types of metal sections above the PMOS active region.

[0012] [Figure 8] This is a block diagram of one embodiment of an exemplary system.

[0013] The embodiments disclosed herein are open to various modifications and alternative forms, but specific embodiments are shown in the drawings and described in detail herein for illustrative purposes. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed in the claims. On the contrary, this application is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the disclosure of this application, as set forth in the appended claims. [Modes for carrying out the invention]

[0014] This disclosure relates to the implementation of a transistor device having an active region of a first transistor type, wherein the active transistor section in the device has a metal gate having a metal having a work function corresponding to the first transistor type, and the inactive (e.g., dummy) transistor section in the device has a metal gate having a metal having a work function corresponding to a second transistor type complementary to the first transistor type. The metal gates are implemented in a variety of devices, including CMOS (complementary metal oxide semiconductor) technology. The work function of the metal may be selected to set an appropriate threshold voltage for NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor) transistors in a particular CMOS device.

[0015] Typically, NMOS and PMOS transistors have metals with very different work functions for their gates. In some CMOS devices or logic circuits, NMOS and PMOS transistors have connected gates. For example, CMOS devices such as inverters, NAND, and NOR gates may have connected NMOS and PMOS metal gates. When the gates are connected, a merge location (e.g., a junction) exists between the metal of the NMOS gate and the metal of the PMOS gate. Differences in the chemical composition of these metals, and the exchange or movement of certain atoms or ions at the merge location, can result in an additional threshold voltage (Vt) shift for one or both NMOS and PMOS transistors. In various examples, the cause of the threshold voltage shift is referred to as the metal boundary effect.

[0016] In some embodiments of circuit or device designs, it is desirable to add (e.g., induce) an additional threshold voltage shift caused by a metal boundary effect to generate a desired threshold voltage characteristic within the device. A current method for inducing an additional threshold voltage shift is to include a metal for a dummy NMOS (or alternatively, PMOS) device next to a metal for a complementary active PMOS (or NMOS) device (e.g., a device under test (DUT)). Figure 1 shows a top plan view of an exemplary device layout having a metal for a dummy NMOS transistor adjacent to a metal for an active PMOS transistor, according to some embodiments. In the illustrated embodiment, the device layout 100 includes three gate structures 110A-C oriented orthogonally to six active region rows 120A-F.

[0017] In various embodiments, active region rows 120A-F include an active region (e.g., an epitaxy region including channel and source / drain regions) for either a first transistor type (e.g., a PMOS or p-type active region) or a second transistor type (e.g., an NMOS or n-type active region). In exemplary embodiments, active region rows 120A / B / E / F are rows having the first transistor type active region 130A / B / E / F, and active region rows 120C / D are rows having the second transistor type active region 135C / D. For example, as shown in Figure 1, the first transistor type active region 130A / B / E / F may be a PMOS active region, and the second transistor type active region 135C / D may be an NMOS active region. Due to the difference in active region types, active region rows 120A / B / E / F have separate source / drain regions from active region rows 120C / D.

[0018] For different transistor types within the active region rows 120A-F, the gate structure 110 may be a metal wire having different work function (WF) metal sections along their lengths corresponding to the active regions of different transistor types. For example, in the illustrated embodiment, the metal wire 110A / B / C includes a first metal section 140A / B / C of a first WF metal type and a second metal section 150A / B / C of a second WF metal type. The first metal section 140A / B / C may be a metal section having a WF corresponding to a PMOS transistor (e.g., a PMOS WF metal section) because the first metal section intersects with the active region 130A / B / E / F of the first transistor type within the active region rows 120A / B / E / F. Correspondingly, the second metal section 150A / B / C may be a metal section having a WF corresponding to an NMOS transistor (e.g., an NMOS WF metal section), since the second metal section intersects with the second transistor-type active region 135C / D in the active region row 120C / D.

[0019] In the illustrated embodiment, device layout 100 is for an active PMOS transistor device. Therefore, the first transistor-type active regions 130A / B / E / F within active region rows 120A / B / E / F form the active (e.g., device under test (DUT)) transistors for device layout 100, and the second transistor-type active regions 135C / D within active region rows 120C / D are "inactive" or "dummy" transistors in the device layout. Placing the dummy NMOS transistors near (e.g., adjacent to) the active PMOS transistors generates a threshold voltage shift in the active PMOS transistors. The selection of a WF (water flow factor) in the metal section (e.g., second metal section 150) within the dummy NMOS transistors can generate a desired threshold voltage shift in the adjacent active PMOS transistors. It should be noted that alternative device layouts having active NMOS transistors and dummy PMOS transistors, as well as corresponding WF metal sections, may also be considered.

[0020] However, arranging a dummy NMOS transistor having an NMOS WF metal section adjacent to (or between) an active PMOS transistor having a PMOS WF metal section comes at the cost of increased usage of circuit or device area. For example, due to process constraints in current circuit / device designs, the minimum number of rows of dummy NMOS (or PMOS) transistors is at least two. Two rows may be the minimum number of rows. This is because the epitaxy of the second transistor type active regions 135C / D in the active region rows 120C / D is different from the epitaxy of the first transistor type active regions 130A / B / E / F in the active region rows 120A / B / E / F, which typically requires a distinction of two rows to switch between different epitaxies. Therefore, as seen in FIG. 1, the device layout 100 includes two rows of dummy NMOS transistors to induce work function threshold voltage shifts in the PMOS transistors above / below the two dummy transistor rows.

[0021] To overcome the area cost of current designs such as the device layout 100 shown in FIG. 1, the present disclosure describes various contemplated device layout (e.g., circuit) designs that leverage metal boundary effects through a single-row-only implementation for dummy MOS "devices" inserted into the layout. In various embodiments, a single row of dummy MOS devices is formed by placing a metal section having a complementary WF functional metal over active regions of the same epitaxy as the active devices in the device layout (e.g., active regions of the same transistor type and common source / drain regions). Device layouts having these single-row dummy MOS devices have the advantage of inducing the same work function threshold voltage shift as current designs, while having more efficient utilization of device area.

[0022] Certain embodiments disclosed herein have four broad elements, namely: 1) multiple active regions of a first type of transistor oriented in rows along a first direction of the horizontal dimension; 2) a gate structure formed above a substrate oriented in a second direction orthogonal to the first direction of the horizontal dimension; 3) a first section of a first metal gate material having a first work function above the first active region of the first row of the first type of transistor; and 4) a second section of a second metal gate material having a second work function above the second active region of the second row of the first type of transistor. In various embodiments, the second metal gate material is adjacent to (e.g., neighboring) the first metal gate material, and as a result, the second metal gate material induces a threshold voltage shift in the active transistor associated with the first metal gate material based on differences in the chemical composition between these metals and the exchange or movement of specific atoms or ions at the merge location. In certain embodiments, the source / drain in the second active region is electrically floating, making the second active region inactive or a dummy transistor. In some embodiments, a third section of a first metal gate material having a first work function lies above a third active region in a third row of a first type of transistor, and a second row lies between the first and third rows. In some embodiments, a cut (e.g., a metal cut or gate cut) may be implemented between the first metal gate material in the first section and the second metal gate material in the third section to suppress a threshold voltage shift in the active transistor associated with the first metal gate material above the third active region.

[0023] Various examples of embodiments having these broad elements are described herein in the present disclosure. It should be noted that the illustrated embodiments of the present disclosure show a design layout of a device having a PMOS active region and a corresponding PMOS active transistor, and an NMOS work function metal induces a threshold voltage shift in some of the PMOS active transistors. These design layouts provide basic building blocks from which many different types of devices can be constructed based on the design layouts. In addition, embodiments may be contemplated based on the illustrated design layout having an NMOS active region and a corresponding NMOS active transistor, where a PMOS work function metal induces a threshold voltage shift in some of the NMOS active transistors.

[0024] Figure 2 shows a top plan view of a contemplated device having a row of NMOS metal sections adjacent to active PMOS metal sections, both metal sections overlying a PMOS active region, in accordance with some embodiments. In the illustrated embodiment, the device layout 200 includes three gate structures 210A to C oriented in a first direction of the horizontal dimension, and six active region rows 220A to F oriented in a second direction of the horizontal dimension, where the second direction is orthogonal to the first direction. In various embodiments, the active region rows 220A to F include first transistor type active regions 230A to F, and each active region is of the same first transistor type (e.g., a PMOS transistor). For example, the first transistor type active regions 230A to F include channels and source / drain regions (e.g., epitaxial regions) for PMOS transistors. All of the active region rows 220A to F are transistors of the same type, and they may use the same epitaxy to have a common type of source / drain region between the rows.

[0025] In certain embodiments, the gate structures 210A to C each have first metal sections 240A to C and second metal sections 250A to C, respectively. The first metal sections 240A to C may be metal sections having work functions corresponding to the transistors of the first transistor-type active regions 230A to F. For example, the first metal sections 240A to C may be metal sections having work functions corresponding to the PMOS transistors of the first transistor-type active regions 230A to F.

[0026] In certain embodiments, a "dummy" (e.g., inactive) device is formed within the device layout 200 by arranging second metal sections 250A-C along gate structures 210A-C. The second metal sections 250A-C may be sections of metal having work functions corresponding to complementary transistor types to the transistor types of the first transistor-type active regions 230A-F. For example, in the illustrated embodiment, the second metal sections 250A-C may be metal sections having work functions corresponding to NMOS transistors when the first transistor-type active regions 230A-F are epitaxy regions for PMOS transistors. Once the second metal sections 250A-C are arranged along gate structures 210A-C, a dummy device 260 is formed within the device layout 200.

[0027] As shown in Figure 2, the dummy device 260 includes a second metal section 250A-C above the first transistor-type active region 230C (dotted line) in the active region row 220C. Having the second metal section 250A-C above the first transistor-type active region 230C makes it possible to form the dummy device 260 within the device layout 200 while maintaining the same epitaxy (e.g., having the same type of source / drain region) between the active region 230C and other first transistor-type active regions 230A / B / D / E / F in the device layout (e.g., active regions that are part of an active transistor (DUT)). For example, the active region 230C may have the same type of source / drain region and a common well as the other active regions 230A / B / D / E / F. Therefore, the dummy device 260 is formed within the device layout 200 without creating additional rows of different epitaxy (for example, an NMOS epitaxy is not required in addition to the PMOS epitaxy in the device layout).

[0028] In certain embodiments, the second metal sections 250A-C are selected for the dummy device 260 such that the dummy device has a sufficiently high threshold voltage so that it has little to no function within the device layout 200. At a sufficiently high threshold voltage, the source / drain regions within the first transistor-type active region 230C may remain electrically floating (e.g., the source / drain regions are disconnected from any power source or power ground associated with the device layout 200). Having such electrically floating source / drain regions within the device layout 200 makes it possible to use a single masking process for all first-type transistor (e.g., PMOS transistor) structures until the process of introducing the second metal sections 250A-C is reached. This process, which uses the same epitaxy across the active region, avoids the need for additional masking processes associated with different epitaxies.

[0029] Several embodiments may be contemplated in which the source / drain region within the first transistor-type active region 230C is connected to other functional components in the device layout 200 (e.g., power / ground connections or other devices). For example, in embodiments where there is little or no side effect or harm to other transistors in the device layout 200, such as an active transistor in active region row 220B or active region row 220D, the source / drain region within the first transistor-type active region 230C may be connected to other source / drain regions of an active transistor.

[0030] In certain embodiments, as shown in Figure 2, the dummy device 260 includes second metal sections 250A-C having a work function complementary (e.g., counter) to the work function of the first metal sections 240A-C. Therefore, if the second metal sections 250A-C are adjacent (e.g., adjacent) and in contact with the first metal sections 240A-C, the second metal sections induce threshold voltage shifts in adjacent active transistors associated with the first metal sections (e.g., transistors associated with the first transistor-type active regions 230B and 230D located above and below the dummy device 260). It should be noted that certain threshold voltage shifts may also be induced in active transistors at greater distances. For example, the first transistor-type active regions 230A, 230E, and 230F may experience some threshold voltage shift depending on the difference in chemical composition between the first and second metals, and the amount of atomic or ion exchange or migration at the merge location between the second metal sections 250A-C and the first metal sections 240A-C.

[0031] In various embodiments, the work function of the second metal sections 250A-C is selected to provide a desired threshold voltage shift in the active transistor of the device layout 200. Thus, the device layout 200 allows a single row (e.g., a row of dummy devices 260) to provide the desired threshold voltage shift in the active portion of the device. Causing the threshold voltage shift with only a single row of dummy / inactive devices saves the use of device area across the vertical height (e.g., along the direction of the gate structure 210) in the device layout 200.

[0032] In some embodiments, the device layout can be designed such that it is desirable that several active transistors adjacent to the dummy device 260 do not have threshold voltage shifts. In such embodiments, cuts or other severances in the metal wires of the gate structure 210 may be made to prevent atomic or ion exchange or migration between the second metal section 250 in the dummy device 260 and the first metal section associated with the active transistors for which threshold voltage shifts are undesirable.

[0033] Figure 3 shows a top plan view of a planned device layout having a cut between rows of NMOS metal sections and active PMOS metal sections to suppress threshold voltage shift in rows of active transistors, according to several embodiments. In the illustrated embodiments, device layout 200 (from Figure 2) is modified to device layout 300 by placing a cut 310 in the gate structure 210A / B / C below a dummy device 260 and between the first metal section 240A / B / C and the second metal section 250A / B / C. The cut 310 may be formed, for example, by forming a trench in the gate structure 210A / B / C along the line of the cut below the dummy device 260. The cut 310 suppresses atomic or ion exchange or migration between the first metal section 240A / B / C and the second metal section 250A / B / C. By suppressing atomic or ion exchange or movement between these metal sections, there is no threshold voltage shift in the active transistor 320 (or other active transistors along the active region row 220D) caused by the presence of gate structures 210A / B / C in the dummy device 260. In some embodiments, the cut 310 may be located at the boundary of a cell or device / transistor set in the device layout 300.

[0034] In some embodiments, a second row of NMOS metal sections may be placed within a device layout having active PMOS transistors to increase the number of active transistors with threshold voltage shifts in the device layout. Figure 4 shows a top plan view of a planned device layout, according to some embodiments, having two rows of NMOS metal sections adjacent to an active PMOS metal section, with both types of metal sections above the PMOS active region. In the illustrated embodiment, device layout 200 (from Figure 2) is modified to device layout 400 by placing a second set of second metal sections 250A' / B' / C' in the active region row 220F instead of the PMOS metal section (e.g., the first metal section 240). Thus, device layout 400 includes two dummy devices, namely dummy device 260A in the active region row 220C and dummy device 260B in the active region row 220F.

[0035] Having a second metal section 250 and dummy devices 260 in two rows of the device layout 400 increases the number of active transistors with threshold voltage shifts in the device layout. For example, in the illustrated embodiment, dummy device 260A induces a threshold voltage shift in the active transistors of the first transistor-type active region 230B and the first transistor-type active region 230D, while dummy device 260B induces a threshold voltage shift in the active transistors of the first transistor-type active region 230E. Note that dummy device 260B also induces a threshold voltage shift in the active transistors of another first transistor-type active region below active region row 220F, unless the dummy device is located at the boundary of the device layout 400.

[0036] In embodiments of device layout 400, the area cost of the device layout is similar to that of device layout 100 shown in Figure 1. For example, both device layouts have an area cost of two rows for the losses of active transistors within the device layout. However, device layout 400 may have other advantages over device layout 100. For example, as described above, device layout 400 maintains a single type of epitaxial process for the implementation of all active region rows across the device layout. Furthermore, device layout 400 can have 2x active transistors have the same amount of threshold voltage effect (e.g., threshold voltage shift) as device layout 100, at the same area cost.

[0037] Figure 5 shows a top plan view of a planned device layout, according to several embodiments, having three rows of NMOS metal sections adjacent to an active PMOS metal section, with both types of metal sections above the PMOS active region. In the illustrated embodiment, device layout 200 (from Figure 2) is modified to device layout 500 by placing a second set 250A' / B' / C' of the second metal section in the active region row 220A and a third set 250A'' / B'' / C'' of the second metal section in the active region row 220E, instead of the PMOS metal section (e.g., the first metal section 240). Thus, device layout 500 includes three dummy devices, namely dummy device 260A in the active region row 220C, dummy device 260B in the active region row 220A, and dummy device 260C in the active region row 220E.

[0038] As shown in Figure 5, dummy rows (e.g., active-region rows 220A / 220C / 220E) are arranged alternately with active rows (e.g., active-region rows 220B / D / F), with each active row having one dummy row above it and another dummy row below it in the figure. When each active row has dummy rows directly above and below it, the threshold voltage shift of the active row is greater than when an active row has only one dummy row either above or below it.

[0039] Therefore, device layouts may be designed using a second metal section (e.g., a metal section with a work function corresponding to a complementary transistor type to an active transistor) based on the use of a single row of the second metal section to generate a desired threshold voltage shift with less area cost, or two (or more) rows of the second metal section to improve other operating characteristics of the device along with the desired threshold voltage shift. Designs for larger device layouts may also be considered, where combinations of a single row and two (or more) rows of the second metal section are placed in different areas of the device layout to obtain the advantages of both variants.

[0040] Embodiments in which different effects in threshold voltage shift are induced may also be considered. For example, in some embodiments, the second metal section may include a metal that increases the threshold voltage of adjacent active transistors. In other embodiments, the second metal section may include a metal that decreases the threshold voltage of adjacent active transistors. Yet another embodiment may include a device layout design having some sections that increase the threshold voltage of adjacent active transistors and some sections that decrease the threshold voltage of adjacent active transistors.

[0041] Additional embodiments may be contemplated in which the second metal section 250 (e.g., a metal section having a work function corresponding to a complementary transistor type to the active transistor) is constrained horizontally within the device layout (e.g., horizontally or x-direction of the device layout as shown in the figure). The position of the second metal section in the x-direction may also be changed between rows of the active region to provide a variant in which the active transistor has a threshold voltage shift in the y-direction. Figures 6 and 7 show several possible variants of the arrangement of the second metal section in the x-direction (along the column associated with the gate structure 210) and the y-direction (along the row associated with the active region row 220) for generating a selective threshold voltage shift in adjacent active transistors based on columns, rows, or combinations thereof.

[0042] Figure 6 shows a top plan view of a planned device layout, according to several embodiments, having rows along the x-direction and alternating NMOS metal sections between adjacent active PMOS metal sections, with both types of metal sections above the PMOS active region. In the illustrated embodiment, the device layout 600 includes a second metal section 650A within an active region row 220C along the gate structure 210A, a second metal section 650B within an active region row 220B along the gate structure 210B, and a second metal section 650C within an active region row 220C along the gate structure 210C. Thus, as shown in Figure 6, the second metal sections 650A / B / C, alternating rows in the x-direction (for example, alternating rows between columns of the gate structure 210 horizontally), form three distinct dummy devices, namely dummy device 660A, dummy device 660B, and dummy device 660C.

[0043] In these arrangements of the second metal sections 650A / B / C, the locations of dummy devices 660A, 660B, and 660C alternate between rows and columns in the device layout 600. The alternating positions of dummy devices 660A and 660B also alternate between rows and columns in the device layout 600, resulting in active transistors having induced threshold voltage shifts. For example, along gate structure 210A (e.g., "column A"), dummy device 660A in active region row 220C induces threshold voltage shifts in active transistors 610B-A in active region row 220B above the dummy device, and in active transistors 610D-A in active region row 220D below the dummy device. Next, along gate structure 210B (e.g., "column B"), dummy device 660B in active region row 220B induces threshold voltage shifts in active transistors 610A-B in active region row 220A above the dummy device, and in active transistors 610C-B in active region row 220C below the dummy device. Along gate structure 210C (e.g., "column C"), dummy device 660C in active region row 220C (same row as dummy device 660A) induces threshold voltage shifts in active transistors 610B-C in active region row 220B above the dummy device, and in active transistors 610D-C in active region row 220D below the dummy device. Thus, active transistors with threshold voltage shifts are alternated between rows in different columns within the device layout 600. It should be further noted that metal sections 650A / B / C may be made of the same metal, or different embodiments may be intended for each of the metal sections and dummy devices, with different metals (and corresponding threshold voltage shifts).

[0044] Embodiments may also be contemplated in which the second metal section 650 is arranged horizontally across two columns for a single dummy device, but not in a third column. Figure 7 shows a top plan view of a contemplated device layout, according to several embodiments, having two columns of NMOS metal sections along a row in the x-direction and an adjacent active PMOS metal section, with both types of metal sections above the PMOS active region. In the illustrated embodiment, the device layout 700 includes dummy devices 660A / B / C from device layout 600 (shown in Figure 6). The device layout 700 further includes a second metal section 650D along gate structure 210A and a second metal section 650E along gate structure 210B in active region row 220F. The second metal sections 650D / E are located in two columns (e.g., "column A" and "column B") in the same row as the first metal section 240C in a third column (e.g., "column C"). The second metal section 650D / E together forms dummy device 760. Thus, the device layout 600 includes four distinct dummy devices, namely dummy device 660A, dummy device 660B, dummy device 660C, and dummy device 760, where dummy devices 660A / B / C are single-row dummy devices and dummy device 760 is a double-row dummy device.

[0045] If the dummy device 760 is a dummy device in two columns, the dummy device induces a threshold voltage shift in the active transistors along the same two columns. For example, in the illustrated embodiment, the dummy device 760 induces a threshold voltage shift in both active transistors 610E-A and 610E-B within the active region row 220E. It should be noted that the dummy device 760 also induces a threshold voltage shift in the active transistors of another first transistor-type active region below the active region row 220F, unless the dummy device is located at the boundary of the device layout 700. It should be further noted that the device layouts in Figures 6 and 7 are provided only as examples, and a variety of additional device layouts may be contemplated without departing from the scope of this disclosure and the appended claims. For example, only a single active region row may include a second metal section 650 constrained in the x direction (for example, the device layout may include only the second metal sections 650A, 650C within the active region row 220C). Exemplary computer system

[0046] Referring next to Figure 8, a block diagram of one embodiment of system 800 is shown, which can incorporate and / or utilize the methods and mechanisms described herein. In the illustrated embodiment, system 800 includes at least one instance of system on chip (SoC) 806, which may include multiple types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other methods, a communication fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors within the SoC 806 include multiple execution lanes and instruction issue queues. In various embodiments, the SoC 806 is coupled to external memory 802, peripherals 804, and a power supply 808.

[0047] A power supply 808 is also provided, which supplies a supply voltage to the SoC 806 and one or more supply voltages to the memory 802 and / or peripheral devices 804. In various embodiments, the power supply 808 represents a battery (e.g., a rechargeable battery for a smartphone, laptop or tablet computer, or other device). In some embodiments, two or more instances of the SoC 806 are included (and two or more external memories 802 are also included).

[0048] Memory 802 is any type of memory, including dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3 and / or low-power versions such as LPDDR2), Rambus DRAM (RDRAM), and static RAM (SRAM). One or more memory devices are coupled to a circuit board to form memory modules such as single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). Alternatively, the devices are mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0049] The peripheral device 804 includes any desired circuitry depending on the type of system 800. For example, in one embodiment, the peripheral device 804 includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, and global positioning systems. In some embodiments, the peripheral device 804 also includes additional storage, such as RAM storage, solid-state storage, or disk storage. The peripheral device 804 includes user interface devices such as a display screen, including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker.

[0050] As illustrated, system 800 is shown to be applicable to a wide area. For example, system 800 may be used as part of the chips, circuits, components, etc. of a desktop computer 810, a laptop computer 820, a tablet computer 830, a cellular or mobile phone 840, or a television 850 (or a set-top box coupled to a television). A smartwatch and a health monitoring device 860 are also illustrated. In some embodiments, the smartwatch may include a variety of general-purpose computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any of the health monitoring-related functions. Other wearable devices, such as devices worn around the neck, implantable devices in the human body, and glasses designed to provide augmented and / or virtual reality experiences, are also intended.

[0051] System 800 may be further used as part of a cloud-based service(s) 870. For example, the aforementioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 800 may be used in one or more devices of a home 880 other than those described above. For example, appliances in a home may monitor and detect conditions of note. For example, various devices in a home (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and alert the homeowner (or repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in the home and automate the adjustment of the heating / cooling system based on the homeowner's response history to various conditions. Figure 8 also shows the application of System 800 to various modes of transport 890. For example, System 800 may be used in control and / or entertainment systems for aircraft, trains, buses, rental cars, private cars, ships ranging from privately owned boats to cruise ships, and scooters (rented or owned). In various cases, System 800 may be used to provide automatic guidance (e.g., autonomous vehicles), general system control, and other methods. Many other embodiments of these are possible and contemplated. Note that the devices and applications shown in Figure 8 are illustrative and not intended to be limiting. Other devices are possible and contemplated. ***

[0052] This disclosure includes references to “one embodiment” or a group of “embodiments” (e.g., “several embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concept. References to “one embodiment,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, and modifications or substitutions within the spirit or scope of this disclosure are intended.

[0053] This disclosure may discuss the potential benefits that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily demonstrate any or all of the potential benefits. Whether a benefit is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the claims may not exhibit some or all of any disclosed benefits. For example, a particular implementation may include other circuits outside the scope of this disclosure that, together with one of the disclosed embodiments, negate or reduce one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation technique or tool) may also negate or reduce the disclosed benefits. Even assuming skilled execution, the realization of benefits may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, the inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on certain occasions, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations on claims that must be satisfied to demonstrate infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvements available to designers who have an interest in this disclosure. The acceptable description of such benefits (e.g., the statement that a particular benefit "may occur") is not intended to convey any doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0054] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single embodiment describes a particular feature, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure. The disclosed embodiments are intended to be illustrative, not limiting, unless there is a statement to the contrary in this disclosure. The foregoing is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that would be obvious to a person skilled in the art who would benefit from this disclosure.

[0055] For example, the features of this application can be combined in any preferred manner. Therefore, new claims can be formulated for any such combination of features during the examination of this application (or an application claiming priority to this application). In particular, referring to the attached claims, features from dependent claims can be combined with features from other dependent claims, including claims dependent on other independent claims, as appropriate. Similarly, features from each independent claim can be combined as appropriate.

[0056] Accordingly, each of the attached dependent claims may be constructed to depend on a single other claim, but additional dependencies are also contemplated. Any combination of features in the dependent claims that are consistent with the present disclosure is contemplated and may be claimed in this application or another application. In summary, the combinations are not limited to those specifically enumerated in the attached claims.

[0057] Where appropriate, claims prepared in one format or legal type (e.g., apparatus) are intended to also support corresponding claims in another format or legal type (e.g., method). ***

[0058] As this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, and the definitions provided through this disclosure, are hereby publicly noted as being used in interpreting the claims made pursuant to this disclosure.

[0059] References to singular items (i.e., nouns or noun phrases preceded by "a," "an," or "the") are intended to mean "one or more" unless explicitly stated in the context. Therefore, references to "items" in the claims do not, without context, preclude additional instances of an item. "Multiple" items refer to a set of two or more items.

[0060] In this specification, the word "may" is used in an allowable sense (i.e., possible, feasible) and not in an obligatory sense (i.e., not required).

[0061] The terms and forms "comprising" and "including" are open-ended and mean "to include, but not to limit."

[0062] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless otherwise explicitly stated in the context. Thus, the enumeration of “x or y” is equivalent to “x or y, or both,” and therefore includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase “either x or y, but not both” clarifies that “or” is used in an exclusive sense.

[0063] The enumerations "w, x, y, z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities, including single elements, up to the total number of elements in the set. For example, in the set [w, x, y, z], these expressions cover any single element in the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0064] In this disclosure, various “labels” may precede nouns or noun phrases. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different examples of the feature. Furthermore, when applied to features, the labels “first,” “second,” and “third” do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0065] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision; that is, the decision may be based on the specified factor alone, or on the specified factor plus other unspecified factors. Consider the phrase "determine A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover even one embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0066] The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not preclude the possibility that additional factors may influence, or otherwise trigger, the effect, either in conjunction with or independently of a specific factor. That is, the effect may depend on these factors alone, or on the specified factor and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase means that B is a factor that triggers the performance of A, or a specific outcome with respect to A. This phrase does not preclude the performance of A from also being in response to other factors, such as C. This phrase also does not preclude the performance of A from being in response to both B and C. This phrase is intended to include embodiments in which A is performed solely in response to B. As used herein, the phrase “in response to” is synonymous with the phrase “in response to at least partially.” Similarly, the phrase “in response to” is synonymous with the phrase “in at least partially.” ***

[0067] Within this disclosure, various entities (which may be referred to as “units,” “circuits,” or other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “configured to perform one or more tasks” is used herein to refer to structures (i.e., physical things). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when the structure is not currently in operation. Thus, entities described or explained as “configured” to perform some task refer to physical things such as devices, circuits, and systems having a processor unit and memory storing program instructions that can be executed to perform the task. This phrase is not used herein to refer to intangible things.

[0068] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. Even if not specifically stated, it is understood that those entities are "configured" to perform those tasks / operations.

[0069] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After proper programming, the FPGA can then be said to be "configured" to perform a particular function.

[0070] For the purposes of a U.S. patent application based on this disclosure, any claim that states a structure is “configured” to perform one or more tasks is not expressly intended to invoke Section 112(f) of the U.S. Patent Act with respect to that claim element. If an applicant wishes to invoke Section 112(f) during the examination process of a U.S. patent application based on this disclosure, it would use “means for” performing the function to describe the claim element.

[0071] This disclosure may describe various “circuits.” These circuits or “circuit configurations” constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), and programmable logic arrays. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuit configurations may include digital components, analog components, or a combination of both, as needed. Certain types of circuits may generally be referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), function units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit configurations.

[0072] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoder unit” may be described as performing the function of “processing the opcode of an instruction and routing the instruction to one or more of several functional units,” meaning that the decoder unit is “configured” to perform this function. The detail of this function is sufficient to imply to a person skilled in the art of computer technology a set of possible structures of the circuit.

[0073] In various embodiments, as described in the previous paragraph, circuits, units, and other elements defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to each other, and the way they interact, form the microarchitecture definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation form of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementation forms can be derived, and all of its implementation forms belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with the microarchitecture definition provided pursuant to this disclosure can implement the structure by coding the circuit / unit / component description in a hardware description language (HDL), such as Verilog or VHDL, using ordinary art without excessive experimentation. The HDL description is often expressed in a form that appears to be functional. However, to those skilled in the art, this HDL description is a method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions can take the form of operation-level code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, in contrast to operation-level code), or structure code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry, generating a mask, and ultimately manufacturing the integrated circuit. Some hardware circuits, or parts thereof, can also be custom-designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuits.An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected integrally to realize a hardware circuit, and / or, in some embodiments, separate elements may be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented on an FPGA. This decoupling between the design of this group of circuits and the subsequent low-level implementation of these circuits generally leads to scenarios where the circuit or logic designer does not specify any particular set of structures for low-level implementation forms other than a description of how the circuit is configured, because this process is performed at different stages of the circuit implementation process.

[0074] The fact that the same specifications of a circuit can be implemented using many different low-level combinations of circuit elements results in a multitude of equivalent structures for that circuit. As mentioned above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. Often, the choice made by different design tools or methods to generate these different implementation forms can be arbitrary.

[0075] Furthermore, in a given embodiment, a single implementation of a specific functional specification of a circuit typically involves a large number of devices (e.g., millions of transistors). Therefore, given this sheer volume of information, it is impractical to fully enumerate the low-level structures used to implement a single embodiment, let alone a vast number of equivalent possible implementations. For this reason, this disclosure describes the circuit structure using functional omissions commonly used in the industry.

Claims

1. An integrated circuit device, circuit board and A plurality of active regions for a first type of transistor formed in the substrate, wherein the active regions include a channel region and a source / drain region for the first type of transistor, and the plurality of active regions are oriented in rows along a first direction in the horizontal dimension with respect to the substrate, An integrated circuit device comprising: a gate structure formed above the substrate in a vertical dimension with respect to the substrate, wherein the gate structure is oriented in columns along a second direction in the horizontal dimension, the second direction being perpendicular to the first direction, and the gate structure is located above at least two rows of the active region in the vertical dimension, wherein the gate structure A first section of the gate structure located above a first active region of at least two rows of the active region in the vertical dimension, wherein the first section comprises a first metallic gate material, the first metallic gate material being associated with an active transistor of the first type of transistor and having a first work function, An integrated circuit device comprising: a second section of the gate structure located above a second active region of at least two rows of the active region in the vertical dimension, the second section comprising a second metal gate material, wherein the second metal gate material in the second section is adjacent to the first metal gate material in the first section, the second metal gate material has a second work function different from the first work function, and the second gate material in the second section adjacent to the first gate material in the first section induces a threshold voltage shift of the active transistor.

2. The device according to claim 1, wherein the first work function corresponds to the first type of transistor, the second work function corresponds to the second type of transistor, and the second type of transistor is complementary to the first type of transistor.

3. The device according to claim 1, wherein the rows of the active region are separated by the rows of the inactive region, and the inactive region provides electrical isolation between adjacent rows of the active region.

4. The gate structure is located above at least one additional row of the active region in the vertical dimension, and the gate structure is The device according to claim 1, wherein a third section of the gate structure is located above the at least one additional row of the active region in the vertical dimension, the third section comprising the first metal gate material, and the third section further comprising a third section adjacent to the second section on the opposite side of the first section in the second direction.

5. The device according to claim 4, wherein the first metal gate material in the third section is adjacent to the second metal gate material in the second section.

6. The device according to claim 5, wherein the first metal gate material in the third section is associated with an active transistor of the first type of transistor, and the second gate material in the second section adjacent to the first gate material in the third section induces a threshold voltage shift of the active transistor.

7. The aforementioned gate structure A fourth section of the gate structure located above the at least one additional row of the active region in the vertical dimension, wherein the fourth section comprises the second metal gate material, and the fourth section further comprises a fourth section adjacent to the third section on the opposite side of the second section in the second direction, The device according to claim 6, wherein both the second gate material in the second section and the second gate material in the fourth section are adjacent to the first gate material in the third section, thereby inducing a shift in the threshold voltage of the active transistor in the third section that is greater than the shift in the threshold voltage that would occur if the second gate material were present only in either the second section or the fourth section.

8. A second gate structure formed above the substrate in the vertical dimension, wherein the second gate structure is oriented in rows along the second direction in the horizontal dimension, the second gate structure is separated from the gate structure in the first direction, and the second gate structure is located above at least two rows of the active region in the vertical dimension, and the second gate structure is further comprising A first section of the second gate structure located above a third active region among at least two rows of the active region, wherein the first section includes the first metal gate material, The device according to claim 1, comprising: a second section of the second gate structure located above a fourth active region of at least two rows of the active region, the second section being adjacent to the first section in the second gate structure, and the second section comprising the second metal gate material.

9. The device according to claim 1, wherein the source / drain region within the second active region is electrically floating.

10. An integrated circuit device, circuit board and A plurality of active regions for a first type of transistor formed in the substrate, wherein the active regions include a channel region and a source / drain region for the first type of transistor, and the plurality of active regions are oriented in rows along a first direction in the horizontal dimension with respect to the substrate, An integrated circuit device comprising: a gate structure formed above the substrate in a vertical dimension with respect to the substrate, wherein the gate structure is oriented in columns along a second direction in the horizontal dimension, the second direction being perpendicular to the first direction, and the gate structure is located above at least two rows of the active region in the vertical dimension, wherein the gate structure A first section of the gate structure associated with the active transistor of the first type of transistor, wherein the first section is located above a first active region of at least two rows of the active region in the vertical dimension, and the first section includes a first metallic gate material having a first work function corresponding to the active transistor, An integrated circuit device comprising: a second section of the gate structure located above a second active region of at least two rows of the active region in the vertical dimension, the second section adjacent to the first section in the gate structure, the second section comprising a second metallic gate material, wherein the second metallic gate material has a second work function corresponding to a second type of transistor, the second type of transistor is complementary to the first type of transistor and the inactive transistor, and the second gate material in the second section adjacent to the first gate material in the first section induces a threshold voltage shift of the active transistor.

11. The device according to claim 10, wherein the first active region includes a p-type channel region and a source / drain region for the first type of transistor, and the second work function is an n-type work function.

12. The device according to claim 10, wherein the first active region includes an n-type channel region and a source / drain region for the first type of transistor, and the second work function is a p-type work function.

13. The gate structure is positioned above at least one additional row of the active region in the vertical dimension, and the gate structure is The device according to claim 10, wherein a third section of the gate structure is located above the at least one additional row of the active region in the vertical dimension, the third section comprises the first metal gate material, and the third section further comprises a third section adjacent to the second section on the opposite side of the first section in the second direction.

14. A second gate structure formed above the substrate in the vertical dimension, wherein the second gate structure is oriented in rows along the second direction in the horizontal dimension, the second gate structure is separated from the gate structure in the first direction, and the second gate structure is positioned above at least two rows of the active region in the vertical dimension, the second gate structure further comprises, A first section of the second gate structure located above a third active region among at least two rows of the active region, wherein the first section includes the first metal gate material, The device according to claim 10, further comprising: a second section of the second gate structure located above a fourth active region of at least two rows of the active region, the second section being adjacent to the first section in the second gate structure, and the second section comprising the second metal gate material.

15. The device according to claim 14, wherein the fourth active region is a part of the active region in the same row as the second active region, and the fourth active region is a part of the active region in the same row that is different from the second active region.

16. The device according to claim 14, wherein the fourth active region is located in a different row of the active region from the second active region.

17. The device according to claim 14, wherein the source / drain region within the second active region is electrically floating.

18. An integrated circuit device, circuit board and A plurality of active regions for a first type of transistor formed in the substrate, wherein the active regions include a channel region and a source / drain region for the first type of transistor, and the plurality of active regions are oriented in rows along a first direction in the horizontal dimension with respect to the substrate, An integrated circuit device comprising: a plurality of gate structures formed above the substrate in a vertical dimension with respect to the substrate, wherein the gate structures are oriented in columns along a second direction in the horizontal dimension, the second direction being perpendicular to the first direction, and the gate structures are positioned above two or more rows of the active region in the vertical dimension; The first gate structure is A first section of the first gate structure located above a first active region among two or more rows of the active region in the vertical dimension, wherein the first section is a first metal gate material, and the first metal gate material includes a first metal gate material having a first work function corresponding to the first type of transistor, A second section of the first gate structure located above a second active region of two or more rows of the active region in the vertical dimension, the second section comprising a second metallic gate material adjacent to the first section in the first gate structure, the second section comprising a second metallic gate material having a second work function which is a counter-type work function for the first type of transistor, The second gate structure is A first section of the second gate structure located above a third active region among two or more rows of the active region in the vertical dimension, wherein the first section includes the first metal gate material, An integrated circuit device comprising: a second section of the second gate structure located above a fourth active region of the two or more active regions in the vertical dimension, wherein the second section is adjacent to the first section in the second gate structure, and the second section includes the second metal gate material.

19. The device according to claim 18, wherein the third active region is a part of the active region in the same row as the first active region, the third active region is a part of the active region in the same row as the first active region, the fourth active region is a part of the active region in the same row as the second active region, and the fourth active region is a part of the active region in the same row as the second active region.

20. The first gate structure described above is A third section of the first gate structure located above at least a seventh active region among two or more rows of the active region in the vertical dimension, wherein the third section comprises the first metal gate material, and the third section is adjacent to the second section on the opposite side of the second section from the first section in the second direction, The device according to claim 18, further comprising: a fourth section of the first gate structure located above an eighth active region of two or more rows of the active region in the vertical dimension, wherein the fourth section comprises the second metal gate material, and the fourth section is adjacent to the third section on the opposite side of the second section in the second direction.

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