Array substrate and display panel

Abstract

The present invention relates to an array substrate and a display panel. The array substrate comprises a base and a drive circuit layer located on the base, the drive circuit layer is provided with a pixel circuit and a light emission control line, the pixel circuit comprises a drive transistor, a first initialization transistor and a first connection part, the first connection part is connected between the first pole of the drive transistor and the first initialization transistor, the orthographic projection of the first connection part and the light emission control line on the base has an overlapping portion, the orthographic projection of the shield part provided on the drive circuit layer on the base overlaps with the overlapping portion, the film layer on which the shield part is located is located between the film layer on which the light emission control line is located and the film layer on which the first connection part is located, and / or at least one organic insulating layer is provided between the film layer on which the first connection part is located and the film layer on which the light emission control line is located, and / or the thickness of the insulating layer between the film layer on which the first connection part is located and the film layer on which the light emission control line is located is greater than 3 μm.

Description

TECHNICAL FIELD

[0001] This application claims priority to the Chinese patent application with application number 202311222580.4 filed with the China National Intellectual Property Administration on September 20, 2023, the entire contents of which are incorporated herein by reference in their entirety.

[0002] The present application relates to the field of display technology, for example, to an array substrate and a display panel. BACKGROUND ART

[0003] With the rapid development of display technology, the application of display products based on Organic Light Emitting Display (OLED) is becoming increasingly widespread.

[0004] However, the display uniformity of OLED display panels still needs to be improved. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] The present application provides an array substrate and a display panel for improving the display uniformity of the display panel. MEANS FOR SOLVING THE PROBLEMS

[0006] Embodiments of the present application The device comprises a base and a drive circuit layer located at the base, the drive circuit layer is provided with a pixel circuit and a light emission control line, the pixel circuit comprises a drive transistor, a first initialization transistor and a first connection part, the first connection part is connected between the first pole of the drive transistor and the first initialization transistor, the orthographic projection of the first connection part and the light emission control line at the base has an overlapping portion, the drive circuit layer is further provided with a shielding portion, the orthographic projection of the shielding portion at the base overlaps with the overlapping portion, the film layer where the shielding portion is located is located between the film layer where the light emission control line is located and the film layer where the first connection part is located, and / or, at least one organic insulating layer is provided between the film layer where the first connection part is located and the film layer where the light emission control line is located, and / or, the thickness of the insulating layer between the film layer where the first connection part is located and the film layer where the light emission control line is located is greater than 3 μm. We provide array substrates.

[0007] The embodiments of this application are as follows: The array substrate comprises any embodiment of the present application, Provides a display panel. [Effects of the Invention]

[0008] In the technical solution of the embodiment of the present application, by providing a shield portion, the orthographic projection of the base of the shield portion overlaps with the overlapping portion, and the film layer on which the shield portion is located is positioned between the film layer on which the light emission control line is located and the film layer on which the first connection portion is located. As a result, the shield portion forms a shielding effect against the signal transmitted by the light emission control line, eliminating or reducing the degree of coupling (e.g., the degree of potential reduction) between the parasitic capacitance generated in the overlapping portion between the light emission control line and the first connection portion and the first pole potential of the drive transistor. This also reduces the difference in coupling between the parasitic capacitance and the first pole potential of the drive transistor in pixel circuits at different locations, making the degree of influence of parasitic capacitance on the drive current of pixel circuits at different locations the same or similar. Furthermore, the display brightness of light-emitting elements at different locations tends to match at the same grayscale, which is advantageous in improving the display uniformity of the display panel and enhancing the display effect of the display panel. By providing at least one organic insulating layer between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located, the direct facing distance between the light emission control signal line and the first connection portion is increased, the dielectric constant of the parasitic capacitance in the overlapping portion is reduced, the parasitic capacitance is reduced, and the influence of parasitic capacitance on the light emission brightness of the light-emitting element is further reduced, which is advantageous in improving the display effect of the display panel. By making the thickness of the insulating layer between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located greater than 3 μm, the direct facing distance between the light emission control signal line and the first connection portion is increased, the parasitic capacitance is reduced, and the influence of parasitic capacitance on the light emission brightness of the light-emitting element is further reduced, which is advantageous in improving the display effect of the display panel. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic diagram of the circuit structure of a pixel circuit in related technologies. [Figure 2] This is a timing chart of the pixel circuit in related technologies. [Figure 3] This is a schematic diagram of the pixel circuit layout structure in related technologies. [Figure 4] This is a schematic diagram of the layout structure of an array substrate according to an embodiment of the present invention. [Figure 5]This is a cross-sectional view along the a0-a0' direction in Figure 4. [Figure 6] This is a schematic diagram of the circuit structure of a pixel circuit according to an embodiment of the present invention. [Figure 7] This is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention. [Figure 8] This is a cross-sectional view along the a1-a2 direction in Figure 7. [Figure 9] This is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention. [Figure 10] This is a cross-sectional view along the b1-b2 direction in Figure 4. [Figure 11] This is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention. [Figure 12] This is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention. [Figure 13] This is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention. [Figure 14] This is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention. [Figure 15] This is a cross-sectional view along the f1-f2 direction in Figure 14. [Figure 16] This is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention. [Figure 17] This is a further cross-sectional view along the a1-a2 direction in Figure 7. [Figure 18] This is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention. [Figure 19] This is a cross-sectional view along the k1-k2 direction in Figure 18. [Figure 20] This is a schematic diagram of the layout structure of the first conductive layer and the second active layer of the array substrate according to an embodiment of the present application. [Figure 21] This is a schematic diagram of the layout structure of the second conductive layer of an array substrate according to an embodiment of the present application. [Figure 22] This is a schematic diagram of the layout structure of the third conductive layer and the first active layer of the array substrate according to an embodiment of the present application. [Figure 23]This is a schematic diagram of the layout structure of the fourth conductive layer of the array substrate according to the embodiments of the present application. [Figure 24] This is a schematic diagram of the layout structure of a further fourth conductive layer of the array substrate according to the embodiments of the present application. [Figure 25] This is a schematic diagram of the layout structure of the fifth conductive layer of the array substrate according to the embodiments of the present application. [Figure 26] This is a schematic diagram of the layout structure of the sixth conductive layer of the array substrate according to the embodiments of the present application. [Figure 27] This is a schematic diagram of the layout structure of the shield layer of the array substrate according to the embodiments of the present application. [Figure 28] This is a schematic diagram of the layout structure of a further array substrate according to the embodiments of the present application. [Figure 29] This is a schematic diagram of the layout structure of a further array substrate according to the embodiments of the present application. [Figure 30] This is a schematic diagram of the layout structure of a further array substrate according to the embodiments of the present application. [Figure 31] This is a schematic diagram of the circuit structure of a further pixel circuit according to the embodiments of the present application. [Figure 32] This is a schematic diagram of the layout structure of a further array substrate according to the embodiments of the present application. [Figure 33] This is a schematic structural diagram of the display panel according to the embodiments of the present application. DESCRIPTION OF EMBODIMENTS

[0010] Furthermore, terms such as “First,” “Second,” etc., in the specification, claims, and drawings of this application are for distinguishing similar subjects and are not required to describe a specific order or priority. It should be understood that the data used in this manner may be interchangeable in appropriate circumstances so that the embodiments of this application described herein may be carried out in an order other than that illustrated or described herein. Also, the terms “includes,” “has,” and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or apparatus that includes a series of steps or units does not have to be limited to the steps or units explicitly described, and may include other steps or units that are not explicitly described or are specific to these processes, methods, products, or apparatus.

[0011] Figure 1 is a schematic diagram of the circuit structure of a pixel circuit in the related technology. As shown in Figure 1, the pixel circuit comprises a first transistor T1', a second transistor T2', a third transistor T3', a fourth transistor T4', a fifth transistor T5', a sixth transistor T6', a seventh transistor T7', an eighth transistor T8', and a first capacitor C1. Figure 2 is a timing chart of the pixel circuit in the related technology. As shown in Figure 2, the driving process of the pixel circuit includes an initialization stage t1, a threshold compensation and data writing stage t2, and an illumination stage t3. In initialization stage t1, the second scan signal S2 on the second scan line Scan2 is low level, and the second scan signal S2 controls the seventh transistor T7' and the eighth transistor T8' to turn on; the third scan signal S3 on the third scan line Scan3 is high level, and the third scan signal S3 controls the fourth transistor T4' to turn on; the eighth transistor T8' transmits the first reset signal transmitted on the first reset signal line Vr1 to the source of the first transistor T1', resetting the source of the first transistor T1'; the seventh transistor T7' transmits the second reset signal transmitted on the second reset signal line Vr2 to the anode of the light-emitting diode D1, resetting the anode of the light-emitting diode D1; and the fourth transistor T4' transmits the third reset signal transmitted on the third reset signal line Vr3 to the gate of the first transistor T1', resetting the gate of the first transistor T1'. In the threshold compensation and data writing stage t2, the first scan signal S1 on the first scan line Scan1 is low level, and the first scan signal S1 controls the second transistor T2' to turn on; the fourth scan signal S4 on the fourth scan line Scan4 is high level, and the fourth scan signal S4 controls the third transistor T3' to turn on; the data voltage transmitted on the data line Data is transmitted to the gate of the first transistor T1' via the second transistor T2', the first transistor T1', and the third transistor T3'; and the third transistor T3' acquires the threshold voltage of the first transistor T1', thereby achieving threshold compensation and data writing to the first transistor T1'.In the light emission stage t3, when the enable signal E2 on the enable line E1 is at a low level, the fifth transistor T5' and the sixth transistor T6' are controlled to turn on. The fifth transistor T5', the first transistor T1', and the sixth transistor T6' form a drive current path, supplying drive current to the light-emitting diode D1 and causing the light-emitting diode D1 to emit light.

[0012] Figure 3 is a schematic diagram of the layout structure of a pixel circuit in the related technology. As shown in Figure 3, the source of the first transistor T1' and the drain of the eighth transistor T8' are electrically connected via a connector L1. There is an overlap between the enable line E1 and the connector L1, forming a parasitic capacitance C2. During the light emission stage of the pixel circuit's drive process, the parasitic capacitance C2 affects the source potential of the first transistor T1', the voltage difference between the gate and source of the first transistor T1', the drive current of the first transistor T1', and the light emission effect of the light-emitting diode D1, preventing the light-emitting diode D1 from emitting light according to a predetermined brightness. Furthermore, one enable line E1 is connected to the fifth transistor T5' and multiple sixth transistors T6' in multiple pixel circuits located in one row. As a result, the voltage drop at different locations of the signal transmitted by the enable line E1 will differ, the potential at different locations on the enable line E1 may differ, and the coupling potential between the parasitic capacitance C2 and the first transistor T1' in the pixel circuits at different locations will differ. The magnitudes of the high and low levels of the enable signal in the enable line E1 connected to pixel circuits located in different rows are related to the distance between the enable line E1 and the drive chip. For example, the greater the distance between the enable line E1 and the drive chip, the smaller the absolute values ​​of the positive high and negative low levels in the enable line E1, and the potential of the enable line E1 connected to pixel circuits located in different rows may differ. Consequently, the coupling potential between the parasitic capacitance C2 and the first transistor T1' in the pixel circuits of different rows will differ. Therefore, the magnitude of the coupling potential corresponding to pixel circuits at different locations will differ, meaning that the degree to which the parasitic capacitance C2 in the pixel circuits at different locations influences the source potential of the first transistor T1' will differ, the degree to which the parasitic capacitance C2 in the pixel circuits at different locations influences the drive current will differ, and furthermore, the influence of the parasitic capacitance C2 in the pixel circuits at different locations on the luminescence brightness of the light-emitting diode D1 will differ, reducing the display uniformity of the display panel.As shown in Figure 2, when the target display brightness is low, dimming is performed using pulse width modulation (PWM) technology, that is, the brightness of the light-emitting diode D1 is controlled by controlling the light-emitting time of the light-emitting diode D1. The more pulses there are, the larger the voltage fluctuation in the enable line E1 becomes, and the larger the difference in coupling between the parasitic capacitance C2 in different pixel circuits and the source potential of the first transistor T1' becomes. That is, the difference in the influence of the parasitic capacitance C2 on the drive current in different pixel circuits becomes larger, the difference in the brightness of the light-emitting diode D1 in different locations becomes larger, and further affects the display uniformity of the display panel.

[0013] This embodiment provides an array substrate. Figure 4 is a schematic diagram of the layout structure of the array substrate according to an embodiment of the present application, Figure 5 is a cross-sectional view along the a0-a0' direction of Figure 4, and Figure 6 is a schematic diagram of the circuit structure of the pixel circuit according to an embodiment of the present application. Referring to Figures 4 to 6, the array substrate comprises a base 110 and a drive circuit layer located on the base 110, the drive circuit layer is provided with a pixel circuit and an emission control signal line EM, the pixel circuit comprises a drive transistor T1, a first initialization transistor T2 and a first connection part 101, the first connection part 101 is connected between the first pole of the drive transistor T1 and the first initialization transistor T2, and the first connection part 101 and the emission control signal line EM The orthographic projection of the base has an overlapping portion 102, and referring to Figure 4, a shield portion 103 is further provided on the drive circuit layer, and the orthographic projection of the shield portion 103 on the base 110 overlaps with the overlapping portion 102, the film layer on which the shield portion 103 is located is located between the film layer on which the light emission control line EM is located and the film layer on which the first connection portion 101 is located, and / or at least one organic insulating layer is provided between the film layer on which the first connection portion 101 is located and the film layer on which the light emission control line EM is located, and / or the thickness D of the insulating layer between the film layer on which the first connection portion 101 is located and the film layer on which the light emission control line EM is located is greater than 3 μm.

[0014] The array substrate includes a plurality of pixel circuits, each pixel circuit being connected to a single light-emitting element OLED in the display panel. The pixel circuit may be composed of devices such as thin-film transistors and capacitors, and is configured to supply a drive current to the light-emitting element OLED, causing the light-emitting element OLED to emit light in response to the drive current. The first pole of the drive transistor T1 may be the source of the drive transistor T1 or the drain of the drive transistor T1. Preferably, the film layer on which the light emission control signal line EM is located, the film layer on which the shield portion 103 is located, and the film layer on which the first connection portion 101 is located are stacked in order along the thickness direction Z of the base (for example, the direction away from the base). The shield portion 103 may include a metallic material, a conductive material such as indium tin oxide (ITO), etc.

[0015] In some embodiments, a shield portion 103 is provided, which is located between the film layer where the light emission control line EM is located and the film layer where the first connection portion 101 is located, and between the light emission control line EM and the first connection portion 101. As a result, the shield portion 103 forms a shield against the signal in the light emission control line EM, eliminating or reducing the degree of coupling (e.g., the degree of potential reduction) between the parasitic capacitance generated in the overlapping portion 102 between the light emission control line EM and the first connection portion 101 and the first pole potential of the drive transistor T1, and also reducing the difference in the coupling between the parasitic capacitance and the first pole potential of the drive transistor T1 in different pixel circuits. As a result, the degree of influence of parasitic capacitance on the drive current in pixel circuits at different locations becomes the same or similar, and furthermore, the display brightness of different light-emitting element OLEDs at the same grayscale tends to match, which is advantageous in improving the display uniformity of the display panel and enhancing the display effect of the display panel.

[0016] In some embodiments, the film layer on which the first connection portion 101 is located and the film layer on which the light emission control line EM is located are laminated along the thickness direction Z of the base. By providing at least one organic insulating layer between the film layer on which the first connection portion 101 is located and the film layer on which the light emission control line EM is located, at least one organic insulating layer is provided between the first connection portion 101 and the light emission control line EM, the orthographic projection of the at least one organic insulating layer on the base overlaps with the overlapping portion 102, the thickness of the dielectric layer between the first connection portion 101 and the light emission control line EM increases, the direct facing distance (distance along the thickness direction Z of the base) between the first connection portion 101 and the light emission control line EM increases, and the parasitic capacitance of the overlapping portion 102 can be reduced. Furthermore, the organic insulating layer reduces the dielectric constant of the parasitic capacitance, further reducing the parasitic capacitance of the overlapping portion 102.

[0017] In some embodiments, at least one organic insulating layer may be provided between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located, and then a shield portion 103 may be provided. This is advantageous in further reducing the influence of parasitic capacitance of the overlapping portion 102 on the potential of the first pole of the drive transistor T1, reducing the influence of parasitic capacitance on the drive current of the drive transistor T1, and further reducing the influence of parasitic capacitance on the light emission brightness of the light-emitting element OLED, thereby improving the display effect of the display panel.

[0018] In some embodiments, the thickness D of the insulating layer between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located (thickness along the thickness direction Z of the base 110; the insulating layer between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located may be a single-layer insulating layer, and D may be the thickness of the single-layer insulating layer; or the insulating layer between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located may be a multi-layer insulating layer, and D may be the sum of the thicknesses of the multi-layer insulating layer) is greater than 3 μm, and the first connection portion 101 is located The orthographic projection of the insulating layer on the base between the film layer and the film layer where the light emission control signal line EM is located overlaps with the overlapping portion 102, the thickness of the dielectric layer between the first connection portion 101 and the light emission control signal line EM increases to more than 3 μm, which corresponds to the direct facing distance between the first connection portion 101 and the light emission control signal line EM at the overlapping portion being greater than 3 μm, the direct facing distance between the first connection portion 101 and the light emission control signal line EM (distance along the thickness direction Z of the base) being large, which reduces the parasitic capacitance of the overlapping portion 102 to less than, for example, 0.85 fF, where 1 pF = 1000 fF.

[0019] In the technical proposal of this embodiment, a shield portion is provided, the orthographic projection of the base of the shield portion overlaps with the overlapping portion, and the film layer on which the shield portion is located is positioned between the film layer on which the light emission control line is located and the film layer on which the first connection portion is located. As a result, the shield portion forms a shielding effect against the signal transmitted by the light emission control line, eliminating or reducing the degree of coupling (degree of potential reduction) between the parasitic capacitance generated in the overlapping portion between the light emission control line and the first connection portion and the first pole potential of the drive transistor. This also reduces the difference in coupling between the parasitic capacitance and the first pole potential of the drive transistor in pixel circuits at different positions, making the degree of influence of parasitic capacitance on the drive current of pixel circuits at different positions the same or similar. Furthermore, the display brightness of light-emitting elements at different positions tends to match at the same grayscale, which is advantageous in improving the display uniformity of the display panel and enhancing the display effect of the display panel. By providing at least one organic insulating layer between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located, the direct facing distance between the light emission control signal line and the first connection portion is increased, the dielectric constant of the parasitic capacitance in the overlapping portion is reduced, the parasitic capacitance is reduced, and the influence of parasitic capacitance on the light emission brightness of the light-emitting element is further reduced, which is advantageous in enhancing the display effect of the display panel. By making the thickness of the insulating layer between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located greater than 3 μm, the direct facing distance between the light emission control signal line and the first connection portion is increased, the parasitic capacitance is reduced, and the influence of parasitic capacitance on the light emission brightness of the light-emitting element is further reduced, which is advantageous in enhancing the display effect of the display panel. Based on the above technical proposal, preferably, a DC potential is applied to the shield portion 103.

[0020] When the DC potential is a fixed-potential signal, no potential change occurs in the shield section 103 when the potential of the light emission control signal line EM changes. Therefore, the first connection section 101 is affected by the potential change of the light emission control signal line EM, and the amount of potential change decreases or becomes zero. This reduces the degree of coupling between the light emission control signal line EM and the potential of the first pole of the drive transistor T1. In other words, the degree of coupling between the potential changing in the light emission control signal line EM and the potential of the first pole of the drive transistor T1 can be reduced, and the difference in coupling between the parasitic capacitance in the pixel circuits at different positions and the potential of the first pole of the drive transistor also becomes smaller. The degree of influence of the parasitic capacitance in the pixel circuits at different positions on the drive current becomes the same or similar. Furthermore, the display brightness of light-emitting element OLEDs at different positions tends to match at the same grayscale, which is advantageous in further improving the display uniformity of the display panel. The DC potential may be a DC potential applied using the pixel circuits, scanning circuits, etc. on the array substrate. The shield section can be electrically connected to the pixel circuits, scanning circuits, etc. on the array substrate to apply the same DC potential, and there is no need to provide a separate power supply. The DC potential may be obtained by providing separate power and signal lines.

[0021] Preferably, the drive circuit layer is further provided with a first power line and / or an initialization signal line, and the shielding portion 103 is electrically connected to the first power line or the initialization signal line.

[0022] The first power supply voltage is transmitted through the first power line, and the first power supply voltage may be a high-level voltage or a low-level voltage. Therefore, when the shield section 103 is connected to the first power line, the signal transmitted through the shield section 103 is a DC signal, i.e., a fixed-potential signal, which reduces the degree of coupling between the light emission control signal line EM and the potential of the first pole of the drive transistor T1. The initialization signal is transmitted through the initialization signal line, and since the initialization signal is a fixed-potential signal, when the shield section 103 is connected to the initialization signal line, the signal transmitted through the shield section 103 is a fixed-potential signal, which can also reduce the degree of coupling between the light emission control signal line EM and the potential of the first pole of the drive transistor T1. To reduce the difficulty of wiring, a DC signal line connected to the shield section 103, such as the first power line or the initialization signal line, may be selected to be nearby.

[0023] Based on the above-mentioned technical proposals, the following describes an installation method in which at least one organic insulating layer is provided between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line is located, but this is not limited to the present invention.

[0024] Preferably, the drive circuit layer includes a first conductive layer M1, a second conductive layer M2, a third conductive layer M3, a fourth conductive layer M4, and a fifth conductive layer M5, which are stacked together, and preferably, the light emission control signal line EM is provided on the first conductive layer M1.

[0025] Preferably, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5 are laminated in order along the direction away from the base. Preferably, the first conductive layer M1, the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5 may include one or more types, such as a metal layer or an indium tin oxide (ITO) layer.

[0026] Preferably, the first connection portion 101 is provided on the side away from the base 110 of the fourth conductive layer M4 or the fourth conductive layer M4. Preferably, when a shield portion 103 is provided in the drive circuit layer, the first connection portion 101 is provided on the side away from the base 110 of the fourth conductive layer M4 or the fourth conductive layer M4. Preferably, when at least one organic insulating layer is provided between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line is located, the first connection portion 101 is provided on the side away from the base 110 of the fourth conductive layer M4.

[0027] In some embodiments, Figure 7 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present application, and Figure 8 is a cross-sectional view along the a1-a2 direction of Figure 7. Preferably, referring to Figures 7 and 8, the first connection portion 101 is provided on the side of the fourth conductive layer M4 away from the base 110. This increases the direct facing distance between the first connection portion 101 and the light emission control signal line EM, which is advantageous in reducing the parasitic capacitance of the overlapping portion 102 between the first connection portion 101 and the light emission control signal line EM. Furthermore, providing the first connection portion 101 on the side of the fourth conductive layer M4 away from the base 110 facilitates the provision of an organic insulating layer, which may be provided between any two of the second conductive layer M2, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5. Organic insulating layers may be provided between the second conductive layer M2 and the third conductive layer M3, between the third conductive layer M3 and the fourth conductive layer M4, and between the fourth conductive layer M4 and the fifth conductive layer M5. This is advantageous in significantly reducing the parasitic capacitance of the overlapping portion 102 and reducing the influence of the parasitic capacitance corresponding to the overlapping portion 102 on the display effect of the display panel.

[0028] Figures 7 and 8 schematically show the situation in which the first connection portion 101 is located on the fifth conductive layer M5, but are not limited to this configuration. Figure 8 shows the situation in which one organic insulating layer (first organic planarization layer PLN1, for example, located between the fourth conductive layer M4 and the fifth conductive layer M5) is provided, but are not limited to this configuration.

[0029] Preferably, the pixel circuit further comprises a data writing transistor T3, as shown in Figure 8, the first pole T31 and the second pole T32 of the data writing transistor T3 are provided on the fourth conductive layer M4, and the gate T33 of the data writing transistor T3 is provided on the first conductive layer M1. Here, the first pole T31 of the data writing transistor T3 is the source of the data writing transistor T3, and the second pole T32 of the data writing transistor T3 is the drain of the data writing transistor T3. Alternatively, the first pole T31 of the data writing transistor T3 is the drain of the data writing transistor T3, and the second pole T32 of the data writing transistor T3 is the source of the data writing transistor T3.

[0030] Preferably, referring to Figures 6 and 8, the pixel circuit includes a storage capacitor Cst, and the first electrode plate C01 of the storage capacitor Cst is provided on the second conductive layer M2.

[0031] Preferably, the pixel circuit further comprises a switch transistor, the switch transistor is connected to the gate of the drive transistor T1, the first gate G1 of the switch transistor is provided in the third conductive layer M3, and the first power line VDD is provided in the fifth conductive layer M5, and the first power line VDD is configured to supply a first power supply voltage to the pixel circuit.

[0032] The switching transistor may be an N-type transistor. The leakage current of the switching transistor is small, the potential change at the gate of the driving transistor T1 is small, which is advantageous for maintaining the gate potential of the driving transistor T1. As a result, the driving current by the driving transistor T1 is stable, and furthermore, the luminescence brightness of the light-emitting element OLED is stable. The first gate of the switching transistor is, for example, a top gate, and the first gate of the switching transistor is provided in the third conductive layer M3. The third conductive layer M3 can be manufactured from nanocesium tungsten oxide (GATO) material.

[0033] For illustrative purposes, refer to Figure 6, where the switch transistor includes a threshold compensation transistor T4 and / or a third initialization transistor T5, the threshold compensation transistor T4 and the third initialization transistor T5 are connected to the gate of the drive transistor T1, and the threshold compensation transistor T4 and the third initialization transistor T5 may be N-type transistors.

[0034] Preferably, referring to Figure 6, the first end of the light-emitting OLED is connected to the pixel circuit, and the second end of the light-emitting OLED is connected to the second power line VSS. The first end of the light-emitting OLED is the anode and the second end is the cathode, or the first end of the light-emitting OLED is the cathode and the second end is the anode.

[0035] Preferably, as shown in Figure 8, the first pole T51 and the second pole T52 of the third initialization transistor T5 are located in the fourth conductive layer M4, and the first gate G1 (top gate) of the third initialization transistor T5 is located in the third conductive layer M3. The third initialization transistor T5 may be provided with a single gate or a double gate structure. Preferably, the second gate G2 (bottom gate) of the third initialization transistor T5 is located in the second conductive layer M2, and the first gate G1 and the second gate G2 of the third initialization transistor T5 are connected and the same signal is applied to them, or the first gate G1 and the second gate G2 of the third initialization transistor T5 are provided in isolation and different signals are applied to them. The first pole T51 of the third initialization transistor T5 is the source of the third initialization transistor T5, and the second pole T52 of the third initialization transistor T5 is the drain of the third initialization transistor T5, or the first pole T51 of the third initialization transistor T5 is the drain of the third initialization transistor T5, and the second pole T52 of the third initialization transistor T5 is the source of the third initialization transistor T5. The active portion of the third initialization transistor T5 is located between the first gate G1 and the second gate G2 of the third initialization transistor T5.

[0036] In some embodiments, preferably, as shown in Figures 7 and 8, the first connection portion 101 is provided on the fifth conductive layer M5. An organic insulating layer is provided between the fourth conductive layer M4 and the fifth conductive layer M5. Preferably, an inorganic insulating layer is provided between any two adjacent first conductive layer M1, second conductive layer M2, third conductive layer M3, and fourth conductive layer M4. This is advantageous in further increasing the direct facing distance between the first connection portion 101 and the light emission control signal line EM, and further reducing the parasitic capacitance of the overlapping portion 102 between the first connection portion 101 and the light emission control signal line EM.

[0037] Based on the above-mentioned technical proposals, preferably with reference to Figure 4, the overlapping portion 102 is located within the orthographic projection of the shield portion 103 on the base 110. This ensures that the orthographic projection of the shield portion 103 on the base 110 completely covers the overlapping portion 102, thereby achieving a good shielding effect. Furthermore, the orthographic projection of the shield portion 103 on the base 110 can also cover the non-overlapping portion of the orthographic projection of the first connection portion 101 on the base 110 and the orthographic projection of the light emission control line EM on the base 110, thereby shielding some of the lateral capacitance between the first connection portion 101 and the light emission control line EM, which is advantageous for better shielding parasitic capacitance and further reduces the influence of parasitic capacitance on the potential of the first pole of the drive transistor T1.

[0038] As an embodiment of this invention, the installation of the shield portion will be described below based on the above-described embodiments, but this is not limited to the present invention.

[0039] In some embodiments, Figure 9 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present application, and Figure 10 is a cross-sectional view along the b1-b2 direction of Figure 4, preferably with reference to Figures 6, 9 and 10, the pixel circuit further comprises a second initialization transistor T6, the drive circuit layer further provides a first initialization signal line Vref1 and a second initialization signal line Vref2, the first initialization transistor T2 is connected between the first initialization signal line Vref1 and the first pole of the drive transistor T1, the second initialization transistor T6 is connected between the second initialization signal line Vref2 and the first end of the light-emitting element OLED, and the shield portion 103 is electrically connected to the first initialization signal line Vref1 or the second initialization signal line Vref2.

[0040] Figures 4 and 10 show the connection between the shield portion 103 and the first initialization signal line Vref1. The shield portion 103 and the first initialization signal line Vref1 (extending along the first direction X) may be provided in the same layer, preferably the shield portion 103 is provided in the third conductive layer M3. Figure 9 shows the connection between the shield portion 103 and the second initialization signal line Vref2. As shown in Figure 9, the shield portion 103 is connected via vias to the second connection and the second initialization signal line Vref2 in the conductive layer on the side away from the base of the shield portion 103 (e.g., the fourth conductive layer). The shield portion 103 and the second initialization signal line Vref2 (extending along the first direction) may be provided in the same layer. Preferably the shield portion 103 is provided in the third conductive layer M3. Multiple structures provided in the same layer can be obtained by patterning the same film layer, which simplifies the process. Multiple structures on the same layer may be made of the same material and can be manufactured simultaneously using the same process. Shielding sections 103 of pixel circuits at different locations can be connected to different signal lines or the same signal line.

[0041] The above initialization signal lines include a first initialization signal line Vref1 and a second initialization signal line Vref2. The signals transmitted by the first initialization signal line Vref1 and the second initialization signal line Vref2 are DC signals, i.e., fixed-potential signals. Therefore, by electrically connecting the shielding section 103 to the first initialization signal line Vref1 and / or the second initialization signal line Vref2, the potential in the shielding section 103 does not change, reducing the coupling between the light emission control signal line EM and the potential of the first pole of the drive transistor T1, and also reducing the difference in coupling between the parasitic capacitance in pixel circuits at different positions and the potential of the first pole of the drive transistor. Furthermore, the light emission brightness of different light-emitting elements OLEDs at the same grayscale becomes closer, which is advantageous in improving the display uniformity of the display panel. Because the distance between the shielding section 103 and the first initialization signal line Vref1 and / or the second initialization signal line Vref2 is short, wiring connections are made easy.

[0042] Preferably, the gates of the first initialization transistor T2 and the second initialization transistor T6 are electrically connected to the same scan signal line. This allows for simultaneous on-up control of the first initialization transistor T2 and the second initialization transistor T6, facilitating simultaneous initialization of the first pole of the drive transistor T1 and the light-emitting element OLED, while also reducing the number of scan signal lines and simplifying the wiring design.

[0043] Preferably, the drive circuit layer further includes a third conductive layer M3, and the pixel circuit further includes a switch transistor, the switch transistor being connected to the gate of the drive transistor T1, and the first gate of the switch transistor being provided in the third conductive layer M3.

[0044] Preferably, the first initialization signal line Vref1 and / or the second initialization signal line Vref2 are provided on the third conductive layer M3. This allows the shielding portion 103 to shield the first connection portion 101 and the light emission control line EM, whether the first connection portion 101 is provided on the fourth conductive layer M4 or on the side of the fourth conductive layer M4 away from the base 110 (for example, on the fifth conductive layer M5), thereby reducing the degree of coupling between the light emission control line EM and the potential of the first pole of the drive transistor T1, and also reducing the difference in coupling between parasitic capacitance in pixel circuits at different locations and the potential of the first pole of the drive transistor, which is advantageous in reducing the degree to which parasitic capacitance affects the display effect of the display panel.

[0045] Preferably, as shown in Figure 10, the gate T11 of the drive transistor T1 and the light emission control signal line EM are provided on the first conductive layer M1, the first electrode plate C01 of the storage capacitor Cst is provided on the second conductive layer M2, the shield portion 103 is provided on the third conductive layer M3, and the first connection portion 101 and the first electrode T21 of the first initialization transistor T2 (the electrode connected to the first electrode of the drive transistor T1) are provided on the fourth conductive layer M4. This makes it easier to connect the shield portion 103 to the first initialization signal line Vref1 located on the third conductive layer M3, and by applying a DC signal to the shield portion 103, the first connection portion 101 and the light emission control signal line EM are shielded more effectively.

[0046] Preferably, as shown in Figure 10, the drive circuit layer further includes a first buffer layer B1, a first gate insulating layer GI1, a capacitive insulating layer CI, a second buffer layer B2, a second gate insulating layer, a first organic planarization layer PLN1, and a second organic planarization layer PLN2. The first buffer layer B1 is located between the base 110 and the first conductive layer M1, and the first buffer layer B1 has an isolation effect, which prevents damage to the base 110 during etching of subsequent film layers and can improve the adhesion of the first conductive layer M1. The first gate insulating layer GI1 is located between the first buffer layer B1 and the first conductive layer M1 and is used to isolate the gate in the first conductive layer M1 (for example, the first pole T11 of the drive transistor T1). The capacitive insulating layer CI is located between the first conductive layer M1 and the second conductive layer M2, and is used to isolate the first electrode plate C01 of the stored capacitance Cst in the second conductive layer M2, thereby preventing the signal in the first conductive layer M1 from interfering with the potential at the first electrode plate C01. The second buffer layer B2 is located between the second conductive layer M2 and the third conductive layer M3, and the second buffer layer B2 has the functions of buffering, protecting, and insulating. The second gate insulating layer is located between the third conductive layer M3 and the first active layer, and the interlayer insulating layer ILD is located between the third conductive layer M3 and the fourth conductive layer M4, and the second gate insulating layer is used to isolate the gate in the third conductive layer M3 (for example, the top gate of the switch transistor described above), thereby achieving an insulating effect. The first organic planarization layer PLN1 is located on the side of the third conductive layer M3 away from the base 110, and the second planarization layer PLN2 is located on the side of the first organic planarization layer PLN1 away from the base 110.

[0047] Figure 11 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention, preferably as shown in Figure 11, the orthographic projection of the first initialization signal line Vref1 on the base 110 is located between the orthographic projection of the second initialization signal line Vref2 on the base 110 and the orthographic projection of the shield portion 103 on the base 110, and the orthographic projection of the first initialization signal line Vref1 on the base 110 is located between the orthographic projection of the second initialization signal line Vref2 on the base 110 and the orthographic projection of the light emission control signal line EM on the base 110.

[0048] Preferably, as shown in Figure 11, the direction of extension (or tendency or approximate direction of extension) of the first initialization signal line Vref1, the second initialization signal line Vref2, and the light emission control signal line EM is the first direction X, and they are arranged along the second direction Y, with the first direction X and the second direction Y intersecting. In other words, the first initialization signal line Vref1 and the light emission control signal line EM do not overlap, and the second initialization signal line Vref2 and the light emission control signal line EM do not overlap.

[0049] Preferably, as shown in Figures 9 and 11, the second initialization signal line Vref2 is electrically connected to the shielding section 103 via the second connection section 104, and the second connection section 104 and the first initialization signal line Vref1 are provided insulated from each other. Preferably, as shown in Figure 11, the film layer where the second connection section 104 is located is located on the side away from the base 110 of the film layer where the first initialization signal line Vref1 is located. Preferably, as shown in Figure 11, the first connection section 101 and the second connection section 104 are provided in the same layer. This makes it easy to electrically connect the second initialization signal line Vref2 and the shielding section 103, and allows the first initialization signal line Vref1 and the second initialization signal line Vref2 to be provided with different initialization signals as needed, without connecting them.

[0050] In some embodiments, Figure 12 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present application, preferably with reference to Figures 6 and 12, wherein the pixel circuit further comprises a storage capacitor Cst, the first electrode plate C01 of the storage capacitor Cst is connected to a first power line VDD, the first electrode plate C01 and the shield portion 103 are electrically connected to form an integrated structure and are provided in the same layer.

[0051] By applying a DC signal to the first electrode plate C01 of the storage capacitance Cst, a DC signal is applied to the shield portion 103, i.e., a signal with a fixed potential is applied, so the potential in the shield portion 103 does not change, the degree of coupling between the light emission control signal line EM and the potential of the first electrode of the drive transistor T1 can be reduced, the difference in coupling between the parasitic capacitance in the pixel circuit at different positions and the potential of the first electrode of the drive transistor is also reduced, and furthermore, the light emission brightness of different light-emitting elements OLEDs at the same grayscale becomes closer, which is advantageous in improving the display uniformity of the display panel.

[0052] Preferably, referring to Figure 12, the drive circuit layer further includes a second conductive layer M2, on which a first electrode plate C01 of a storage capacitance Cst is provided. Preferably, the second electrode plate of the storage capacitance Cst is also used as the gate of the drive transistor T1. As a result, when the first connection portion 101 is provided on the fourth conductive layer M4, or on the side of the fourth conductive layer M4 away from the base 110 (for example, on the fifth conductive layer M5), the shield portion 103 can shield both the first connection portion 101 and the light emission control line EM, reducing the degree of coupling between the light emission control line EM and the potential of the first electrode of the drive transistor T1, and also reducing the difference in coupling between parasitic capacitance in pixel circuits at different locations and the potential of the first electrode of the drive transistor, which is advantageous in reducing the degree of influence of parasitic capacitance on the display effect of the display panel.

[0053] In some embodiments, Figure 13 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present application, preferably with reference to Figure 13, wherein a first power line VDD is provided in the drive circuit layer, the first power line VDD includes electrically connected first sub-lines L1 and second sub-lines L2, the pixel circuit further comprises a first light emission control transistor T7, the first light emission control transistor T7 is electrically connected to the second sub-line L2, the second sub-line L2 is electrically connected to a shielding portion 103, preferably the shielding portion 103 extends along a first direction, the first sub-line L1 extends along a first direction X, the extending direction of the second sub-line L2 intersects the first direction X, the first sub-line L1 and the second sub-line L2 are provided in the same layer, preferably the first light emission control transistor T7 is connected between the first pole of the drive transistor T1 and the second sub-line L2, and the gate of the first light emission control transistor T7 is electrically connected to a light emission control signal line EM. This allows a DC potential to be applied to the shield portion 103, making it easier to reduce the coupling between the parasitic capacitance and the potential of the first pole of the first transistor T1'.

[0054] Preferably, the drive circuit layer may further include a fourth conductive layer M4 and a fifth conductive layer M5, with the first connection portion 101 provided on the fifth conductive layer M5 and the shield portion 103 provided on the fourth conductive layer M4. As a result, the film layer where the shield portion 103 is located is positioned between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located, and by shielding the signal transmitted by the light emission control signal line EM, the degree of coupling between the light emission control signal line EM and the potential of the first pole of the drive transistor T1 can be reduced, and the difference in coupling between parasitic capacitance in pixel circuits at different positions and the potential of the first pole of the drive transistor is also reduced, which is advantageous in reducing the degree to which parasitic capacitance affects the display effect of the display panel.

[0055] The first direction X may be the row direction of the array substrate, that is, the row direction in which the pixel circuit array is arranged. The first sub-line L1 can be electrically connected to the first electrode plate C01 of the storage capacitor Cst.

[0056] Preferably, as shown in Figure 13, the first sub-wire L1 and the second sub-wire L2 are provided in the fifth conductive layer M5, and the second sub-wire L2 is electrically connected to the shield portion 103 via a via.

[0057] By electrically connecting the second sub-line L2 of the first power line VDD to the shield section 103, a DC signal is applied to the shield section 103, preventing sudden changes in potential in the shield section 103. This is advantageous in reducing the coupling between the light emission control signal line EM and the potential of the first pole of the drive transistor T1. It also reduces the difference in coupling between the parasitic capacitance in pixel circuits at different locations and the potential of the first pole of the drive transistor. Furthermore, it brings the light emission brightness of different light-emitting OLEDs at the same grayscale closer, which is advantageous in further improving the display uniformity of the display panel.

[0058] Preferably, as shown in Figure 13, in three adjacent pixel circuits along a first direction X, the shield portion 103 in the intermediate pixel circuit is connected to the shield portion 103 in the pixel circuit located on one side, and the distance between the first connection portion 101 in the intermediate pixel circuit and the first connection portion 101 in the pixel circuit located on one side (which may be a distance along the first direction X) is smaller than the distance between the first connection portion 101 in the intermediate pixel circuit and the first connection portion 101 in the pixel circuit located on the other side (which may be a distance along the first direction X). In other words, the shield portions 103 in two adjacent pixel circuits in the first direction X are connected, and the first connection portions 101 in these two adjacent pixel circuits are provided adjacent to each other. This corresponds to one shield portion 103 corresponding to two adjacent pixel circuits in the first direction. The first direction X may be the row direction. The second direction Y may be the column direction. Figure 13 illustrates a 2x4 pixel circuit, where, in the four pixel circuits in the same row, the distance between the first connection points 101 in the two leftmost pixel circuits is smaller than the distance between the first connection points 101 in the two intermediate pixel circuits. Preferably, two adjacent pixel circuits in the first direction are arranged mirror-symmetrically. This reduces the number of shielding units 103, eliminating the need to manufacture one shielding unit 103 corresponding to each pixel circuit, and simplifying the wiring.

[0059] Preferably, as shown in Figures 4, 9, and 13, one shield portion 103 corresponds to one pixel circuit. Multiple pixel circuits are each provided with a shield portion 103, and the shield portions 103 for two adjacent pixel circuits are provided with a gap between them.

[0060] Based on the above technical proposals, the parasitic capacitance corresponding to the overlapping portion 102 between the orthographic projection at the base of the first connection portion 101 and the orthographic projection at the base of the light emission control signal line EM is orthogonal capacitance, and there is a possibility that lateral capacitance will occur in the portion where the first connection portion 101 and the light emission control signal line EM do not overlap. In order to further reduce the influence of parasitic capacitance on the potential of the first pole of the drive transistor T1, a policy for reducing lateral capacitance will be described below, but this is not limited to the present invention.

[0061] Preferably, referring to Figure 4, the light-emitting control signal line EM comprises a main body EM1 extending along a first direction X and an extension EM2 extending along a third direction H, the first direction X and the third direction H intersect, and the orthographic projection of the shield portion 103 on the base 110 at least partially covers the orthographic projection of the extension EM2 on the base 110.

[0062] When the third direction H is oblique to the first direction X, there is an angle between the main body EM1 and the extension EM2, and when the first connection part 101 approaches the angle, lateral capacitance is likely to occur at the angle. By providing the shield part 103 such that the orthographic projection on the base 110 of the shield part 103 covers at least partially the orthographic projection on the base 110 of the extension part EM2, it is possible to ensure that the shield part 103 covers the angle between the main body EM1 and the extension part EM2, the shield part 103 can shield the signal in the light emission control line EM, which is advantageous in reducing lateral capacitance at the angle, further reducing the influence of parasitic capacitance on the potential of the first connection part 101, further reducing the influence of parasitic capacitance on the potential of the first pole of the drive transistor T1, further reducing the influence of parasitic capacitance on the drive current generated by the drive transistor T1, and further reducing the influence of parasitic capacitance on the light emission brightness of the light-emitting element OLED, which is advantageous in further enhancing the display effect of the display panel.

[0063] Figure 14 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present invention, and Figure 15 is a cross-sectional view along the f1-f2 direction of Figure 14. Preferably, referring to Figures 14 and 15, the array substrate further comprises a shield layer M0, the shield layer M0 is located between the base 110 and the drive circuit layer, and there is a gap 120 between the orthographic projection of the first connection portion 101 on the base 110 and the orthographic projection of the light emission control signal line EM on the base 110, and the orthographic projection of the shield layer M0 on the base 110 and the gap 120 overlap at least partially.

[0064] The first connection portion 101 and the light emission control signal line EM are coupled in the gap 120, generating lateral capacitance. The orthographic projection of the shield layer M0 on the base 110 overlaps at least partially with the gap 120, and the shield layer M0 is not located between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located, but the electric field lines formed by the lateral capacitance are multidirectional. Therefore, the shield layer M0 can achieve the effect of shielding some of the electric field lines and reducing lateral capacitance, which is advantageous in further reducing parasitic capacitance due to coupling between the light emission control signal line EM and the first connection portion 101, and reducing the influence of parasitic capacitance on the potential of the first pole of the drive transistor T1.

[0065] Preferably, a DC potential is applied to at least a portion of the shielding layer M0.

[0066] Preferably, the shield layer M0 is electrically connected to the first power line VDD. Therefore, when a DC signal is applied to the shield layer M0, no fluctuations occur in the potential of the shield layer M0, the shield layer M0 can perform a good shielding function, and it is advantageous in reducing the lateral capacitance between the first connection part 101 and the light emission control signal line EM. Furthermore, by applying a stable voltage to the shield layer M0, it can perform an electrostatic shielding function. The shield layer M0 may include a metal layer or the like.

[0067] Preferably, the orthographic projection of the shield layer M0 on the base 110 overlaps with at least a portion of the active area of ​​the channel region of the drive transistor T1. This allows the shield layer M0 to act as an electrostatic shield for the drive transistor T1, preventing static electricity from affecting the characteristics of the drive transistor T1, preventing changes in the threshold voltage of the drive transistor T1, and ensuring the stability of the drive current of the drive transistor T1. Furthermore, it is possible to prevent static charge from damaging the gate of the drive transistor T1 and achieve the effect of protecting the drive transistor T1.

[0068] Preferably, the shield layer M0 is an electrostatic shielding layer and / or a light-shielding layer.

[0069] If the shield layer M0 is an electrostatic shielding layer, it is possible to prevent electrostatics from affecting the characteristics of the drive transistor T1 and to prevent electrostatics from affecting the display effect of the display panel. If the shield layer M0 is a light-shielding layer, it is possible to reduce the effect of ambient light on the characteristics of the drive transistor T1, which is advantageous in ensuring the stability of the drive current of the drive transistor T1 and improving the display effect of the display panel.

[0070] Based on the above-mentioned technical proposals, preferably with reference to Figure 4, a first initialization signal line Vref1 is further provided in the drive circuit layer, the first initialization transistor T2 is connected between the first initialization signal line Vref1 and the first pole of the drive transistor T1, the extension direction (or tendency of extension) of the first initialization signal line Vref1 and the light emission control line EM is the first direction X and they are arranged along the second direction Y, and the orthographic projection of the first initialization signal line Vref1 on the base 110 and the orthographic projection of the light emission control line EM on the base 110 are separated and do not overlap. In other words, the position of the original first initialization signal line Vref1 does not change, and the first initialization signal line Vref1 is not moved to form the shield portion 103. When the shield portion 103 is connected to the first initialization signal line Vref1, the shield portion 103 and the first initialization signal line Vref1 may be an integrated unit or connected as separate structures, and are not limited thereto.

[0071] Preferably, referring to Figure 4, the shield portion 103 and the first initialization signal line Vref1 are electrically connected to form an integrated structure and are provided on the same layer, and the shield portion 103 is connected to one of the two opposing sides along the second direction Y of the first initialization signal line Vref1, and the first direction X and the second direction Y intersect, and may be, for example, perpendicular. In other words, the shield portion 103 may be a portion that extends to one of the two opposing sides along the second direction Y of the first initialization signal line Vref1, that is, a portion that extends to the position of the overlapping portion 102, and it is ensured that the orthographic projection of the shield portion 103 on the base 110 overlaps with the overlapping portion 102, thereby achieving a good shielding effect and effectively reducing the degree of influence on the potential of the first pole of the drive transistor T1 due to the parasitic capacitance corresponding to the overlapping portion 102.

[0072] Preferably, Figure 16 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present application, referring to Figure 16, the drive circuit layer further includes a first active layer 130, a third conductive layer M3, a second active layer 140, and a first conductive layer M1, the active portion of the drive transistor T1 is located on the second active layer 140, the gate of the drive transistor T1 is located on the first conductive layer M1, and the first initialization signal line Vref1 is located on the third conductive layer M3 or on the side of the third conductive layer M3 away from the base 110.

[0073] Preferably, the second active layer 140, the first conductive layer M1, the first active layer 130, and the third conductive layer M3 are laminated in order along the direction away from the base 110.

[0074] Preferably, the pixel circuit further comprises a threshold compensation transistor T4, which is connected between the gate and a second pole of the drive transistor T1, the active portion of the threshold compensation transistor T4 is located in the first active layer 130, and the gate of the threshold compensation transistor T4 is located in the third conductive layer M3, and / or, the pixel circuit further comprises a third initialization transistor T5, which is electrically connected to the gate of the drive transistor T1, the active portion of the third initialization transistor T5 is located in the first active layer 130, and the gate of the third initialization transistor T5 is located in the third conductive layer M3. Preferably, the second active layer 140 contains polycrystalline silicon, and the first active layer 130 contains a metal oxide.

[0075] The second active layer 140 contains polycrystalline silicon, for example, Psi, and the driving transistor T1 may be a P-type transistor, with the active portion of the driving transistor T1 located in the second active layer 140. The gate of the driving transistor T1 is located in the first conductive layer M1 and is likely to overlap with the active portion located in the second active layer 140. The threshold compensation transistor T4 and the third initialization transistor T5 may be N-type transistors, with the gates of the threshold compensation transistor T4 and the third initialization transistor T5 located in the third conductive layer M3 and being likely to overlap with the active portion located in the first active layer 130.

[0076] Preferably, the shield layer M0, first buffer layer B1, second active layer 140, first gate insulating layer GI1, first conductive layer M1, capacitive insulating layer CI, second conductive layer M2, second buffer layer B2, first active layer 130, second gate insulating layer GI2, third conductive layer M3, interlayer insulating layer ILD, fourth conductive layer M4, first organic planarization layer PLN1, fifth conductive layer M5, second organic planarization layer PLN2, and sixth conductive layer M6 are laminated in order along the direction away from the base 110.

[0077] Preferably, the pixel circuit further comprises a first light emission control transistor T7, the first light emission control transistor T7 is connected between the first pole of the drive transistor T1 and the first power line VDD, and the gate of the first light emission control transistor T7 is electrically connected to the light emission control line EM, and / or, the pixel circuit further comprises a second light emission control transistor T8, the second light emission control transistor T8 is connected between the second pole of the drive transistor T1 and the first end of the light-emitting element OLED, and the gate of the second light emission control transistor T8 is electrically connected to the light emission control line EM, and / or, the pixel circuit further comprises a data writing transistor T3, the data writing transistor T3 is connected between the data line Data and the first pole of the drive transistor T1, and / or, the pixel circuit further comprises a storage capacitor Cst, the storage capacitor Cst is connected between the first power line VDD and the gate of the drive transistor T1.

[0078] Preferably, referring to Figures 4 and 6, the drive circuit layer further comprises a first scan signal line SP1, which is electrically connected to the gate of a data writing transistor T3, and is configured to control the data writing transistor T3 to turn on during the data writing phase so as to write the data voltage in the data line Data to the first pole of the drive transistor T1. Preferably, the first scan signal line SP1 is provided in the first conductive layer M1.

[0079] Preferably, referring to Figures 4 and 6, the drive circuit layer further comprises a second scanning signal line SP2, which is electrically connected to the gates of the first initialization transistor T2 and the second initialization transistor T6, and is configured to control the first initialization transistor T2 and the second initialization transistor T6 to turn on in the first initialization stage, thereby initializing the first pole of the drive transistor T1 and the light-emitting element OLED. Preferably, the second scanning signal line SP2 is provided in the first conductive layer M1.

[0080] Preferably, referring to Figures 4 and 6, the drive circuit layer further comprises a third scan signal line SN1, which is electrically connected to the gate of a third initialization transistor T5, and is configured to control the third initialization transistor T5 to turn on in the second initialization stage and initialize the gate of the drive transistor T1. Preferably, the third scan signal line SN1 is provided in the second conductive layer M2 and the third conductive layer M3, and preferably, the third scan signal line SN1 in the second conductive layer M2 and the third scan signal line SN1 in the third conductive layer M3 are connected, for example, at a location close to the bezel area of ​​the display area of ​​the display panel.

[0081] Preferably, referring to Figures 4 and 6, the drive circuit layer further comprises a fourth scanning signal line SN2, which is electrically connected to the gate of a threshold compensation transistor T4. The fourth scanning signal line SN2 is configured to control the threshold compensation transistor T4 to turn on during the threshold compensation phase, causing the threshold compensation transistor T4 to threshold compensate the drive transistor T1. Preferably, the fourth scanning signal line SN2 is provided in the third conductive layer M3 and the second conductive layer M2. Preferably, the fourth scanning signal line SN2 in the second conductive layer M2 and the fourth scanning signal line SN2 in the third conductive layer M3 are connected, for example, at a location close to the bezel area of ​​the display area of ​​the display panel.

[0082] Preferably, referring to Figure 9, the first connection portion 101 includes a connected first portion 1011 and a second portion 1012, the first portion 1011 being electrically connected to the first pole of the drive transistor T1, and the second portion 1012 being electrically connected to the first initialization transistor T2, the first portion 1011 extending along a first direction X, and the second portion 1012 extending along a second direction Y, the first direction X and the second direction Y intersect, and the orthographic projection of the second portion 1012 and the light emission control line EM on the base 110 has an overlapping portion 102, and the orthographic projection of the first portion 1011 on the base 110 is located on one of the two opposing sides along the second direction Y of the orthographic projection of the light emission control line EM on the base 110. With such an arrangement, when the shield portion 103 shields the overlapping portion 102, it does not overlap with vias, i.e., it avoids vias, and prevents vias from damaging or short-circuiting the shield portion 103. Preferably, there is a gap 120 between the orthographic projection of the first portion 1011 on the base 110 and the orthographic projection of the light emission control signal line EM on the base 110. By providing the shield layer M0 such that the orthographic projection on the base 110 and the gap 120 overlap at least partially, the shield layer M0 can achieve the effect of shielding some power lines and reducing lateral capacitance.

[0083] Preferably, referring to Figure 14, the first connection portion 101 includes a first portion 1011, a second portion 1012, and a third portion 1013 connected in order, the first portion 1011 being electrically connected to the first pole of the drive transistor T1, the third portion 1013 being electrically connected to the first initialization transistor T2, the first portion 1011 and the third portion 1013 extending along a first direction X, the second portion 1012 extending along a second direction Y, the first direction X and the second direction Y intersect, and the second portion 1012 and the base 11 of the light emission control line EM The orthographic projections at 0 have overlapping portions, and the orthographic projections of the first portion 1011 and the third portion 1013 at base 110 are located on opposite sides along the second direction Y of the orthographic projection of the light emission control line EM at base 110, preferably with a gap 120 between the orthographic projection of the first portion 1011 at base 110 and the orthographic projection of the light emission control line EM at base 110, and with a gap 120 between the orthographic projection of the third portion 1013 at base 110 and the orthographic projection of the light emission control line EM at base 110.

[0084] To facilitate wiring design, the first connection section 101 is configured to consist of sequentially connected first section 1011, second section 1012, and third section 1013, for example, the first section 1011, second section 1012, and third section 1013 being an integrated structure. This allows the shield section 103 to shield the overlapping section 102 without overlapping with vias, i.e., avoiding vias and preventing vias from damaging the shield section 103 or causing short circuits. The first section 1011 and the third section 1013 have the same extending direction (or tendency to extend) as the light-emitting control signal line EM, and there is a gap 120 between the orthographic projection of the first section 1011 on the base 110 and the orthographic projection of the light-emitting control signal line EM on the base 110, and there is a gap 120 between the orthographic projection of the third section 1013 on the base 110 and the orthographic projection of the light-emitting control signal line EM on the base 110, making it easy to form a lateral capacitance by coupling at the gap 120. In this embodiment, the technical proposal is set such that the orthographic projection of the shield layer M0 on the base 110 and the gap 120 overlap at least partially, thereby enabling the shield layer M0 to shield some power lines and achieving the effect of reducing lateral capacitance. Furthermore, the shield portion 103 may cover the gap 120, that is, the orthographic projection of the shield portion 103 on the base 110 and the gap 120 overlap at least partially, achieving the effect of further reducing lateral capacitance.

[0085] Figure 17 is a further cross-sectional view along the a1-a2 direction of Figure 7, preferably with reference to Figure 17, wherein multiple organic insulating layers are provided between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located, and / or the organic insulating layer includes an organic planarization layer, and / or at least one organic insulating layer and at least one inorganic insulating layer are provided laminated along the thickness direction Z of the base 110 between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located.

[0086] By providing multiple organic insulating layers between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located, the thickness of the dielectric layer between the first connection portion 101 and the light emission control signal line EM increases, the direct facing distance between the first connection portion 101 and the light emission control signal line EM increases, and the parasitic capacitance of the overlapping portion 102 can be reduced. Furthermore, the multiple organic insulating layers effectively reduce the dielectric constant of the parasitic capacitance, further reducing the parasitic capacitance of the overlapping portion 102. As shown in Figure 15, the organic insulating layer includes a first organic planarization layer PLN1 and a third organic planarization layer PLN3, where the first organic planarization layer PLN1 is located on the side of the third conductive layer M3 away from the base 110, the third organic planarization layer PLN is located on the surface of the first organic planarization layer PLN1 away from the base 110, and the second planarization layer PLN2 is located on the surface of the third organic planarization layer PLN away from the base 110. For example, the third organic planarization layer PLN3 may be an additional organic planarization layer. This allows the first organic planarization layer PLN1 and the third organic planarization layer PLN3 to isolate the first connection part 101 from the light emission control signal line EM, which is advantageous in reducing the parasitic capacitance of the light emission control signal line EM and the first connection part 101, and further reduces the influence of parasitic capacitance on the potential of the first pole of the drive transistor T1.

[0087] By providing at least one organic insulating layer and at least one inorganic insulating layer (for example, one or more of a capacitive insulating layer CI, a second buffer layer B2, a second gate insulating layer GI2, and an interlayer insulating layer ILD) laminated along the thickness direction Z of the base 110 between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located, the orthographic projection of one or more organic insulating layers on the base 110 overlaps with the overlapping portion 102, and the orthographic projection of one or more inorganic insulating layers on the base 110 also overlaps with the overlapping portion 102. This further increases the distance between the first connection portion 101 and the light emission control signal line EM in the thickness direction Z of the display panel, which is advantageous in further reducing the parasitic capacitance of the light emission control signal line EM and the first connection portion 101. The inorganic insulating layer may include one or more types such as silicon oxide, silicon nitride, and silicon oxynitride. The organic insulating layer may contain one or more types of materials such as polyimide, polyacrylate, polyetherimide, polyethylene terephthalate, and polyethylene naphthalate.

[0088] Preferably, an organic insulating layer, or at least one organic insulating layer and at least one inorganic insulating layer, is provided between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located. The thickness D of the insulating layer between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located is greater than 2.6 μm, which corresponds to a direct facing distance of more than 2.6 μm at the overlapping portion of the first connection portion 101 and the light emission control signal line EM, thereby reducing the parasitic capacitance between the light emission control signal line EM and the first connection portion 101, for example, to less than 0.85 fF.

[0089] Preferably, only an inorganic insulating layer is provided between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located. The thickness D of the insulating layer between the film layer where the first connection portion 101 is located and the film layer where the light emission control signal line EM is located (corresponding to the insulating layer in the overlapping portion 102) is greater than 3 μm, which corresponds to a direct facing distance of greater than 3 μm at the overlapping portion of the first connection portion 101 and the light emission control signal line EM, thereby reducing the parasitic capacitance between the light emission control signal line EM and the first connection portion 101, for example, to less than 0.85 fF.

[0090] Based on the above-mentioned technical proposals, Figure 18 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present application, and Figure 19 is a cross-sectional view along the k1-k2 direction of Figure 18. Referring to Figures 18 and 19, preferably the drive circuit layer further includes a sixth conductive layer M6, the sixth conductive layer M6 located on the side of the fifth conductive layer M5 away from the base 110, and the sixth conductive layer M6 comprises a first power line VDD and a data line Data. The first power line VDD supplies a first power supply voltage to the pixel circuit, and the data line Data is configured to supply a data voltage to the pixel circuit so that the pixel circuit generates a drive current based on the data voltage and the first power supply voltage.

[0091] As shown in Figure 19, the fourth conductive layer M4 further comprises the first pole of the drive transistor T1 (for example, the source of the drive transistor T1).

[0092] Preferably, in some embodiments, after the wiring setup of the first power line VDD and the data line Data is completed, if there is space in the sixth conductive layer M6 to place the first connection part 101, the first connection part 101 can be provided in the sixth conductive layer M6. This further increases the direct facing distance between the first connection part 101 and the light emission control signal line EM, further reduces parasitic capacitance due to coupling between the first connection part 101 and the light emission control signal line EM, ensures the stability of the first electrode potential of the drive transistor T1, and further ensures the stability of the drive current by the drive transistor T1. An organic insulating layer may be provided between the fifth conductive layer M5 and the sixth conductive layer M6. The sixth conductive layer M6 may include one or more types of materials such as a metal layer and an indium tin oxide (ITO) layer.

[0093] When the first connection portion 101 is provided in the sixth conductive layer M6, the shield portion 103 may be provided in the third conductive layer M3, the fourth conductive layer M4, or the fifth conductive layer M5. When the shield portion 103 is provided in the fifth conductive layer M5, the shield portion 103 is connected to the first power line VDD in the fifth conductive layer M5, and a DC potential can be applied to the shield portion 103, making it easier to shield the light emission control signal line EM and the first connection portion 101.

[0094] Based on the above-mentioned technical proposals, the following will describe the structure of multiple film layers in the array substrate, but this is not intended to limit the present invention.

[0095] Figure 20 is a schematic diagram of the layout structure of the first conductive layer and the second active layer of an array substrate according to an embodiment of the present invention, preferably referring to Figure 20, the first conductive layer M1 comprises a second electrode plate C02 (i.e., the gate of the drive transistor T1) having an emission control line EM, a first scanning signal line SP1, a second scanning signal line SP2, a third initialization signal line Vref3, and a storage capacitance Cst, with the extension direction (or tendency to extend) being the first direction X.

[0096] Figure 21 is a schematic diagram of the layout structure of the second conductive layer of an array substrate according to an embodiment of the present invention. Preferably, referring to Figure 21, the second conductive layer M2 comprises a first electrode plate C01 of storage capacitance Cst, a third scanning signal line SN1 and a fourth scanning signal line SN2 whose extending direction (or tendency to extend) is the first direction X. The bottom gate of the third initialization transistor T5 can be formed in the overlapping region of the third scanning signal line SN1 and the first active layer 130 in the second conductive layer M2. The bottom gate of the threshold compensation transistor T4 can be formed in the overlapping region of the fourth scanning signal line SN2 and the first active layer 130 in the second conductive layer M2.

[0097] Figure 22 is a schematic diagram of the layout structure of the third conductive layer and the first active layer of an array substrate according to an embodiment of the present application. Preferably, referring to Figure 22, the third conductive layer M3 includes a first initialization signal line Vref1, a second initialization signal line Vref2, a third scanning signal line SN1, and a fourth scanning signal line SN2, whose extending direction (or tendency to extend) is in the first direction X. The top gate of the third initialization transistor T5 can be formed in the overlapping region of the third scanning signal line SN1 and the first active layer 130 in the third conductive layer M3. The top gate of the threshold compensation transistor T4 can be formed in the overlapping region of the fourth scanning signal line SN2 and the first active layer 130 in the third conductive layer M3.

[0098] The third scanning signal line SN1 in the second conductive layer M2 and the third scanning signal line SN1 in the third conductive layer M3 are electrically connected, for example, via vias. The fourth scanning signal line SN2 in the second conductive layer M2 and the fourth scanning signal line SN2 in the third conductive layer M3 are electrically connected, for example, via vias. As a result, the bottom gate and top gate of the threshold compensation transistor T4 are connected, and the bottom gate and top gate of the third initialization transistor T5 are connected.

[0099] Figure 22 shows, but is not limited to, a situation where the shield portion 103 is located on the third conductive layer M3 and the shield portion 103 is electrically connected to the first initialization signal line Vref1.

[0100] Figure 23 is a schematic diagram of the layout structure of the fourth conductive layer of an array substrate according to an embodiment of the present invention. Preferably, referring to Figure 23, the fourth conductive layer M4 includes a first connection portion 101, a first initialization signal line Vref1 whose extending direction (or tendency to extend) is the second direction Y, a second initialization signal line Vref2, and a third initialization signal line Vref3. As shown in Figure 22, the first initialization signal line Vref1 located in the third conductive layer M3 (extending along the first direction X) and the first initialization signal line Vref1 located in the fourth conductive layer M4 (extending along the second direction Y) form a mesh structure, and the first initialization signals transmitted to different positions (different pixel circuits) via the first initialization signal line Vref1 are close together, which is advantageous for improving the display uniformity of the display panel. Similarly, the second initialization signal line Vref2 located in the third conductive layer M3 (extending along the first direction X) and the second initialization signal line Vref2 located in the fourth conductive layer M4 (extending along the second direction Y) form a mesh structure, and the third initialization signal line Vref3 located in the first conductive layer M1 (extending along the first direction X) and the third initialization signal line Vref3 located in the fourth conductive layer M4 (extending along the second direction Y) also form a mesh structure, which is advantageous for improving the display uniformity of the display panel. The first power line located in the fifth conductive layer M5 (extending along the first direction X) and the first power line located in the sixth conductive layer M6 (extending along the second direction Y) also form a mesh structure.

[0101] Each signal line may extend in a straight line, a broken line, a curve, or other irregular shape (e.g., dendritic) along its direction of extension (general direction of extension or tendency of extension).

[0102] Preferably, the shield section 103 is electrically connected to the third initialization signal line Vref3 and a DC potential can be applied to it. In the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 extending along the first direction X, and in the first initialization signal line Vref1, the second initialization signal line Vref2, and the third initialization signal line Vref3 corresponding to the pixel circuits of the same row, the orthographic projection of the third initialization signal line Vref3 on the base 110 is located away from the orthographic projection of the first initialization signal line Vref1 and the second initialization signal line Vref2 on the base 110 of the shield section 103, and since the first initialization signal line Vref1 and the second initialization signal line Vref2 are closer to the shield section 103 than the third initialization signal line Vref3, it is easier to connect the shield section 103 to the first initialization signal line Vref1 or the second initialization signal line Vref2 and to wire them together.

[0103] Figure 24 is a schematic diagram of the layout structure of the fourth conductive layer of a further array substrate according to an embodiment of the present invention, and preferably, referring to Figure 24, if the first connection portion 101 is provided on the side of the fourth conductive layer M4 away from the base 110, the first connection portion 101 is not provided on the fourth conductive layer M4.

[0104] Figure 25 is a schematic diagram of the layout structure of the fifth conductive layer of an array substrate according to an embodiment of the present application. Preferably, referring to Figure 25, the fifth conductive layer M5 is provided with a first power line VDD whose extension direction (or tendency to extend) is the first direction X, the first sub-line L1 corresponds to the main body, and the second sub-line L2 corresponds to the branching portion. Figure 25 shows, but is not limited to, a situation where the first connection portion 101 is located in the fifth conductive layer M5.

[0105] Figure 26 is a schematic diagram of the layout structure of the sixth conductive layer of an array substrate according to an embodiment of the present invention, and preferably, referring to Figure 26, the sixth conductive layer M6 comprises a first power line VDD whose extending direction (or tendency to extend) is the second direction Y and a data line Data whose extending direction (or tendency to extend) is the second direction Y.

[0106] Preferably, as shown in Figure 26, the sixth conductive layer M6 further comprises a data connection line Fa, which is configured to connect the drive chip and the data line Data. Providing the data connection line Fa in the sixth conductive layer M6 reduces the wiring in the bezel area (non-display area) of the display panel, which is advantageous for realizing a narrow bezel.

[0107] Figure 27 is a schematic diagram of the layout structure of the shield layer of the array substrate according to an embodiment of the present application, and preferably, referring to Figure 27, the orthographic projection of the shield layer M0 on the base 110 overlaps at least partially with the gap 120.

[0108] Figure 28 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present application, showing a situation where the first connection portion 101 is located on the fifth conductive layer M5. Figure 29 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present application, showing a situation where the first connection portion 101 is located on the fourth conductive layer M4 and the shield portion 103 is electrically connected to the first electrode plate C01 of the storage capacitance Cst. Figure 30 is a schematic diagram of the layout structure of a further array substrate according to an embodiment of the present application, showing a situation where the first connection portion 101 is located on the fifth conductive layer M5 and the shield portion 103 is located on the fourth conductive layer M4. Preferably, referring to Figures 28 to 30, the orthographic projection of the first initialization signal line Vref1 on the base 110 and the orthographic projection of the light emission control signal line EM on the base 110 are separated, i.e., do not overlap.

[0109] Preferably, Figure 31 is a schematic diagram of the circuit structure of a further pixel circuit according to an embodiment of the present application, the pixel circuit further comprising a first light emission control transistor T7, the first light emission control transistor T7 being connected between the second pole of the drive transistor T1 and the first power line VDD, the gate of the first light emission control transistor T7 being electrically connected to the light emission control line EM, and / or the pixel circuit further comprising a second light emission control transistor T8, the second light emission control transistor T8 being connected between the first pole of the drive transistor T1 and the first end of the light-emitting element OLED, the gate of the second light emission control transistor T8 being electrically connected to the light emission control line EM, and / or the pixel circuit further comprising a data writing transistor T3, the data writing transistor T3 being connected between the data line Data and the second pole of the drive transistor T1, and / or the pixel circuit further comprising a storage capacitor Cst, the storage capacitor Cst being connected between the first power line VDD and the gate of the drive transistor T1. Preferably, the pixel circuit further comprises a threshold compensation transistor T4, which is connected between the gate and the first pole of the drive transistor T1.

[0110] The difference between the circuit structure in Figure 31 and the circuit structure in Figure 6 lies in the application position of the first initialization transistor T2. In Figure 31, the first initialization transistor T2 is connected to the drain of the drive transistor T1, while in Figure 6, the first initialization transistor T2 is connected to the source of the drive transistor T1. The structure and function of the corresponding elements in the circuit structure of Figure 31 and the circuit structure of Figure 6 are the same or similar, and are therefore omitted from this explanation. In Figure 31, the first pole of the drive transistor T1 corresponds to the drain, and the second pole of the drive transistor T1 corresponds to the source. In Figure 6, the first pole of the drive transistor T1 corresponds to the source, and the second pole of the drive transistor T1 corresponds to the drain.

[0111] Figure 32 is a schematic diagram of a further array substrate layout structure according to an embodiment of the present invention. The layout structure in Figure 32 corresponds to the circuit in Figure 31. The circuit in Figure 6 corresponds to the layout structures and film layer structures in Figures 4 to 30. In the layout structures and film layer structures corresponding to the circuit in Figure 6, one end of the first connection part 101 connected to the drive transistor T1 can be changed from being connected to the source of the drive transistor to being connected to the drain of the drive transistor. The positions and functions of the corresponding shield parts 103 and other elements are the same or similar and are not described here. The pixel circuit (for example, the circuit in Figure 6 and the circuit in Figure 31) can be dimmed using pulse width modulation (PWM) technology, and the light emission control signal may include multiple pulses in the light emission stage within the refresh cycle of one screen. The timing waveform diagrams and operating processes of the circuit in Figure 6 and the circuit in Figure 31 are the same or similar as in Figures 1 and 2 and are not described here.

[0112] Preferably, the first light-emitting control transistor T7 is connected between the second pole of the drive transistor T1 and the second sub-wire L2.

[0113] This embodiment further provides a display panel, and Figure 33 is a schematic diagram of the structure of a display panel according to an embodiment of the present application. As shown in Figure 33, the display panel comprises an array substrate according to any of the above embodiments. The display panel may be any product or component having a display function, such as a mobile phone, tablet computer, television, display, notebook computer, or digital photo frame. Since the display panel comprises an array substrate according to any embodiment of the present application, it has the same beneficial effects as the array substrate according to any embodiment of the present application, and a detailed explanation is omitted here.

[0114] The specific embodiments described above do not limit the scope of protection of this application. Those skilled in the art will understand that various modifications, combinations, subcombinations, and substitutions are possible based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection. T11: First pole, gate 0045, 0046

Claims

1. The device comprises a base and a drive circuit layer located on the base, the drive circuit layer is provided with a pixel circuit and a light emission control line, the pixel circuit comprises a drive transistor, a first initialization transistor and a first connection part, the first connection part is connected between the first pole of the drive transistor and the first initialization transistor, and the orthographic projection of the first connection part and the light emission control line on the base has an overlapping portion. A shield portion is further provided on the drive circuit layer, the orthographic projection of the shield portion on the base overlaps with the overlapping portion, and the film layer on which the shield portion is located is located between the film layer on which the light emission control line is located and the film layer on which the first connection portion is located. and / or, at least one organic insulating layer is provided between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located. and / or, the thickness of the insulating layer between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located is greater than 3 μm. Array substrate.

2. A DC potential is applied to the shield portion. The array substrate according to claim 1.

3. The drive circuit layer is further provided with a first power line and / or an initialization signal line, and the shielding portion is electrically connected to the first power line or the initialization signal line. The array substrate according to claim 1.

4. The drive circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are stacked together. The light emission control signal line is provided in the first conductive layer. The pixel circuit further comprises a storage capacitor, and the first electrode plate of the storage capacitor is provided on the second conductive layer. The pixel circuit further comprises a switch transistor, the switch transistor is connected to the gate of the drive transistor, and the first gate of the switch transistor is provided in the third conductive layer. The first connection portion is provided on the side of the fourth conductive layer or the base of the fourth conductive layer that is away from it. A first power line is provided in the fifth conductive layer, and the first power line is configured to supply a first power voltage to the pixel circuit. The array substrate according to claim 1.

5. The first connection portion is provided in the fifth conductive layer, The organic insulating layer is provided between the fourth conductive layer and the fifth conductive layer. An inorganic insulating layer is provided between any two adjacent pairs of the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer. The array substrate according to claim 4.

6. The overlapping portion is located within the orthographic projection of the base of the shield portion. The film layer on which the light emission control signal line is located, the film layer on which the shield portion is located, and the film layer on which the first connection portion is located are arranged in order in a manner that moves away from the base. The array substrate according to any one of claims 1 to 5.

7. The pixel circuit further comprises a second initialization transistor, and the drive circuit layer is further provided with a first initialization signal line and a second initialization signal line, the first initialization transistor is connected between the first initialization signal line and the first pole of the drive transistor, and the second initialization transistor is connected between the second initialization signal line and the first end of the light-emitting element. The shield portion is electrically connected to the first initialization signal line or the second initialization signal line. The gates of the first and second initialization transistors are electrically connected to the same scan signal line. The array substrate according to any one of claims 1 to 5.

8. The drive circuit layer further includes a third conductive layer, and the pixel circuit further comprises a switch transistor. The switch transistor is connected to the gate of the drive transistor, and the first gate of the switch transistor is provided in the third conductive layer. The shield portion is provided on the third conductive layer. The first initialization signal line and / or the second initialization signal line are provided in the third conductive layer. The orthographic projection of the first initialization signal line on the base is located between the orthographic projection of the second initialization signal line on the base and the orthographic projection of the shield portion on the base, and the orthographic projection of the first initialization signal line on the base is located between the orthographic projection of the second initialization signal line on the base and the orthographic projection of the light emission control signal line on the base. The extension direction of the first initialization signal line, the second initialization signal line, and the light emission control signal line is the first direction and they are arranged along the second direction, and the first direction and the second direction intersect. The second initialization signal line is electrically connected to the shield portion via the second connection portion, and the second connection portion is provided insulated from the first initialization signal line, The film layer in which the second connection portion is located is located on the side of the film layer in which the first initialization signal line is located that is away from the base. The first connection portion and the second connection portion are provided on the same layer. The array substrate according to claim 7.

9. The aforementioned pixel circuit further includes a storage capacitor, and the first electrode plate of the storage capacitor is connected to a first power line. The first electrode plate and the shield portion are electrically connected to form an integrated structure and are provided in the same layer. The drive circuit layer further includes a second conductive layer, and the first electrode plate of the storage capacitance is provided on the second conductive layer. The second electrode plate of the storage capacitor is also used as the gate of the drive transistor. The array substrate according to any one of claims 1 to 5.

10. A first power line is provided in the drive circuit layer, and the first power line includes electrically connected first sub-lines and second sub-lines, and the pixel circuit further comprises a first light emission control transistor, the first light emission control transistor is electrically connected to the second sub-line, The second sub-wire is electrically connected to the shield portion. The shield portion extends along a first direction, the first sub-wire extends along a first direction, the direction of extension of the second sub-wire intersects with the first direction, and the first sub-wire and the second sub-wire are provided on the same layer. The first light-emitting control transistor is connected between the first pole of the drive transistor and the second sub-wire, or the first light-emitting control transistor is connected between the second pole of the drive transistor and the second sub-wire. The gate of the first light-emitting control transistor is electrically connected to the light-emitting control signal line. The drive circuit layer further includes a fourth conductive layer and a fifth conductive layer, the shield portion is provided on the fourth conductive layer, the first sub-wire and the second sub-wire are provided on the fifth conductive layer, and the second sub-wire is electrically connected to the shield portion via vias. The array substrate according to any one of claims 1 to 5.

11. Of the three adjacent pixel circuits along the first direction, the shield portion of the intermediate pixel circuit is connected to the shield portion of the pixel circuit located on one side, and the distance between the first connection portion of the intermediate pixel circuit and the first connection portion of the pixel circuit located on one side is smaller than the distance between the first connection portion of the intermediate pixel circuit and the first connection portion of the pixel circuit located on the other side. Two adjacent pixel circuits along the first direction are arranged in mirror symmetry. The array substrate according to claim 10.

12. The light-emitting control signal line comprises a main body extending along a first direction and an extension portion extending along a third direction, and the first direction and the third direction intersect. The orthographic projection of the shield portion on the base at least partially covers the orthographic projection of the extension portion on the base. The array substrate according to claim 1.

13. The shield layer is located between the base and the drive circuit layer, There is a gap between the orthographic projection of the base of the first connection portion and the orthographic projection of the base of the light emission control signal line, The orthographic projection of the shield layer on the base overlaps at least partially with the gap. A DC potential is applied to at least a portion of the shield layer, The shield layer is electrically connected to the first power line. The orthographic projection of the shield layer on the base overlaps with at least a portion of the active portion of the channel region of the drive transistor. The shielding layer is an electrostatic shielding layer and / or a light-shielding layer. The array substrate according to claim 1.

14. A first initialization signal line is further provided in the drive circuit layer, and the first initialization transistor is connected between the first initialization signal line and the first pole of the drive transistor. The extension direction of the first initialization signal line and the light emission control line is a first direction, and the first initialization signal line and the light emission control line are arranged along a second direction, the orthographic projection of the first initialization signal line on the base and the orthographic projection of the light emission control line on the base are separated, and the first direction and the second direction intersect. The array substrate according to any one of claims 1 to 5.

15. The shield portion and the first initialization signal line are electrically connected to form an integrated structure and are provided in the same layer, and the shield portion is connected to one of the two opposing sides of the first initialization signal line along the second direction. The drive circuit layer further includes a first active layer, a third conductive layer, a second active layer, and a first conductive layer, wherein the active portion of the drive transistor is located on the second active layer, the gate of the drive transistor is located on the first conductive layer, and the first initialization signal line is located on the third conductive layer or on the side of the third conductive layer away from the base. The pixel circuit further includes a threshold compensation transistor, the threshold compensation transistor being connected between the gate and a second pole of the drive transistor, or the threshold compensation transistor being connected between the gate and a first pole of the drive transistor, the active portion of the threshold compensation transistor being located in the first active layer, and the gate of the threshold compensation transistor being located in the third conductive layer. The pixel circuit further comprises a third initialization transistor, the third initialization transistor being electrically connected to the gate of the drive transistor, the active portion of the third initialization transistor being located in the first active layer, and the gate of the third initialization transistor being located in the third conductive layer. The second active layer contains polycrystalline silicon, and the first active layer contains a metal oxide. The array substrate according to claim 14.

16. The aforementioned pixel circuit is A first light-emitting control transistor is connected between the first pole of the drive transistor and the first power line, and its gate is electrically connected to the light-emitting control line. A second light-emitting control transistor is connected between the second pole of the drive transistor and the first end of the light-emitting element, and its gate is electrically connected to the light-emitting control line. A data writing transistor connected between the data line and the first pole of the drive transistor, The system further comprises a storage capacitor connected between the first power line and the gate of the drive transistor, Alternatively, the pixel circuit is A first light-emitting control transistor is connected between the second pole of the drive transistor and the first power line, and its gate is electrically connected to the light-emitting control line. A second light-emitting control transistor is connected between the first pole of the drive transistor and the first end of the light-emitting element, and its gate is electrically connected to the light-emitting control signal line. A data writing transistor connected between the data line and the second pole of the drive transistor, The system further comprises a storage capacitor connected between the first power line and the gate of the drive transistor, The array substrate according to claim 1.

17. The first connection portion includes a first portion, a second portion, and a third portion connected in order, the first portion being electrically connected to the first pole of the drive transistor, the third portion being electrically connected to the first initialization transistor, the first portion and the third portion extending along a first direction, the second portion extending along a second direction, the first direction and the second direction intersect, the orthographic projection of the second portion and the light emission control line on the base overlap, the orthographic projections of the first portion and the third portion on the base are located on opposite sides of the orthographic projection of the light emission control line on the base along the second direction, There is a gap between the orthographic projection of the base of the first portion and the orthographic projection of the light emission control signal line on the base, and there is a gap between the orthographic projection of the base of the third portion and the orthographic projection of the light emission control signal line on the base, The array substrate according to claim 1 or 15.

18. Multiple organic insulating layers are provided between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located. and / or, the organic insulating layer includes an organic planarizing layer, and / or, between the film layer in which the first connection portion is located and the film layer in which the light emission control signal line is located, at least one organic insulating layer and at least one inorganic insulating layer are provided, laminated along the thickness direction of the base. and / or, an organic insulating layer is provided between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located, and the thickness of the insulating layer between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located is greater than 2.6 μm. The array substrate according to any one of claims 1 to 5.

19. Only an inorganic insulating layer is provided between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located, and the thickness of the insulating layer between the film layer where the first connection portion is located and the film layer where the light emission control signal line is located is greater than 3 μm. The array substrate according to any one of claims 1 to 5.

20. The array substrate comprises the one described in any one of claims 1 to 19. Display panel.

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