Narrowing vector store instruction

Abstract

The device comprises an instruction decoding circuit (10) for decoding instructions and an issuer circuit (12) for issuing at least one microoperation to control processing circuits (16, 56) for performing processing operations. The instruction decoding circuit is configured to issue at least one microoperation to control the processing circuits to narrow the data elements of the multiple vector source registers from a second data element size to a first data element size smaller than the second data element size, in response to decoding a narrowing vector store instruction that specifies multiple vector source registers, each specifying a vector operand, and to store at least one narrowed data element vector containing the data elements of the multiple vector source registers narrowed to the first data element size in a location in the memory system.

Description

Technical Field

[0001] The present technology relates to the field of data processing.

Background Art

[0002] Processing circuitry may support a vector processing architecture in which vector instructions can trigger vector operations that are performed on vector operands containing multiple data elements. Performing vector operations using vector instructions can enable the instruction fetch and decode overhead for a given operation performed on each of a set of data elements to be reduced compared to a scalar implementation that processes each data element individually using separate scalar instructions.

[0003] At least some examples comprise instruction decoding circuitry for decoding instructions, and issue circuitry for issuing at least one micro-operation for controlling processing circuitry to perform processing operations corresponding to a given instruction in response to decoding of the given instruction by the instruction decoding circuitry, the instruction decoding circuitry being responsive to decoding of a narrowing vector store instruction that specifies at least one address operand and a plurality of vector source registers each specifying a vector operand having a given vector length, to control the issue circuitry to issue the at least one micro-operation for controlling the processing circuitry to narrow data elements of the plurality of vector source registers from a second data element size to a first data element size that is smaller than the second data element size, and store at least one narrowed data element vector including the data elements of the plurality of vector source registers narrowed to the first data element size to a location in a memory system, where the location in the memory system corresponds to a target memory address determined based on the at least one address operand.

[0004] At least some examples provide computer-readable code for fabricating a device comprising: an instruction decoding circuit for decoding instructions; and an issuer circuit for issuing at least one microoperation to control the processing circuit to perform a processing operation corresponding to a given instruction in response to decoding a given instruction by the instruction decoding circuit, wherein the instruction decoding circuit controls the issuer circuit to issue at least one microoperation to control the processing circuit to narrow the data elements of the vector source registers from a second data element size to a first data element size smaller than the second data element size in response to decoding a narrowing vector store instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, and the at least one narrowed data element vector, comprising the data elements of the plurality of vector source registers narrowed to the first data element size, is stored in a location in the memory system, the location in the memory system corresponding to a target memory address determined based on at least one address operand.

[0005] At least some examples provide a method in which at least one microoperation is issued to control the processing circuit to perform a processing operation corresponding to the given instruction in response to decoding an instruction decoding circuit specifying a plurality of vector source registers, each specifying a vector operand having a given vector length, to narrow the data elements of the plurality of vector source registers from a second data element size to a first data element size, where the first data element size is smaller than the second data element size, and to store at least one narrowed data element vector containing the data elements of the plurality of vector source registers narrowed to the first data element size in a memory system location, where the memory system location corresponds to a target memory address determined based on at least one address operand.

[0006] At least some examples include a computer program for controlling a host data processing device to provide an instruction execution environment for executing target program code, comprising: instruction decoding program logic for decoding instructions of target program code; and processing program logic for executing processing operations corresponding to a given instruction decoded by the instruction decoding program logic, wherein the instruction decoding program logic, in response to decoding a narrowing vector store instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, processes the data elements of the plurality of vector source registers from a second data element size to a first data element size, and the first data The present invention provides a computer program configured to control issuing program logic to issue at least one microoperation for controlling processing program logic to store at least one narrowed data element vector, which includes data elements of a plurality of vector source registers narrowed to the first data element size, where the data element size is narrowed to a first data element size, and the data elements of a plurality of vector source registers narrowed to the first data element size, in a location in a simulated address space, where the location in the simulated address space corresponds to a target memory address determined based on at least one address operand.

[0007] At least some examples provide a storage medium that stores the aforementioned computer-readable code or computer program. The storage medium may be a non-temporary storage medium.

[0008] Further aspects, features, and advantages of this technique will become apparent from the following example description, which should be read in conjunction with the attached drawings. [Brief explanation of the drawing]

[0009] [Figure 1]This section provides an example of a processing system that supports vector processing. [Figure 2] An example of a vector register having a vector length specified by a vector length parameter is illustrated below. [Figure 3] A first example of an instruction decoding circuit and an instruction issuing circuit is illustrated, in which case they are located within a processor such as a Central Processing Unit (CPU). [Figure 4] This example illustrates the use of a coprocessor to handle a subset of operations that are offloaded from the stream of operations that should be performed by the main processor. [Figure 5] This example illustrates the functionality of both non-interleaved and interleaved variations of the narrowing vector store instruction. [Figure 6] This example illustrates the functionality of non-interleaved variations of narrowing vector store instructions with predication. [Figure 7] Let's illustrate the data processing method with an example. [Figure 8] This example illustrates how to process a narrowing vector store instruction. [Figure 9] This example illustrates how to handle interleaved variations of narrowing vector store instructions. [Figure 10] This example illustrates how to handle non-interleaved variations of narrowing vector store instructions. [Figure 11] Let's illustrate this with a simulation example. [Modes for carrying out the invention]

[0010] The device comprises an instruction decoding circuit for decoding instructions, and an issuer circuit for issuing at least one microoperation to control the processing circuit to execute a processing operation corresponding to a given instruction in response to the decoding of a given instruction by the instruction decoding circuit. Designing the instruction set supported by the instruction decoding circuit can be a relatively complex task, as the available coding space may be limited compared to the wide range of operations that may theoretically be supported, and therefore, justification for providing support for a particular instruction will be necessary. Design selections and compromises made regarding which operations are supported and how those instructions are coded can affect the performance and power consumption of the processing circuit. Other factors to consider may be the practicality of implementing the circuit that executes the instructions and the flexibility that the architectured instructions provide to support different microarchitecture design selections for the circuit implementation. Therefore, the mere fact that a given operation is theoretically possible does not automatically mean that it is desirable to be able to wrap a given operation as a particular instruction. Designers of instruction set architectures are generally very cautious about adding new instructions to the instruction set, as removing an instruction is extremely difficult once it's included, as it will need to be supported to allow legacy software that uses it to continue functioning. If an instruction is introduced that proves problematic to implement in circuit hardware, or because the encoding space is insufficient to represent another, more desirable operation, the consequences of such a poorly considered addition to the instruction set will likely linger for a long time. Therefore, caution is exercised when considering additions to the instruction set.

[0011] In the following example, the instruction decoding circuit supports a narrowing vector store instruction, which specifies at least one address operand and a number of vector source registers, each specifying a vector operand having a given vector length. In response to decoding the narrowing vector store instruction, the instruction decoding circuit: ● Narrowing the data elements of multiple vector source registers from a second data element size to a first data element size, where the first data element size is smaller than the second data element size, and ● Control an issuer circuit to issue at least one microoperation to control a processing circuit to store at least one narrowed data element vector, which includes data elements of a plurality of vector source registers narrowed to a first data element size, in a memory system location, the memory system location corresponding to a target memory address determined based on at least one address operand.

[0012] Therefore, the narrowing vector store instruction allows both the narrowing of vector elements from multiple source registers and the storage of the narrowed vector elements from those multiple source registers into memory to be performed in response to a single instruction.

[0013] This instruction can be useful for workloads that process data structures where the storage format of data elements stored in memory is compressed compared to the processing format in which the data elements undergo processing operations in the processing circuit. For example, maintaining a vector in a vector register with a second data element size may be useful to allow for higher precision to be maintained during intermediate steps of vector processing operations performed on those data elements, while storing a vector with elements narrowed to a first data element size can provide a higher-density storage format that reduces memory storage overhead for a given number of data elements at the expense of precision. An example of a workload type in which this is useful is image processing workloads where it may be very common for pixel data to be stored in memory with a smaller data element size, while having a larger data element size when loaded from memory to apply image processing kernels such as filtering, resizing, or rotation.

[0014] Vector processing architectures can be attractive for this type of workload because they can apply iterative operations to multiple data elements in response to a single instruction. However, the inventors have recognized that existing vector instruction sets may be inefficient for handling this type of workload.

[0015] The narrowing-vector-store instructions described herein may be more efficient than alternative instructions because both the narrowing and store operations are performed in response to a single architectural instruction, and no additional architectural registers (represented by one of a limited set of architectural register identifiers that can be encoded in instruction coding) are required to hold one or more temporary narrowed vectors between the narrowing operation and the store (in contrast, such architectural registers would be consumed if the narrowing and store instructions were performed as separate architectural instructions, and the narrowing instruction was a register-to-register instruction rather than a register-to-memory instruction). Therefore, narrowing-vector-store instructions can help reduce register strain, which tends to improve performance because the code is less likely to exhaust extra architectural registers and there is less need to spill register data into memory that should have been held in the register file corresponding to the architectural vector register.

[0016] Furthermore, providing instructions that can store at least one narrowed data element vector into memory from two or more source vector registers can maintain the memory throughput (amount of data processed per store instruction) that would be achieved for an equivalent non-narrowing vector store instruction. In contrast, an alternative narrowing store instruction that stores narrowed data elements into memory from a single vector source register would have reduced memory throughput compared to an equivalent non-narrowing vector store instruction. This is because, in the case of a narrowing store instruction, the data element size is reduced, and therefore, if the amount of data in the vector source register contains a given number of elements of larger size, then when the elements are narrowed to a smaller size and stored in memory, the amount of data stored in memory will be reduced compared to the amount of data in the vector source register. Thus, a narrowing store instruction acting on a single vector source register will have reduced memory throughput compared to a non-narrowing vector store instruction. However, storing narrowing data elements in memory from multiple vector source registers means that the total amount of data stored per store operation is not reduced compared to non-narrowing vector store instructions, since the data is stored from two or more vector source registers, and therefore memory throughput can be maintained. A larger number of store instructions per amount of memory data processed will incur a greater cost in terms of memory control bandwidth (e.g., an increase in the number of memory translation lookups, load / store unit slots consumed, etc., which limits the bandwidth available for other operations and therefore can limit performance). This cost can be reduced for a given amount of memory throughput by using the narrowing vector store instructions described above.

[0017] Therefore, a narrowing vector store instruction, which stores a narrowed data element vector in memory from multiple vector source registers, can offer several advantages for supporting workloads that require data elements to be processed with a data element size larger than the storage format of these data elements in memory, thus justifying the extra encoding space consumed by providing this type of instruction in the instruction set.

[0018] A narrowing vector store instruction specifies two or more vector source registers. The vector source registers may be explicitly identified by two or more source register fields in the encoding of the narrowing vector store instruction. Alternatively, the instruction may explicitly identify the first of the two or more source registers in the register fields of the instruction encoding, and one or more of the other vector source registers may be implicitly identified as vector source registers whose architecture register identifiers are predeterminedly offset from the architecture register identifier of the first source register. For example, the two or more vector source registers may be registers associated with a contiguous set of architecture register identifiers starting from the architecture register identifier of the first source register, which is explicitly encoded in the instruction encoding. This technique restricts the software developer or compiler to select registers with contiguous architecture register identifiers as sources for the narrowing vector store instruction, which has the advantage of reducing the amount of encoding space required to encode multiple source registers, and this can be useful because instruction encoding space can be valuable.

[0019] Regardless of the particular technique obtained for encoding the vector source registers within an instruction, each vector source register explicitly or implicitly identified by the instruction is associated with a different architectural register identifier, and thus may be separately specified as a source register or a destination register by another instruction of the instruction set supported by the instruction decode circuitry. That is, when a given vector instruction specifies a source / destination vector register field to specify the identifier of the corresponding vector register used as a source / destination operand, each vector source register of the narrowing vector store instruction may have an associated architectural register identifier corresponding to a different encoding of the source / destination register field of the given vector instruction. Accordingly, each source register of the narrowing vector store instruction could be independently specified as an operand for a vector operation, or as a destination to be updated based on the result of a vector operation.

[0020] A narrowing vector store instruction may be mapped to one or more microoperations by the instruction decoding circuit. In some examples, providing a single narrowing vector store instruction may result in a reduction in the number of microoperations issued compared to examples using two or more instructions. For example, one method for storing narrowed vector data elements from multiple vector source registers into memory involves first using a register-to-register compression instruction to narrow the data elements, combining the narrowed data elements from the multiple vector source registers, writing the result to an architecture register, and then using a store instruction to retrieve the narrowed data from the destination register of the compression instruction and store that data in memory. The store instruction itself may be mapped to two microoperations: a microoperation to retrieve data from the source register, and a microoperation to calculate the destination address and perform the store operation on the data retrieved from the register in the first microoperation. Therefore, if the store instruction is followed by a compression instruction, it may involve the use of at least three microoperations. In response to this, the instruction decoder can map narrowing vector store instructions to fewer microoperations to reduce the number of microoperations required to perform the operation, and thus reduce the overhead associated with performing the operation.

[0021] In particular, the at least one micro-operation may include a first micro-operation and a second micro-operation, wherein the first micro-operation is adapted to control the processing circuitry to form at least one narrowed data element vector, and the second micro-operation is adapted to control the processing circuitry to consume the at least one narrowed data element vector formed by the first micro-operation and store the consumed at least one narrowed data element vector to a location in a memory system. In some examples, the second micro-operation may also control the processing circuitry to determine, based on at least one address operand, the location in the memory system at which the at least one narrowed data element vector is to be stored. For a narrowing vector store instruction, since the narrowed data is not stored in an architectural register in an intermediate step between narrowing and storage to memory, a micro-operation for retrieving the data from the architectural register may not need to be provided, and instead the micro-operation for storing the data to memory can consume the data directly from the micro-operation for narrowing the data elements. Thus, providing a single architectural instruction that stores narrowed data elements from a plurality of vector source registers to memory may lead to a reduction in the micro-operations issued, and thus an improvement in performance compared to examples where the operation is performed using two or more instructions.

[0022] The amount of data stored in memory in response to a narrowing vector store instruction is not particularly limited. However, in some cases, the encoding of a narrowing vector store instruction allows the size of at least one narrowed element vector stored in memory to be equal to a given vector length. In some cases of predication, the predicate operand of a narrowing vector store instruction may select the active portion of data smaller than a given vector length, so it is not mandatory for every instance of a narrowing vector store instruction to store an amount of data larger than or equal to a given vector length. Nevertheless, the maximum amount of data that can be stored by a narrowing vector store instruction may be greater than or equal to a given vector length. This is significantly different from a narrowing vector store instruction that specifies a single vector source register, where if there is a single vector register with a given vector length as the source, and the data elements of that single vector register are narrowed, the resulting data stored in memory will be smaller than the given vector length. In contrast, because this narrowing vector store instruction specifies two or more vector source registers, the total amount of data stored from multiple vector source registers may be greater than or equal to the size of a given vector length, even after the elements have been narrowed. This helps to increase the number of narrowed data elements stored in memory relative to a given amount of overhead associated with executing the store instruction.

[0023] Several examples may support non-interleaved variations of the narrowing vector store instruction. The instruction decoding circuit may control the issuing circuit to issue at least one microoperation to control the processing circuit to store at least one narrowed data element vector in a memory location in response to a non-interleaved variation of the narrowing vector store instruction, where the narrowed data element corresponding to one of a plurality of source vector registers is provided to a contiguous portion of at least one narrowed data element vector without interleaving the narrowed data elements corresponding to any other of the plurality of source vector registers. Thus, the narrowed data element vector may contain multiple distinct portions, where each of the plurality of vector source registers corresponds to one portion, and each portion contains the narrowed data element of the corresponding vector source register. Non-interleaved variations may be useful for supporting workloads where the storage structure in memory does not pack multiple channels in an interleaved manner (compared to the interleaved variations discussed below).

[0024] A non-interleaved variation of a narrowing vector store instruction may specify at least one predicate register, each predicate register specifying element predicate information indicating which data elements of a plurality of vector source registers are masked data elements, and for masked data elements, at least one corresponding portion of the narrowed data element vector specifies a value independent of the masked data element. For example, for a portion of the memory system location where a narrowed data element corresponding to a given masked data element would have been written if no predication had been applied, a value independent of the masked data element (e.g., zero) may be written instead. Alternatively, portions of the memory system corresponding to masked data elements of vector source registers may be excluded from the store operation, and the store operation may not store any data in those portions of the memory system. Predication information may be represented in various ways. In some examples, at least one predicate value may specify a predicate mask having several bit fields, each indicating whether a corresponding set of one or more elements is masked or not. Alternatively, a predicate counter could be used to indicate the total number of unmasked data elements (which can be implicitly considered as starting to be stored in the memory system from the first data element of the narrowed data element vector). In other words, the predicate counter could indicate the boundary between the initial set of unmasked data elements and the subsequent set of masked data elements. This allows the software to prevent store operations for narrowing vector store instructions from spilling into subsequent areas of memory beyond the end of the data structure being processed, even if the data structure being processed has a total number of data elements that does not correspond to exactly multiples of the number of elements that can be processed using a single instance of a narrowing vector store instruction, regardless of the particular way the predicate value represents the masked data elements.

[0025] For non-interleaved variations of a narrowing vector store instruction, element predication information can be specified by at least one predicate register, at the granularity of the narrowed data elements to be stored in memory. Typically, element predication information for a store instruction can be sized to correspond to a given vector length, such that a single predicate register corresponds to a single vector source register. However, since elements are narrowed before being stored in response to a narrowing vector store instruction, the amount of element predicate information provided for a given portion of memory at the narrowed data size can actually be applied to a larger amount of data in the source register. This means that a given predicate register with a given granularity can correspond to two or more vector source registers. Thus, a given predicate register can specify element predication information corresponding to two or more of the multiple vector source registers of a narrowing vector store instruction. This can reduce the amount of predicate registers required for a given operation.

[0026] In some examples, the instruction decoding circuit may control the issuing circuit to issue at least one microoperation to control the processing circuit to narrow data elements to a first data element size that is no more than 1 / N times the size of a second data element, in response to a narrowing vector store instruction specifying N vector source registers. For example, if two source vector registers are specified, the narrowed data elements may be no more than half the size of the data elements in the source vector registers. This ensures that the narrowed data element vector is no more than or equal to a given vector length. This means that the amount of data stored in memory in response to a narrowing vector store instruction is no more than or equal to the amount of data that would be stored in memory in response to a conventional store acting on a single source register with a given vector length. In this way, the control information that would have been used to control a store operation with a given vector length size does not need to be extended to accommodate the narrowing vector store instruction. For example, a predicate value or other control value may have a size corresponding to a given vector length, and therefore, by then restricting the narrowed data element vector to a given vector length, this control information does not need to be expanded, and the narrowing vector store instruction is not associated with additional overhead.

[0027] Several examples may support interleaved variations of narrowing vector store instructions. The instruction decoding circuit controls the issuing circuit to issue at least one microoperation to control the processing circuit to store in the memory system an interleaved narrowing data element vector comprising multiple interleaved narrowing data element channels, each of which corresponds to one of the source vector registers. The interleaved variations act on memory structures containing multiple interleaved data element channels, such as complex numbers represented as separate real and imaginary parts in two channels, or pixel data for images represented in red, green, blue, RGB (red, green, blue) or red, green, blue, alpha, RGBA (red, green, blue, alpha) formats, but may be useful in supporting processing workloads that require processing kernels to be applied to individual data channels extracted from the stored multi-channel structure. Therefore, although data can be stored in vector registers within separate channels for processing, it may be desirable to re-store the data in memory in an interleaved pattern so that channels corresponding to specific groups of elements (e.g., specific pixels) are stored together in memory.

[0028] Subsequently, by combining interleaving operations with store operations, the number of microoperations can be reduced (by eliminating the microoperation required to retrieve interleaved elements from architectural registers for subsequent store operations), and register strain can be reduced because interleaved elements do not need to be temporarily allocated to architectural registers in the intermediate step between interleaving and storing.

[0029] The interleaving pattern for storing a narrowed data element vector in a memory location can be implicitly defined by the encoding of the interleaving variant of the narrowing vector store instruction. Therefore, the deinterleaving variant of the narrowing vector store instruction does not need to specify an index operand that specifies an index value that explicitly identifies which of the source data elements will be inserted at each element position of the narrowed data element vector stored in the memory location. For example, an implicitly defined interleaving pattern may be a pattern in which narrowed data elements are selected sequentially from each vector source register to provide the next element of the narrowed data element vector (for example, in an image processing example, if there are separate source registers for the R, G, B, and A channels, elements may be selected sequentially from each register to provide the interleaved vector of narrowed data elements RGBARGBARGBA...). Therefore, the interleaved variations of the narrowing vector store instruction may be architecturally constrained to control the processing circuitry to execute a specific implicitly defined interleaved pattern, and cannot support any arbitrary general-purpose reordering where any single data element from the source vector can be arbitrarily reordered to any position in the narrowed data element vector. Using an implicitly defined interleaved pattern may be advantageous because controlling general-purpose reordering using an index vector would require the index values ​​of the index vector to be pre-calculated in software for a specific vector length, and the limited range of available index values ​​for each index value of the index vector may constrain the maximum vector length that can be supported by the general-purpose reordering operation controlled by the index vector, thus making it difficult to write vector length-independent software according to a scalable vector architecture (discussed further below).These problems can be avoided by providing an interleaved variant of the narrowing vector store instruction that uses an implicitly defined interleaved pattern, enabling scalable vectorization software to handle workloads that act on narrower data elements stored in memory as packed, interleaved data structures.

[0030] The interleaved variant of the narrowing vector store instruction may also specify at least one predicate value that specifies element predicate information indicating which data elements in multiple vector source registers are masked data elements, and for masked data elements, at least one corresponding portion of the narrowed data element vector specifies a value independent of the masked data element. However, unlike the non-interleaved variant, in the interleaved variant, it may be useful to specify element predication information at the element group granularity, where each element group contains one data element from each of multiple interleaved channels. For example, all elements within the same element group may have predicates for these elements controlled by the same mask bits of a predicate mask specified as at least one predicate value. Alternatively, in the case of a predicate counter, a monotonically incrementing value of the predicate counter causes consecutive element groups to be selected as active (for example, a count value of 3 causes further element groups (containing multiple data elements) that would be masked if the count value were 2 to be selected as active). Therefore, in the case of interleaved transformations, instruction encoding constrains predication to either masking all data elements in the same element group or not masking any data elements, and it would be impossible to partially mask some elements of the same element group while not masking other elements within the same element group. Applying predication at the element group granularity typically means either having to process each channel of a given element group or not having to when multiple channels of interleaved data need to be interleaved, and therefore there is little benefit in supporting partial predication, which may be particularly useful for interleaved transformations.When interleaving elements of a single element group, common predicate control can be applied to the corresponding element positions within each vector source register. Therefore, limiting predication to the granularity of element groups also simplifies microarchitecture implementation.

[0031] The number of vector source registers specified by a narrowing vector store instruction can vary. Some examples may support a two-register variation of the narrowing vector store instruction. For example, in an interleaved variation, this may be useful for supporting the interleaving of the real and imaginary parts of complex values. Other examples may support three-register and / or four-register versions of the instruction, or support additional vector source registers. An interleaved variation with three vector source registers may be useful for supporting operations on RGB format image data. An interleaved variation with four vector source registers may be useful for supporting operations on RGBA format image data. On the other hand, supporting three or more vector source registers, whether the variation is interleaved or non-interleaved, can help increase memory throughput and allow for fewer loop iterations of the vectorization scheme processed for a given amount of data. When two or more variations of an instruction are supported to accommodate various numbers of vector source registers, each variation of the instruction may be distinguished by the instruction opcode of these variations or by another field of the instruction that identifies the number of vector source registers.

[0032] The processing circuit is configured to narrow the data elements of multiple vector source registers from a second data element size to a first data element size. This method is performed in a manner that is not particularly limited. For example, rounding can be performed when reducing the number of bits to the first data element size. In some cases, if the first number of bits is too small to represent the value of the data element, the narrowed data element may be a saturation value that takes the maximum value representable in a data element of the first size.

[0033] However, in workloads where data is stored in memory at a narrower size and operates in registers of a larger size, rounding may often not need to be considered. This is because in these workloads, the increase in data element size is not to represent values ​​larger than those that could be represented with the smaller data element size, but rather to improve precision, and therefore the value to be stored in memory can be expected to be no larger than what could be represented using the first data element size. For example, data may be stored in memory as an integer with a first data element size, loaded and expanded to a second data element size, converted to a more precise representation (e.g., integer to floating-point), operated on, converted back to a less precise representation (rounding may be performed at this stage), and then specified by a narrowing vector store instruction. Thus, the narrowed and stored data can be expected to be no significantly larger than the element that would have been initially loaded from memory with the first data element size. Therefore, in some examples, the processing circuit is configured to narrow a given data element by selecting a portion of the least significant bits of the given data element, where part of the portion has a size equal to the size of the first data element, as the narrowed data element. Narrowing by truncation in this way is easy to implement and avoids the overhead of unnecessary rounding when rounding is not expected to be necessary.

[0034] In some examples, a narrowing vector store instruction may allow at least one narrowing data element vector to be stored to have a total size of more than twice the given vector length. For example, this could be useful in an implementation that stores RGBA data from four vector source registers in a 2x narrowing operation, resulting in data equivalent to two vectors (i.e., data twice the size of the given vector length) being stored in memory. Memory throughput can be increased by enabling the storage of data of two or more vector lengths in a single instruction.

[0035] Some implementations may support fixed definitions for the first and second data element sizes (for example, using a fixed ratio between the first and second data element sizes, e.g., making the second data element size twice or four times the first data element size).

[0036] However, in some examples, at least one of the first and second data element sizes is variable depending on at least one control parameter associated with the narrowing vector storage instruction. For example, this control parameter may include one or more of the instruction's opcode, an instruction encoding field for specifying element size information, and / or parameters stored in a control register for specifying element size information. For example, multiple variations of the instruction may be provided to support 2x and / or 4x widening operations and to act on elements of various sizes in memory, corresponding to various settings of the control parameter. For example, multiple variations may be provided for cases where the first and second data element sizes are, for example, 8 bits and 16 bits, 8 bits and 32 bits, and / or 16 bits and 32 bits, respectively.

[0037] In some implementations, a given vector length may be implicitly defined as a fixed value in the instruction set architecture. In other examples, a given vector length may be variable based on parameters associated with a narrowing vector store instruction.

[0038] However, it may be useful for the device to have a vector length memory circuit for storing a vector length parameter that indicates a given vector length. This can help support vector length-independent software written according to a scalable vector instruction set architecture, in which case the same software could run on various processing platforms (which implement various vector lengths as given vector lengths), but the given vector length used to execute narrowing vector store instructions is unknown at compile time, so that the operation of these instructions, such as loop control instructions, can be adapted to the implemented vector length based on a given vector length read from the vector length memory circuit.

[0039] In some examples, a device comprising an instruction decoding circuit and an issuing circuit may also include a processing circuit controlled by the issuing circuit to perform operations corresponding to narrowing vector store instructions.

[0040] However, in other examples, for at least a subset of instruction types, the issuing circuit may issue at least one microoperation corresponding to a narrowing vector store instruction to an off-chip processing circuit on a separate integrated circuit from the issuing circuit. Therefore, it is not necessary for the processing circuit that performs an operation in response to a narrowing vector store instruction to be part of the same device as the instruction decoding and issuing circuit that decodes the narrowing vector store instruction and issues one or more corresponding microoperations. For example, the off-chip processing circuit may include a coprocessor whose operations can be offloaded by a main processor comprising an instruction decoding and issuing circuit, in which case the coprocessor may be implemented on a chiplet separate from the main processor's instruction decoding / issuing circuit logic.

[0041] In some examples, a coprocessor may be configured to perform processing operations on a subset of instruction types offloaded by the main processor, and the coprocessor may include an instruction decoding circuit and an issuing circuit for decoding the instructions of that subset of instruction types. The coprocessor may be located on the same chip as the main processor or on a different chip. For a subset of instruction types offloaded to the coprocessor, the coprocessor may have its own internal instruction decoding and issuing circuits, and therefore the techniques discussed above may also be implemented within the coprocessor.

[0042] Therefore, there are various use cases in which instruction decoding and issuing circuits that support narrowing vector store instructions can be provided.

[0043] The techniques discussed above can be implemented in a device having hardware circuits provided for implementing instruction decoding circuits, issuing circuits (and processing circuits, if provided in the same device) as discussed above. However, the same techniques can also be implemented in a computer program that runs on a host data processing device and provides an instruction execution environment for the execution of target code. Such a computer program can control the host data processing device to simulate an architectural environment that would be provided on a hardware device that actually supports the target code according to a given instruction set architecture, even if the host data processing device itself does not support that architecture.

[0044] A computer program may have instruction decoding program logic that emulates the functionality of the instruction decoding circuit discussed above, and processing program logic that executes processing operations corresponding to a given instruction decoded by the instruction decoding program logic. For example, the instruction decoding program logic may include if / then statements to control the selection of a corresponding code sequence (part of the processing program logic) written in the native instruction set of the host data processing device in response to a given instruction in the target code, and the execution of that code sequence will control the host data processing device to execute the operation corresponding to the decoded instruction. The instruction decoding program logic and processing program logic support narrowing vector store instructions as discussed above, so that the corresponding narrowing store operation (with optional interleaving) is executed by the processing program logic. However, the register and memory address spaces that are expected to be provided by the instruction set architecture of the target program code do not actually need to be provided to the host device. Therefore, such register and memory address spaces can be simulated by mapping these register and memory address spaces onto the host's storage circuits (e.g., the registers and memory of the host device). Therefore, in the simulation embodiment, the store target address of a narrowing vector store instruction (calculated based on at least one address operand) represents an address in the simulated address space (which may differ from the address space used to access the host memory of the host data processing unit), and the vector source register may be emulated using the corresponding region of the host storage circuit rather than being mapped to an arbitrary specific hardware register file.

[0045] Such simulation computer programs can be useful, for example, when legacy code written for a particular instruction set architecture is running on a host processor that supports a different instruction set architecture. Furthermore, running software in a simulation environment allows for testing of the software in parallel with ongoing development of hardware devices supporting the new architecture. Therefore, simulation can enable the start of software development for a new version of an instruction set architecture before dealing with hardware that supports the new architecture version. The simulation program may be stored in a storage medium, which may be a non-temporary storage medium.

[0046] Here, we will explain a specific example with reference to a diagram.

[0047] Figure 1 schematically illustrates an example of a data processing device 2. The data processing device has a processing pipeline 4 that includes several pipeline stages. In this embodiment, the pipeline stages include a fetch stage 6 for fetching instructions from the instruction cache 8; a decode stage 10 (an example of an instruction decoding circuit) for decoding the fetched program instructions to generate microoperations (decoded instructions) to be processed by the remaining stages of the pipeline; an issue stage 12 (an example of an issue circuit) for checking whether the operands required for a given microoperation are available in register 14 and, if the operands required for a given microoperation are available, for issuing the microoperation for execution; an execution stage 16 (an example of a processing circuit) for executing data processing operations corresponding to the microoperation by processing the operands read from register 14 to generate result values; and a write-back stage 18 for writing the results of the processing back to register 14. This is merely one example of a possible pipeline configuration, and it will be understood that other systems may have additional stages or different configurations of stages. For example, in an out-of-order processor, a register renaming stage may be included to map architectural registers specified by program instructions or microoperations to physical register specifiers that identify physical registers in register 14. In some examples, there may be a one-to-one relationship between a program instruction decoded by the decoding stage 10 and the corresponding microoperation processed by the execution stage. Alternatively, there may be a one-to-many or many-to-one relationship between program instructions and microoperations; for example, a single program instruction may be split into two or more microoperations, or two or more program instructions may be merged so that they are processed as a single microoperation.

[0048] Execution stage 16 includes several processing units for performing different classes of processing operations. For example, the execution unit may include a scalar processing unit 20 (for example, equipped with a scalar arithmetic / logic unit (ALU) 20 for performing arithmetic or logical operations on scalar operands read from register 14), a vector processing unit 22 for performing vector operations on vectors having multiple vector elements, and a load / store unit 28 for performing load / store operations to access data in memory systems 8, 30, 32, and 34. Other examples of processing units that can be provided in the execution stage include a floating-point unit for performing operations involving values ​​expressed in floating-point format, or a branch unit for processing branch instructions.

[0049] Register 14 includes a scalar register 25 for storing scalar values, a vector register 26 for storing vector values, and a predicate register 27 for storing predicate values. The predicate value 27 may be used by the vector processing unit 22 when processing vector instructions, and the predicate value in a given predicate register indicates which vector elements of the corresponding vector operand stored in vector register 26 are active (unmasked) vector elements or inactive (masked) vector elements (operations corresponding to inactive data elements may be suppressed or may not affect the result value generated by the vector processing unit 22 in response to a vector instruction).

[0050] The memory management unit (MMU) 36 controls address translation between virtual addresses (specified by instruction fetches from the fetch circuit 6 or load / store requests from the load / store unit 28) and physical addresses that identify locations within the memory system, based on address mappings defined in a page table structure stored within the memory system. The page table structure can also define memory attributes that can specify access permissions for corresponding pages in the address space, for example, specifying whether a region of the address space is read-only or read / write, specifying which privilege levels are permitted to access the region, and / or specifying other properties that govern how the corresponding region of the address space can be accessed. Entries from the page table structure may be cached in a translation lookaside buffer (TLB) 38, which is a cache maintained by the MMU 36 to cache page table entries or other information in order to speed up access to page table entries from the page table structure shown in memory.

[0051] In this example, the memory system includes a Level 1 data cache 30, a Level 1 instruction cache 8, a shared Level 2 cache 32, and main system memory 34. This is merely one example of a possible memory hierarchy, and it will be understood that other cache arrangements are possible. The specific types of processing units 20-28 shown in execution stage 16 are merely examples, and other implementations may have different sets of processing units or include multiple instances of the same type of processing unit to handle multiple microoperations of the same type in parallel. Figure 1 is merely a simplified representation of some components of a possible processor pipeline configuration, and it will be understood that the processor may include many other elements not shown for brevity.

[0052] Figure 2 illustrates the set of architecture registers available for reference by instructions encoded according to the instruction set architecture (ISA) supported by processing system 2. Figure 2 does not show a physical register file provided in hardware to implement these architecture registers, but simply indicates which registers are logically available for reference by instructions. The specific mapping of architecture registers logically referenced by instructions to physical storage within the physical register file 14 can be implemented in many different ways (e.g., a one-to-one mapping between architecture registers and physical registers in an in-order processor, or a variable mapping between architecture registers and physical registers controlled by register renaming in an out-of-order processor).

[0053] In this example, ISA supports the following: ● A general-purpose register set 25, which includes general-purpose scalar registers for specifying scalar operands for scalar processing operations. ● A set of vector registers 26, which includes vector registers for specifying vector operands for vector processing operations, matrix operations, or other SIMD operations. ● A predicate register set 27 comprising predicate registers for specifying predicate values ​​for performing vector operations, matrix operations, or other SIMD operations, and ● A set of control registers 40 for storing control values ​​to control the operation of the processing unit 2. The information stored in the control registers may be set automatically in response to a specific event, or it may be programmable based on the execution of a system register update instruction.

[0054] In this example, the ISA supported by the processor 2 is a scalable vector ISA (also known as a "vector length independent" vector ISA) that supports vector instructions acting on vectors of scalable vector length, enabling the same instruction sequence to be executed on devices having hardware that supports different maximum vector lengths. This allows hardware designers of different processor implementations to select different maximum vector lengths depending on whether the design priorities for these implementations are high performance or reduced circuit area and power consumption, while software written according to the scalable vector ISA can run across any hardware platform that supports the scalable vector ISA, regardless of the specific maximum vector length supported by that particular hardware platform, thus eliminating the need for software developers to adapt their software to a specific hardware platform. Therefore, the vector length used for the vector register 26 accessed by a particular vector instruction of the scalable vector ISA (and thus the predicate length of the corresponding predicate register 27) is unknown at compile time (neither defined to be fixed in the ISA itself nor specified by a parameter of the software itself). The operations performed in response to a given vector instruction in a scalable vector ISA may differ depending on the vector length chosen for a particular hardware implementation (for example, hardware supporting a larger maximum vector length can process more vector elements for a given vector instruction than hardware supporting a smaller maximum vector length). Therefore, implementations with shorter vector lengths may require more loop iterations to perform a particular function than implementations with longer vector lengths.

[0055] Within the fixed coding space available for encoding ISA instructions, the vector length agnostic property of scalable vector ISAs is useful because, considering the wide range of requirements scaling from relatively small, energy-efficient microcontrollers to servers and other high-performance computing systems, it is not feasible to create different instructions for each different vector length that may be required by processor designers. By not having a fixed vector length known at compile time, the same ISA can be used to address multiple markets without the effort of software developers in tailoring the code to each performance / power / area point.

[0056] To achieve the scalability of the Scalable Vector ISA, the functionality of the vector instructions in the Scalable Vector ISA is defined in the architecture by referring to a parameter indicating the vector length in use (e.g., VL43 or SVL42, as shown in Figure 2, which will be described in more detail below) (taking into account the maximum vector length supported in hardware and any software-defined limitations using control register 40), the parameter VL or SVL being unknown at compile time. Therefore, the execution of the same vector instruction on different systems can produce different results (typically varying in terms of the number of vector elements produced, a subset of which may have the same result value on different platforms, but generally, platforms implementing larger vector lengths can produce additional vector elements compared to platforms implementing smaller vector lengths). The predicate value defined in predicate register 27 can be used to control which elements are produced in a given instance of the instruction and can be set on a vector length-independent basis, such as by using a comparison instruction to automatically generate the predicate value for a particular loop iteration, or by applying some generally defined predicate pattern that can scale to different vector lengths. Certain instructions may update loop control parameters, such as element count values, to track how many vector elements have been processed so far. As a result, implementations with wider vector lengths may require fewer loop iterations than those with narrower vector lengths. Therefore, across all loop iterations, both implementations with wider and narrower vector lengths may achieve the same result but at different levels of performance.

[0057] This particular example of the ISA also supports two different modes for performing vector operations: a non-streaming operation mode and a streaming operation mode. Mode indicator status information 41, stored in the control register 40, indicates whether the current mode is non-streaming mode or streaming mode, and can be set in response to the execution of a mode change instruction. Scalar operations using the general-purpose register 25 can be processed in the same way regardless of whether the current mode is non-streaming mode or streaming mode, but operations using the vector register 26 and predicate register 27 can be processed differently depending on whether the current mode is streaming mode or non-streaming mode.

[0058] In non-streaming mode, the vector register 26 is architecturally specified to have a vector register length VL, identified by the non-streaming vector length specification value 43 specified in the control register 40, and the predicate register 27 is architecturally specified to have a register length VL / X, where X is a constant corresponding to the minimum supported vector element size (for example, in an implementation where the minimum vector element size is 8 bits, X can be equal to 8). In streaming mode, the vector register 26 is architecturally specified to have a streaming mode vector length SVL, identified by the streaming vector length specification value 42 (which is separate from the non-streaming vector length specification value 43) specified in the control register 40, and the predicate register 27 is architecturally specified to have a register length SVL / X. Therefore, both the vector register 26 and the predicate register 27 can be considered to logically change their register lengths when there is a mode change between streaming mode and non-streaming mode.

[0059] Both the non-streaming vector length specification 43 and the streaming mode vector length specification 42 can be implemented in different ways. In some examples, these vector length specifications 43, 42 may simply be hardwired state information that is not programmable by software, or simply indicate the maximum register length supported by hardware for each mode. This is read by software to identify a specific vector length implemented on the hardware on which the program is running, and as a result, the same software may run on different hardware with different vector lengths.

[0060] In another example, this ISA may support more privileged software that can limit the maximum vector length available to software running with lower privileges. For example, given software may be restricted so as not to utilize the full vector length supported by the hardware in order to conserve power. Thus, the vector length specifications 43 and 42 may contain information that can be set by the software to specify the vector length used in each mode. Nevertheless, even if more privileged software applies restrictions on the vector length, the vector length for application software remains unknown at compile time because it is unknown whether the vector length actually implemented on a particular processor is greater or less than the limit defined in length specifications 43 and 42. For implementations that have hardware that supports a maximum vector length smaller than the limit defined in length specifications 43 and 42, the vector length smaller than indicated by the limit is actually used. For example, the effective vector length considered by the software may correspond to the minimum of the maximum vector length supported by the hardware for the current mode and the vector length limit set by the software. The vector length specifications 43 and 42 can be banked per exception level so that different limits on the maximum supported vector length can be specified for software running at different exception levels (for example, software at one exception level may be allowed to use longer vector lengths than software at another exception level).

[0061] Therefore, there are various ways in which the control state information stored in the control register 40 can affect vector operations where the vector length is useful, but generally, several pieces of state information are available that allow software to determine the effective vector length used for each mode. Thus, a given vector length is defined for a vector associated with a given vector instruction being executed.

[0062] Supporting both non-streaming and streaming modes can be useful because it provides hardware microarchitecture designers with greater flexibility to support different hardware implementations, such as those shown in Figures 3 and 4. In the example in Figure 3, vector instructions are executed by the processing circuit 16 of the main processor 2 without any operations being offloaded to the coprocessor. On the other hand, in the example in Figure 4, a coprocessor 50 is provided to perform a specific subset of vector operations using vector registers 26 and predicate registers 27. The coprocessor 50 may include a coprocessor decoding circuit 52 for decoding instructions issued to the coprocessor 50 by the issuing circuit 12 of the main processor 2, and a coprocessor issuing circuit 54 for receiving the decoded microoperations from the coprocessor decoding circuit 52, determining when the operands for those instructions become available, and issuing the microoperations to the coprocessor processing circuit 56 when the operands are available. The coprocessor 50 may have its own register storage 58, separate from the register storage 14 and the main processor 2. The coprocessor 50 can access a shared memory system shared with the main processor 2, and therefore can execute vector load / store instructions to load / store data from / to memory (for example, the coprocessor 50 may have access rights to one or more of the main processor's data caches 30, 32, and may access main memory 34). The coprocessor processing circuit 56 refers to the operands stored in the coprocessor register storage 58 and the data accessed from the memory system, and executes load / store and calculation operations represented by instructions offloaded to the coprocessor 50 by the main processor 2.

[0063] The architecturally defined streaming processing modes and the separate vector length representations 42, 43 for each mode make it easier for the hardware to determine whether instructions requiring vector registers should be offloaded to the coprocessor 50 or executed within the local execution unit 16 of the main processor 2. This also allows the software to explicitly specify whether a particular workload is better suited to execution on the general-purpose execution unit 16 of the processor 2 or on the more specialized hardware of the coprocessor 50. This means that for vector processing routines requiring smaller vectors and / or workloads where vector operations are interspersed with scalar operations, it may be more appropriate for the vector operations to be processed on the general-purpose execution unit 16 local to the processor 2 itself, while the coprocessor 50 may be more suitable for processing "streaming" workloads (e.g., workloads associated with machine learning applications such as neural network processing) that require high throughput of vector operations on large datasets where the need for intervening scalar operations is relatively small.

[0064] For such streaming workloads, longer vector lengths can be useful in reducing the instruction fetch / decode overhead associated with processing a given number of vector elements. Therefore, while this ISA does not require longer vector lengths (the vector length for non-streaming mode may be selected from a specific set of supported vector lengths, and the streaming mode vector length may be selected from a second set of supported vector lengths; there is no fixed relationship between the lengths selected for non-streaming and streaming modes), in implementations that choose to provide a coprocessor 50 to support streaming vector modes, it is relatively likely that the streaming mode vector length will be larger than, and in some cases several times larger than, the non-streaming mode vector length. As just one example (other lengths may also be used), one implementation might choose to implement a maximum vector length of 128 bits in non-streaming mode and 512 bits in streaming mode, and thus the predicate register would have an architectural vector length of 16 bits in non-streaming mode and 64 bits in streaming mode.

[0065] In the example using the coprocessor 50 shown in Figure 4, the coprocessor 50 may be on the same chip (integrated circuit) as the main processor 2, or on a separate chip. For example, the main processor 2 and the coprocessor 50 may be implemented as separate chiplets on an interposer, each chiplet being manufactured as a separate component and then assembled on the interposer.

[0066] Therefore, considering the instruction decoding circuit, issuing circuit, and processing circuit for implementing the narrowing vector store instruction referred to in this application, several different implementation forms are possible, including the following: ●A first example in which the instruction decoding circuit 10, the issuing circuit 12, and the processing circuit 16 are all located within the processor 2, as shown in Figure 3. ●A second example of a coprocessor processing circuit 56 within a coprocessor 50, in which the instruction decoding circuit 10 and the issuing circuit 12 are located within the main processor 2, but the processing circuit that executes the narrowing vector store instruction may be either on the same integrated circuit as the main processor 2 (at least in some operating modes such as the streaming mode described above) or an off-chip processing circuit 56 on a separate integrated circuit from the main processor 2. In other operating modes (e.g., non-streaming mode), the processing circuit that executes the narrowing vector store instruction may be the processing circuit 16 of the main processor 2, as in the first example. ● In a third example, as shown in Figure 4, the responsibility for decoding a narrowing vector store instruction into one or more microoperations rests with the coprocessor decoding circuit 52, and therefore the device that processes the narrowing vector store instruction can be considered as a coprocessor 50, which may or may not be on the same chip as the main processor 2. In this case, the instruction decoding circuit, issuing circuit, and processing circuit may be the coprocessor decoding circuit 52, the coprocessor issuing circuit 54, and the coprocessor processing circuit 56, respectively.

[0067] Since the processing circuits that actually perform operations on narrowing vector store instructions may be on a different chip from the instruction decoding circuits 10, 52 and issuing circuits 12, 54 that decode and issue narrowing vector store instructions, it is not necessary for the processing circuits 16, 56 themselves to be in the same device as the instruction decoding circuits 10, 52 and issuing circuits 12, 54.

[0068] While the example in Figure 2 discusses a scalable vector ISA, the narrowing vector store instruction described in this patent application may also be applied to a non-scalable vector ISA where the vector length is known at compile time (either fixed in the architecture or variable based on a software-specified parameter). Furthermore, although separate scalable vector ISAs supporting non-streaming and streaming modes have been described above, the narrowing vector store instruction may also be provided within a scalable vector ISA that does not support streaming mode, such that the mode indicator 41 and streaming vector length parameter 42 are not provided, and a given vector length used for the vector instruction is defined by the VL parameter 43.

[0069] Figure 5 shows examples of both non-interleaved and interleaved variations of the narrowing vector store instruction.

[0070] When processing certain workloads, such as image processing workloads, it may be relatively common to store data elements with smaller data element sizes in memory, but then pad the data when it is loaded from memory into registers to process it as a wider data type. For example, 8-bit pixel data stored in memory may be widened to 16 bits per data element to enable higher precision processing. After processing, the data may be stored back into memory as a narrower data type, and therefore may be narrowed before being stored in memory. However, existing vector architectures may be inefficient when handling this type of operation.

[0071] One approach is to use a narrowing store instruction that specifies a single vector source operand. This instruction can narrow the elements of a source register and store them in a contiguous region of memory. However, this approach does not allow interleaving elements of a source vector register with elements of other source registers. Interleaving may be necessary in some workloads where narrowing stores might be used, such as image processing, to store data from different channels (which can be loaded into different registers for separate processing) as interleaved data element channels for each pixel position (for example, separate R, G, B, and A channels can be stored in memory as RGBARGBA...). In addition, in the case of a narrowing store instruction that specifies a single vector source operand, less data will be stored in memory than the entire vector length. Since a single vector source operand will have a size up to the vector length, the amount stored in memory after narrowing will be less than the vector length. A store operation may be capable of processing data of at least vector length, and therefore, by storing data less than vector length, the available capacity of the store operation may not be used (and the number of elements processed per store instruction is reduced, and therefore additional instances of the store instruction to be executed to process a given number of elements may be required, increasing the load / store unit and memory translation overhead when processing that number of elements).

[0072] To enable interleaving the entire vector length of data and storing it in memory, an alternative technique might be to use a compressed instruction that retrieves data from two or more source registers, narrows and combines the data elements from those two or more source registers, and stores the result in an architecture destination register. This could be followed by a store instruction to retrieve the narrowed and combined elements from the architecture destination register and store the result in a memory location. However, a problem with this technique is that architecture registers are allocated as destinations for compressed instructions, which means that software will quickly exhaust any surplus architecture vector register identifiers available to identify new variables, potentially leading to increased register strain and performance degradation due to increased memory operations to spill out variables into memory that may not fit in the architecture register space. A further problem with this technique is that it can be broken down into a larger number of microoperations than could be used with different techniques. In particular, a store instruction can be broken down into two microoperations: the first microoperation ("STDATA") retrieves data from the architecture source register (the destination register for compressed instructions), and the second microoperation ("STADDRESS") stores the retrieved data in memory. However, in the technique discussed below, which uses narrowing vector store instructions, the first of these microoperations can be avoided because the narrowed and combined data elements are not stored in the architecture register at an intermediate stage of the operation.

[0073] These problems can be addressed by providing a narrowing vector store instruction as an instruction supported in the instruction set architecture, which specifies at least one address operand to define a target memory address for a store operation and specifies multiple vector source registers 26. This instruction can also specify predicate information, for example, using a predicate register 27. The function of the instruction is to cause processing circuits 16, 56 to narrow the data elements of the multiple specified vector source registers from a second data element size to a first data element size, and to store the narrowed data element vector having the first data element size from the multiple vector source registers in a memory location corresponding to the target memory address.

[0074] Therefore, in the example in Figure 5, the instruction specifies two vector source registers Z1 and Z2 and is used to store in memory a narrowed data element vector having a first data element size (e.g., 8 bits) from the elements of the two source registers Z1 and Z2, each having a second data element size (e.g., 16 bits). Each source register has a given vector length VL, SVL currently used for the vector processing operation.

[0075] For example, the narrowing vector store instruction could take on a variety of operands, such as: ST1B{ <z1> .H, <z2> .H}, <p0>[X17,X16]

[0076] Of course, the instruction encoding considered by instruction decoding circuits 10 and 52 will include a binary value encoded to represent the corresponding information. Here, ST1B represents the type of instruction and may correspond to an opcode encoded in binary encoding. Register identifiers Z1 and Z2 identify two vector source registers. In some examples, these may all be explicitly identified in the instruction encoding, or alternatively, the instruction may be constrained to select a group of vector registers as source registers having adjacent register identifiers, where only one of these register identifiers is explicitly encoded in the instruction encoding, and the others are implicitly specifically offset relative to the encoded register identifier. Notation .H indicates that the second data element size used for the non-narrowed data element is a "half-word" size (16 bits) (as opposed to byte size .B (8 bits) or full word size .W (32 bits)). In this example, it is implicit that the first data element size of the narrowed data element stored in memory is 8 bits, but other examples may include an operand to identify the first data element size. The predicate register identifier P0 identifies the predicate register that provides the predicate value. Register identifiers X17 and X16 represent address operands used to identify the target memory address (for example, X17 may identify the base register, and X16 may identify the register used to specify the offset to be added to the value stored in the base register to generate the target address). It should be understood that this is merely one example of an addressing mode, and any other addressing mode may also be used (for example, other examples may use an immediate value, a program counter value, and / or a stack pointer value as one of the address operands).

[0077] Therefore, when an instruction is decoded by the instruction decoding circuits 10 and 52, the instruction decoding circuits 10 and 52 generate at least one microoperation, which, when issued by the issuing circuits 12 and 54, causes the processing circuits 16 and 56 to narrow the data elements of multiple vector source registers from a second size to a first size, and to store the narrowed data element vector in a location in memory. This narrowing may be performed by taking a portion of the least significant bit of each data element, which has a size equal to the narrowed data element size. For example, as illustrated in Figure 5, element A1 may be narrowed to element A1', which includes the least significant bit of A1 (for example, expecting the most significant bits of A1 to be zero).

[0078] Both interleaved and non-interleaved variations are possible. Using the interleaved variation, the narrowed data element vector stored in memory may contain interleaved elements from each of the vector source registers, for example, A1B1A2B2... This can be particularly useful in examples of processing data within channels. For example, in image processing data, individual pixels may be represented by R, G, and B values ​​stored together in memory as RGBRGB, etc. Each channel can be processed as a separate channel, but can then be de-interleaved at load so that it can be interleaved again at storage. Therefore, a variation of the narrowing vector store instruction that interleaves elements from multiple vector source registers can be particularly useful. In the non-interleaved variation, the narrowed data element vector stored in memory may contain a contiguous portion from each vector source register, for example A1A2A3A4B1B2B3B4, without the interposition of elements from other vector source registers. This modification may be useful in workloads where the contents of each vector source register are processed separately both in memory and in the register.

[0079] Figure 5 shows an example of a two-source register instruction, but it will be understood that other variations may be able to store data from a different number of vector source registers (for example, a three-register variation may be provided to handle RGB interleaved data, and a four-register variation may be provided to handle RGBA data).

[0080] Furthermore, to support different element sizes for the first and second data element sizes, variations may be provided that have different ratios between the second and first data element sizes (e.g., quadruple narrowing instead of double narrowing). Narrowing from 16 bits to 8 bits is just one example; other examples include varying one or both of the first / second data element sizes based on programmable parameters referenced by the instruction (either in the instruction coding itself, in the control register, or a combination of both). Using a specific combination of the number of vector source registers and the narrowing, the operation can store data corresponding to two or more vector lengths in memory. Thus, a narrowing vector store instruction can generate two or more narrowed data element vectors. For example, in the case of four vector source registers with double narrowing, this would mean that two narrowed data element vectors would be stored in memory.

[0081] Using this type of instruction can offer several advantages. This may mean fewer microoperations can be issued to the processing circuit. In particular, because there is no architectural register that serves as the destination for the narrowing operation, the microoperation for storing the narrowed element in memory can directly consume the result of the narrowing operation and does not need to provide a microoperation for retrieving data from a register (for example, it does not need to include the "STDATA" microoperation). Also, an architectural register does not need to be specified for storing the result of the narrowing operation. Furthermore, by storing the entire vector length of data in memory, memory throughput can be increased compared to examples where less than the entire vector length of data is stored in memory.

[0082] Figure 6 shows a non-interleaved variation of a narrowing store instruction with predication applied. Two predicate values ​​Pg are illustrated, which may be provided in registers specified by the narrowing vector store instruction (or, at least in the case of counters, may be specified in the encoding of the narrowing vector store instruction). The predicate values ​​control the predication at the granularity of the narrowed data elements in memory. As shown in Figure 6, if elements of the narrowed data element vector to be stored in memory appear to be masked by a predicate (for example, if the corresponding element of the predicate has the value "0" in Figure 6, or if the value is at an element position with an index higher than the predicate counter value), the store operation may not store that element in memory. For example, in Figure 6, elements 0-8 of the narrowed data element vector are not masked, and elements 9-15 are masked, so only the values ​​of elements 0-8 are stored in memory.

[0083] It can be seen that predicates operate at the granularity of data elements in memory. For example, a predicate mask may have elements that are provided in a one-to-one relationship with the elements in the narrowed data element vector, or each increment of a predicate counter may correspond to a narrowed data element, and the predicate counter may have a maximum value corresponding to the number of narrowed data elements. If the store instruction is non-narrowing such that the source vector register has the same number of elements as the vector stored in memory, this would mean that the predicate register can only be used for predication of one source vector register. However, a narrowing vector store instruction reduces the size of the elements in the vector source registers, which means that each source vector register has fewer data elements than the narrowed data element vector, so the predicate value can then be used for predication of two or more vector source registers. Figure 6 shows in particular how the predicate mask Pg can be used for predication of elements from both vector source registers Z1 and Z2.

[0084] Figure 6 illustrates predication for non-interleaved variations, but it will be understood that predication can also be applied to interleaved variations of narrowing vector store instructions. However, in interleaved variations, the predicate value can control predication at the element group granularity, rather than at the narrowing data element granularity. Each element group contains a contiguous block of narrowed data elements in a memory-based structure, and each element group contains a single data element from each of the channels. If a given element group is indicated as being masked by a predicate, the narrowed data elements corresponding to that group are not stored in memory as part of the store operation. For example, in Figure 5, the element group may contain elements A1'B1', and a single bit of the predicate mask can control whether both elements are stored in memory or neither is stored in memory in response to the narrowing vector store instruction.

[0085] Figure 7 shows how data processing is performed. In step 100, instruction decoding circuits 10 and 52 decode instructions encoded according to a given instruction set architecture. In step 102, in response to the decoding of instructions by the instruction decoding circuits 10 and 52, issue circuits 12 and 54 issue at least one microoperation corresponding to the instruction. In step 104, processing circuits 16 and 56 perform the corresponding processing operation in response to at least one microoperation.

[0086] Figure 8 illustrates the steps performed in step 104 to process the operation when the instruction decoded in step 100 is a narrowing vector store instruction. In step 110, processing circuits 16 and 56 narrow the data elements of multiple vector source registers from a second data element size to a first data element size. In step 112, processing circuits 16 and 56 store the narrowed data element vector, which includes the data elements narrowed in step 110, in a memory location corresponding to a target memory address calculated based on at least one address operand of the narrowing vector store instruction.

[0087] Figure 9 illustrates the steps performed for the processing operation executed in step 104, when the instruction decoded in step 100 is an interleaved variation of a narrowing vector store instruction. In step 120, processing circuits 16, 56 narrow the data elements of multiple vector source registers from a second data element size to a first data element size. In step 122, processing circuits 16, 56 interleave the narrowed data elements from multiple vector source registers within the narrowed data element vector. Thus, the narrowed data element vector contains multiple interleaved channels, each channel corresponding to one of the multiple vector source registers. In step 124, the processing circuit stores the interleaved narrowed data element vector in a memory location corresponding to a target memory address calculated based on at least one address operand of the narrowing vector store instruction. In step 124, predication may be applied so that a subset of the elements of the narrowed data element vector are not stored in memory. The predicate value applied in step 124 may be applied at a granularity of element groups containing elements at the same position in each of the multiple vector source registers, and these element groups are provided in the contiguous portion of the narrowed data element vector.

[0088] Figure 10 illustrates the steps performed for the processing operation executed in step 104, when the instruction decoded in step 100 is a non-interleaved variation of a narrowing vector store instruction. In step 130, processing circuits 16, 56 narrow the data elements of a plurality of vector source registers from a second data element size to a first data element size. In step 132, processing circuits 16, 56 provide at least one narrowed data element vector, where the narrowed data element corresponding to one of the given source vector registers is provided to a contiguous portion of the narrowed data element vector without the interposition of narrowed data elements corresponding to any other of the plurality of source vector registers. Thus, each element may be obtained from the first vector source register, then each element may be obtained from the second vector source register, and so on. In step 134, the processing circuit stores the narrowed data element vector in a memory location corresponding to a target memory address calculated based on at least one address operand of the narrowing vector store instruction. In step 134, predication may be applied so that a subset of the elements of the narrowed data element vector are not stored in memory. The predicate value used to control the predicate in step 134 may correspond to two or more of the multiple vector source registers.

[0089] The concepts described herein may be embodied in computer-readable code for the fabrication of devices that embody the described concepts. For example, computer-readable code can be used in one or more stages of a semiconductor design and fabrication process, including an electronic design automation (EDA) stage, to fabricate an integrated circuit comprising a device that embodies the concepts. The computer-readable code described herein may additionally or alternatively enable the definition, modeling, simulation, verification, and / or testing of devices that embody the concepts described herein.

[0090] For example, computer-readable code for fabricating a device that embodies a concept described herein may be embodied in code that defines a hardware description language (HDL) representation of the concept. For example, the code may define register-transfer-level (RTL) abstractions of one or more logic circuits for defining a device that embodies a concept. The code may define HDL representations of one or more logic circuits that embodied the device in Verilog, SystemVerilog, Chisel, or Very High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) and intermediate representations such as FIRRTL. Computer-readable code may provide definitions that embodied the concept using system-level modeling languages ​​such as SystemC and SystemVerilog, or other behavioral representations of the concept that may be interpreted by a computer to enable simulation, functional and / or formal verification, and testing of the concept.

[0091] Additionally or alternatively, computer-readable code may define low-level descriptions of integrated circuit components that embody the concepts described herein, such as one or more netlists or integrated circuit layout definitions, including representations such as GDSII. One or more netlists or other computer-readable representations of integrated circuit components may be generated by applying one or more logic synthesis processes to the RTL representations to generate definitions used for fabricating devices that embody the invention. Alternatively or additionally, one or more logic synthesis processes may generate bitstreams from computer-readable code that are loaded into a field-programmable gate array (FPGA) to configure the FPGA to embody the concepts described herein. The FPGA may be deployed for the purpose of verifying and testing the concept before fabrication in an integrated circuit, or the FPGA may be deployed directly into a product.

[0092] Computer-readable code may include, for example, a mixture of code representations for the fabrication of a device, including one or more RTL representations, netlist representations, or other computer-readable definitions used in semiconductor design and fabrication processes for fabricating a device embodying the present invention. Alternatively or additionally, the concept may be defined as a combination of computer-readable definitions used in semiconductor design and fabrication processes for fabricating a device and computer-readable code that defines instructions to be executed by the device once it is defined to be fabricated.

[0093] Such computer-readable code may be placed on any known temporary computer-readable medium (such as wired or wireless transmission of code over a network) or on a non-temporary computer-readable medium such as a semiconductor, magnetic disk, or optical disk. Integrated circuits fabricated using computer-readable code may include components such as a central processing unit, graphics processing unit, neural processing unit, digital signal processor, or one or more other components that individually or collectively embody a concept.

[0094] Figure 11 illustrates possible simulator implementations. While the above embodiments implement the present invention in terms of devices and methods for operating specific processing hardware that supports the technique, it is also possible to provide an instruction execution environment according to the embodiments described herein, which are implemented by the use of a computer program. Such a computer program is often referred to as a simulator, insofar as it provides a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 330 having host memory circuits 332 (e.g., registers and / or memory), and optionally run a host operating system 320 that supports the simulator program 310. In some configurations, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or multiple different instruction execution environments may be provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such techniques may be justified in certain situations, such as when it is desirable to run native code on a different processor for reasons of compatibility or reuse. For example, a simulator implementation may provide an instruction execution environment with additional functionality not supported by the host processor hardware, or it may provide an instruction execution environment typically associated with a different hardware architecture. An overview of the simulation is provided in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990 USENIX Conference, pages 53-63.

[0095] While embodiments have been described with reference to specific hardware components or features, in simulated embodiments, equivalent functionality may be provided by suitable software components or features. For example, certain circuits may be implemented as computer program logic in simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures stored in the host storage (e.g., memory or registers) of the host processor 330 in simulated embodiments. In configurations where one or more of the hardware elements referenced in the above embodiments reside on host hardware (e.g., the host processor 330), some simulated embodiments may utilize the host hardware, if preferred.

[0096] The simulator program 310 may be stored in a computer-readable storage medium (which may be a non-temporary medium) and provides the target code 300 (which may include an application, operating system, and hypervisor) with the same program interface (instruction execution environment) as the hardware architecture interface modeled by the simulator program 310. Thus, program instructions of the target code 300 can be executed from within the instruction execution environment using the simulator program 310, and as a result, a host computer 330 that does not actually have the hardware functions of the device 2 discussed above (e.g., the instruction decoder 10 and processing circuit 16 that support the narrowing vector store instruction discussed above) can emulate these functions.

[0097] Therefore, the simulator program 310 may have instruction decoding program logic 312 for decoding the instructions of the target code 300 and mapping them to the corresponding instruction set in the native instruction set of the host device 330, which is provided as part of the processing program logic 313 of the simulator program. The instruction decoding program logic 312 includes decoding program logic 313 for decoding the narrowing vector store instructions described above. The register emulation program logic 314 maps the register access requested by the instructions of the target code to access the corresponding data structure maintained in the host memory circuit 332 of the host device 330, such as by accessing the registers or data in the memory of the host device 330. The memory management program logic 316 implements address translation, page table walk, and access permission checks to simulate the access of the simulated address space by the target code 300 in a manner corresponding to the MMU 36 described in the hardware-implemented embodiment above. The memory address space simulation program logic 318 is provided to map simulated physical addresses obtained by the memory management program logic 316 based on address translation using page table information maintained by the software of the target program code 300 to host virtual addresses used to access the host memory of the host processor 330. These host virtual addresses can themselves be translated to host physical addresses using the standard address translation mechanism supported by the host (the translation of host virtual addresses to host physical addresses is outside the scope of what is controlled by the simulator program 310).

[0098] In this application, the phrase "configured to..." is used to mean that an element of the device has a configuration that enables it to perform a defined operation. In this context, "configuration" means the arrangement or interconnection of hardware or software. For example, the device may have dedicated hardware to provide the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not mean that an element of the device must be modified in any way to provide the defined operation.

[0099] In this application, the enumeration of features preceded by the phrase "at least one of ~" means that any one or more of those features can be provided individually or in combination. For example, "[A], [B], and [C]" includes any of the following options: A alone (without B or C), B alone (without A or C), C alone (without A or B), a combination of A and B (without C), a combination of A and C (without B), a combination of B and C (without A), or a combination of A, B, and C.

[0100] While illustrative embodiments of the present invention are described in detail herein with reference to the accompanying drawings, it will be understood that the present invention is not limited to those exact embodiments, and that various changes and modifications can be made to the embodiments without departing from the scope of the present invention as defined by the appended claims. < / z2> < / z1>

Claims

1. It is a device, An instruction decoding circuit for decoding instructions, The system comprises an issuer circuit for issuing at least one microoperation to control a processing circuit to execute a processing operation corresponding to a given instruction in response to the decoding of a given instruction by the instruction decoding circuit, The instruction decoding circuit, in response to decoding a narrowing vector store instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, The data elements of the plurality of vector source registers are narrowed from a second data element size to a first data element size, where the first data element size is smaller than the second data element size, and A device configured to control an issuer circuit to issue at least one microoperation to control the processing circuit to store at least one narrowed data element vector, which includes data elements of the plurality of vector source registers narrowed to the first data element size, in a location in the memory system, wherein the location in the memory system corresponds to a target memory address determined based on the at least one address operand.

2. The at least one microoperation includes a first microoperation and a second microoperation, The apparatus according to claim 1, wherein the first microoperation controls the processing circuit to form the at least one narrowed data element vector, and the second microoperation controls the processing circuit to consume the at least one narrowed data element vector formed by the first microoperation and to store the consumed at least one narrowed data element vector in the location in the memory system.

3. The apparatus according to claim 2, wherein the second microoperation controls the processing circuit to determine the location in the memory system based on the at least one address operand.

4. The apparatus according to any one of claims 1 to 3, wherein the encoding of the narrowing vector store instruction enables the size of the at least one narrowed element vector to be equal to the given vector length.

5. The apparatus according to any one of claims 1 to 4, wherein the instruction decoding circuit is configured to control the issuing circuit to issue the at least one microoperation to control the processing circuit to store the at least one narrowed data element vector in the location in memory in response to a non-interleaved variation of the narrowing vector store instruction, and the narrowed data element corresponding to a given one of the plurality of source vector registers is provided to a contiguous portion of the at least one narrowed data element vector without interleaving the narrowed data element corresponding to any other of the plurality of source vector registers.

6. The non-interleaved variation of the narrowing vector store instruction specifies at least one predicate register, each predicate register specifying element predicate information indicating which data elements of the plurality of vector source registers are masked data elements, and for the masked data elements, the corresponding portion of the at least one narrowed data element vector specifies a value independent of the masked data element. The apparatus according to claim 5, wherein a given predicate register specifies element predicate information corresponding to two or more of the plurality of vector source registers.

7. The apparatus according to any one of claims 1 to 6, wherein the instruction decoding circuit is configured to control the issuing circuit to issue the at least one microoperation to control the processing circuit to narrow the data elements to a first data element size that is 1 / N times or less the size of the second data element, in response to the narrowing vector store instruction specifying N vector source registers.

8. The apparatus according to any one of claims 1 to 7, wherein the instruction decoding circuit is configured to control the issuing circuit to issue the at least one microoperation to control the processing circuit to store in the memory system an interleaved variation of the narrowing vector store instruction, wherein each of the interleaved channels comprises at least one interleaved narrowed data element vector, each of which comprises a plurality of interleaved narrowed data element channels corresponding to one of the source vector registers.

9. The apparatus according to claim 8, wherein an interleaving pattern for interleaving the data elements of the plurality of source vector registers into the at least one narrowed data element vector is implicitly defined by encoding the interleaving variation of the narrowing store instruction.

10. The apparatus according to claim 8 or 9, wherein the plurality of vector source registers include at least three vector source registers.

11. The apparatus according to any one of claims 1 to 10, wherein the processing circuit is configured to narrow a given data element by selecting a portion of the least significant bit of the given data element, wherein the portion has a size equal to the size of the first data element, as the narrowed data element.

12. The apparatus according to any one of claims 1 to 11, wherein the first data element size and the second data element size are variable according to a control parameter associated with the narrowing vector store instruction.

13. The apparatus according to any one of claims 1 to 12, wherein the first size is less than or equal to half the second size.

14. The apparatus according to any one of claims 1 to 13, further comprising a vector length storage circuit for storing a vector length parameter indicating the given vector length.

15. The apparatus according to any one of claims 1 to 14, comprising the processing circuit.

16. The apparatus according to any one of claims 1 to 15, wherein the issuing circuit is configured to issue the at least one microoperation to an off-chip processing circuit on an integrated circuit separate from the issuing circuit for at least a subset of instruction types.

17. The apparatus according to any one of claims 1 to 15, comprising a coprocessor configured to perform processing operations on a subset of instruction types offloaded by a main processor, wherein the coprocessor comprises an instruction decoding circuit for decoding instructions of the subset of instruction types, and an issuing circuit.

18. A computer-readable code for the manufacture of a device, wherein the device is An instruction decoding circuit for decoding instructions, The system comprises an issuer circuit for issuing at least one microoperation to control a processing circuit to execute a processing operation corresponding to a given instruction in response to the decoding of a given instruction by the instruction decoding circuit, The instruction decoding circuit, in response to decoding a narrowing vector store instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, The data elements of the plurality of vector source registers are narrowed from a second data element size to a first data element size, where the first data element size is smaller than the second data element size, and Computer-readable code configured to control an issuer to issue at least one microoperation to control the processing circuit to store at least one narrowed data element vector, which includes data elements of the plurality of vector source registers narrowed to the first data element size, in a location in the memory system, wherein the location in the memory system corresponds to a target memory address determined based on the at least one address operand.

19. It is a method, Decoding the instructions, This includes issuing at least one microoperation to control a processing circuit to perform a processing operation corresponding to a given instruction in response to decoding the given instruction, In response to decoding a narrowing vector store instruction specifying at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, The data elements of the plurality of vector source registers are narrowed from a second data element size to a first data element size, where the first data element size is smaller than the second data element size, and A method in which at least one microoperation is issued to control the processing circuit to store at least one narrowed data element vector, which includes data elements of the plurality of vector source registers narrowed to the first data element size, in a location in the memory system, wherein the location in the memory system corresponds to a target memory address determined based on the at least one address operand.

20. A computer program for controlling a host data processing device in order to provide an instruction execution environment for executing target program code, Instruction decoding program logic for decoding the instructions of the target program code, Includes processing program logic for executing processing operations corresponding to a given instruction decoded by the instruction decoding program logic, The instruction decoding program logic responds to decoding a narrowing vector store instruction that specifies at least one address operand and a plurality of vector source registers, each specifying a vector operand having a given vector length, The data elements of the plurality of vector source registers are narrowed from a second data element size to a first data element size, where the first data element size is smaller than the second data element size, and A computer program configured to control issuing program logic to issue at least one microoperation to control the processing program logic to store at least one narrowed data element vector, which includes data elements of the plurality of vector source registers narrowed to the first data element size, in a location in a simulated address space, wherein the location in the simulated address space corresponds to a target memory address determined based on the at least one address operand.

21. A storage medium storing a computer-readable code according to claim 18 or a computer program according to claim 20.

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