Semiconductor devices by layer transfer

Abstract

The integrated circuit is formed on a single-crystal silicon carbide substrate, or a composite substrate having a top layer of single-crystal silicon carbide (and optionally a bottom layer of polycrystalline silicon carbide or a sacrificial material). The active layer (which may be an oxide such as Ga2O3) is epitaxially grown on the substrate, and the active elements are formed on the active layer. Handles are bonded to the top surface of the active elements. At least a portion of the substrate is removed from the back of the integrated circuit.

Description

[Technical Field]

[0001] Related applications This application is a continuation of U.S. Provisional Patent Application No. 63 / 584,661, filed on 22 September 2023 and entitled “Semiconductor Devices”, a continuation of U.S. Application No. 18 / 394,688, entitled “Semiconductor Devices”, granted on 27 August 2024 as U.S. Patent No. 12,074,195, entitled “Semiconductor Devices”, a continuation of U.S. Application No. 18 / 628,178, entitled “Semiconductor Devices”, and a continuation of U.S. Application No. 18 / 830,089, entitled “Semiconductor Devices”, filed on 5 April 2024, all of which are incorporated herein by reference for all purposes. [Background technology]

[0002] High-power semiconductor devices operating at high voltages (e.g., over 1.3kV) have been fabricated using various types of semiconductor materials. For example, Schottky diodes using silicon carbide (SiC) material have replaced silicon (Si) in high-power applications such as power conversion and automotive electronics. Recently, beta-phase gallium oxide (β-Ga2O3) has become available as a standalone technology and is being used to form high-power Schottky diodes (potentially with improved performance and lower cost) as an equivalent SiC alternative. SiC is a wide-bandgap (WBG) semiconductor compared to Si. By leveraging the fundamental advantages gained by WBG, it can be engineered to improve high-power performance. Similarly, semiconductors can potentially outperform SiC and further improve device performance as the bandgap increases. Various polytopes of gallium oxide (Ga2O3) semiconductors have bandgap ranges of 4.5eV to 5.0eV (E) compared to the bandgap of SiC (approximately 3.2eV) and Si (approximately 1.1eV). gThis increased band gap can be advantageously used to improve the on-state resistance of the diode (i.e., reduce losses) and increase the blocking voltage capability (i.e., improve isolation). [Overview of the project] [Problems that the invention aims to solve]

[0003] Despite intensive development of high-voltage β-Ga2O3 diodes and transistors, fundamental limitations still exist for widespread acceptance in high-power applications. [Means for solving the problem]

[0004] In some embodiments, the techniques described herein relate to a method for manufacturing an integrated circuit, the method comprising: preparing a composite substrate having an upper substrate layer containing single-crystal silicon carbide and a lower substrate layer containing polycrystalline silicon carbide; epitaxially growing an active layer on the upper substrate layer; forming active elements in and on the active layer; bonding handles to the upper surfaces of the active elements; and removing the lower substrate layer.

[0005] In some embodiments, the techniques described herein relate to a method for manufacturing an integrated circuit, the method comprising: preparing a substrate containing single-crystal silicon carbide; epitaxially growing an active layer containing an oxide on the substrate; forming active elements in and on the active layer; bonding handles to the upper surfaces of the active elements; and removing at least a portion of the substrate from the back surface of the integrated circuit.

[0006] In some embodiments, the techniques described herein relate to a method for manufacturing an integrated circuit, the method comprising: preparing a composite substrate having an upper substrate layer comprising single-crystal silicon carbide and a lower substrate layer comprising a sacrificial material capable of forming structural supports for the formation of an integrated circuit device; forming a single-crystal transition layer on the upper substrate layer; epitaxially growing an active layer on the single-crystal transition layer; forming active elements in and on the active layer; bonding handles to the upper surfaces of the active elements; and removing the lower substrate layer.

[0007] Embodiments of this disclosure will be described with reference to the accompanying drawings. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic cross-sectional view of a vertical multilayer semiconductor diode device according to an exemplary embodiment. [Figure 2A] This is a simplified band diagram of a vertical multilayer semiconductor diode device according to several embodiments. [Figure 2B] This is a plot of the trend of the critical electric field that can be supported with respect to the semiconductor bandgap energy. [Figure 2C] This is a plot of specific on-resistance versus breakdown voltage for silicon, silicon carbide, and gallium oxide semiconductors. [Figure 3] A and B are schematic diagrams of the substrate and drift layer of a vertical multilayer semiconductor diode device, as shown in Figure 1, according to several embodiments, and corresponding plots of exemplary variations in doping concentration (i.e., doping density) as a function of vertical height. [Figure 4] This is a schematic cross-sectional view of a vertical multilayer semiconductor diode device according to another exemplary embodiment. [Figure 5] Figure 4 shows schematic diagrams of the substrate, transition layer, and drift layer of a vertical multilayer semiconductor diode device, as shown in several embodiments, and a corresponding plot of exemplary variations in doping concentration as a function of vertical height. [Figure 6]Figure 4 shows schematic diagrams of the substrate, transition layer, and drift layer of a vertical multilayer semiconductor diode device, as shown in several embodiments, and a related plot of another exemplary variation in doping concentration as a function of vertical height. [Figure 7] Figure 4 shows schematic diagrams of the substrate, transition layer, and drift layer of a vertical multilayer semiconductor diode device as shown in several embodiments, along with related plots of another exemplary variation in doping concentration as a function of vertical height, and further, related plots of an exemplary variation in composition as a function of vertical height. [Figure 8A] This is a schematic cross-sectional view of a vertical multilayer semiconductor diode device according to another exemplary embodiment. [Figure 8B] This is a schematic cross-sectional view of a vertical multilayer semiconductor diode device according to another exemplary embodiment. [Figure 8C] The table shows combinations of n-type and p-type layers having ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 8D] The table shows combinations of n-type and p-type layers having ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 8E] The table shows combinations of n-type and p-type layers having ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 8F] The table shows combinations of n-type and p-type layers having ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 9A] This is an exemplary process flow for designing vertical multilayer semiconductor diode devices according to several embodiments. [Figure 9B] This shows the spatial variation of the conduction and valence band edge energy diagrams of a vertical multilayer semiconductor device oriented along the growth direction, according to an exemplary embodiment. [Figure 9C] This is a spatial variation of the conduction band edge energy diagram of a vertical multilayer semiconductor device oriented along the growth direction, according to an exemplary embodiment. [Figure 10] This is a plot of the variation in yield voltage against the drift region donor doping concentration of β-Ga2O3 at several film thicknesses according to several embodiments. [Figure 11A] This is a plot of the metallic work function energy of several selected metals and the corresponding Schottky barrier energy for the (-201) orientation plane of β-Ga2O3, according to several embodiments. [Figure 11B] This is a semi-logarithmic-linear forward bias current-voltage of a Schottky barrier diode according to several embodiments. [Figure 11C] This is a linear-linear forward bias current-voltage of a Schottky barrier diode according to several embodiments. [Figure 12] This is a plot of the spatial variation of the conduction band energy of the Schottky barrier formed between nickel and the (-201) oriented plane of β-Ga2O3, as a function of the drift donor carrier concentration, according to several embodiments. [Figure 13] This is a plot of the spatial variation of the conduction band energy of the Schottky barrier formed between the nickel-MgO intermediate layer and the (-201) oriented plane of β-Ga2O3, as a function of the drift donor carrier concentration, according to several embodiments. [Figure 14] This is a schematic cross-sectional view of a vertical multilayer semiconductor structure that forms a Schottky barrier diode containing alpha-phase Ga2O3 and alpha-phase (AlxGa1-x)2O3 epitaxially formed on SiC substrates of A-plane, R-plane, and M-plane according to several embodiments. [Figure 15]This is a schematic cross-sectional view of a vertical multilayer semiconductor structure that forms a Schottky barrier diode containing beta-phase Ga2O3 and beta-phase (AlxGa1-x)2O3 epitaxially formed on a C-plane SiC substrate, according to several embodiments. [Figure 16] This is a plot of the spatial variation of the conduction band energy of a Schottky barrier formed between a nickel-5 nm thick MgO interlayer and a (-201) oriented plane of β-Ga2O3, as a function of drift donor carrier concentration, according to several embodiments. [Figure 17] This is a plot of the spatial variation of the conduction band energy of a Schottky barrier formed between a nickel-15 nm thick MgO interlayer and a (-201) oriented plane of β-Ga2O3, as a function of drift donor carrier concentration, according to several embodiments. [Figure 18] This is a schematic current-voltage plot of a vertical multilayer semiconductor Schottky barrier diode, illustrating the characteristics associated with reverse and forward bias operation in several embodiments. [Figure 19A] This is a plot of the quantum mechanical tunneling probability (coefficient) of electron transport in the conduction band, calculated as a function of incident electron energy for a Schottky barrier with a [Ni / β-Ga2O3] multilayer structure, according to several embodiments. [Figure 19B] This is a plot of the quantum mechanical tunneling probability (coefficient) of electron transport in the conduction band, calculated as a function of incident electron energy for a Schottky barrier with a [Ni / MgO / β-Ga2O3] multilayer structure, according to several embodiments. [Figure 19C] This is a plot of the spatial variation of the conduction and valence band edges along the growth direction of a multilayer diode structure containing a [Ni / ZnGa2O4 intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate] in several embodiments. [Figure 19D]This is a plot of spatial variations of the conduction and valence band edges along the growth direction of a multilayer diode structure containing [Ni / ZnGa2O4 intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate], shown near the depletion region formed by the Schottky barrier, according to several embodiments. [Figure 19E] This is an IV plot of a simulation of a multilayer semiconductor Schottky barrier diode under forward bias conditions, according to several embodiments. [Figure 19F] This is an IV plot of a simulation of a multilayer semiconductor Schottky barrier diode under forward bias conditions, according to several embodiments. [Figure 20] The following schematic diagrams illustrate distinct functional regions of a vertical multilayer semiconductor device, including a Schottky metal, an intermediate region, a drift region, a transition region, a substrate, and a rear contact (not shown), according to several embodiments, where the intermediate region and the transition region are formed as multiple semiconductor layers. [Figure 21A] The plots show the spatial variations of the conduction and valence band edges along the growth direction of multilayer diode structures including [Ni / superlattice intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate] in several embodiments, where the finite number of periods in the superlattice intermediate layer includes, for example, a [ZnGa2O4 / Ga2O3] bilayer pair. [Figure 21B] The plots show the spatial variations of the conduction and valence band edges along the growth direction of multilayer diode structures including [Ni / superlattice intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate] in several embodiments, where the finite number of periods in the superlattice intermediate layer includes, for example, a [ZnGa2O4 / Ga2O3] bilayer pair. [Figure 21C] Schematic space band energy diagrams of metal-oxide-metal (MOM) heterostructures in several embodiments are shown, illustrating the band bending due to high field effects for biased MOM structures. [Figure 22]This is a plot of spatial variations of conduction and valence band edges along the growth direction of a multilayer diode structure, including an exemplary [Ni / β-Ga2O3 drift layer / 4H-SiC substrate], as a function of an applied reverse bias, including the barrier reduction effect due to a surface electric field generated across the Schottky barrier potential, according to several embodiments. [Figure 23] The plots show the spatial variation of the conduction band edge along the growth direction of a multilayer diode structure, including an exemplary [Ni / β-Ga2O3 drift layer / 4H-SiC substrate], as a function of an applied reverse bias, including the barrier reduction effect due to a surface electric field generated across the Schottky barrier potential, in several embodiments, and illustrate how the Schottky barrier height and width vary as the surface electric field varies from 0 MV / cm to 1 MV / cm. [Figure 24] The plots of the calculated effective barrier width and potential energy height of a Schottky heterojunction as a function of the applied reverse bias and therefore the surface electric field are shown for several embodiments. [Figure 25] In several embodiments, the calculated quantum mechanical tunneling coefficient is shown as a function of the surface electric field with respect to the incident electron energy passing through the Schottky barrier formed by the [Ni / β-Ga2O3 / 4H-SiC] structure. [Figure 26] In several embodiments, the calculated quantum mechanical tunneling coefficient is shown as a function of the surface electric field with respect to the incident electron energy passing through the Schottky barrier formed by the [Ni / 5nm MgO / β-Ga2O3 / 4H-SiC] structure. [Figure 27] In several embodiments, the calculated component contributions of thermionic emission current and quantum mechanical tunneling current are plotted against the applied surface electric field as a function of several substrate temperatures, and the device structure includes a vertical multilayer semiconductor structure [Ni / β-Ga2O3 / 4H-SiC]. [Figure 28]In several embodiments, the calculated component contributions of thermionic emission current and quantum mechanical tunneling current are plotted against the applied surface electric field as a function of several substrate temperatures, and the device structure includes a vertical multilayer semiconductor structure [Ni / 5nm MgO / β-Ga2O3 / 4H-SiC]. [Figure 29A] Plots of calculated static and optical (high-frequency) dielectric constants for several selected semiconductor and oxide materials according to several embodiments are shown, and the trend of dielectric constant versus material bandgap energy is disclosed. [Figure 29B] Figure 29A shows plots of field-induced conduction band edge barrier drop energy versus material bandgap energy using the optical dielectric constant calculated in several embodiments, with three exemplary field intensities plotted for a 5 μm slab. [Figure 29C] The empirical trends of interface state parameters and minimum surface density of states, which vary as a function of material bandgap energy, are plotted for several embodiments. [Figure 30] The top figure plots the spatial variation of conduction band edges along the growth direction of superlattice delta-doped drift regions using exemplary Ga2O3 host layers bonded to a Ni Schottky barrier and deposited on a SiC substrate, according to several embodiments, while the bottom figure shows a periodic doping layer that intermittently intersperses (puctuates) undoped regions. [Figure 31] The plots of the effective donor doping concentration to thickness ratio g of delta-doped superlattice drift regions are shown for several embodiments. [Figure 32A] This is a plot of the forward bias IV curves for two configurations of a vertical multilayer Schottky barrier diode containing a delta-doped SL Ga2O3 drift region, according to several embodiments. [Figure 32B] This is a plot of the forward bias IV curves for two configurations of a vertical multilayer Schottky barrier diode containing a delta-doped SL Ga2O3 drift region, according to several embodiments. [Figure 33]A and B plot the spatial variation of the conduction band edge along the growth direction of a double barrier intermediate region containing [ZnGa2O4 / Ga2O3 / ZnGa2O4] formed between the Ni metal and the Ga2O3 drift region according to several embodiments, and show the quantized electronic energy states for zero and high surface electric fields applied to this structure. [Figure 34] The calculated electrostatic potential and field lines are plotted for exemplary [metal / Ga2O3 / SiC] vertical structures with outermost Ni contacts surrounded by a separator layer dielectric material, according to several embodiments. [Figure 35A] The image shows a top view of an example of a diode formed on a Ga2O3 / SiC multilayer structure using a circular Schottky barrier metal and a circular field plate metal contact, according to several embodiments. [Figure 35B] The cross-sectional view shows an example of a diode formed on a Ga2O3 / SiC multilayer structure using a circular Schottky barrier metal and a circular field plate metal contact, according to several embodiments, where the top field plate contact is separated from the surface of the Ga2O3 drift layer using a separation layer. [Figure 36] The calculated electrostatic potential and field lines are plotted for exemplary [metal / Ga2O3 / SiC] vertical structures with an outermost Ni contact surrounded by a separator layer dielectric material and a further field plate located on the separator layer, and electrically in contact with a Schottky barrier contact, according to several embodiments. [Figure 37A] A schematic top view of multiple close-packed circular Schottky barrier metal contacts separated by a fixed radius, according to several embodiments, is shown. [Figure 37B] Figure 37A is a cross-sectional view of the structure showing the relationship between the Schottky barrier metal, the field plate contact, the separation layer, the drift layer, the substrate, and the rear ohmic contact according to several embodiments. [Figure 38A]The process flow for forming an upper Schottky metal mesa region on an epitaxial drift layer formed on a substrate is schematically shown according to several embodiments. [Figure 38B] The process flow for forming an upper Schottky metal mesa region on an epitaxial drift layer formed on a substrate is schematically shown according to several embodiments. [Figure 38C] The process flow for forming an upper Schottky metal mesa region on an epitaxial drift layer formed on a substrate is schematically shown according to several embodiments. [Figure 39A] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39B] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39C] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39D] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39E] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39F] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39G] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 40] This is a two-dimensional thermal model of a vertical multilayer semiconductor diode used to solve conduction-dominant heat transfer due to convection and radiation occurring at the boundary, according to several embodiments. [Figure 41] This is a plot of the temperature-dependent thermal conductivity of single-crystal SiC and Ga2O3 materials according to several embodiments. [Figure 42]This is a steady-state thermal distribution contour map of a 2D diode model composed of a Ga2O3 drift layer and a Ga2O3 substrate with electrical conductivity and low thermal conductance. The steady-state current induces ohmic heating within region F8, and the metal contacts are connected to a thermal reservoir. [Figure 43] The steady-state thermal distribution contour plots of several embodiments of a 2D diode model composed of a Ga2O3 drift layer and an electrically conductive and high thermal conductance SiC substrate are shown, where the steady-state current induces ohmic heating within region F8, and the metal contacts are connected to a thermal reservoir. [Figure 44] The following are plots of transient heat transfer and dissipation rates in multilayer semiconductor diodes with respect to forward bias current pulses in several embodiments, comparing Ga2O3 and SiC substrate configurations. [Figure 45] This is a two-dimensional thermal model of a vertical multilayer semiconductor diode, configured as a mesa-type drift region and used to resolve conduction-dominant heat transfer due to convection and radiation occurring at the boundary, according to several embodiments. [Figure 46] These are steady-state thermal distribution contour plots of a 2D diode model composed of a mesa-type Ga2O3 drift layer and a Ga2O3 substrate with electrical conductivity and low thermal conductance, according to several embodiments. The steady-state current induces ohmic heating within region F8, and the metal contacts are connected to a thermal reservoir. [Figure 47] The steady-state thermal distribution contour plots of several embodiments of a 2D diode model composed of a mesa-type Ga2O3 drift layer and an electrically conductive and high-thermal-conductance SiC substrate are shown, where the steady-state current induces ohmic heating within region F8, and the metal contacts are connected to a thermal reservoir. [Figure 48] The absolute energy alignment of the conduction and valence bands with respect to the vacuum energy is plotted for the surface orientation dependence of β-Ga2O3 and for Si polar and C polar 4H-SiC C-plane surfaces according to several embodiments. [Figure 49]The following are plots of the spatial conduction band energy diagrams near the β-Ga2O3 / Si polar 4H-SiC heterojunction in several embodiments, where the lowest energy quantum confinement electron wavefunction lies below the Fermi energy level. [Figure 50] The cross-sections of the atomic crystal structure of a 4H-SiC polytope along the

[0001] direction according to several embodiments are shown. [Figure 51] The atomic crystal structure configurations of 4H-SiC polytopes shown on C-plane hexagonal surfaces according to several embodiments are shown. [Figure 52] This is a cross-sectional view of the monoclinic β-Ga2O3 crystal structure along the [-201] direction according to several embodiments. [Figure 53] The oxygen sublattice arrangement on the (-201)β-Ga2O3 surface according to several embodiments is shown. [Figure 54] Several embodiments show a Si or C hexagonal sublattice on a 4H-SiC(0001) surface. [Figure 55] Several embodiments show the oxygen hexagonal sublattice on the surface of (-201)β-Ga2O3. [Figure 56] The surface orientations and polarities of two slabs containing (-201) oriented β-Ga2O3 and 4H-SiC (Si polar or C polar) are shown according to several embodiments. [Figure 57A] The atomic arrangements of bulk 4H-SiC crystals having a Si polar surface and a SiC surface, which are preferentially terminated with Si atoms comprising a first oxygen adsorption atomic layer, are shown according to several embodiments. [Figure 57B] The atomic arrangements of bulk 4H-SiC crystals having a C polar surface and a SiC surface, preferentially terminated with Si atoms comprising a first oxygen adsorption atomic layer, are shown according to several embodiments. [Figure 57C] The atomic arrangements of bulk 4H-SiC crystals having a Si polar surface and a SiC surface, preferentially terminated with C atoms, comprising a first oxygen adsorption atomic layer and a second Ga adsorption layer, are shown according to several embodiments. [Figure 57D]The atomic arrangements of bulk 4H-SiC crystals having a C polar surface and a SiC surface, preferentially terminated with C atoms, comprising a first oxygen adsorption atomic layer and a second Ga adsorption layer, are shown according to several embodiments. [Figure 57E] Several embodiments demonstrate possible atomic arrangements on a deliberately miscut 4H-SiC(0001) surface as a template for further Ga2O3 film growth, and the subsequent formation of epitaxial Ga-O bonds. [Figure 57F] The images show a cross-section of a miscut 4H-SiC(0001) crystal that creates a film-forming surface tilted with respect to the 4H-SiC crystal axis, using multiple steps according to several embodiments, and creating a ledge on the SiC surface. [Figure 57G] This is an exemplary process flow for heterogeneous deposition of oxide semiconductors onto a pre-selected surface orientation of a SiC substrate, according to several embodiments, and illustrates process steps for manipulating the substrate and / or oxide semiconductor surface species and state as preparation for the oxide epitaxy and / or metal deposition sequence of the device structure. [Figure 57H] This is an exemplary process flow for heterogeneous deposition of oxide semiconductors using a growth interruption method to improve film quality, according to several embodiments. [Figure 58] The images show a series of complete reflection fast electron diffraction (RHEED) images due to azimuth rotation around the rotation axis of epitaxial growth in several embodiments. The long, sharp RHEED streaks indicate the atomic-level flatness and high crystalline quality of the 2 μm Si-doped β-Ga2O3(-201) oriented film deposited on a 0-degree miscut n+4H-SiC(0001) substrate. [Figure 59] These are a series of RHEED images obtained by azimuth rotation around the rotation axis of epitaxial growth. In some embodiments, long, sharp RHEED streaks indicate the atomic-level flatness and high crystal quality of a 2 μm Si-doped β-Ga2O3(-201) oriented film deposited on a 4-deg miscut n+4H-SiC(0001) substrate, and RHEED dots represent electron beam transmission through the step edge. [Figure 60] Figures A and B show the in-situ laser reflectances used for epitaxial deposition of β-Ga2O3(-201) aligned films on n+4H-SiC(0001) substrates in several embodiments. The periodic thickness oscillations shown in the experimental data in Figure 60B are a result of a constant Ga2O3 growth rate initially deposited on the bare n+SiC substrate. [Figure 61A] The X-ray diffraction symmetric dicrystalline rocking curves of single-crystal β-Ga2O3(-201) oriented films on n+4H-SiC(0001)_0deg miscuts are plotted according to several embodiments, where the sharp β-Ga2O3 peak indicates beta-phase pure growth conditions. [Figure 61B] Contour plots of the reciprocal space map (RSM) of a β-Ga2O3(-201) oriented film on an n+4H-SiC(0001)_0deg miscut, showing the reciprocal space map (RSM) of the asymmetric Bragg SiC(107) peak according to several embodiments. [Figure 61C] Contour plots of the reciprocal lattice space map of β-Ga2O3(-201) oriented films on n+4H-SiC(0001)_0deg miscuts, showing the RSM of the asymmetric Bragg β-Ga2O3(-403) peak in several embodiments. [Figure 62] This is a top view of the atomic arrangement of a Ga2O3 crystal showing the (0001) plane and a hexagonal oxygen sublattice according to several embodiments. [Figure 63] This is a top view of the atomic arrangement of a wurtzite-type phase Ga2O3 crystal exhibiting a (0001) plane and a hexagonal oxygen sublattice according to several embodiments. [Figure 64] These are schematic diagrams of the bulk and surface regions of an oxide epitaxial layer according to several embodiments, in which hydrogen-like (hydrogenic) impurities are arranged within the structure. [Figure 65] This is a plot of the spatial energy band diagrams of Ga2O3 multilayer structures showing the surface depletion effect and the accumulation effect at its surface, according to several embodiments. [Figure 66]A and B are plots of calculated forward bias IV curves for a Schottky barrier diode containing Ni / β-Ga2O3 / 4H-SiC, showing three cases of surface modification of a β-Ga2O3 semiconductor according to several embodiments and their effect on the diode's turn-on voltage. [Figure 67] This plot shows the calculated forward bias IV curves for a series of Schottky barrier diodes, including [high work function metal / β-Ga2O3 / 4H-SiC], illustrating the effects of two cases of surface modification (cleaning and depletion) of β-Ga2O3 semiconductors according to several embodiments and their impact on the diode's turn-on voltage. [Figure 68A] This is an exemplary process flow sequence, according to several embodiments, for fabricating an oxide semiconductor region, subsequently performing surface modification, and then favorably capping it with a high work function metal. [Figure 68B] This is an exemplary manufacturing process flow sequence, according to several embodiments, in which a first metal layer is deposited in situ on a modified surface of an epitaxial oxide layer, followed by further processing steps. [Figure 69] Several embodiments show possible atomic arrangements near a metal oxide heterojunction, where the surface portion of a single-crystal β-Ga2O3 region having epitaxial coordination in an epitaxial metal region is shown together with an interfacial oxygen-terminated layer. [Figure 70A] Several embodiments of a multilayer epitaxial structure including a SiC substrate, an epitaxial semiconducting oxide layer, and an epitaxial metal layer are schematically shown. [Figure 70B] The RHEED images of highly symmetrical surface diffractograms of the structure shown in Figure 70A are shown for several embodiments. [Figure 70C] The RHEED images of highly symmetrical surface diffractograms of the structure shown in Figure 70A are shown for several embodiments. [Figure 70D]The RHEED images of highly symmetrical surface diffractograms of the structure shown in Figure 70A are shown for several embodiments. [Figure 70E] The RHEED images of highly symmetrical surface diffractograms of the structure shown in Figure 70A are shown for several embodiments. [Figure 70F] Figure 70A shows wide-angle X-ray diffraction plots of the completed multilayer structures according to several embodiments. [Figure 70G] High-resolution X-ray diffraction plots of the completed multilayer structure in Figure 70A are shown according to several embodiments. [Figure 71A] The bandgap energy variations with respect to composition of binary and ternary compositions in the form of (Ga2O3)x(ZnO)1-x and (Al2O3)x(ZnO)1-x, suitable for integration with the vertical multilayer semiconductor devices disclosed herein, are plotted according to several embodiments. [Figure 71B] The bandgap energy variations with respect to composition of binary and ternary compositions in the form of (Ga2O3)x(MgO)1-x and (Al2O3)x(MgO)1-x, suitable for integration with the vertical multilayer semiconductor devices disclosed herein, are plotted according to several embodiments. [Figure 72] The bandgap energy variations with respect to composition of ternary and quaternary compositions in the form of (ZnxMgO1-x)Ga2O4 and (ZnxMgO1-x)Al2O4, suitable for integration with the vertical multilayer semiconductor devices disclosed herein, are plotted according to several embodiments. [Figure 73] The bandgap energy variations with respect to composition of ternary and quaternary compositions in the form of (AlxGaO1-x)2ZnO4 and (AlxGaO1-x)2MgO4, suitable for integration with the vertical multilayer semiconductor devices disclosed herein, are plotted according to several embodiments. [Figure 74] This is a spatial energy band diagram of a [metal / n+Ga2O3 / 4H-SiC / metal] multilayer structure showing the effect of donor doping concentration in the 4H-SiC region according to several embodiments. [Figure 75] This is a spatial energy band diagram of a [metal / n+Ga2O3 / 4H-SiC / metal] multilayer structure showing the effect of donor doping concentration in the 4H-SiC region according to several embodiments. [Figure 76] This is a cross-sectional view of a portion of a device, including an epitaxial oxide region, a Schottky metal contact, and a dielectric isolation region, according to several embodiments. [Figure 77] This is a plot of the spatial energy band diagram of a heterojunction formed between an oxide semiconductor drift region and a heterogeneous oxide film or material region forming a separation region, according to several embodiments. [Figure 78A] This is a table of calculated dielectric constants for a series of exemplary oxide and fluoride materials compatible with the vertical multilayer device structures disclosed herein, according to several embodiments. [Figure 78B] This is a model of electrostatic interaction between equal but oppositely charged charges located separately in two different dielectric materials, according to several embodiments. It shows symmetric equipotential lines distributed between +Q and -Q charges in the case of equal dielectric material slabs. [Figure 78C] This is a model of electrostatic interaction between equal but oppositely charged charges located separately in two different dielectric materials, according to several embodiments. It shows asymmetric equipotential lines distributed between +Q and -Q charges in the case of slabs made of different dielectric materials. [Figure 78D] This is a model of electrostatic interaction between equal but oppositely charged charges located separately in two materials, according to several embodiments. It shows a symmetrical distribution of the electric field magnitude as a line distributed between the +Q and -Q charges in the case of equal dielectric constant material slabs. The concept of dielectric screening is demonstrated to this disclosure using UWBG materials with different dielectric constants. [Figure 78E]This is a model of electrostatic interaction between equal but oppositely charged charges located separately in two materials, according to several embodiments. It shows the asymmetric distribution of the electric field magnitude as a line distributed between +Q and -Q charges in the case of slabs of materials with different dielectric constants. The concept of dielectric screening is demonstrated to this disclosure using UWBG materials with different dielectric constants. [Figure 78F] These are plots of the parallel EY electric field component and the perpendicular EX electric field component near the heterointerface of the electrostatic model structures shown in Figures 78D and 78E, respectively, according to several embodiments. [Figure 78G] These are plots of the parallel EY electric field component and the perpendicular EX electric field component near the heterointerface of the electrostatic model structures shown in Figures 78D and 78E, respectively, according to several embodiments. [Figure 79] This is a two-dimensional electrostatic model of an exemplary multilayer semiconductor diode structure, including a lower electrode, a substrate, a drift layer, and a field plate electrode embedded within an isolation region dielectric, according to several embodiments. The field plate electrode is drawn asymmetrically around the longitudinal centerline of the structure, simultaneously simulating a structure without a field plate on the left and a structure with a field plate on the right. The isolation layer dielectric is thick, representing a field plate isolated from the drift region. [Figure 80] This is a two-dimensional electrostatic model of an exemplary multilayer semiconductor diode structure, including a lower electrode, a substrate, a drift layer, and a field plate electrode embedded within an isolation region dielectric, according to several embodiments. The field plate electrode is drawn asymmetrically around the longitudinal centerline of the structure, simultaneously simulating a structure without a field plate on the left and a structure with a field plate on the right. The isolation layer dielectric is thin, representing a field plate isolated from the drift region. [Figure 81] The following are electrostatic simulations of split-field plate designs with thin dielectric spacing according to several embodiments, and the resulting spatial variations in electric field strength, comparing the isolation layers in two cases: low-k dielectric (Figure 81) and high-k dielectric (Figure 82). [Figure 82]The following are electrostatic simulations of split-field plate designs with thin dielectric spacing according to several embodiments, and the resulting spatial variations in electric field strength, comparing the isolation layers in two cases: low-k dielectric (Figure 81) and high-k dielectric (Figure 82). [Figure 83] The following are electrostatic simulations of split-field plate designs with thick dielectric spacing according to several embodiments, and the resulting spatial fluctuations of the electric field strength near the interface between the drift region and the isolation region, comparing the isolation layer in two cases: low-k dielectric (Figure 83) and high-k dielectric (Figure 84). [Figure 84] The following are electrostatic simulations of split-field plate designs with thick dielectric spacing according to several embodiments, and the resulting spatial fluctuations of the electric field strength near the interface between the drift region and the isolation region, comparing the isolation layer in two cases: low-k dielectric (Figure 83) and high-k dielectric (Figure 84). [Figure 85] The following are electrostatic simulations of split-field plate designs with thin dielectric spacing according to several embodiments, and the resulting spatial fluctuations of the electric field strength near the interface between the drift region and the isolation region, comparing the isolation layer in two cases: low-k dielectric (Figure 85) and high-k dielectric (Figure 86). [Figure 86] The following are electrostatic simulations of split-field plate designs with thin dielectric spacing according to several embodiments, and the resulting spatial fluctuations of the electric field strength near the interface between the drift region and the isolation region, comparing the isolation layer in two cases: low-k dielectric (Figure 85) and high-k dielectric (Figure 86). [Figure 87] This is a plot of the magnitude of the electric field generated within the structure at the heterointerface between the drift layer and the isolation layer, extending laterally along the x-direction. The device structure has a thin field plate / isolation layer / drift layer spacing according to several embodiments. Figure 87 is for the case of a low-k dielectric isolation layer, and Figure 88 is for the case of a high-k dielectric isolation layer. [Figure 88]This is a plot of the magnitude of the electric field generated within the structure at the heterointerface between the drift layer and the isolation layer, extending laterally along the x-direction. The device structure has a thin field plate / isolation layer / drift layer spacing according to several embodiments. Figure 87 is for the case of a low-k dielectric isolation layer, and Figure 88 is for the case of a high-k dielectric isolation layer. [Figure 89] These are plots of the spatial variation of potential energy occurring within the structure at the heterointerface, across three horizontal planes, namely slightly above and below the heterointerface between the drift layer and the isolation layer. The device structure is a thin field plate / isolation layer / drift layer spacing, depending on several embodiments. Figure 89 shows the case for a low-k dielectric isolation layer, and Figure 90 shows the case for a high-k dielectric isolation layer. [Figure 90] This is a plot of the magnitude of the electric field generated within the structure at the heterointerface between the drift layer and the isolation layer, extending laterally along the x-direction. The device structure has a thin field plate / isolation layer / drift layer spacing according to several embodiments. Figure 89 is for the case of a low-k dielectric isolation layer, and Figure 90 is for the case of a high-k dielectric isolation layer. [Figure 91] This is a simulation plot investigating the effect of the dielectric constant of the isolation layer on the dielectric constant of the drift region, applicable to thin field-plate isolation in several embodiments. The upper electrode structure includes a right side (rhs) with a field plate and a left side (lhs) without a field plate. The maximum electric field at the heterointerface between the drift layer and the upper electrode (or isolation layer) is calculated for the rhs and lhs portions of the electrode as a function of the dielectric constant of the isolation layer. [Figure 92] Figure 91 is a plot obtained from calculations showing the ratio γ of the maximum electric field with and without a field plate in several embodiments. [Figure 93] A two-dimensional electrostatic model is shown, used to simulate the effect of the dielectric constant of the separation layer in the case of a simple upper metal mesa-type contact, according to several embodiments. [Figure 94]In some embodiments, the plot of the maximum surface electric field at the heterointerface between the isolation layer (or upper metal) and the drift layer surface is shown as a function of the dielectric constant of the isolation layer, illustrating the electric field screening effect of the high-k dielectric isolation layer. [Figure 95] This is a photograph of a fabricated wafer containing multiple vertical device structures showing Ni Schottky barrier metal patterns used in exemplary designs according to several embodiments. The rear contacts are not processed in this stage and exhibit the transparent properties of the material. [Figure 96A] In some embodiments, alternative device designs, referred to herein as "T-channel" designs, are presented. [Figure 96B] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96C] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96D] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96E] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96F] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96G] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96H] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 97]The following are exemplary device configurations according to several embodiments, and the device configuration shown in Figure 96A is repeated to form an array of devices on a common SiC substrate. [Figure 98A] Examples of devices having the “T-channel” design described with respect to Figure 96A, with the addition of a transition layer, an intermediate layer, or both, are shown according to several embodiments. [Figure 98B] Examples of devices having the “T-channel” design described with respect to Figure 96A, with the addition of a transition layer, an intermediate layer, or both, are shown according to several embodiments. [Figure 98C] Examples of devices having the “T-channel” design described with respect to Figure 96A, with the addition of a transition layer, an intermediate layer, or both, are shown according to several embodiments. [Figure 99] This is a comparison of the absolute energy scales of conduction and valence electron edge energy alignment for N-polar and Ga-polar GaN surfaces, Ga-polar and O-polar Pna21 Ga2O3 surfaces, monoclinic β-Ga2O3(-201) surfaces, and SI-polar and C-polar 4H-SiC surfaces according to several embodiments. [Figure 100A] This shows possible combinations of polarity-mixed multilayer semiconductor structures containing [GaN / Ga2O3 / 4H-SiC] according to several embodiments. [Figure 100B] This shows possible combinations of polarity-mixed multilayer semiconductor structures containing [GaN / Ga2O3 / 4H-SiC] according to several embodiments. [Figure 100C] This shows possible combinations of polarity-mixed multilayer semiconductor structures containing [GaN / Ga2O3 / 4H-SiC] according to several embodiments. [Figure 100D] This shows possible combinations of polarity-mixed multilayer semiconductor structures containing [GaN / Ga2O3 / 4H-SiC] according to several embodiments. [Figure 101A] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101B]Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101C] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101D] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101E] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101F] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 102A] A table is shown illustrating combinations of n-type and p-type layers with ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 102B] A table is shown illustrating combinations of n-type and p-type layers with ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 102C] A table is shown illustrating combinations of n-type and p-type layers with ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 103] This is an exemplary manufacturing process flow in which, according to several embodiments, an epitaxial Ga2O3 layer is formed on a SiC substrate, followed by the creation of a GaN template layer and the growth of an optional GaN epitaxial layer. According to some embodiments, this structure is then processed to form Schottky metal electrodes (multiple possible). [Figure 104] This is a double-crystal X-ray diffraction plot showing a symmetric W-2q scan of an epitaxial multilayer structure in which Ga polar wurtzite-type GaN is formed on the final surface of a β-Ga2O3(-201) epitaxial layer formed on a SiC or sapphire C-plane substrate, according to several embodiments. [Figure 105A] The images show plots of the spatial energy band diagrams for vertical multilayer semiconductor devices containing [Ni / Ga polar GaN / β-Ga2O3(-201)N drift / n+4H-SiC] in several embodiments, where the polarization-induced band curvature is due to the thickness of the top layer of Ga polar GaN, and simulations were performed for three GaN layer thicknesses. [Figure 105B] The images show plots of the spatial energy band diagrams for vertical multilayer semiconductor devices containing [Ni / Ga polar GaN / β-Ga2O3(-201)N drift / n+4H-SiC] in several embodiments, where the polarization-induced band curvature is due to the thickness of the top layer of Ga polar GaN, and simulations were performed for three GaN layer thicknesses. [Figure 105C] This is a plot of the spatial valence band energy profile near the [Ni / Ga polar GaN / β-Ga2O3] region, showing the quantum confinement heavy hole wavefunction state of at least eight energy levels at the GaN interface, according to several embodiments. [Figure 105D] This is a plot of a series of simulations of the spatial conduction band energy near the [Ni / Ga polar GaN / β-Ga2O3] region, showing the variation in electron barrier height as a function of GaN layer thickness, according to several embodiments. [Figure 105E] Figures 55-58 show plots of the calculated maximum conduction energy barrier height as a function of the GaN layer thickness for the device structures in several embodiments. [Figure 106A] This is a schematic cross-section of a vertical multilayer semiconductor stack. The outermost surface portion of the oxide layer, which indicates surface roughness, is shown. [Figure 106B]This is a schematic cross-section of a vertical multilayer semiconductor stack. It shows the outermost surface portion of the oxide layer, planarized after epitaxial growth to demonstrate a lower surface roughness, according to several embodiments. [Figure 107] A series of simplified cross-sectional views of semiconductor devices or structures illustrating exemplary layer transfer processes according to several embodiments are shown. [Figure 108A] A simplified cross-sectional view of an example of a semiconductor device shown in Figure 107 illustrates an exemplary layer transfer process according to several embodiments. [Figure 108B] A simplified cross-sectional view of an example of a semiconductor device shown in Figure 107 illustrates an exemplary layer transfer process according to several embodiments. [Figure 109A] A simplified cross-sectional view of another example of a semiconductor device shown in Figure 107 illustrates an exemplary layer transfer process according to several embodiments. [Figure 109B] A simplified cross-sectional view of another example of a semiconductor device shown in Figure 107 illustrates an exemplary layer transfer process according to several embodiments. [Figure 110A] A series of simplified cross-sectional views illustrating the formation of exemplary semiconductor devices using a composite substrate, based on several embodiments, are shown. [Figure 110B] A series of simplified cross-sectional views illustrating the formation of exemplary semiconductor devices using a composite substrate, based on several embodiments, are shown. [Figure 110C] Simplified perspective views of exemplary semiconductor devices shown in Figures 110A and 110B, according to several embodiments, are shown. [Figure 110D] Simplified cross-sectional views of exemplary semiconductor devices shown in Figures 110A and 110B, according to several embodiments, are shown. [Figure 110E] Simplified cross-sectional views of other examples of semiconductor devices shown in Figures 110A and 110B are shown according to several embodiments. [Figure 110F]Simplified perspective views of other examples of the semiconductor device shown in Figures 110A and 110B are shown according to several embodiments. [Figure 110G] Simplified cross-sectional views of another example of a semiconductor device shown in Figures 110A and 110B, which is a flip-chip configuration comprising an integrated circuit receiver or interposer board or wafer, according to several embodiments. [Modes for carrying out the invention]

[0009] In the following description, similar reference numerals indicate the same or corresponding parts throughout the drawings.

[0010] This disclosure describes a semiconductor device in which an oxide active layer(s) is formed on a substrate containing silicon carbide, which is epitaxially formed. The substrate may be a single-crystal SiC wafer or a composite substrate containing a single-crystal layer (e.g., single-crystal SiC or oxide) on a bottom layer (e.g., polycrystalline SiC). Part or all of the substrate is removed from the semiconductor device (after the formation of the oxide active layer(s) and other active layer elements as epitaxial semiconducting oxides). Partial or complete removal of the substrate allows for the formation of other material layers (e.g., thermal conductive layers or regions) on or near the bottom surface of the bottom oxide active layer. (Furthermore, an optional electrical insulating material layer or a material layer with a wide bandgap may be formed between the substrate and the active layer.) The removal of part or all of the substrate is performed using a layer transfer technique in which a handle (e.g., a handle wafer, polycrystalline SiC, sintered ceramic, ceramic plate, metal foil, alumina, high-melting-point metal, boron nitride (BN), graphite, or diamond-like material) is bonded to the upper surface of a structure formed on the substrate. (The handle provides structural support to prevent damage to the semiconductor device during subsequent processing.) The combined wafer structure (i.e., the original substrate, the handle, and the active layer between them) can then be processed to remove all or part of the substrate by bottom processing.

[0011] In some embodiments, the thermal conductive layer can be polycrystalline SiC, deposited microcrystalline diamond, copper, aluminum nitride, etc., which have a higher thermal conductivity than the substrate and are therefore better suited to satisfying heat dissipation requirements. Thus, a substrate with the best compatibility for forming the epitaxial semiconducting oxide of the oxide active layer(s) can be selected without being constrained by heat dissipation problems. Then, a thermal conductive layer can be selected to improve heat dissipation.

[0012] Furthermore, in some embodiments, the handles can be removed before or after dicing the individual IC chips (which mainly consist of oxide active layers, thermal conductive layers, optional interconnection layers, and other related layers). In this case, structural support for the remaining layers can be provided by the remaining portion of the substrate (if not completely removed) or by a second handle transferred onto the bottom surface of the remaining semiconductor device.

[0013] Furthermore, the substrate removal function is compatible with the use of composite substrates including a base layer and a surface layer. The surface layer can be a high-quality single-crystal SiC layer suitable for forming epitaxial semiconducting oxides of the oxide active layer(s), while the base layer can be a lower-quality (i.e., lower-quality than the surface layer) structural layer made from a less restrictive material than the surface layer (e.g., a bulk layer of polycrystalline SiC). Thus, composite substrates can be less expensive than substrates made entirely of single-crystal SiC layers. In some cases, the quality of the base layer is less important because it is removed after it no longer needs to provide structural support for the layers formed on top of it.

[0014] This disclosure also describes semiconductor diode devices comprising at least one epitaxial oxide material deposited on a silicon carbide (SiC) substrate, wherein the epitaxial oxide material forms an epitaxial oxide layer (or drift layer) and a metal layer (e.g., an epitaxial metal layer) on the epitaxial oxide layer. In some embodiments, the materials of the metal layer and the epitaxial oxide layer are selected to form a Schottky junction. The epitaxial oxide material advantageously comprises a wide band gap (e.g., about 2.5 eV to about 10 eV, or about 3 eV to about 10 eV, or about 4.5 eV to about 7 eV).

[0015] In some embodiments, the semiconductor devices described herein include layers in addition to the epitaxial oxide layer (or drift layer) on the SiC substrate. For example, an epitaxial transition layer can be formed between the SiC substrate and the epitaxial oxide layer. In some cases, the transition layer can provide intermediate level doping between the substrate and the epitaxial oxide layer and / or control interfacial strain, thereby affecting the electronic and structural properties of the semiconductor diode device, as further described herein. In another example, an intermediate layer can be formed between the epitaxial oxide layer and a metal layer. The intermediate layer can alter the Schottky barrier properties, as further described herein, thereby affecting the electronic properties of the semiconductor diode device, such as the turn-on voltage and / or reverse breakdown voltage. In some cases, the structure may include both a transition layer and an intermediate layer. The intermediate layer and the transition layer may each be a single layer or may include multiple material layers, such as a superlattice layer or a chirp layer.

[0016] Furthermore, in some cases, the semiconductor diode devices described herein may include an isolation layer surrounding the metal layer. The isolation layer may be advantageous in reducing surface current and controlling the electrostatic vector field of the device described herein. The isolation layer may include a material having a higher band gap than the material of the epitaxial oxide layer (or drift layer), and may be crystalline (e.g., an epitaxial material), amorphous, or polycrystalline. The dielectric constant of the isolation layer material may be lower or higher than that of the epitaxial oxide layer (or drift layer). In some cases, the isolation layer is an oxide. In some cases, the isolation layer is an epitaxial layer formed on the epitaxial oxide layer (or drift layer).

[0017] The materials, structures, and methods described herein can be used in two-terminal, three-terminal, or other multi-terminal semiconductor devices, such as Schottky barrier (SB) diodes, p / n junction diodes, PIN diodes, transistors, switches, high-power switches, RF switches, varactors, light-emitting devices, semiconductor devices having quantum wells or superlattices, and semiconductor devices having composition (or doping density) gradients.

[0018] The semiconductor devices described herein (e.g., vertical semiconductor diode devices) enable high dielectric breakdown voltages in the off or blocking state (i.e., high breakdown voltages can be greater than 50V, greater than 100V, or between 50V and 10,000V). Essentially, power P is the product of voltage (V) and current (I). For a given operating power, a decrease in current results in the ability to utilize higher voltages. Generally, since current scales with respect to the cross-sectional area of ​​the device or conductor, higher operating voltages result in lower ohmic heating losses (I). 2 R on Lowering the on-resistance (R) makes it possible to miniaturize the device. on Reducing ) further reduces losses.

[0019] As requirements for high-power semiconductor devices operating above 1.3kV become more stringent, there is a need for improved simultaneous size-weight and power (SWaP) metrics. Compact, high-power-density SWaP power conversion configurations present challenges to conventional technologies. Semiconductor devices containing Ga2O3 have been proposed, but this material has low thermal conductivity, meaning that heat, once generated, must often be dissipated using complex thermodynamic arrangements. On the other hand, all-SiC devices currently available exhibit lower breakdown voltages compared to equivalent devices containing Ga2O3 of the same thickness and doping concentration (or conductivity). The terms “doping concentration” and “doping density” are used interchangeably herein.

[0020] This disclosure provides a solution to the above problem and a path to dramatic improvement, comparing a silicon carbide (SiC) substrate with good thermal and electrical conductivity to a device having a SiC epitaxial layer on a SiC substrate, with respect to a given longitudinal thickness and doping concentration (or conductivity), the breakdown voltage V br This includes a hybrid approach that combines layers of semiconducting devices formed from epitaxially deposited oxide materials (e.g., Ga2O3) with increased activity. A further advantage of bonding oxide semiconducting active regions to SiC is the improved flexibility of possible device configurations (i.e., heterojunction engineering). The structures and methods described herein can also enable reductions in manufacturing costs.

[0021] In some examples of semiconductor diode devices including an epitaxial oxide layer on a silicon carbide (SiC) substrate, the SiC substrate can be made from a crystalline polytype of 4H-SiC, 2H-SiC, 6H-SiC, or 3C-SiC. The orientation of the SiC substrate can be C-plane SiC (0001), A-plane SiC (11-20), R-plane SiC (10-12), or M-plane SiC (1-100). Single-crystal SiC has a thermal conductivity of about 300 to 500 W / (m-K), which is significantly higher than other semiconductor substrate materials such as Ga₂O₃ (about 20 to 30 W / (m-K)) or Si (about 100 to 150 W / (m-K)). The high thermal conductivity of SiC is advantageous for high-power electronic device structures epitaxially formed on SiC substrates, as it improves heat dissipation through the substrate.

[0022] In some examples of semiconductor diode devices on a silicon carbide (SiC) substrate, the epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer is made of Ga₂O₃ (e.g., α-phase or β-phase), (Al x Ga 1-x )₂O₃ (e.g., α-phase or β-phase) (wherein 0≦x≦1), Mg x Ga 2(1-x) O 3-2x (wherein 0≦x≦1), Mg x Al 2(1-x) O 3-2x (wherein 0≦x≦1), (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Al y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), Mg x Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), Mgx Al y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Ni x Ga y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Ni x Al y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (In the formula, 0 <x<1、また0<y<1)、または(Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein the formula 0≦x≦1, 0≦y≦1, and 0≦z≦1), or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4 (wherein 0≦(x,y,z)≦1), or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z The formula may contain one or more of the following: (wherein 0 ≤ (p, x, y, z) ≤ 1).

[0023] The oxygen content of the epitaxial oxide materials described herein (e.g., the epitaxial oxide materials described above) can vary in some embodiments. For example, different crystal symmetries of the epitaxial oxide materials described above may result in compositions with varying oxygen content (e.g., having less or more oxygen fractions) compared to the listed compositions. In some cases, the ratio of metal atoms to oxygen atoms may be smaller or larger than that in the compounds described herein, due to defects in the material (e.g., oxygen or metal vacancies and / or interstitial atoms).

[0024] The epitaxial oxide materials described herein (e.g., epitaxial oxide layers (or drift layers), transition layers, intermediate layers, and / or separation layers) can be doped to be p-type or n-type. For example, (Al x Ga 1-x Epitaxial oxides such as 2O3 can be doped to the n-type using exogenous dopants such as Si, Ge, or Sn. In various examples, the dopant may be spatially confined (e.g., in one or more doping layers within a given region). In one example, the dopant may be confined in two or more spatially separated doping layers within a region (e.g., two spatially separated doping layers within a transition layer), or in another example, the doping layers may extend across a region or a portion of a region.

[0025] In some embodiments, any of the epitaxial layers of the structures and devices described herein (e.g., epitaxial oxide layers (or drift layers), transition layers, intermediate layers, and / or separation layers) may include the following:

[0026]

number

[0027] In Material 1, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1. These ranges differ from each other because, for example, some embodiments of Material 1 (represented by the above formula) include binary materials, while other embodiments include binary or ternary materials. In other cases herein, the subscripts in the formula of a material can include or exclude zero and / or 1 to distinguish binary, ternary, quaternary, or other materials. The atomic species of Material 1 may be selected from trivalent A={Al, Ga, RE, Bi, B', In} and divalent B={Ni, Mg, Zn}, wherein O=oxygen, Al=aluminum, Ga=gallium, RE=at least one rare earth (e.g., lanthanide), Bi=bismuth, B'=boron, In=indium, Zn=zinc, Mg=magnesium, and Ni=nickel.

[0028] For example, in the above formula of Material 1, when x=1 / 2, the epitaxial layer of the structure or device described herein may include A₂B₁O₄. Examples of such materials are Al₂Mg₁O₄, Ga₂Mg₁O₄, Al₂Zn₁O₄, Ga₂Zn₁O₄, Al₂Ni₁O₄, Ga₂Ni₁O₄, and RE₂Zn₁O₄.

[0029] In another example, in the above formula of Material 1, when x=1 / 3, the epitaxial layer of the structure or device described herein may include A₂B₂O₅. Examples of such materials are Al₂Mg₂O₅, Ga₂Mg₂O₅, Al₂Zn₂O₅, Ga₂Zn₂O₅, Al₂Ni₂O₅, and Ga₂Ni₂O₅.

[0030] In another example, in the above formula of Material 1, when x=1 / 4, the epitaxial layer of the structure or device described herein may include A₂B₃O₆. Examples of such materials are Al₂Mg₃O₆, Ga₂Mg₃O₆, Al₂Zn₃O₆, Ga₂Zn₃O₆, Al₂Ni₃O₆, and Ga₂Ni₃O₆.

[0031] In another example, in the above formula for Material 1, when x=1 / 5, the epitaxial layer of the structure or device described herein can comprise A2B4O7. Examples of such materials are Al2Mg4O7, Ga2Mg4O7, Al2Zn4O7, Ga2Zn4O7, Al2Ni4O7, and Ga2Ni4O7.

[0032] In another example, in the above formula, when x=3 / 4, the epitaxial layer of the structure or device described herein can comprise A6B1O 10 . Examples of such materials are Al6Mg1O 10 , Ga6Mg1O 10 , Al6Zn1O 10 , Ga6Zn1O 10 , Al6Ni1O 10 , Ga6Ni1O 10 , and RE6Zn1O 10 .

[0033] In other examples, x in the above formula for Material 1 can be any value of 0≦x≦1, 0<x≦1, 0≦x<1, and 0<x<1. For example, more dilute compositions such as 0≦x≦0.1 or 0.9≦x≦1.0 are also possible.

[0034] In some embodiments, any of the epitaxial layers of the structures and devices described herein (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) can comprise the following.

[0035] [Formula]

[0036] For Material 2, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1, and 0≦y≦1, 0<y≦1, 0≦y<1, or 0<y<1. The atomic species of Material 2 can be selected from trivalent A and C selected from two of {Al, Ga, RE, Bi, B', In}, and divalent B={Ni, Mg, Zn}, where O=oxygen in the formula.

[0037] For example, in the above formula for Material 2, when x=1 / 2 and y=1 / 10, the epitaxial layer of the structure or device described in the present specification can be (A 0.1 C 0.9 )2B1O4. Examples of such materials include (Al 0.1 Ga 0.9 )2Mg1O4, (Al 0.1 Ga 0.9 )2Ni1O4, (Bi 0.1 Ga 0.9 )2Mg1O4, (RE 0.1 Ga 0.9 )2Zn1O4, and (RE 0.1 Al 0.9 )2Zn1O4.

[0038] In some embodiments, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described in the present specification can include the following.

[0039] [Formula]

[0040] For Material 3, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1, 0≦y≦1, 0<y≦1, 0≦y<1, or 0<y<1, and 0≦z≦1, 0<z≦1, 0≦z<1, or 0<z<1. The above formula for Material 3 is also constrained such that the sum y+z≦1. The atomic species of Material 3 can be selected from trivalent A, D and C selected from three of {Al, Ga, RE, Bi, B', In}, and divalent B={Ni, Mg, Zn}, where O=oxygen in the formula.

[0041] For example, in the above formula for Material 3, when x=1 / 2, y=18 / 20, and z=1 / 20, the epitaxial layer of the structure or device described in the present specification can be (A 0.9 D 0.05 C 0.05)2B1O4 can be included. Examples of such materials are (Ga 0.9 Al 0.05 In 0.05 )2Mg1O4, (Ga 0.9 Al 0.05 In 0.05 )2Ni1O4, (B’ 0.05 Bi 0.05 Ga 0.9 )2Mg1O4, (RE 0.05 In 0.05 Ga 0.9 )2Zn1O4, and (RE 0.05 Ga 0.9 Al 0.05 )2Zn1O4.

[0042] In some embodiments, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein can include the following.

[0043] [Equation]

[0044] In Material 4, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1, and 0≦y≦1, 0<y≦1, 0≦y<1, or 0<y<1. The atomic species of Material 4 can be selected from trivalent A={Al, Ga, RE, Bi, B’, In} and divalent B and C selected from at least two of {Ni, Mg, Zn}, wherein O=oxygen in the formula.

[0045] For example, in the above formula of Material 4, when x=1 / 2 and y=1 / 4, the epitaxial layer of the structure or device described herein can include A2B 0.25 C 0.75 O4. Examples of such materials are Ga2Mg 0.25 Zn 0.75 O4, Al2Mg 0.25 Zn 0.75 O4, Ga2Mg 0.25 Ni 0.75O4, and Ga2Zn 0.25 Mg 0.75 O4.

[0046] In some embodiments, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein can include the following.

[0047] [Formula]

[0048] In Material 5, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1, 0≦y≦1, 0<y≦1, 0≦y<1, or 0<y<1, and 0≦z≦1, 0<z≦1, 0≦z<1, or 0<z<1. The atomic species of Material 5 may be selected from trivalent A or D selected from at least two of {Al, Ga, RE, Bi, B', In}, and divalent B and C selected from at least two of {Ni, Mg, Zn}, where O=oxygen in the formula.

[0049] For example, in the above formula of Material 5, when x=1 / 2, y=1 / 2, and z=1 / 2, the epitaxial layer of the structure or device described herein can be A1D1B 0.5 C 0.5 O4. Examples of such materials include Al1Ga1Ni 0.5 Mg 0.5 O4, In1Ga1Zn 0.5 Mg 0.5 O4, and RE1Al1Zn 0.5 Ni 0.5 O4.

[0050] In some embodiments, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein can include the following.

[0051] [Mathematical Formula]

[0052] In Material 6, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1. The atomic species of Material 6 can be selected from trivalent A={Al, Ga, RE, Bi, B', In} and divalent B={Ge, Si, Sn}, where in the formula, O=oxygen, Al=aluminum, Ga=gallium, RE=at least one rare earth (for example, a lanthanide), Bi=bismuth, B'=boron, Ge=germanium, Si=silicon, and Sn=tin.

[0053] For example, in the above formula of Material 6, when x=1 / 2, the epitaxial layer of the structure or device described in the present specification may comprise A2B1O5. Examples of such materials are Al2Si1O5, Ga2Ge1O5, Al2Ge1O5, RE2Sn1O5, B'2Ge1O5, and In2Ge1O5.

[0054] For example, in the above formula of Material 6, when x=3 / 4, the epitaxial layer of the structure or device described in the present specification may comprise A6B1O 11 . Examples of such materials are Al6Ge1O 11 , RE6Ge1O 11 , and B'6Si1O 11 .

[0055] In some embodiments, any of the epitaxial layers (for example, the epitaxial oxide layer (or drift layer), the transition layer, the intermediate layer, and / or the isolation layer) of the structures and devices described in the present specification may comprise the following.

[0056] [Mathematical Formula]

[0057] For Material 7, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1. The atomic species of Material 7 can be selected from trivalent A={Mg, Ni, Zn} and divalent B={Ge, Si, Sn}, wherein O=oxygen, Mg=magnesium, Ni=nickel, Zn=zinc, Ge=germanium, Si=silicon, and Sn=tin.

[0058] For example, in the above formula of Material 7, when x=1 / 2, the epitaxial layer of the structure or device described in the present specification may comprise A₁B₁O₃. Examples of such materials are Zn₁Si₁O₃, Zn₁Ge₁O₃, Ni₁Ge₁O₃, Mg₁Sn₁O₃, Mg₁Zn₁O₃, and Ni₁Sn₁O₃.

[0059] For example, in the above formula of Material 7, when x=2 / 3, the epitaxial layer of the structure or device described in the present specification may comprise A₂B₁O₄. Examples of such materials are Zn₂Si₁O₄, Mg₂Ge₁O₄, Ni₂Ge₁O₄, Mg₂Sn₁O₄, Mg₂Si₁O₄, and Ni₂Si₁O₄.

[0060] It should be understood that for any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein, the compositional fraction (e.g., x, y and / or z) of any of the formulas of the materials described herein (e.g., Materials 1 to 7 described above) may vary within the layer from the exact amount. For example, the compositional fraction may vary due to crystal lattice defects (e.g., vacancies, antisite defects, and / or interstitial species) and random fluctuations within the physical composition. Therefore, the compositional fractions of the formulas of the materials described herein can, in some cases, be regarded as the average composition of the layer.

[0061] Furthermore, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein may have a stoichiometric composition of the materials described herein such as Ga₂O₃ (e.g., Materials 1 to 7 described above), or Ga₂O (3-p) (wherein 0 < p < 2 represents an oxygen-deficient composition or a gallium-rich composition) may also be understood to include non-stoichiometric compositions. Another example of a non-stoichiometric composition is Ga (2-q) O₃, wherein 0 < q < 1 represents an oxygen-rich composition and / or a gallium-deficient composition. Any of the oxide compositions (e.g., Materials 1 to 7) described herein can be stoichiometric or non-stoichiometric in the present structures and devices.

[0062] Furthermore, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein may comprise a dilute alloy composition of any of the oxide compositions (e.g., Materials 1 to 7) described herein. A dilute alloy composition is one in which the dilute component of the material is present at a concentration of less than 0.1. For example, one of Materials 1 to 7 can comprise values of x, y, and / or z of less than 0.1, or less than 0.05, or less than 0.01. In some cases, dopant species (e.g., Si, Ge, or Sn) can be incorporated into the materials described herein (e.g., one of Materials 1 to 7 formed in the epitaxial layer) at a composition of less than 0.1, or less than 0.05, or less than 0.01.

[0063] The epitaxial oxide layer may also have crystal symmetry and orientation that enables the formation of an epitaxial layer on a SiC substrate. In some examples, the epitaxial oxide material is selected to have a lattice mismatch with the SiC substrate of less than 10%, or less than 8%, or less than 6%, or less than 5%, or less than 2%. The thickness of the epitaxial oxide layer can be less than the critical layer thickness of the material (below this critical layer thickness, the epitaxial oxide layer may be elastic and strained and substantially coherent with the substrate; above this critical layer thickness, the epitaxial oxide layer relaxes or is partially relaxed). For example, the thickness of the epitaxial oxide layer can be 1 nm to 100 microns, or 100 nm to 10 microns, or 1 nm to 1 micron, or 5 nm to 500 nm.

[0064] In some examples, the semiconductor diode devices disclosed herein include short-period superlattices (SPSLs). The epitaxial oxide layer may include an SPSL, and / or other layers of the device (e.g., a transition layer, or an intermediate layer) may include an SPSL. In some cases, the SPSL includes sub-layers of alternating wider bandgap material and narrower bandgap material (a barrier layer and a well layer, respectively). The thickness of the barrier or well sub-layer in the SPSL can be less than 1 monolayer (ML) to 5 ML, or less than 1 ML to 10 ML, or less than 1 ML to 20 ML. Barrier and / or well sub-layers having a thickness of less than 1 ML or 1 unit cell along the growth direction may be discontinuous in the lateral direction (i.e., parallel to the main surface of the layer).

[0065] In some examples, the semiconductor diode devices disclosed herein include a chirp layer. The epitaxial oxide layer may include a chirp layer, and / or other layers of the device (e.g., a transition layer, or an intermediate layer) may include a chirp layer. The chirp layer is similar to SPSL in that it also includes sublayers of alternating wider bandgap material and narrower bandgap material (a barrier layer and a well layer, respectively), but the chirp layer has sublayer properties that vary throughout the chirp layer. For example, the chirp layer may have two different compositions to form the barrier layer and the well sublayer (Al x Ga 1-x ) may include alternating sublayers of 2O3 (i.e., two different values ​​of x). The barrier sublayer and / or well sublayer vary in thickness through the chirp layer. In another example, the chirp layer is made of (Al to form the barrier sublayer and well sublayer. x Ga 1-x ) may include alternating sublayers of 2O3, and the barrier sublayer and / or well sublayers change composition through the chirp layer. In another example, the chirp layer is (Al to form the barrier sublayer and well sublayer. x Ga 1-x It may include alternating sublayers of 2O3, and the barrier sublayers and / or well sublayers vary in thickness and / or composition through the chirp layer.

[0066] In yet another example, a bulk-like gradient band gap has a band gap energy E that varies along the growth direction z. g It may be incorporated into a device having (z). The variation can be linear or nonlinear, monotonic or non-monotonic along the growth direction. For example, (Al x Ga 1-x The gradient layers of 2O3 may be formed such that the alloy composition x is a function of the growth direction z, such as x(z).

[0067] Digital alloys formed using SPSL or bulk-like alloys are possible, and further variations in effective material properties can be given along the growth direction.

[0068] This specification also describes a method for forming semiconductor diode devices disclosed herein, comprising an epitaxial oxide layer on a silicon carbide (SiC) substrate and a metal layer (such as an epitaxial metal layer) on the epitaxial oxide layer. Such a method may include forming highly crystalline and epitaxial oxide layers on a SiC substrate using epitaxial layer growth techniques, such as molecular beam epitaxy (MBE), gas-source molecular beam epitaxy (GS-MBE), plasma-source MBE (P-MBE), metal-organic vapor deposition (MOCVD), atomic layer deposition (ALD), vacuum laser ablation source, vapor deposition (VPE), gas source, sputtering source, electron beam deposition source, and plasma deposition. Other epitaxial layer growth techniques may also be applicable, ultimately resulting in a highly crystalline oxide film formed on the surface of the substrate.

[0069] In a typical embodiment, an in-situ (out-of-situ) metal layer can be formed (or deposited) on an epitaxial oxide layer. In another embodiment, the in-situ metal layer can be formed directly on the pristine final surface of the epitaxial oxide. Furthermore, the in-situ metal layer can be formed on a deliberately prepared final epitaxial oxide surface. Even further, the metal layer can be formed on a deliberately prepared final epitaxial oxide surface, a process that does not expose the structure or surface to a contaminating environment. Metal layers such as those of elements Ni, Cu, Al, Ti, Pd, Pt, Ir, Er, Gd, Mo, W, Os, and their alloys can be deposited to form a non-epitaxial metal layer using physical vapor deposition techniques, such as MBE, sputtering, pulsed laser deposition, or thermal deposition of metal. Alternatively, or further, an epitaxial metal layer can be formed on the epitaxial oxide layer using an epitaxial layer growth technique (e.g., MBE, MOCVD, or another epitaxial layer growth technique) to form a substantially crystalline first metal layer that is in direct contact with the epitaxial oxide layer to form a metal oxide heterojunction. Further metal or conductive layers may be formed on the final surface of the first metallic crystalline metal layer that forms the metal oxide heterojunction. In some cases, multiple epitaxial and / or non-epitaxial metal layers can be deposited. For example, epitaxial and / or non-epitaxial metal layers can be deposited in different areas of the device to perform different functions. The metal layer can also contain multiple epitaxial and / or non-epitaxial metal layers within the same area of ​​the device, for example, a first layer being a sticking layer and subsequent layers adhering to that sticking layer. In some cases, the metal layer may include a first epitaxial layer, forming a low-defect interface with the semiconductor layer below, and the non-epitaxial metal layer may be deposited on top of the epitaxial metal layer.

[0070] Metal-induced gap states (MIGS) are known in the prior art for metal contacts to semiconductor surfaces. Simply put, MIGS arise from a mismatch of different crystal structures, including metal-oxide semiconductor interfaces, resulting in unfavorable junction configurations at metal-oxide heterointerfaces. The passivation of the aforementioned interfacial dangling bond can be used to reduce the effect of MIGS on Schottky barrier reduction.

[0071] In some embodiments, the semiconductor devices disclosed herein involve a direct and bonding arrangement of bonds across a metal-oxide heterointerface, where a substantially epitaxial (i.e., crystalline) first metal layer is formed on an anionic or cationic oxide surface.

[0072] In some cases, a separation layer can be formed between an epitaxial oxide layer and a metal layer (e.g., an epitaxial metal layer) using epitaxial layer growth techniques (e.g., MBE, MOCVD, or another epitaxial layer growth technique). In some cases, a passivation layer can be formed on the device. The passivation layer may be made of, for example, aluminum oxide (Al2O3), magnesium oxide (MgO), or zinc-magnesium-gallium oxide (Zn x Mg 1-x )Ga2O4, Aluminum-gallium oxide (Al x Ga 1-x )2O3, Nickel-zinc-magnesium-gallium-aluminum oxide (Ni x Zn y Mg 1-x-y )(Ga p Al 1-p )O q Magnesium germanium oxide (Mg) x Ge y O z Alternatively, it may contain silicon dioxide (SiO2), where the subscripts x, y, z, p, and q indicate atomic fractions representing various crystalline, polycrystalline, or amorphous forms.

[0073] In some cases, one or more layers (e.g., an epitaxial oxide layer, an epitaxial metal layer or metal layer, a separation layer, and / or a passivation layer) can be patterned to form a device, for example, using photolithography and etching techniques (e.g., using photoresist, plasma etching, and / or metal lift-off processes). Alternatively, damascene metal patterning can be utilized, where the oxide is used as a trench and then chemically and mechanically polished as needed.

[0074] Figure 1 shows a schematic cross-sectional view of a vertical multilayer semiconductor diode device 100 according to an exemplary embodiment.

[0075] In this example, the semiconductor device 100 is made of silicon carbide (SiC) and has a width w sub and thickness t sub The substrate 110 includes a substrate having the following characteristics. In one example, the substrate 110 is formed from a 4H-SiC polytope of SiC. In another example, the substrate 110 is formed from 2H-SiC, 6H-SiC, or 3C-SiC.

[0076] In some cases, the substrate 110 is a bulk material, such as single-crystal SiC. In some cases, the substrate 110 may include an optional bulk substrate layer 112 and an optional surface layer 114. A substrate 110 including both a bulk substrate layer 112 and a surface layer 114 is referred to herein as a “composite substrate”. For example, the bulk substrate layer 112 may be polycrystalline silicon carbide (SiC) and the surface layer 114 may be a single-crystal layer of SiC. In such a structure, the surface layer 114 may be a thin layer (e.g., 100 nm to 5 microns, or 100 nm to 1 micron) that serves as a template for epitaxial growth, and the bulk substrate layer 112 may be a material having high thermal conductivity and / or selected electrical conductivity (e.g., electrical conductivity or insulation). For example, the surface layer 114 may consist of one or more single-crystal layers of 4H-SiC polytopes of SiC, or it may be 2H-SiC, 6H-SiC, or 3C-SiC. In other examples, the surface layer 114 may consist of one or more single-crystal oxide materials (e.g., Ga2O3, Al2O3, or Al x Ga 1-x )2O3, where 0≦x≦1) may be included in the formula. For example, the surface layer 114 may include any of the oxide materials described herein, for example, any of the compositions of materials 1 to 7.

[0077] Such composite substrates can be formed, for example, by removing layer 114 from a single-crystal substrate (e.g., a single-crystal SiC substrate, or an oxide substrate) and bonding or joining it to a bulk substrate layer 112 (e.g., a polycrystalline SiC, or a bulk layer of another material with high thermal conductivity). In such cases, the single-crystal substrate layer (e.g., SiC, Ga2O3, or Al2O3) can be removed and bonded or joined to the bulk substrate layer 112. In other examples, an epitaxially grown layer (e.g., any of the compositions of materials 1 to 7, or epitaxially grown SiC) can be removed from the grown substrate and bonded or joined to the bulk substrate layer 112. In some cases, the bulk substrate layer 112 can be formed from a material with high thermal conductivity and optionally high electrical conductivity, such as polycrystalline SiC, a metal (e.g., Ni, Al, or Cu), or a ceramic material (e.g., AlN or BN).

[0078] A method for transferring a single crystal surface layer 114 from a donor substrate to a bulk substrate layer 112 involves forming a weak crystal layer or a defective crystal layer (e.g., H) beneath the surface layer 114 (e.g., the surface layer 114 of the donor substrate, or the surface layer 114 which is an epitaxial layer on the donor substrate). + Or He + This may include ion implantation (using Si+ or C ions). The ion-implanted surface can then be bonded to a bulk substrate layer 112. Heat and / or pressure can then be applied to form an optional bonding layer 116, as further described below. Force can then be applied between the donor substrate and the bulk substrate layer 112, so that the structure is separated at the ion-implanted layer (if it is the weakest layer), removing most of the donor wafer but leaving the surface layer 114 bonded to the bulk substrate layer 112. In some cases, the surface of the transferred surface layer 114 can then be smoothed, the composite substrate can be annealed, and / or other processes can be performed to prepare the composite substrate for epitaxial growth.

[0079] In other cases, the bulk substrate layer 112 may be single-crystal SiC, and the surface layer 114 may be a modified, thermally treated, or chemically treated surface region or near-surface region, for example, to reconfigure the surface for epitaxial growth, or to convert it to graphene or oxide on which an epitaxial oxide layer can be grown. The composite substrate may be advantageous because the bulk substrate layer 112 can be fabricated from a less restrictive material than the surface layer 114. To be used as a template for the epitaxial growth of the oxide layer, the surface layer 114 may be a single-crystal material with compatible lattice constants and crystal structure and may have sufficiently high material quality (e.g., may have a low concentration of threading dislocations). Since the bulk substrate layer 112 of the composite substrate does not need to be single-crystal, it may be fabricated from an electrically and thermally conductive material to which the surface layer 114 can be bonded. In this disclosure, substrates of various embodiments may utilize the composite substrate shown in Figure 1.

[0080] In some cases, a thin bonding layer 116 is formed between the bulk substrate layer 112 and the surface layer 114. For example, the bonding layer 116 is made of a metallic or metalloid material (e.g., metallic or metalloid Si, C, or Si × C y It may include compounds. In some cases, the bonding layer 116 may be thermally and electrically conductive. For example, a metallic or semimetallic bonding layer may be formed between a surface layer 114 (e.g., single-crystal SiC) and a bulk substrate layer 112 (e.g., polycrystalline SiC) as a result of surface activation and thermal bonding.

[0081] In some cases, the bulk substrate layer 112 may be thinned after device manufacturing (e.g., by mechanical processes, etching processes, or chemical mechanical polishing) to further reduce the effective electrical and / or thermal resistance of the bulk substrate layer 112. This may be advantageous because the cost of layer 112 may be significantly lower than the cost of a single-crystal, high-quality surface layer 114.

[0082] The longitudinal direction of the multilayer semiconductor device 100 is defined to be approximately perpendicular to the outermost surface 111 of the substrate 110, as indicated by the arrows of dimension "z" which increase upward in the longitudinal direction. Above the SiC substrate 110, and in this example above the outermost surface 111 of the substrate 110, the layer thickness t D An epitaxial drift layer 120 (or drift region) is formed, comprising a semiconductor oxide material having a surface 121. Above the epitaxial drift layer 120, in this case above the surface 121 of the epitaxial drift layer 120, a metal layer 130 (or upper contact region) is formed. In some embodiments, the material properties of the drift layer 120 and the metal layer 130 are selected to form a Schottky potential barrier in the interface region 140 between the metal layer 130 and the epitaxial drift layer 120. In other embodiments, the material properties of the metal layer 130 are selected to form an ohmic contact with the semiconductor device 100. The metal layer 130 can be either an epitaxial metal layer or a non-epitaxial metal layer with a drift layer below it. In some cases, the metal layer 130 is an epitaxial metal layer that forms a low-defect interface with the epitaxial oxide layer 120 (compared to the interface formed between the epitaxial oxide layer 120 and the non-epitaxial metal layer) to form a Schottky barrier junction. The second metal layer 132 forms an ohmic (or nearly ohmic) electrical contact with the substrate 110 on the back surface opposite the outermost surface 121.

[0083] The layer thickness is not shown to scale in Figure 1 or any other figure in this specification showing a schematic cross-sectional view of a vertical multilayer semiconductor diode device. For example, the thickness of the substrate t sub The thickness of the drift layer 120 is t D It can be much thicker. In some cases, the thickness of the substrate t sub The thickness of the drift layer 120 can be 1 mm to 3 mm, or 100 microns to 1 mm, or 10 microns to 500 microns. D This can be 10 nm to 100 microns, or 1 micron to 100 microns.

[0084] As shown in Figure 1, the device 100 may include an ohmic anode contact region 151 ("A") and an ohmic cathode contact region 152 ("C"), which may be formed on or within the metal layer 130 and on or within the metal layer 132, respectively. In one example, the ohmic anode contact region 151 includes the metal layer 130. In one example, the ohmic cathode contact region 152 includes the metal layer 132.

[0085] In one example, the SiC substrate 110 may be doped to be n-type or p-type, thereby conferring a conduction type determined by the charge carriers, either electrons or holes. If the substrate 110 is a composite substrate, the bulk substrate layer 112 and / or surface layer 114 may be doped to be n-type or p-type, thereby conferring a conduction type determined by the charge carriers, either electrons or holes.

[0086] In some cases, the epitaxial drift layer 120 includes a semiconductor oxide material. The epitaxial drift layer 120 may include any of the oxide materials described herein, for example, any of the compositions of materials 1 to 7.

[0087] In various examples, the epitaxial drift layer 120 is made of Ga2O3 or (Al x Ga 1-x It is a semiconductor oxide material in the form of 2O3 (wherein the formula 0≦x≦1).

[0088] In another form, the epitaxial drift layer 120 is Mg x Ga 2(1-x) O 3-2x (wherein the formula 0≦x≦1), or Mg x Al 2(1-x) O 3-2x This refers to a semiconductor oxide material in the form of a ternary oxide, which includes but is not limited to the case where 0 ≤ x ≤ 1 (wherein the formula).

[0089] In another form, the epitaxial drift layer 120 is (Mg x Zn 1-x )z (Al y Ga 1-y ) 2(1-z) O 3-2z wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1, is a semiconductor oxide material in the form of the above formula.

[0090] In another form, the epitaxial drift layer 120 is (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z wherein 0≦x≦1, 0≦y≦1, and 0≦z<1, is a semiconductor oxide material in the form of the above formula.

[0091] In another form, the epitaxial drift layer 120 is (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z wherein 0<x<1, 0≦y≦1, and 0≦z<1, is a semiconductor oxide material in the form of the above formula.

[0092] In some examples, the epitaxial drift layer 120 is Ga₂O₃ (e.g., α-phase or β-phase), (Al x Ga 1-x )₂O₃ (e.g., α-phase or β-phase) (wherein 0≦x≦1), Mg x Ga 2(1-x) O 3-2x (wherein 0≦x≦1), Mg x Al 2(1-x) O 3-2x (wherein 0≦x≦1), (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Aly O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Mg x Ga y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Mg x Al y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Ni x Ga y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Ni x Al y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (In the formula, 0 <x<1、また0<y<1)、または(Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein the formula 0≦x≦1, 0≦y≦1, and 0≦z≦1), or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4 (wherein 0≦(x,y,z)≦1), or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z The formula may contain one or more of the following: (wherein 0 ≤ (p, x, y, z) ≤ 1).

[0093] In other examples, the epitaxial drift layer 120 is doped to be n-type or p-type. In some cases, one or more impurity species may be added to the epitaxial drift layer 120 to exogenously dope the layer. In some cases, the epitaxial drift layer 120 may be a polar material doped via polarization doping.

[0094] In another example, the epitaxial drift layer 120 is formed from β-Ga2O3(-201), and the substrate 110 is formed from C-plane SiC(0001). If the substrate 110 is a composite substrate, the surface layer 114 may include C-plane SiC(0001), and the bulk substrate layer 112 may include polycrystalline SiC.

[0095] In another example, the epitaxial drift layer 120 is formed from β-Ga2O3(-201), the substrate 110 is formed from C-plane SiC(0001), and the oxide is formed on the silicon polar (Si polar) SiC surface.

[0096] Another example has an epitaxial drift layer 120 formed from β-Ga2O3(-201), the substrate 110 is formed from C-plane SiC(0001), and the oxide is formed on the carbon polar (C polar) SiC surface.

[0097] In one example, the epitaxial drift layer 120 is formed entirely or partially from alpha-phase α-Ga2O3 having crystal symmetry group R3m, and the substrate 110 is formed from 4H-SiC. The epitaxial oxide α-Ga2O3 is formed mainly as an A-plane oriented epitaxial film on A-plane oriented 4H-SiC(11-20), R-plane 4H-SiC(10-12), or M-plane 4H-SiC(10-10) surfaces. That is, an A-plane α-Ga2O3 oriented epitaxial film is possible on A-plane, R-plane, and M-plane 4H-SiC surfaces. The SiC surface can be selected from silicon polarity or carbon polarity orientation. The polarity of the surface directly affects the heterojunction formed with the epitaxial oxide, and this epitaxial oxide can be used as a form of polarization control at the interface, and polarization doping can also be easily performed. The epitaxial oxide of the epitaxial drift layer 120 may be nonpolar, semipolar, or polar, depending on the oxide crystal symmetry group and film orientation relative to the substrate surface.

[0098] In one example, the epitaxial drift layer 120 is β-(Al x Ga 1-x )2O3 (0≦x≦1) is formed from. In another example, the epitaxial drift layer 120 is β-(Al x Ga 1-x The substrate 110 is formed from 2O3 (0 ≤ x ≤ 0.3) and from C-plane SiC (0001). The SiC substrates described herein can be silicon-polar or carbon-polar. In the case of a composite substrate, the surface layer 114 can be silicon-polar or carbon-polar single-crystal SiC, and the bulk substrate layer 112 can be another material. This is a potential advantage of composite substrates because the surface layer 114 can be a material that can be used as a template for the epitaxial growth of the oxide layer, and the bulk substrate layer 112 can be made from a less restrictive material.

[0099] Furthermore, SiC substrates may be prepared to be intentionally miscut within the surface to expose multiple atomic steps and terraces. For example, a miscut C-plane 4H-SiC(0001) oriented surface may be prepared to form a miscut angle between 0 and 6 degrees oriented toward the A-plane(11-20). A 4-degree miscut is a standard type of substrate used in conventional techniques for growing epitaxial SiC films on n-type doped 4H-SiC substrates. Several examples of this disclosure provide insight that 4-degree miscut 4H-SiC may be advantageous for improving the crystallographic quality of epitaxial oxides.

[0100] In some cases, the SiC substrate is not miscut, meaning that the surface orientation plane of the substrate is approximately parallel to the crystal plane of the SiC in the substrate. For example, an unmiscut substrate can have an angle between 0 and 1 degree between the surface orientation plane of the substrate and the crystal plane of the SiC in the substrate. For instance, an unmiscut substrate can have a C-plane 4H-SiC(0001) oriented surface with a miscut angle between 0 and 1 degree that is oriented towards the A-plane (11-20).

[0101] In one example, the epitaxial drift layer 120 is α-(Al x Ga 1-x The substrate 110 is formed from 2O3 (0≦x≦1), and is formed from A-plane SiC (1-100), R-plane SiC (2100), or M-plane SiC (1-100). Furthermore, the surface orientation of the SiC substrate having these orientations may be miscut by approximately 0-6 degrees to improve the crystalline properties of the epitaxial oxide. In other cases, the SiC substrate may not be miscut (i.e., have a miscut angle of 0-1 degree).

[0102] In some examples, the composition of the epitaxial drift layer 120 varies in the longitudinal direction. Similarly, the doping concentration may also vary in the longitudinal direction. In various examples, the drift layer 120 may have a combination of (i) a constant doping concentration and a constant composition in the longitudinal direction, (ii) a gradient doping concentration and a constant composition in the longitudinal direction, (iii) a constant doping concentration and a gradient composition in the longitudinal direction, or (iv) a gradient doping concentration and a gradient composition in the longitudinal direction.

[0103] In some embodiments, the epitaxial drift layer 120 may be formed as a superlattice comprising several different or dissimilar oxide materials. In some embodiments, the drift layer 120 may be formed as a chirp layer comprising several oxide materials, the chirp layer being similar to a superlattice with layers whose thickness varies through the drift layer 120. The superlattice or chirp layer may include a wider bandgap material and a narrower bandgap material, respectively, forming a potential energy barrier and a well layer. In some cases, the superlattice or chirp layer of the drift layer 120 may have, longitudinally, (i) a constant doping concentration and a constant composition, (ii) a graded doping concentration and a constant composition, (iii) a constant doping concentration and a graded composition, or (iv) a combination of a graded doping concentration and a graded composition. When the doping and / or composition is graded, the changes in doping and / or composition may be formed by varying the barrier and / or well layer through the drift layer 120. For example, the thickness of the barrier layer and / or well layer can be varied to form a gradient composition through the drift layer 120. In another example, the doping concentration of the barrier layer and / or well layer can be varied to form a gradient doping profile through the drift layer 120. In some cases, the doping concentration, thickness, and / or composition can be varied within one or more barrier layers and / or well layers of the superlattice or chirp layer of the drift layer 120 to form a gradient doping concentration and / or gradient composition.

[0104] In some examples, the configuration may be maintained in which the epitaxial drift layer 120 is formed above the substrate 110, even though one or more layers formed from non-semiconductor oxide materials or non-SiC materials may be formed between the substrate 110 and the drift layer 120. For example, a single-crystal metal layer, a semimetallic layer, or an insulating layer can be formed between the substrate 110 and the drift layer 120. Such layers can be useful for improving contact resistance or for providing a tunnel barrier within the low-resistance (or ohmic) contact between the substrate 110 and the drift layer 120.

[0105] Figure 2A shows a simplified electron energy band diagram 200 of a vertical multilayer semiconductor diode device, where the increasing direction of "z" corresponds to an upward shift in the vertical direction as shown in Figure 1. In this example, the band diagram 200 shows the Schottky barrier junction (SBJ) region 210, the drift region 220, the n-doped substrate 225, and the ohmic junction region 230 corresponding to the ohmic contact (OC) region of the diode device 100, where the drift layer is an n-doped semiconductor oxide material. Schottky metal (SM) and ohmic metal (OM) have high potential energy barriers φ, respectively. SB and a low energy barrier φ C Selected to achieve this. SM and OM may be different metals or the same metal. Valence band E v (z) and conduction band E c The energy of (z) is given as a function of the longitudinal distance z, and the band gap energy E g This is also shown.

[0106] As can be seen from the inspection, at the interface between the equilibrium epitaxial metal layer 130 and the epitaxial drift layer 120, the Fermi energy level E F The Schottky potential barrier φ coincides across the entire interface. SB A depletion region is formed, and the distance z is within the epitaxial drift layer. depl It extends downwards only.

[0107] Figure 2B shows the electron energy band gap E crit Critical field E that can be supported by various semiconductors having g This shows an empirically derived relationship between the two. The avalanche breakdown process by high-energy carrier-induced collision ionization governs the maximum sustainable electric field that the host semiconductor can support (i.e., the critical voltage or breakdown voltage over a finite thickness of the semiconductor is V). br (as defined). The maximum electric field at breakdown (also known as the critical electric field, E) crit (also known as) is the semiconductor bandgap E g It is known that this increases as the bandgap widens. Figure 2B shows selected data and fitted relationships for non-intentionally doped (NID) semiconductors ranging from small ("NBG", e.g., InAs, InP, GaAs, InGaP) to wide ("WBG", e.g., GaN, ZnO, SiC) and ultra-wide bandgap ("UWBG", e.g., diamond, Ga2O3, AlN, ZnGaO). The dashed line 250 is the fit to the data, yielding the power law shown. The solid line 255 is the preferred fit to the WBG and UWBG data, yielding the power law shown. This dependency (solid line 255) is a major determinant for the adoption of wide bandgap (WBG) semiconductors for high-power electronic devices, and, in this disclosure, ultra-wide bandgap (UWBG) semiconductors.

[0108] Figure 2C plots key relationships between the merit indices that describe a given semiconductor. The specific on-resistance per unit thickness of the material.

[0109]

number

[0110] This determines the efficiency or loss of the diode in the conduction state.

[0111]

number

[0112] V br The plot illustrates the fundamental trends of a given semiconductor technology. The plot shows that both WBG 4H-SiC and UWBG β-Ga2O3 are significantly more advantageous than bulk Si, with on-resistance reduced by 3 to 4 orders of magnitude for a given maximum operating voltage. In particular, the devices of this disclosure leverage the advantages of UWBG Ga2O3 to further expand the possible improvements in high-power device design compared to WBG SiC. Shaded bands represent variations in possible material properties such as crystallinity, defects, and carrier mobility. Figure 2C can be used as a guide for designing high-power diode operation and illustrates the trade-off between low loss and high-voltage operation.

[0113] Figure 3A shows a schematic representation of the substrate 110 and drift layer 120 of a vertical multilayer semiconductor diode device as shown in Figure 1, and the doping concentration N as a function of the vertical height z. A,D The diagram shows the corresponding plot 301 of exemplary variations at the donor site and acceptor site (A and D refer to the donor site and acceptor site, respectively). For example, a highly doped n-type (e.g., n + The doped substrate 110 has high N D Concentration (for example, 10 18 cm -3 ~10 20 cm -3 , or 10 19 cm -3 ~10 20 cm -3 ) also has a highly doped p-type (e.g., p + The doped substrate 110 has high N A Concentration (for example, 10 18 cm -3 ~10 20 cm -3 , or 10 19 cm -3 ~10 20 cm -3) has. In this example, there is a discrete change between the drift layer doping concentration 320 and the substrate doping concentration 310 that occurs at the interface 111 between the substrate layer 110 and the drift layer 120. In this example, the drift layer 120 has a lower dopant concentration than the substrate 110. For example, the doped n-type drift layer 120 has 10 15 cm -3 ~10 18cm-3 N D The doped p-type drift layer 120 may have a concentration of 10 15 cm -3 ~10 18 cm -3 N A It may have a concentration. In some embodiments, both the substrate 110 and the drift layer 120 are doped n-type, or both are doped p-type.

[0114] Figure 3B shows a schematic representation of the substrate 110 and drift layer 120 of a vertical multilayer semiconductor diode device as shown in Figure 1, and the doping concentration N as a function of the vertical height z. A,D The example plot 303 shows the corresponding variation at the donor site and acceptor site (A and D refer to the donor site and acceptor site, respectively). In this example, the p-type SiC substrate 110 is N A Concentration 312 (for example, about 10 17 cm -3 ~about 10 20 cm -3 , or about 10 19 cm -3 ~about 10 20 cm -3 ) has, and the n-type drift layer doping concentration 320 is N D Concentration (for example, about 10 15 cm -3 ~about 10 20 cm -3 , or about 10 17 cm -3 ~about 10 20 cm -3 , or about 10 15 cm -3 ~about 10 18 cm -3) has. In such embodiments, a p / n junction is formed between the SiC substrate 110 and the drift layer 120. For example, the drift layer 120 may include epitaxial Ga2O3. In such an example, the metal contact 130 in Figure 1 may be a metal that forms an ohmic contact with the drift layer 120. When the SiC substrate 110 is doped to the p type, the metal 130 may be a metal selected from Ti, Al, Ni, Au, Pt, Mo, and / or Ta, as well as their alloys and layered stacks. The thickness of the drift layer 120 can be about 100 nm to 100 microns, or about 500 nm to about 5 microns, or about 1 micron to about 15 microns, or about 3 microns to about 5 microns. The SiC substrate 110 may be Si polar or C polar and may optionally have a miscut oriented surface to modify the material quality of the oxide. In some examples, the miscut angle can be in the range of 0.5 to 10 degrees, or 1 to 5 degrees, or 1 to 4 degrees. The substrate miscut may be selected to provide steps and terraces to aid oxide epitaxy.

[0115] Figure 4 shows a schematic cross-sectional view of a vertical multilayer semiconductor diode device 400 according to an exemplary embodiment. The device 400 in this example is similar to the device 100 in Figure 1, but the device 400 further includes a transition layer 160 positioned between the substrate 110 and the drift layer 120. In various examples, the intermediate transition layer 160 may be formed from SiC, a semiconductor oxide material, or a combination of both materials. The transition layer 160 has a layer thickness t T It has.

[0116] In some cases, the transition layer 160 comprises a semiconductor oxide material. The transition layer 160 may include any of the oxide materials described herein, for example, any of the compositions of materials 1 to 7. The transition layer 160 may include a single semiconductor oxide composition, or more than one sublayer having different semiconductor oxide compositions, which can be selected from materials 1 to 7 (for example, the sublayers may form a double layer, a multilayer structure, a superlattice, or a chirp layer). In some cases, the transition layer 160 comprises a gradient composition (for example, a linear, stepwise, or chirp composition gradient) comprising one or more of materials 1 to 7. In some cases, the transition layer 160 comprises one or more of materials 1 to 7 that are doped with a single dopant concentration or with a dopant concentration that varies with depth in the transition layer 160.

[0117] In some examples, the transition layer 160 is Ga2O3 (e.g., α-phase or β-phase), (Al x Ga 1-x )2O3 (e.g., α-phase or β-phase) (wherein 0≦x≦1), Mg x Ga 2(1-x) O 3-2x (in the formula, 0≦x≦1), Mg x Al 2(1-x) O 3-2x (In the formula, 0≦x≦1), (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Ga y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Al y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Mg x Ga y O z In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Mg x Al y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Nix Ga y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Ni x Al y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (In the formula, 0 <x<1、また0<y<1)、または(Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein the formula 0≦x≦1, 0≦y≦1, and 0≦z≦1), or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4 (wherein 0≦(x,y,z)≦1), or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z The formula may contain one or more of the following: (wherein 0 ≤ (p, x, y, z) ≤ 1).

[0118] Figure 5 shows a schematic diagram of the substrate 110, transition layer 160, and drift layer 120 of a vertical multilayer semiconductor diode device as shown in Figure 4, and the doping concentration N as a function of the vertical height z. A,D An illustrative plot of the variation is shown.

[0119] In this example, the transition layer doping concentration 560 can have a doping concentration between the substrate doping concentration 510 and the drift layer doping concentration 520 due to discrete changes in the doping concentration between the substrate 110 and the transition layer 160, and between the transition layer 160 and the drift layer 120. In one example, the substrate 110 is n + It's okay to dope (i.e., 10 19 ~1020 cm -3 The transition layer 160 has a doping concentration of n - It is okay to dope (i.e., about 10 18 cm -3 , or 10 17 cm -3 ~10 18 cm -3 (Having a doping concentration of n), the drift layer 120 is n -- It's okay to dope (i.e., 10 15 cm -3 ~10 17 cm -3 (having a doping concentration of ), as a result, it moves vertically upward from the substrate 110 to the drift layer 120, n + From the doping area n -- A transition can occur during the doping region. Similarly, a p-type device can be formed, and the substrate 110 is p + The transition layer 160 is doped with p - Doped, drift layer 120 is p -- These layers are doped with the above doping concentrations of the acceptor, not the donor. In other cases, the substrate 110 is n + or p + It can be doped, and the drift layer 120 is each n (to form a Schottky barrier junction) - or p - The transition layer 160 can be doped, and the transition layer 160 can have a doping concentration between the doping concentration of the substrate 110 and the doping concentration of the drift layer 120. For example, the transition layer 160 may be formed from SiC, and the drift layer 120 may be formed from a semiconductor oxide material. In another example, the transition layer 160 (TL) may be formed from a semiconductor oxide material, and the drift layer 120 may be formed from the same semiconductor oxide material as TL or a different oxide material. In one example, the transition layer 160 may be formed from a material selected to provide a structural matching region between the substrate 110 and the drift layer 120. For example, Mg x Zn y Ni z (Al p ,Ga1-p )O q The transition layer 160, which includes a semiconductor oxide material in the form of [a specific type of material], can be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 can be Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. Another example of a semiconductor oxide material is silicon oxycarbide Si x C y O z It is in the form of a transition layer 160 and can be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. Yet another example of a semiconductor oxide material is silicon oxynitride (Si). x N y O z It is in the form of a transition layer 160 and can be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. Another example of the transition layer 160 is silicon germanium carbide Si. x Ge y C z The material includes a transition layer 160, and therefore, the interface strain formed between the SiC substrate 110 and the drift layer 120 can be controlled, and the drift layer 120 is Ga2O3 or compositionally graded Al x Ga 1-x Contains O3.

[0120] In some cases of structures 400 and 500, the transition layer 160 and the drift layer 120 contain n-type Ga2O3 (e.g., epitaxially deposited single-crystal Ga2O3), and the transition layer doping concentration 560 is at least an order of magnitude higher than the drift layer doping concentration 520. The doping concentration in the transition layer 160 can be constant (as shown in Figure 5) or can be spatially variable in the growth direction (as shown in Figures 6 and 7, and further described later). The doping concentration of the transition layer 160 can be less than or equal to the doping concentration of the SiC substrate 110. The Ga2O3 transition layer 160 can have a thickness of about 10 nm to about 1 micron. The thickness of the Ga2O3 drift layer can be about 1 micron to 100 microns, or about 2 microns to about 15 microns, or about 3 microns to about 10 microns. The SiC substrate 110 can be Si polar or C polar and optionally may have a miscut oriented surface.

[0121] The surface of a SiC substrate or layer can be intentionally terminated with one or more species. For example, intentional surface termination of a SiC surface can substantially include silicon (Si), carbon (C), oxygen (O), or nitrogen (N) termination species. Termination with a single species (e.g., uniform termination) can be advantageously used to seed the epitaxial deposition of semiconductor oxides (or metal oxide films), resulting in interfacial bonding with a lower lattice mismatch (or reduced mismatch, or an acceptable mismatch) compared to when the surface is not terminated with a single species. For example, in a vacuum, a SiC surface can be prepared to form a Si-terminated surface. The Si-terminated surface can then preferentially react with reactive oxygen species to form a -C-Si-O- bond arrangement. Conversely, a C-terminated surface can be prepared so that the reaction with reactive oxygen produces a Si-CO- arrangement at the immediate interface. The oxygen can then readily bond with Ga (or another cation atom) to subsequently form a Ga2O3 single-crystal epitaxial layer.

[0122] Other possible interface layers can also be advantageously used. For example, silicon oxycarbide Si with a transition layer. x C y O z The interface surface including can also be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x Contains O3.

[0123] Alternatively, silicon carbon nitride (Si) can be included in the transition layer. x C y N z The interface surface including can also be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x Contains O3.

[0124] Germanium nitride Ge can be included in the transition layer 160. x N y The interface surface including can also be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x Contains O3.

[0125] Another example of a transition layer oxide is one in the form of magnesium oxide (MgO), which can be included in the transition layer 160 and formed between the SiC substrate 110 and the drift layer 120, where the drift layer 120 is Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. In the case of a 4H-SiC(0001) surface, the thickness of the MgO(111) oriented transition layer can be as thin as a few unit cells.

[0126] Another example of a transition layer oxide is a zinc gallium oxide (e.g., spinel crystal symmetry ZnGa2O4, e.g., having an Fd3m space group) which can be included in the transition layer 160 and formed between the SiC substrate 110 and the drift layer 120, where the drift layer 120 is Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. In the case of a 4H-SiC(0001) surface, the thickness of the ZnGa2O4(111) oriented transition layer may be one or just a few unit cells, or more.

[0127] In other examples, one or more layers formed from non-semiconductor oxide materials or non-SiC materials may be formed between the substrate 110 and the transition layer 160, and / or between the transition layer 160 and the drift layer 120. For example, a single-crystal metal layer, a semimetallic layer, or an insulating layer can be formed between the substrate 110 and the transition layer 160. Such layers can be useful for improving contact resistance or for providing a tunnel barrier to form a low-resistance (or ohmic) contact between the substrate 110 and the transition layer 160.

[0128] Figure 6 shows a schematic diagram of the substrate 110, transition layer 160, and drift layer 120 of a vertical multilayer semiconductor diode device as shown in Figure 4, and the doping concentration N as a function of the vertical height z. A,D Another exemplary variation is shown in related plot 601. Figure 6 shows an example in which the transition layer 160 has a variable doping density (i.e., doping concentration). The transition layer 160 may have a variable doping density that varies longitudinally, perpendicular to the outermost surface of the substrate. In some cases, the variable doping density of the transition layer 160 includes a doping density (e.g., the average doping density of the layer) that is between the doping density of the substrate and the doping density of the drift layer.

[0129] In this example, the transition layer doping concentration 660 has a monotonic gradient in the z direction, starting at a doping concentration lower than (i.e., less than) that of the substrate 110 and ending at a doping concentration approximately equal to that of the drift layer 120. In some cases, the transition layer doping concentration 660 has a monotonic variation, starting at a doping concentration approximately equal to that of the substrate or between the substrate doping concentration 610 and the drift layer doping concentration 620, and ending at a doping concentration approximately equal to that of the drift layer or between the substrate doping concentration 610 and the drift layer doping concentration 620. In one example, the transition layer doping concentration 660 may match the substrate doping concentration 610 at the interface between the substrate 110 and the transition layer 160, and then continuously change to match the drift layer doping concentration 620 at the interface between the transition layer 160 and the drift layer 120. In one example, the change in the transition layer doping concentration 660 may be substantially linear as a function of the vertical height z (see, for example, Figure 6). In another example, the transition layer concentration 660 may change continuously (i.e., without large stepwise changes, e.g., monotonically or nonlinearly) as a function of the vertical height z. In yet another example, the transition layer concentration 660 may change stepwise as a function of the vertical height z. The transition layer 160 in Figure 6 (for example, with respect to the transition layer 160 in Figure 4) may have any of the attributes of the transition layer 160 described above.

[0130] In one example, the initial transition layer doping concentration 660 at the interface between the substrate 110 and the transition layer 160 may differ from the substrate doping concentration 610 (for example, as shown in Figure 6). Similarly, in another example, the final transition layer doping concentration 660 (moving upward in the z direction) at the interface between the transition layer 160 and the drift layer 120 may differ from the drift layer doping concentration 620.

[0131] Referring back to Figure 1, discrete compositional changes, such as those occurring in the SiC substrate 110 and the oxide-based drift layer 120 (e.g., Ga2O3), can cause defects on the interface surface 111, which can affect carrier transport across the heterointerface between the substrate 110 and the drift layer 120 (e.g., discontinuities in the conduction and valence bands can lead to potential energy confinement or barrier and / or electrically active defects and / or crystallographic defects). In some cases, differences in the material properties of the substrate 110 and the drift layer 120 (e.g., lattice constants, crystal symmetry and / or orientation) can also cause through-dislocations to form in the drift layer 120, which can lead to defects at the interface 121 between the drift layer and the layer above it (e.g., the metal layer 130). Defects at interface 121 can affect carrier transport across the heterointerface between the drift layer 120 and the layer above it (e.g., the metal layer 130), potentially affecting, for example, the Schottky barrier diode properties.

[0132] Figure 7 shows a schematic diagram of the substrate 110, transition layer 160, and drift layer 120 of a vertical multilayer semiconductor diode device as shown in Figure 4. Figure 7 also shows the doping concentration N as a function of vertical height z. A,D Related plot 701 of another exemplary variation, and the band gap energy E resulting from varying the composition as a function of vertical height z. G Related plot 702 of the exemplary variation is also shown. In this example, the SiC substrate has a first bandgap energy of approximately 3.2 eV 770. As can be seen from this example, the bandgap energy of the transition layer 160 is 780 eV. G This is close to the first bandgap energy of substrate 110, which is 770, and the bandgap energy of drift layer 120 is 790E. G It increases almost linearly as a function of vertical height up to a value close to . In another example, the changing composition of the transition layer 160 is from the bandgap energy of the substrate 110 to the bandgap energy of the drift layer 120 of 790E G It may be selected to cause a gradual increase.

[0133] In this example, the transition layer doping concentration of 760 is the same as the transition layer doping concentration of 660 in Figure 6, and can have all the same characteristics as described above. Figure 7 shows an example in which the transition layer doping concentration of 760 starts at a doping concentration approximately equal to that of the substrate 110 (substrate doping concentration 710) and ends at a doping concentration approximately equal to that of the drift layer 120 (drift layer doping concentration 720).

[0134] In some cases of structures 400, 600, and 700, the transition layer 160 and the drift layer 120 contain n-type Ga2O3 (e.g., epitaxially deposited single-crystal Ga2O3). In such cases, the doping concentration 660 or 760 in the transition layer 160 is at least an order of magnitude higher than the drift layer doping concentration 620 or 720. The doping concentration 660 or 760 in the transition layer 160 can be constant (as shown in Figure 5) or can be spatially variable in the growth direction (as shown in Figures 6 and 7). If the doping concentration is spatially variable within the transition layer 160, at least one of the values ​​of the doping concentration 660 or 760 in the transition layer 160 is at least an order of magnitude higher than the drift layer doping concentration 620 or 720. For example, the transition layer 160 may include a doping concentration gradient of 660 or 760, and a doping concentration equal to or similar to the drift layer doping concentration of 620 or 720 at the interface between the transition layer 160 and the drift layer 120. In such a case, the doping concentration gradient of 660 or 760 can be increased between the drift layer 120 and the SiC substrate 110 until it is at least an order of magnitude greater than the doping concentration of 720 in the drift layer 120. In other examples, the doping concentration of the transition layer 160 may be higher than the doping concentration of the drift layer 120, and there may be a discrete variation in the doping density between the transition layer 160 and the drift layer 120. In such a case, there may be spatially variable doping concentrations within the transition layer 160 such that some or all of the doping concentrations in the transition layer 160 are at least an order of magnitude higher than the doping concentrations in the drift layer 120. The doping concentration of the transition layer 160 may be less than or equal to the doping concentration of the SiC substrate 110. The Ga2O3 transition layer 160 can have a thickness of approximately 10 nm to approximately 1 micron. The thickness of the Ga2O3 drift layer 120 can be approximately 1 micron to 100 microns, or approximately 2 microns to approximately 15 microns, or approximately 3 microns to approximately 10 microns. The SiC substrate 110 can be Si polar or C polar and optionally may have a miscut oriented surface.

[0135] Figure 8A is a schematic cross-sectional view of a vertical multilayer semiconductor device 800 according to an exemplary embodiment, comprising a substrate 110, a drift layer 120, an intermediate layer 170, and a metal layer 130. In this example, device 800 is similar to device 100 in Figure 1, but further includes an intermediate layer 170 formed from a semiconductor oxide and disposed between the drift layer 120 and the metal layer 130. The intermediate layer 170 has a layer thickness t I In this example, the intermediate layer 170 is formed directly on the outermost surface 121 of the drift layer 120, and the metal layer 130 is formed on the outermost surface 171 of the intermediate layer 170.

[0136] In some cases, the intermediate layer 170 may contain a high carrier concentration to form an ohmic contact between the drift layer 120 and the metal layer 130. For example, if the drift layer 120 is n-type, the intermediate layer 170 may contain a high n-type doping concentration (e.g., N D about 10 19 cm -3 Or 10 20 cm -3 ), or if the drift layer 120 is p-type, a high p-type doping concentration (e.g., N A about 10 19 cm -3 Or 10 20 cm -3 ) may include. In such cases, the doping concentration in the drift layer is lower (e.g., about 10%). 15 cm -3 ~about 10 18 cm -3 , or 10 15 cm -3The doping concentration of the intermediate layer 170 may be at least an order of magnitude higher than the doping concentration of the drift layer 120 to form an ohmic contact with the metal layer 130. Such an ohmic contact may be useful, for example, if a p / n junction exists between other layers of the structure. For example, a p / n junction can be formed using a p-type SiC substrate 110 and an n-type drift layer 120 (e.g., including epitaxial Ga2O3), or between an n-type drift layer and a p-type epitaxial layer, as further described herein. The thickness of the drift layer 120 can be about 1 to 100 microns, or about 3 to 15 microns, or about 3 to 5 microns. The SiC substrate 110 can be Si-polar or C-polar and optionally may have a miscut oriented surface.

[0137] Figure 8B shows a schematic cross-sectional view of a vertical multilayer semiconductor diode device 802 according to an exemplary embodiment. In this example, device 802 is similar to device 800 but further includes a transition layer 160 disposed between the substrate 110 and the drift layer 120, similar to device 400 in Figure 4.

[0138] A further advantage of the epitaxial oxide-SiC hybrid structures described herein is the availability of additional doping methods to form doping regions (e.g., planar doping regions, selective area doping regions, or doping regions via layer depth or thickness) within the host oxide region. For example, SiC can be effectively doped to p-type or n-type using in-situ epitaxial layer growth or post-epitaxial layer growth ion implantation followed by high-temperature recrystallization annealing. Diffusion doping of SiC is not an effective method for post-growth doping and / or selective area doping due to the high SiC bond energy that hinders doping of favorable activated impurity species. In contrast, post-growth diffusion doping can be used to dope oxides (e.g., Ga2O3) and can be very effective. As an example, spin-on-glass dopants can be selectively applied to the surface of Ga2O3 as a blanket layer, or to selected areas, and impurity species can be transported into the oxide material using a diffusion-driven process. A characteristic of oxides is that when dopant species are driven into an oxide with a relatively low thermal budget, they can be activated, for example, using rapid thermal annealing techniques. For example, diffusion-driven dopants can change the conductivity of Ga2O3 from low n-type doping used in drift layers to semi-insulating conductivity using doping species such as Mg, H, Fe, and Zn. In another example, Si or Ge can be used to increase the n-type doping of Ga2O3 by at least an order of magnitude, in some cases. In yet another example, spin-on-glass can be used to provide a surface reservoir of dopant impurities that can be driven into the relevant oxide region. Spin-on dopants can be patterned to provide selective area doping. The lateral and longitudinal range of the doping region can be controlled using diffusion time and temperature. Spin-on-glass materials may include SiO2, GeO2, Fe2O3, B2O3, MgO, P2O5, or hydrogen-containing materials.Accordingly, not only ion implantation or in-situ epitaxial layer doping, but also post-growth diffusion drive processes for doping the epitaxial oxide layer to be n-type or p-type can be used.

[0139] In one example, the intermediate layer 170 has a wider bandgap E than that of the semiconductor oxide material from which the drift layer 120 is formed G is formed of a different semiconductor oxide. In one example, the oxide material of the intermediate layer 170 is selected to improve diode performance characteristics such as turn-on voltage and / or reverse breakdown voltage. In some cases, the intermediate layer 170 adjusts the Schottky potential barrier φ S which in turn changes the performance characteristics of the diode, such as turn-on voltage and / or reverse breakdown voltage. In some cases, the intermediate layer 170 has a correspondingly varying bandgap E G can be formed with a graded semiconductor oxide composition. In another example, the intermediate layer has, for example, (e.g., the Schottky potential barrier φ S by varying it) has a multilayer, superlattice, or chirped layer configuration comprising two or more different semiconductor oxide materials selected to enhance reverse breakdown voltage performance. In some cases, it may be advantageous for the bandgap of the intermediate layer 170 to be larger than the bandgap of the drift layer 120. For example, drift layer 120 can comprise Ga2O3, and intermediate layer 170 can comprise (Al x Ga 1-x )2O3, where 0<x≦1, or where 0<x≦0.3.

[0140] In another example, the intermediate layer 170 has a narrower or smaller bandgap E than that of the semiconductor oxide material from which the drift layer 120 is formed GIt is formed from different semiconductor oxides having the following properties. In one example, the intermediate layer 170 is selected to improve diode performance characteristics such as turn-on voltage and / or reverse breakdown voltage. For example, a material with a narrow bandgap can advantageously form an improved depletion region between the drift layer 120 and the intermediate layer 170 by exhibiting opposite conduction-type charge carriers. For example, nickel oxide (NiO), copper oxide (Cu2O), lithium oxide (Li2O), or composite oxides such as spinel crystal structures NiGa2O4, ZnGa2O4, MgGa2O4 are n-type (Al x Ga 1-x ) can be given p-type properties that can be advantageously used in the heterojunction formed with the 2O3UWBG drift layer 120. Furthermore, ternary or spinel oxides in the form of NiGa2O4, Cu2GaO4 and LiGaO2 may also be used in the intermediate layer 170. As a further example, an intermediate layer comprising multiple layers of p-type NiO / NiGaO formed on Ga2O3 may also be employed. For example, NiGaO can be formed explicitly or by intermixing NiO and Ga2O3 by high-temperature annealing. In some cases, the intermediate layer 170 has a smaller band gap than the drift layer 120, and by band alignment, there is a conduction band that is offset at the interface between the intermediate layer 170 and the drift layer 120. In such cases, even though the intermediate layer 170 has a smaller band gap than the drift layer 120, the intermediate layer 170 can form an electron tunnel barrier between the drift layer 120 and the Schottky metal layer 130.

[0141] The structures in Figures 8A and 8B may include an n-type or p-type 4H-SiC substrate 110, an n-type or p-type epitaxial oxide drift layer 120 (e.g., n-type Ga2O3 or p-type NiO), an optional n-type or p-type intermediate layer 170 (e.g., n-type Ga2O3 or p-type NiO), and a metal contact layer 130 that can form ohmic contact or a Schottky barrier with the intermediate layer 170. Furthermore, an optional n-type or p-type transition layer 160 (e.g., SiC or Ga2O3) may be included as shown in Figure 8B. The polar 4H-SiC substrate may be doped to n-type or p-type using endogenous and / or exogenous dopants, and / or may have n-type or p-type induced charges by polarity. The epitaxial oxide drift layer 120 and the intermediate layer 170 can also be polar in some cases (e.g., using Pna21Ga2O3), in which case they can be doped with endogenous and / or exogenous dopants and / or have n-type or p-type induced charges depending on their polarity. In other cases, the epitaxial oxide drift layer 120 and the intermediate layer 170 can be nonpolar and can be doped to n-type or p-type using endogenous and / or exogenous dopants.

[0142] Figures 8C to 8F show tables representing combinations of n-type and p-type layers having ohmic contacts ("metal S") to a SiC substrate and ohmic or Schottky contacts ("metal E") to an epitaxially grown semiconductor layer, according to several embodiments. The structures shown in Figures 1, 4, 8A, and 8B may include layers having the doping types shown in the respective tables in Figures 8C to 8F. In some cases, the n-type or p-type doping of the SiC (e.g., 4H-SiC) substrate 110 ("substrate" in Figures 8C to 8F) is 1e15cm -3 ~1e21cm -3 , or 1e17cm -3 ~1e20cm -3 , or 1e15cm -3 Less than, or 1e21cm -3It can be super. The n-type or p-type doping of the epitaxial oxide drift layer 120 ("Oxide" in Figures 8C to 8F) (e.g., n-type Ga2O3 or p-type NiO), the intermediate layer 170 ("IL" in Figures 8C to 8F) (e.g., n-type Ga2O3 or p-type NiO), and the transition layer 160 ("TL" in Figures 8C to 8F) are each 1e15cm². -3 ~1e21cm -3 , or 1e16cm -3 ~1e20cm -3 , or 1e15cm -3 ~1e18cm -3 , or 1e15cm -3 Less than 1e20cm -3 It can be super. The "i" (endogenous or not intentionally doped), "n--", or "p--" layer is approximately 1 e15 cm². -3 , or approximately 1 e 15 cm -3 It can have a doping density of less than 1 e 15 cm. The "n-" or "p-" layer is approximately 1 e 15 cm. -3 ~About 1e16cm -3 It can have a doping density of approximately 1 e 16 cm². The "n" or "p" layer is approximately 1 e 16 cm². -3 ~About 1e18cm -3 It can have a doping density of approximately 1 e 18 cm². The "n+" or "p+" layer is approximately 1 e 18 cm². -3 Over, or approximately 1e19cm -3 Over, or approximately 1 e 20 cm -3It is possible to have doping densities of over 100. It will be understood that these ranges can overlap by up to an order of magnitude. In general, increasing the band gap energy of the host material for the same impurity incorporation for doping may substantially lower the activated doping density. Thus, the substrate 110, the epitaxial oxide drift layer 120 (e.g., n-type Ga2O3 or p-type NiO), the intermediate layer 170 (e.g., n-type Ga2O3 or p-type NiO), and the transition layer 160 can each be n-type (e.g., n-, n, n+, etc.), p-type (p-, p, p+, etc.), or i-type (e.g., endogenous, or undoped, and can also be n-- or p--) layers in the structure and device.

[0143] Ohmic contacts to the SiC substrate ("metal S" in Figures 8C-8F) are optional and may be omitted in some cases. For example, the layers of the structure can be patterned and selectively etched so that two or more contacts are created on two or more epitaxial layers of the structure instead of on the back surface of the substrate.

[0144] For example, Figure 8E includes cases where the [polar 4H-SiC110 / epitaxial oxide 120 / interlayer 170 / metal 130] structure is an nnn Schottky metal structure or a ppp Schottky metal structure. In such cases, the Schottky metal contact 130 ("metal E" in Figures 8C-8F) forms a Schottky barrier with the n-type or p-type epitaxial oxide drift layer 120 and the interlayer 170. The resulting structure can be used to form diodes, transistors, or other devices. For example, metal oxide semiconductor field-effect transistors (MOSFETs) can be formed using ion implantation to form doping regions beneath the source and drain contacts (source and drain regions, respectively), and the oxide layer of these structures can be used as a channel region, which is separated from the gate contact (gate region) by a gate oxide. The epitaxial interlayer 170 can form the gate oxide, or in other cases, a non-epitaxial (e.g., sputtered) gate oxide can be deposited. Furthermore, similar structures can be formed using the [polar 4H-SiC110 / transition layer 160 / epitaxial oxide 120 / metal 130] structure shown in Figure 8D, which includes nnn Schottky metal structures or ppp Schottky metal structures.

[0145] In another example, Figure 8E includes cases where the [polar 4H-SiC110 / epitaxial oxide 120 / interlayer 170 / metal 130] structure is an nnp ohmic contact structure, an nnp Schottky metal structure, a ppn ohmic contact structure, or a ppn Schottky metal structure. In such cases, a p / n junction is formed between the epitaxial oxide layer and the interlayer. Furthermore, if a Schottky metal is present, a Schottky barrier is formed with the n-type or p-type interlayer. This Schottky barrier can function to increase or decrease the built-in potential within the device and / or to form wells for 2D electron gas or 2D hole gas, as will be further described below. The resulting structure can be used to form diodes, transistors, or other devices. For example, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be formed using ion implantation to form doping regions beneath the source and drain contacts. In another example of a transistor, the intermediate layer can be patterned and selectively etched to form doping regions beneath the source and drain contacts, and the gate oxide can be formed between the epitaxial oxide drift layer 120 and the gate contact. In other cases, LEDs can be formed using such structures in which the epitaxial oxide and / or polar group III nitride layers emit light. Furthermore, similar structures can be formed using the [polar 4H-SiC110 / transition layer 160 / epitaxial oxide 120 / metal 130] structure shown in Figure 8D, including nnp ohmic contact structures, nnp Schottky metal structures, ppn ohmic contact structures, or ppn Schottky metal structures.

[0146] In another example, Figures 8E and 8F include cases where the [polar 4H-SiC 110 / epitaxial oxide 120 / intermediate layer 170 / metal 130] structure can be a pnn ohmic contact structure, a pnn Schottky metal structure, an npp ohmic contact structure, or an npp Schottky metal structure. In such cases, the p / n junction is formed between the polar 4H-SiC substrate and the epitaxial oxide layer. Furthermore, an optional n-type or p-type transition layer 160 (e.g., SiC, or Ga2O3) can be included between the polar 4H-SiC substrate and the epitaxial oxide layer, and the p / n junction interface can be moved to the interface between the polar 4H-SiC substrate and the transition layer, or to the interface between the transition layer and the epitaxial oxide layer. Furthermore, if a Schottky metal is included, a Schottky barrier can be formed with the n-type or p-type intermediate layer. This Schottky barrier can function as a second built-in potential within the device, and if the potentials are in opposite directions (e.g., forming a back-to-back potential), the structure can, in some cases (e.g., in metal-insulator-semiconductor (MIS) transistor architectures), be used as a transistor or switch. The resulting structure can be used to form diodes, transistors, or other devices. For example, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be formed using ion implantation to form doping regions beneath the source and drain contacts. In other cases, an LED can be formed using such a structure in which the epitaxial oxide and / or polar group III nitride layer emits light. Furthermore, similar structures can be formed using the [polar 4H-SiC110 / transition layer 160 / epitaxial oxide 120 / metal 130] structure shown in Figure 8D, including pnn ohmic contact structures, pnn Schottky metal structures, npp ohmic contact structures, or npp Schottky metal structures.

[0147] In another example, Figures 8E and 8F include cases where the [polar 4H-SiC110 / epitaxial oxide120 / interlayer170 / metal130] structure can be a pnp ohmic contact structure, a pnp Schottky metal structure, an npn ohmic contact structure, or an npn Schottky metal structure. In such cases, a p / n junction is formed between the polar 4H-SiC substrate and the epitaxial oxide layer, and a p / n junction is formed (in the opposite direction) between the epitaxial oxide layer and the interlayer. Furthermore, an optional n-type or p-type transition layer 160 (e.g., SiC, or Ga2O3) can be included between the polar 4H-SiC substrate and the epitaxial oxide layer, and the p / n junction interface can be moved to the interface between the polar 4H-SiC substrate and the transition layer, or to the interface between the transition layer and the epitaxial oxide layer. Furthermore, if a Schottky metal is included, a Schottky barrier is formed with the n-type or p-type interlayer. This Schottky barrier can function to increase or decrease the built-in potential within a device and / or to form wells for 2D electron gas or 2D hole gas, as further described below. The resulting structure can be used to form diodes, transistors, or other devices. For example, a bipolar junction transistor (BJT) can be formed by patterning and selectively etching a structure to form separate contacts in the p-type and n-type layers of an npn or pnp structure. In such a device, metal contacts adjacent to the oxide or intermediate layer can form either the source or drain contact of the BJT, and additional source or drain contacts can be formed. In other cases, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be formed using patterning and selective etching and / or ion implantation of the intermediate layer to form doping regions beneath the source and drain contacts. In other cases, an LED can be formed using such a structure in which an epitaxial oxide and / or polar group III nitride layer emits light.Furthermore, similar structures can be formed using the [polar 4H-SiC110 / transition layer 160 / epitaxial oxide 120 / metal 130] structure shown in Figure 8D, which includes a pnp ohmic contact structure, a pnp Schottky metal structure, an npn ohmic contact structure, or an npn Schottky metal structure.

[0148] Another possible utility of the intermediate layer 170 is the favorable reaction of the Schottky metal 130 with selective alloying regions 141. The selective alloying regions 141 can be formed by rapid thermal annealing or a diffusion process.

[0149] Any of the drift layer 120, transition layer 160, and / or intermediate layer 170 (for example, those of devices 100, 400, 800, or 802 in Figures 1, 4, 8A, and 8B) may include a single epitaxial oxide layer or multiple layers of epitaxial oxide material (e.g., two-layer, three-layer, superlattice, and / or chirp layers). The two-layer, three-layer, and other multilayer structures of layers 120, 160, and / or 170 may include different compositions and / or different doping densities. In different examples, the total number of layers in any of the drift layer 120, transition layer 160, and / or intermediate layer 170 may be 1 to 100, or 1 to 20, or 1 to 10.

[0150] Any of the drift layer 120, transition layer 160, and / or intermediate layer 170 (for example, those of devices 100, 400, 800, or 802 in Figures 1, 4, 8A, and 8B respectively) may comprise a superlattice and / or chirp layer containing an epitaxial oxide semiconductor material. A superlattice, such as a short-period superlattice, includes alternating layers (i.e., barrier layers and well layers) that form a unit cell, and the unit cell is repeated to form the superlattice. A chirp layer is similar to a superlattice in that it also includes alternating layers, but the layer thickness and / or layer composition changes monotonically along the thickness (or growth direction) of the chirp layer. The thickness of each barrier layer, well layer, and / or unit cell within a superlattice or chirp layer can be less than 1 monolayer (ML) to 100ML, or less than 1ML to 20ML, or less than 1ML to 10ML, or less than 1ML to 5ML, or 1ML to 20ML, or 1ML to 10ML, or 1ML to 5ML. Layers with a thickness of less than 1ML may be discontinuous in the transverse direction (i.e., in the direction parallel to the surface of the substrate from which the layer grows).

[0151] By using superlattices to form digital alloys, the barrier layer and well layer of the superlattice have material properties that differ from the material properties of the barrier layer and the material properties of the well layer, resulting in an overall material property (i.e., composite material property) where the superlattice has these properties. Furthermore, by using superlattices, the effects of electrons and / or holes in a device can be modified, for example, by creating a barrier in the flow of electrons and / or holes across the superlattice.

[0152] Furthermore, chirp layers can be used to form digital alloys and to impact electrons and / or holes in devices as described herein. In addition, chirp layers introduce varying material parameters within the chirp layer, such as varying average lattice constants, varying average band gaps, and / or varying average doping densities. For example, chirp layers can be used to form electron blocking layers (EBLs). Chirp layers can also be used to change the lattice constant in a structure, for example, by forming a drift layer on a SiC substrate, where the drift layer has a different lattice constant than SiC.

[0153] Figure 9A shows the desired R ON and V br This document discloses design flow 9900 for achieving target performance of UWBG power devices based on specifications. In practice, a device simulator utilizing a Poisson solver and quantum mechanical model for a specific semiconductor is used to model the performance. This modeling is described in block 9910 (Target R of Schottky barrier "SB" diode). ON and V br Select (), block 9912 (select the bandgap of the drift layer), block 9914 (select the conductivity / doping of the drift layer), and block 9916 (V br This may include selecting the thickness of the drift layer. Flow 9900 targets R before proceeding further. ON This may include decision point 9920 to determine whether it is acceptable. ON If this is unacceptable, the flow returns to block 9914 to re-select the drift layer parameters. ONIf acceptable, flow 9900 proceeds to block 9930 (optional selection of substrate / drift transition layer), block 9932 (selection of Schottky barrier configuration), block 9934 (selection of substrate ohmic configuration), and block 9936 (simulation of design). If the design meets the specifications in block 9940, the device is manufactured in block 9950. If the design does not meet the specifications, the flow returns to block 9912 to re-select the parameters for each layer of the device. 1D, 2D, and 3D simulation tools can be used in combination with the finite element electrostatic solver to describe the electric field distribution within the device structure in detail.

[0154] Figure 9B is the energy band diagram 2000 of a detailed simulation of the conduction and valence band edges of the vertical multilayer semiconductor device shown in Figure 4, and shows the region (from left to right) containing the drift layer 2012 and the transition layer 2014 (β-Ga2O3(-201) in this example) and the Schottky barrier metal 2010 (Ni in this example) that forms the rectifier junction, and the substrate 2016 (Si polar 4H-SiC(0001) in this example). The band diagram was constructed from detailed knowledge of the band structure and absolute electron affinity of each material, which enables the determination of accurate heterojunction offsets. The substrate is n-type doped 4H-SiC.

[0155]

number

[0156] Therefore, the transition layer is n-type β-Ga2O3.

[0157]

number

[0158] Therefore, the drift region is

[0159]

number

[0160] This is the result.

[0161]

number

[0162] An ideal case of nickel Schottky metal with a barrier height of is shown, and the Fermi energy is chosen as the zero-energy reference. The diode is substantially a unipolar device, and the majority carriers are electrons. Holes in the valence band can be negligibly ignored. Furthermore, the detailed band structure of β-Ga2O3 shows that the hole mass is significantly heavier compared to 4H-SiC. The mobility of holes in the valence band is also limited by the flat valence band energy dispersion in crystal momentum space.

[0163] Referring to Band Diagram 2001 in Figure 9C, it can be seen that effective n-type doping of the drift layer has a strong influence on the depletion width of the Schottky potential penetrating the drift region. Band Diagram 2001 is an enlarged view of the energy band values ​​(y-axis) from 0eV to 1.4eV from Energy Band Diagram 2000. Depletion potential Z depl The width of φ affects the reverse bias leakage behavior, SB This determines the thermionic emission process under forward bias. As expected, the size or extent of the depletion region decreases as the doping concentration increases. The ohmic contact layer located directly beneath the substrate (e.g., the ohmic cathode contact region 152 in Figure 4) is not shown in Band Diagram 2001. The energy band diagram 2001 shows the ideal Schottky barrier potential φ arising from the metal-semiconductor junction. SB It also shows that the Schottky barrier energy reduction effect due to image force, etc., has not been demonstrated (this is important, but does not deviate from the main conclusions above).

[0164] In this example shown in Figures 9B and 9C, the doping concentration of the SiC substrate is approximately 10 19 ~about 1020 cm -3 Because of the high concentration of n-type (i.e., n+), the electrical conductivity is high. When the epitaxial layer is deposited on a Si polar surface, the back surface of the substrate is substantially C polar. Ohmic contacts to the C polar surface of the SiC substrate can be formed using Ti, Ti / Al, or nickel. Nickel silicide is formed when a portion of the Ni and Si deposited from the SiC surface region reacts with the Ni. x Si 1-x This can be formed by high-temperature annealing. In some cases, high-temperature processing may cause carbonization of the SiC surface, which is unfavorable for creating ohmic contacts. In one example, a thin Si-based layer (approximately 1-3 nm) can be deposited on the SiC surface, after which Ni can be deposited. This prevents Si loss from the SiC surface, and Ni x Si 1-x It promotes formation. That is, the n+SiC / Si / Ni stack is n+SiC / Ni × Si 1-x The deposition can be heat-treated to form Ni. Alternatively, Ni and / or Si can be deposited in situ by heating. The Schottky barrier potential φ exceeds the limits possible in simple metal-semiconductor junctions. SB To enhance this, it is also possible to insert an intermediate layer (e.g., intermediate layer 170 in Figure 8A or 8B), as further described herein.

[0165] Figure 10 shows L ドリフト = The breakdown voltage V of β-Ga2O3 as a function of n-type doping concentration at selected thicknesses of 0.3, 1, 3, 10, and 30 μm. br Plot 3000 shows that, for a given slab thickness, the yield voltage decreases as the doping density increases, and inflection points 3005, 3010, 3015, 3020, and 3025 are (L ドリフト ,V br ,N d This shows the optimal selection of L. ドリフト If you select =3μm, V br = 1.2kV becomes possible N d = 5 × 1016 cm -3 This is the optimal configuration.

[0166] Generally speaking, the on-resistance of a vertical multilayer semiconductor device under forward bias is mainly N d The breakdown voltage V under reverse bias is determined by [variables]. br is N d It is determined by the thickness of the drift region.

[0167] Figure 11A is a plot of experimental work functions (shown on the x-axis) for various high work function metals preferred for forming Schottky barrier junctions into ultrawide bandgap semiconductor oxide materials, as determined in this disclosure. The energy selection of the work function of the metals is plotted on the left y-axis, with Cu having the lowest value and osmium having the highest. Vacuum energy E vac If we define E as zero, the work function energy WF of the metal is understood to have a value of WF < 0. vac Based on this, the electron affinity X of the conduction band edge of a given semiconductor is A This can be used to compare the absolute energy alignment of metals and semiconductors. In Figure 11A, the ideal Schottky barrier height (φ) of various metals in the case of a metal / β-Ga2O3(-2O1) oriented clean surface is shown. SB ) are plotted as data points on the right y-axis. Selenium (Se) and osmium (Os) have the highest φ SB It provides approximately 1.4 eV. In practice, all the metals listed in this figure can be used to form Schottky barrier diodes, but Ni, Pt, and Pd are particularly stable.

[0168] The unique feature described herein is the β-Ga2O3(-201) oriented surface. As described below, this surface can be advantageously modified so that the surface depletion charge is engineered to produce an improved Schottky barrier diode. By shallowly depleting the n-type doped β-Ga2O3(-201) surface, relative φ for all metals, as shown in the diamond data points, is achieved. SB A significant increase can be achieved. Upon closer examination of Figure 11A, Cu metal / depleted β-Ga2O3(-201) exhibits similar φ to Ir metal / clean β-Ga2O3(-201). SB It can be seen that this can be achieved. Clean surfaces and depletion surfaces are described later in this disclosure. Using any of the metals in Figure 11A, an oxide layer can be formed between the Schottky metal contact layer and the drift layer, as described further herein. For example, the Schottky metal may include platinum, the drift layer may include Ga2O3 (or a different epitaxial oxide as described herein), and an intermediate layer containing PtO2 can be formed between the Schottky metal contact layer and the drift layer. The metal oxide of the intermediate layer (e.g., PtO2, or a metal oxide containing any of the metals in Figure 11A) can be deposited as an oxide (e.g., using MBE, ALD, MOCVD, or another epitaxial or non-epitaxial growth method) or as a metal that is subsequently oxidized to form a metal oxide.

[0169] Figures 11B and 11C show various doping concentrations N, as shown in Figures 9B and 9C. ドリフト The forward bias current-voltage (IV) behavior of a diode formed using Schottky barrier metal (SBM)=Ni deposited on the depletion surface of a β-Ga2O3(-201)n-type drift layer having a thickness of 2 μm is plotted. This structure is deposited on a Si polar 4H-SiC n-type substrate. Referring to Figure 11B at room temperature T=25C, the semi-logarithmic IV plot is approximately V F The forward bias voltage V is used until it turns on at =1V. F It shows an increasing subthreshold current along with φ. SBThermionic emission (TE) transport of electrons exceeding a certain value occurs when the applied forward bias voltage V F Forward conduction current density J TE It governs and follows the following equation.

[0170]

number

[0171] The Richardson constant is,

[0172]

number

[0173] It can be explicitly calculated as follows:

[0174]

number

[0175] is the effective electron mass, n is the ideal constant, q is the electron charge, k B is the Boltzmann constant. Therefore, in the case of conduction where TE is dominant, a strong temperature dependence is expected. In the example in Figures 11B-11C involving Ni / clean β-Ga2O3, the effective electron mass of the drift layer is

[0176]

number

[0177] And as a result, A * = 36A / cm² 2 This is the result. In practice, the ideal factor n can be extracted from a manufactured diode and fitted to the subthreshold slope 4005 in Figure 11B using Equation 1 above. The ideal factor can be in the range of 1 ≤ n ≤ 3 (for example, 1 ≤ n ≤ 2 in some examples), and N ドリフト It depends on.

[0178] Figure 11C shows a linear IV plot of the example in Figure 11B, with a turn-on voltage of 4010.

[0179]

number

[0180] As will be shown later in the differential resistance section, the on-resistance is n-type doping N ドリフト It decreases as increases.

[0181] Figure 12 is an energy band diagram 5000 of a simulation of the conduction band edge of a vertical multilayer semiconductor device having configuration 5050, which includes a substrate layer of SiC(0001) (i.e., SiC with (0001) orientation), a TL of n+β-Ga2O3(-201), a drift layer formed from β-Ga2O3(-201) (i.e., β-phase Ga2O3 with (-201) orientation), and a metal layer formed of Ni(111) (i.e., Ni with (111) orientation). In this example, the Schottky potential barrier value is approximately 1.15 eV, and the drift layer doping is 1 × 10⁻¹⁶, as shown by the five curves plotted in the energy band diagram 5000. 15 ≤N ドリフト ≤ 5 × 10 17 cm -3 It fluctuates within the range of N. The depletion layer width is N as shown in the figure. ドリフト Strongly controlled by, as a result N ドリフト = 5 × 10 17 cm -3 In the case of (curve 5010), a thin quantum mechanical barrier is formed, and carrier transport will be a combination of TE and quantum mechanical tunneling. That is, the total current density J across the barrier. tot The thermionic current J depends on temperature and the peak energy barrier. TE and quantum mechanical tunneling component J tun Having these two components, J tot =J TE +J tun This is the result. N ドリフト → 1 × 10 15 cm -3If the value is small, the width of the depletion barrier is J tun →Decreases to 0. Conversely, quantum tunneling through potential barriers becomes particularly important in the design of high-voltage reverse-bias operation.

[0182] Figure 13 is the energy band figure 6000 of a simulation of the conduction band edge of a vertical multilayer semiconductor device having configuration 6050, which is similar to that shown in Figure 12 except that it includes an additional intermediate layer (IL) with a thickness of 100 angstroms and formed of single-crystal MgO(111) (i.e., MgO in the (111) orientation). The simulation shows that in this example, the inclusion of the intermediate layer increases the Schottky potential barrier to a value of approximately 3.1 eV. Of particular interest is MgO, which exhibits a small electron affinity compared to Ga2O3 and SiC. As expected, drift layer doping is 1 × 10⁻⁶ 15 ≤N ドリフト ≤ 5 × 10 17 cm -3 While the depletion layer width is strongly controlled when it fluctuates between these values, unlike the device in Figure 12, the IL presents a fixed quantum mechanical tunneling barrier against electron transport. The increased barrier potential of the device in Figure 13 can further be used to adjust the diode's turn-on voltage (or threshold voltage). For example, selecting an IL oxide with a large bandgap and low electron affinity results in a large SB potential, which, when used, allows for the engineering design of the diode's turn-on voltage. This is particularly advantageous for creating high-voltage diodes that are less susceptible to low-voltage noise. A large barrier potential is also advantageous for reducing reverse leakage current at high reverse electrical biases and high electric fields.

[0183] The intermediate layer 170 may include an epitaxial semiconductor oxide material formed on the epitaxial drift layer. In some cases, the intermediate layer 170 includes an epitaxial oxide material, and the structure further includes an epitaxial metal layer (e.g., metal layer 130 in Figure 8B) formed on the epitaxial intermediate layer 170. The intermediate layer 170 may include any of the oxide materials described herein, for example, any of the compositions of materials 1 to 7. The intermediate layer 170 may include a single semiconductor oxide composition, or more sublayers having different semiconductor oxide compositions, which can be selected from materials 1 to 7 (e.g., the sublayers may form a two-layer, multilayer, superlattice, or chirp layer). In some cases, the intermediate layer 170 may include a gradient composition (e.g., a linear, stepwise, or chirp composition gradient) containing one or more of materials 1 to 7. In some cases, the intermediate layer 170 contains one or more of materials 1 to 7 that are doped with a single dopant concentration or with dopant concentrations that vary with depth in the intermediate layer 170.

[0184] In some examples, the intermediate layer (e.g., intermediate layer 170 in Figure 8A or Figure 8B) may be formed from or include a material selected from one or more of the following materials: • Epitaxial single crystal, polycrystalline, or amorphous Al2O3 • Epitaxial single crystal, polycrystalline, or amorphous NiO · Epitaxial β-(Al x Ga 1-x )2O3(0≦x≦0.3) (See Figure 8) • Epitaxial α-(Al x Ga 1-x )2O3(0≦x≦1)(See Figure 7) • Epitaxial (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (0≦x,y,z≦1) • Epitaxial Zn x Ga y Oz (0≦x,y,z≦1) ·Epitaxial Zn x Al y O z (0≦x,y,z≦1) ·Epitaxial Mg x Ga y O z (0≦x,y,z≦1) ·Epitaxial Mg x Al y O z (0≦x,y,z≦1) ·Epitaxial Ni x Ga y O z (0≦x,y,z≦1) ·Epitaxial Ni x Al y O z (0≦x,y,z≦1) ·Epitaxial (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (0<x<1 and 0<y<1) ·Epitaxial (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (0≦x,y,z≦1).

[0185] In some examples, the drift layer may be made with the same composition as the intermediate layer, but may have a different doping concentration. In some examples, the drift layer may be made with a different composition from the intermediate layer and may have a different doping concentration.

[0186] Other crystal plane orientations of SiC (e.g., 4H-SiC in particular) can also be favorably used for the epitaxial growth of other oxide compositions and polytopes for the devices, structures, and methods described herein. For example, A-plane, R-plane, and M-plane 4H-SiC substrates can be prepared from bulk-grown single-crystal materials by preferentially dicing along specific crystal planes, followed by chemical mechanical polishing (CMP) to form epitaxy-ready surfaces. Furthermore, some examples may involve epitaxially depositing alpha-phase Ga2O3 films on the aforementioned finely inclined SiC substrate surfaces. The ability to form α-Ga2O3 provides at least two improvements applicable to this disclosure. Firstly, at room temperature, α-Ga2O3 has a larger fundamental band gap energy (E) than β-Ga2O3. g (αGa2O3)=5.4eV>E g (βGa2O3) = 4.7 eV) is observed, which favorably increases the critical field and improves the performance of the diode. Secondly, α-Ga2O3 grown on the A, R, and M surfaces can achieve a complete alloy range when alloyed with Al, thus E g α(Al) x Ga 1-x )2O3 becomes possible. The range of such large bandgap engineering for creating heterojunctions dramatically improves the performance of possible diodes (and other devices such as p / n junction diodes, transistors, switches, varactors, or light-emitting devices) compared to conventional devices.

[0187] Figures 14 and 15 show examples of other vertical multilayer semiconductor device configurations including an intermediate layer according to the present disclosure. Figure 14 shows a SiC substrate oriented in the A-plane, R-plane, or M-plane, an α-Ga2O3 drift layer, and an α-(Al x Ga 1-x An example of structure 7000 is shown, which includes an α-(Al)2O3 intermediate layer (with 0≦x≦1) and a metal layer forming a Schottky barrier. The intermediate layer has an α-(Al)2O3 intermediate layer with a growth direction-dependent alloy content x(z). x Ga 1-x)2O3 gradient alloys are also possible. Figure 15 shows a SiC substrate oriented in the C plane, a β-Ga2O3 drift layer, and β-(Al x Ga 1-x An example of structure 8000 is shown, which includes a β-Ga2O3 intermediate layer (with 0 ≤ x ≤ 0.3) and a metal layer forming a Schottky barrier. In practice, the maximum Al content that can maintain the single-crystal beta phase is x ~ 0.3, or in some cases x = 0.4, which is a heterojunction to x = 0, i.e., β-Ga2O3 / β-(Al x Ga 1-x This represents the maximum band gap that can be implemented as 2O3.

[0188] Figures 16 and 17 are simulation energy band diagrams of two exemplary vertical multilayer semiconductor device configurations having intermediate layer (IL) thicknesses of approximately 50A and 150A, respectively. Both devices include a 4H-SiC substrate, a Ga2O3 drift layer, an MgO intermediate layer, and a Ni metal layer. Drift layer doping is shown by five curves plotted in energy band diagrams 9000 and 10000, resulting in 1 × 10⁻⁶ energy bands. 15 ≤N ドリフト ≤ 5 × 10 17 cm -3 It varies within the range. In some examples, the thickness of the interlayer may be configured to control the quantum mechanical tunneling current, for example, under a reverse bias near the reverse breakdown voltage. In some examples, the thickness of the interlayer may be configured to mitigate the decrease in Schottky barrier height resulting from metal-induced gap states at the metal-interlayer interface. In these examples in Figures 16 and 17, the IL is selected as UWBG MgO and shows the band curvature of the conduction band edge with various drift region dopings for two examples of MgO thickness (50A in Figure 16 and 150A in Figure 17). Figure 16 represents a thin quantum mechanical tunneling barrier, while the thicker barrier in Figure 17 reduces or blocks quantum mechanical tunneling. This design option is advantageous for managing reverse leakage at high voltages and electric fields.

[0189] Figure 18 shows a simplified example of a typical current-voltage characteristic curve 11000 for a vertical multilayer semiconductor device according to this disclosure. Under reverse bias, voltage breakdown (V br The previous leakage current region itself consists of the following three regions, namely, • A thermionic emission region ("thermionic emission region") that occurs in low to medium electric fields, where the current originates from charge carriers with sufficient energy to overcome the potential barrier, • A combination of quantum tunneling and thermionic emission occurring in a medium electric field ("tunneling & thermionic emission combination region"), wherein the current arises from a combination of charge carriers having sufficient energy to overcome the potential barrier (i.e., thermionic emission) and charge carriers passing through the potential barrier by tunneling effect, and the quantum tunneling and thermionic emission combination region. This includes quantum tunneling regions ("QM tunneling regions") that occur in high electric fields, where the current originates from charge carriers that pass through a potential barrier via the tunneling effect.

[0190] In conventional devices, the actual reverse bias breakdown voltage (V br The yield strength in the drift region is determined not only by the device structure, the specific material properties used, and the possible AC leakage paths when exposed to extreme electric fields.

[0191] For example, a simple metal-semiconductor Schottky barrier presents only a potential with limited quantum mechanical barrier height and asymmetric width. In some cases, due to tunneling current, devices with Schottky barrier junctions in extremely high electric fields may exhibit a lower-than-expected reverse breakdown voltage due to barrier drop effects (BLE).

[0192] Furthermore, the breakdown voltage field value and the low, medium, and high field values ​​in Figure 18 can vary depending on the materials and device structure used. For example, the low field can be less than 100 V / cm or less than 1000 V / cm, the medium field can be between 100 V / cm and 1000 V / cm or between 1000 V / cm and 10,000 V / cm, and the high field can be greater than 1000 V / cm or greater than 10,000 V / cm.

[0193] The reverse bias current has a thermionic current component J. TE and quantum mechanical tunneling current component J tun By including the superposition of these, we get the following:

[0194]

number

[0195] In the equation, T(E) is the quantum mechanical (QM) transmission probability as a function of the incident electron energy with respect to the potential barrier, and E f This is the Fermi energy reference of the conduction band energy. Upper and lower bounds of the integral.

[0196]

number

[0197] This ranges from the injection of incident quasi-ballistic electrons into the structure. Figures 19A and 19B show the Fermi level (E F Plots 12000 and 12100, respectively, of the QM tunneling current transmission coefficient / probability T(E) as a function of the injected electron energy for (=0). Insets 12001 and 12101 show the respective energy barriers within the conduction band edge and the electrons passing through each barrier by tunneling effect in these examples. The curves are calculated using the finite element method for piecewise approximations of the spatial potential coupled to the complex transfer matrix for each subdomain, considering the real and imaginary parts of the reflected and transmitted wave functions. Figure 19A shows N ドリフト = 5e16cm-3 In this case, the band structure shown in Figure 9C corresponds to T(E) 12010, showing significant SB penetration below the potential barrier maximum (indicated by arrow 12015), and approaching 1 above this barrier. Note that even for incident energies above the potential maximum, T(E) < 1. The triangular potential represents an asymmetric barrier that suppresses QM interference between the reflected electron wavefunction and the transmitted electron wavefunction. Arrow 12015 corresponds to the height of the Schottky barrier in this example.

[0198] Introducing a wider bandgap IL between the Schottky metal and the Ga2O3 drift layer can be used to effectively increase the potential barrier of the rectifying contact. In Figure 19B, the IL provides a maximum potential barrier of 3.0 eV. A MgO with an electron affinity of (MgO) = -1.0 eV (Eg = 7.8 eV) is selected. While doping of the drift layer has a slight effect on the T(E) characteristics, the thickness of the MgO layer has a dramatic effect on the vibrational behavior observed in Figure 19B. The "soft turn-on" T(E) curve 12110 is affected by the thin MgO layer L IL This is for the case where (MgO)=5nm, and the sharp "turn-on" and narrow resonance T(E) curve 12120 is for thicker L IL This is the case where (MgO) = 10 nm. Referring again to equation (2), we can use T(E) to calculate the reverse leakage current with respect to the surface electric field. The introduction of UWBG IL significantly reduces the reverse leakage current, which is advantageous for applications to high-voltage diodes, for example, by increasing the forward-reverse (on-off) ratio.

[0199] Ni / metal IL=ZnGa2O4NID 10nm / Ge:β-Ga2O35e16cm -3 / TL=Ge:β-Ga2O31e17cm -3 / 1e19cm -3Further examples of ILs containing a ZnGa2O4(111) orientation layer inserted into a device on a 4H-SiC Si polar substrate are shown in Figures 19C and 19D. Figure 19C shows a band diagram 12200 along the growth direction z, and Figure 19D shows a magnified view 12300 of the conduction band near the Schottky barrier (at z=0nm). The IL effectively increases the Schottky barrier potential, which directly affects the performance of the diode, as shown in Figures 19E and 19F. The semi-logarithmic forward bias IV curve plot 12400 in Figure 19E shows that the subthreshold gradient for the metal intermediate substrate structure (MIS) (IL=Zn2Ga2O4) is shifted to a higher voltage compared to the Ni / β-Ga2O3 diode (MS curve) for the clean and depleted β-Ga2O3(-201) surface. The plot 12500 in Figure 19F shows a linear IV forward bias comparison for the three cases from Figure 19E. The introduction of IL also has the effect of increasing the impedance of the device in conduction mode.

[0200] Including an intermediate layer in various embodiments brings about many advantages, including the following: • When the band gap of the intermediate layer is larger than the band gap of the drift region, it has the advantage of improving the turn-on voltage to a higher value; • The advantage of reducing the Schottky potential barrier height from its theoretical expected value is the reduction in the occurrence rate of defects and / or metal-induced gap states (MIGS) between the metal layer and the drift layer. While MIGS may exist between the intermediate layer and the metal layer, their effect on the barrier height is reduced because this interface is separated from the semiconductor / metal Schottky junction interface. The advantage of increasing the reverse breakdown voltage through both thermionic emission and quantum tunneling; and; • A wider bandgap interlayer offers the advantage of spatially separating the metal-induced gap state (MIGS) from the active semiconductor oxide material on the surface of the drift region, which helps maintain the Schottky barrier potential and reduce reverse leakage current.

[0201] The devices and methods of this disclosure utilize the unique insight that by configuring the intermediate layer to present further limitations on the tunnel current, the performance in the high-field region can be improved under reverse bias, and as a result, the reverse breakdown voltage of the device can be further improved.

[0202] In any of the examples described herein, the intermediate layer may include repeating properties. These repeating properties may be repeating compositional variations (e.g., in a superlattice structure) or repeating doping concentration variations (e.g., in the concentration of exogenous dopant species or in the concentration of defects or vacancies within the crystal layer).

[0203] Figure 20 is a schematic cross-sectional view of a vertical multilayer semiconductor device 14000, where the repeatability of the intermediate layer (IL) 1450 or the transition layer (TL) 1460 is achieved by forming the IL and / or TL as a superlattice or multilayer epitaxial stack. The substrate 1400 is SiC, such as 4H polytope. The substrate may have specific micro-inclined surface orientations, i.e., C-plane, A-plane, R-plane, or M-plane, as known in the literature. The micro-inclined planes may be axial or intentionally mis-cut toward a specific crystal plane. For example, the mis-cut angle of the C-plane may range from 0 to 6 degrees. The transition layer 1460 may be a semiconducting oxide, a non-oxide, or a combination thereof. For example, the transition layer 1460 may be silicon germanium carbide (Si), which allows for in-plane lattice constant and strain adjustment to match the drift region composition. x Ge y C 1-x-y ) may include. Other optional TL and IL compositions may include polar or nonpolar semiconductors. For example, nitrogen-polar or metallic-polar aluminum nitride (AlN) may be formed.

[0204] In the example in Figure 20, the superlattice within at least a portion of the IL (or TL) is formed from two repeating sublayers 14010 and 14020 (or sublayers 14030 and 14040 of the TL) with varying thicknesses that cross the intermediate layer. In another example, the superlattice may form a digital alloy. In yet another example, the superlattice may be formed from three or more repeating sublayers of either constant or varying thickness. In various examples, the superlattice may be periodic or aperiodic.

[0205] By using A-face, R-face, and M-face 4H-SiC, α-(Al) with space group R3c is obtained. x Ga 1-x This enables epitaxial selective growth of α-(Al x Ga 1-x Epitaxial growth of )2O3 is possible over the entire alloy range of 0 ≤ x ≤ 1. Therefore, TL or IL is α-(Al x Ga 1-x )2O3 / α-(Al y Ga 1-y ) may include a superlattice of 2O3 (0≦x≦1, 0≦y≦1, and x≠y). This allows the band gap to be adjusted from 4.7eV (x=0) to 8.6eV (x=1) while imposing a conduction band discontinuity of about 4eV on the electron confinement and transport design. (Al x Ga 1-x )2O3 / α-(Al y Ga 1-y Biaxial strain occurs at heterointerfaces due to a mismatch in lattice constants between 2O3 layers, but this can be controlled by selecting an appropriate layer thickness.

[0206] Figure 21A is a simplified energy band diagram 15000 of a vertical multilayer semiconductor device having a structure similar to structure 14000 in Figure 20, and including an intermediate layer formed of a finite-period superlattice with sublayers of ZnGa2O4(111) and β-Ga2O3(-201). Other numbers of layers and / or other combinations of superlattice materials are also possible. The complete conduction and valence energy band diagram 15000 shows the stepped potential barrier (φ) arising from the superlattice structure of the intermediate layer and the Ga2O3 drift layer. S Figure 21B shows the effective φ. S = 2.25eV and N ドリフト = 5e16cm -3 An enlarged energy band diagram 15020 is shown near the metal / SL IL / drift layer. In one example, the superlattice structure is configured such that increasing the equivalent potential barrier reduces the quantum mechanical tunneling transmission coefficient and tunes the thermionic emission onset to a higher turn-on voltage. The increased effective barrier potential energy can also improve the high-temperature performance of the device. Furthermore, as mentioned above, the leakage current associated with quantum tunneling through the potential barrier under reverse bias can be reduced by increasing the effective barrier potential energy using such a structure.

[0207] In practice, Schottky barriers and UWBG intermediate layers can be realized in the devices, structures, and methods described herein, but a phenomenological potential barrier reduction effect (BLE) exists under the influence of high electric fields. In particular, BLE correlates with both the bandgap energy and dielectric constant of the specific material used. Figure 21C shows the bandgap E g (Distance between dashed lines) is provided, and furthermore, it is sandwiched between the two metals 15031 and 15033, so heterojunction φ B A potential barrier with zero bias (V=0) is formed with a thickness L. IL A schematic diagram of the energy diagram 15030 of the semiconductor slab (oxide 15032) is shown. When a bias is applied, the metal-oxide-metal (MOM) structure changes its band diagram as shown in the figure under an electric field E z =V / LIL This generates a rectangular barrier (V=0) which becomes a distorted parallelogram 15035 (V<0) (for example, with some band curvature).

[0208] Electrons injected into the oxide layer from the metal electrode on the left induce equal but opposite positive image charges in the metal. When electrons are injected into the oxide layer at a distance z>0, a Coulomb image force F arises between charges separated by a distance of 2z. im It can be expressed by the following formula.

[0209]

number

[0210] As a result, the electrostatic potential V is expressed by the following equation V im (z) is generated.

[0211]

number

[0212] Clearly, the MOM oxide barrier space potential under bias is composed of (i) a rectangular barrier potential, (ii) a linear electric field, and (iii) an image potential, as follows:

[0213]

number

[0214] Figure 22 shows the ideal Ni / 1e16cm -3 Ga2O3 / n + Ga2O3 / n + The enantiomeric band curvature of an example Schottky barrier, including a 4H-SiC device, is shown. Figure 23 shows the expansion of the band curvature near the potential peak. For UWBG oxides, sensitivity analysis revealed that BLE is available φ B This is shown to be relatively small compared to [another factor].

[0215] BLE is the peak barrier potential φB ΔE can be quantitatively expressed using high-frequency (optical) dielectric constant and applied electric field. バリア It serves to reduce only that much.

[0216] Condition dV 酸化物 The maximum value is obtained when / dz=0, and from the heterointerface

[0217]

number

[0218] Being in a distant location results in the following:

[0219]

number

[0220] Figure 22 shows that an example of a metal Schottky barrier device includes BLE. This example is N ドリフト = 1e16cm -3 φ B This concerns Schottky barrier metals (SBMs) with a voltage of 1.3 eV. n + β - Ga2O3(-2O1) 1e17cm -3 The transition layer is nitrogen-doped n+1e18cm -3 The material was deposited on a 4H-SiC substrate. Band diagrams for zero bias (0V) and reverse bias (4V and 8V) are plotted showing the change in depletion width. Figure 23 shows a magnified view of the conduction band of Figure 22 near the Schottky barrier peak for a series of applied reverse bias voltages and the resulting surface electric field. Band drop effects and band bending are shown.

[0221] Figure 24 shows the effective barrier height reduction energy ΔE バリア (Curve 15110 and the right y-axis) and effective barrier width W バリア (Extracted values ​​of curve 15120 and the left y-axis) Surface electric field E FzPlot it as a function of E. Fz When the depletion field is 0 MV / cm, the internal electric field becomes approximately 52 kV / cm.

[0222] Referring again to Equation 2, the tunneling current also depends on temperature and the transmission coefficient of electrons passing through the barrier as a function of the surface electric field (see Figure 23).

[0223] Figures 25 and 26 show two device configurations (i) Ni SBM / 5e16cm² in Figure 25 -3 Ga2O3 / n+4H-SiC, and (ii) Ni SBM / 5nm MgO IL / 5e16cm² as shown in Figure 26. -3 The quantum mechanical transmission coefficient of Ga2O3 / n+4H-SiC) was calculated, and the device in Figure 26 incorporates a UWBG 5nm MgO intermediate layer. Transmission coefficient T(E e ,E Fz ) is the Fermi energy (E フェルミ (Assuming E is zero) for the incident electron energy E e The potential profile depends on the surface electric field E Fz It depends on E. The tunnel current integral is E e The process is carried out over the range from 0 to the maximum potential energy shown in Figure 23, yielding the curves in Figures 27 and 28.

[0224] Figures 27 and 28 show the total current (J) for each of the two device structures shown in Figures 25 and 26. tot Thermionic current (J) therm ) and tunnel current (J tun Plot the calculated contribution of ). Three exemplary operating temperatures, namely T s The values ​​of 300K, 400K, and 500K are shown, representing the operating temperatures discussed above for the thermal performance of oxide / SiC hybrid devices.

[0225] A closer examination of the curve shown in detail in Figure 27 reveals that the surface electric field E zWhen the critical surface field E is low (≤0.5 MV / cm), it can be seen that the reverse leakage current of a Schottky barrier diode is mainly determined by the thermionic current component. z When the field strength exceeds >0.5 MV / cm, temperature-dependent tunneling current becomes dominant, overwhelming the contribution of thermionic emission. This demonstrates the importance of designing heterojunction Schottky barriers to manage and limit reverse leakage current in high surface field regimes.

[0226] Figure 28 shows an analogy plot of the calculated reverse leakage current for a diode structure in which a UWBG 5nm MgO interlayer is intentionally incorporated between the Schottky metal and the Ga2O3 drift region. Examining the curve in Figure 28 reveals that thermionic emission and tunneling components are dominant at the critical surface field E z A decrease of ≤0.25 MV / cm is shown. However, the absolute reverse leakage currents of both the thermionic and tunneling components are dramatically reduced compared to the case in Figure 27 where the IL is absent. Thus, this disclosure shows that the UWBG intermediate layer may be advantageous in improving the reverse leakage performance of the Schottky barrier diodes disclosed herein.

[0227] From first-principles theoretical calculations and experimental data, the band gap E of non-oxide and oxide materials g Static dielectric constant (low frequency) for [the specified value]

[0228]

number

[0229] (High frequency) optical dielectric constant

[0230]

number

[0231] The following trend is obtained. Using density functional theory, the energy band structure and dielectric dispersion of various crystal structures were simulated. Figure 29A plots several selected oxide materials and their band gap energy E g It has been shown that as ε increases, the dielectric constant generally decreases (falls). Static dielectric constant ε 静的 and optical permittivity ε 光学 They show a similar trend, but as shown in the figure, the degree of curvature differs.

[0232] Figure 29B shows the results when three different electric fields are applied to a 5 μm thick slab using a selected oxide semiconductor. g ΔE for バリア This shows the expected variation. The barrier degradation is observed to be higher as the band gap increases, partly due to dynamic screening which decreases with increasing band gap. Furthermore, because the time associated with electrons passing through the barrier is very short, the high-frequency (optical) dielectric constant should be used for screening models related to barrier degradation. High surface electric fields can be adapted using an intermediate layer, as described for applications to high-voltage rectifiers.

[0233] Figure 29C discloses further trends available for the advantageous incorporation of intermediate oxide materials into diode structures. Given the interface quality S of the surface state int The figure of merit of the (interface state parameter) can also be estimated in relation to the trend of the dielectric constant. For clarity, it is defined as follows:

[0234]

number

[0235] In the formula, 0≦S int ≤ 1, and S int =1 represents an ideal surface with a surface density of states of 0, S int =0 represents an infinite surface density of states. Also, if an empirical fit for the induced gap state is estimated, the minimum surface density of states

[0236]

number

[0237] It can become this, and is also related to the dielectric constant by the following equation.

[0238]

number

[0239] During the ceremony,

[0240]

number

[0241] Therefore, a typical dipole crosses at least one unit cell of the material, and in the case of MgO, it is δ ~ 0.43 nm.

[0242] Referring again to both Figures 19C and 21A, heterostructure designs incorporating an intermediate layer (e.g., MgO, or other material(s)) between the metal and Ga2O3 allow for a reduction in surface density of states while maintaining the high barrier potential required for forward bias rectification and low reverse leakage current.

[0243] In another example, the repeatability of an intermediate or drift layer is achieved by introducing repeated spatial modulation of the doping concentration as a function of the growth direction ("z"). For example, the intermediate or drift layer may have a single material composition, and the conduction band potential may be modulated using repeated spatial modulation of the doping concentration. In one example, the spatial extent of the doping region is very small, and it has a very high doping concentration. In another example, the doping region extends over more than one unit cell of the host composition, but is less than about 10 nm. In yet another example, the doping region is

[0244]

number

[0245] It contains extremely high doping concentrations. In yet another example, the doped region is called a delta-doping region, and the thickness of the doped area is approximately 10-20 nm or less. In some cases, the thickness of the doped region is equivalent to more than one monolayer of the host material composition. For very thin doped regions, an equivalent two-dimensional doping density is achieved.

[0246]

number

[0247] As shown in the following equation, bulk-like

[0248]

number

[0249] It can be stipulated in relation to this.

[0250]

number

[0251] In other words,

[0252]

number

[0253] area density

[0254]

number

[0255] It is equivalent to this. In one example, repeated spatial modulation of doping concentration can result in a homoepitaxial superlattice-type structure similar to the superlattice described above, except that the sublayers have a constant composition but different doping concentrations, instead of having sublayers with different compositions.

[0256] In another example, the repeatability of the intermediate layer includes both repeated spatial modulation of the doping concentration and repeated changes in the composition of the intermediate layer.

[0257] An example of a homoepitaxial delta-doped superlattice (δ-SL) forming the drift region of Schottky barrier diode 16000 is shown in Figure 30. Nickel metal forms SB ("SB metal") in the delta-doped SL drift region ("δ-doped SL") formed using a shallow dopant of either Sn, Ge, or Si in the host β-Ga2O3 composition (i.e., Ga2O3 is used throughout the drift region). Plot 16100 shows sheet density doping in two different periods of the periodic [δ-doped Ga2O3 / NID Ga2O3] superlattice (δ-SL) extending over 2 μm and forming the drift layer of the overall structure, Ni / δ-doped SL drift / n+TL / n+4H-SiC.

[0258]

number

[0259] This shows that the SB potential is maximized by direct contact between the Ni metal with a high work function and the first NID Ga2O3 layer in the δ-SL. As an example, two δ-SL periods are selected and the conduction band diagrams as a function of the growth direction are plotted. Plot 16100 shows that

[0260]

number

[0261] The first δ-SL 16110, which contains a period 19 times longer than the first,

[0262]

number

[0263] The curve shown represents the second δ-SL 16120, which includes four times the period of the previous one. The ratio of the SL doping region is defined as follows:

[0264]

number

[0265] As a result, the first δ-SL and the second δ-SL have γ1=20 and γ2=80, respectively.

[0266] The band structure again functions as a Schottky barrier diode, with δ-SL being the first and second δ-SLs, respectively.

[0267]

number

[0268] and 1.3e16cm -3 It has an effective bulk doping density. Compared to continuous co-doping growth of Ga2O3, the advantage of using periodic δ-doping in the drift region to achieve an effective bulk-like n-type doping level is that higher epitaxial material quality can be realized. Generally, 1e17cm -3Higher-level n-type impurity doping within the above range results in a relative decrease in crystallinity during co-doped epitaxial growth. Furthermore, reactive oxygen species may interact with Si, Ge, or Sn doping sources in the growth reactor, potentially forming undesirable byproducts. Periodic and short doping bursts during epitaxial growth allow for the confinement of dopants within small layers, and subsequent NID material growth also tends to repair any crystal strain by incorporating impurity atoms into the Ga2O3 crystal lattice. This method of periodic doping further improves the crystallinity of the doped drift region, which is effective for coating thick drift regions of 5 microns or more.

[0269] Figure 31 shows the target using δ-SL.

[0270]

number

[0271] This shows the design space to achieve three different 2D sheet doping densities, i.e.,

[0272]

number

[0273] 1.0 e 12 cm -2 (1e18cm -3 ), and 2.9e12cm -2 (5e18cm -3 An exemplary configuration is shown using individual delta-doping layer lengths L(δ-doping) = 5 nm, where the sheet doping densities between curves can be interpolated.

[0274] Figures 32A and 32B are shown below.

[0275]

number

[0276] and 2.5e16cm -3 Figure 30 shows the forward bias IV curves of a Schottky barrier diode incorporating examples of two δ-SL drift regions, with Figure 32A using a semi-logarithmic scale and Figure 32B using a linear scale. The subthreshold slopes are equivalent, but the differential resistance is as expected.

[0277]

number

[0278] That one is more expensive. In another example, an intermediate layer is formed containing at least one quantum well (QW) sublayer sandwiched between wider bandgap layers, the QW being formed by electron confinement by a potential well thus formed. The QW has at least one quantized discrete energy level within the narrow bandgap QW layer. In one example, the quantum well sublayer is configured such that a resonant tunneling current can only be generated in a specific bias configuration, i.e., the quantum well sublayer is configured to have a bias-dependent tunneling current. In one example, this can be used in a voltage-dependent switch to create a pulsed current or a bistable switch. Such a device may be a resonant tunneling diode having two electrical terminals and exhibiting a nonlinear IV response. The nonlinear IV response may have negative differential resistance properties, which can be advantageously used in switching or oscillating circuit configurations of electrical circuits.

[0279] In another example, this two-terminal switch can be used as part of a power converter to control the pulse width and duration of the current.

[0280] An example of a vertical conduction resonant tunneling diode is described below. The double barrier interlayer incorporating a single QW is β-(Al 0.2 Ga 0.8 )2O3 / β-Ga2O3 / β-(Al 0.2 Ga 0.8) is formed using a 2O3 heterostructure, which is further deposited on an n-type β-Ga2O3 drift layer and then deposited on a SiC conductive substrate. β-(Al 0.2 Ga 0.8 The thickness of the 2O3 barrier is thin enough to allow electron tunneling, for example, L バリア =1~10nm, or along the growth direction (Al 0.2 Ga 0.8 ) is equal to a unit multiple of the 2O3 crystal unit cell (e.g., 1, 2, 3, 5, or 1 to 10). The thickness of the β-Ga2O3 layer containing QW can be selectively n-type doped or NID, and has a thickness of approximately 1 monolayer to about 10 monolayers, where 1 monolayer is defined as half the unit crystal dimension along the epitaxial growth direction. β-Ga2O3

[0281]

number

[0282] and 4H-SiC

[0283]

number

[0284] Because the effective electron mass is relatively large in both (which is essentially isotropic with respect to crystal momentum), quantum confinement occurs even in shallow potential wells of physically thin QW layers. For example, the structure has two types of electric field strengths (i.e.

[0285]

number

[0286] When ) is applied along z, a double heterostructure containing a thin QW (α-(Al x Ga 1-x )2O3 / QW α-Ga2O3 / α-(Al x Ga 1-xThe 2O3 / drift α-Ga2O3 is shown in Figures 33A and 33B. The QW thickness was selected as 1 nm to achieve only two quantum confinement states in the potential well, and the barrier composition x=1 gives the highest barrier potential. The wider the QW thickness, the more quantum confinement states are supported. Lowest energy quantum confinement electron space wavefunction profile

[0287]

number

[0288] These are plotted with respect to their quantized energy levels within the QW. The barrier states described above are also plotted to represent the propagation states. To achieve significant barrier penetration of the electron wavefunction, the barrier thickness can be as small as 1 nm or less. Such resonant tunneling structures require precise epitaxial growth to precisely control the layer thickness and enable resonance.

[0289] The advantage of the devices and structures described herein lies in the fact that the thermal conductivity of SiC is approximately two orders of magnitude greater than that of Ga2O3, which advantageously allows heat generated within the oxide drift layer to conduct rapidly through the SiC substrate until it is completely dissipated from the device. The self-heating effect in conventional all-Ga2O3 power devices using thick β-Ga2O3 substrates is one of the most challenging problems in the practical application of high power density technology. In contrast to all-SiC devices using thick SiC substrates, the Ga2O3 substrates in conventional devices exhibit low thermal conductivity, requiring other forms of thermal management, such as substrate thinning and integration with diamond heat spreaders. This disclosure describes devices, structures, and methods that simultaneously improve the electrical performance of devices utilizing UWBG oxide materials by integrating with a SiC substrate with extremely high thermal conductance and low electrical resistance. In other words, a simultaneous solution for the electrical and thermal performance of the device becomes possible. This represents a significant improvement in the overall performance of the device compared to thermally insulating and electrically conductive β-Ga2O3 substrates.

[0290] Furthermore, a further advantage of the hybrid integration of semiconducting oxide-SiC materials when forming Schottky barrier diodes, as described in this disclosure, is the improved electrostatic field distribution within the device.

[0291] Figure 34 shows a plot of simulated field lines 915 (and associated potential lines 910) for a vertical multilayer semiconductor device, which is similar in configuration to device 100 shown in Figure 1, but includes a separation layer 180 surrounding a metal layer 130 that functions to reduce surface current and manage the electrostatic vector field. The field lines 915 and equipotential lines 910 shown in Figure 34 represent the expected potential differences between the conductive substrate 110 and the metal layer 130 in the range of approximately 100 V to approximately 10,000 V.

[0292] In this example, the contact (metal layer 130) patterned with Ni metal is located on a β-Ga2O3 drift layer 120 placed on a conductive 4H-SiC substrate 110. The isolation layer 180 is selected from low dielectric constant compositions, for example, Al2O3. The device is surrounded by vacuum or air. The contact (metal layer 130) is forced to a positive potential (+V), and the conductive substrate 110 is forced to a negative potential (-V).

[0293] As can be seen from the inspection, the electric field line 915 is directed from the surface boundary of the rectangular contact toward the conductive substrate surface 110, forming an equipotential line between the metal layer 130 and the substrate 110. Plot 900 shows a high concentration of electric field within the region of the isolation layer 180 and drift layer 120 near the corner of the metal layer 130. As can be understood, in certain situations, the magnitude of the electric field

[0294]

number

[0295] Because the electric field is highly concentrated, it can exceed the breakdown field of the host material (for example, as shown in Figure 2B). In practice, sharp angles in conductive features concentrate the electric field and can be rounded if possible. In metal patterning manufacturing methods such as the lift-off method or damascene method, it is usually not possible to create features that are perfectly rounded in the longitudinal section. However, in-plane (outermost surface) patterning of contacts can be controlled by lithographic representation to form circular pads or rounded corners, etc., which can also help reduce the electric field density.

[0296] It should be noted that the isolation layer 180 contains a material with a substantially larger band gap than the oxide active drift layer. In its original state, the isolation layer 180 is not effectively insulating. Low electrical conductivity also indicates the selection of a suitable material for the isolation layer 180. Compatibility with the UWBG active drift region 120 is another factor for the isolation layer 180 material. In some cases, the isolation layer 180 also has a low dielectric constant so that the electric field strength within the host isolation layer 180 can be reduced. Again, referring to the exemplary selection of materials in Figure 29A, which shows the trend of dielectric constant by band gap energy, there is a range of suitable materials that are compatible with the Ga2O3 active drift layer and can be used for the material of the isolation layer 180.

[0297] In some examples, the separation layer 180 can include one or more materials with lower dielectric constants and higher band gaps than the drift layer semiconductor. If the drift layer contains Ga2O3, separation layer compositions of MgO and Al2O3 are possible. SiO2 has even better separation layer properties, but actual deposition methods (such as PECVD) produce a hydrogenated H:SiO2 film that is amorphous and has properties significantly different from single-crystal quartz (α-SiO2). Atomic layer deposition of Al2O3 is one of the most preferred methods for producing high-quality amorphous and conformal coatings, while exhibiting a larger effective band gap and lower dielectric constant than Ga2O3. ALD deposition amorphous (Al) for x>0 x Ga 1-x)2O3, or other materials described herein, may also be used.

[0298] Referring again to the mesa-type metal contact device, Figure 34 shows that the electric field around contact 130 is relatively infinite (unbounded). Improved high-voltage contact arrangements can be implemented to manage the lateral range of the electric field while fixing and maintaining the contact area 130 in the drift region.

[0299] Figures 35A and 35B show a top view and a schematic cross-sectional view, respectively, of a vertical multilayer semiconductor diode device 1000, according to an exemplary embodiment that incorporates a lateral field-plate arrangement to modify the vector electric field of the device.

[0300] In this example, device 1000 includes a substrate 1010 (Figure 35B), an epitaxial drift layer 1020, and a metal layer 1030, as previously described (for example, in device 100 in Figure 1). In this example, a separation layer 1080 is formed on the epitaxial drift layer 1020 and surrounds the metal layer 1030. A field plate arrangement is formed on the outermost surface of the metal layer 1030 and the outermost surface of the separation layer 1080 in the form of a field plate layer 1090, which is made of metal and has a central aperture 1091 of a size and shape that exposes the metal layer 1030. In this example, both the metal layer 1030 and the field plate layer 1090 have a circular configuration, and the separation layer 1080 has a ring or annular configuration that surrounds (or wraps around) the metal layer 1030. The field plate layer has an outer diameter d FP And, an overhang above the separation layer 1080 lol FP It has the following characteristics.

[0301] In this example, the metal layer 1030, the separation layer 1080, and the field plate layer 1090 each have complementary circular or annular configurations, which typically helps minimize edges where stronger electric fields may be formed. In other examples, the Schottky barrier metal of the metal layer 1080 may have an n-gonal configuration (e.g., rectangle, elongated stripe with rounded corners, hexagon, etc.), and the other layers may have complementary configurations as needed. Figure 35B shows the diameter d of the Schottky barrier metal layer 1030. SBM , diameter d of field plate layer 1090 FP and annular width w FP Furthermore, the thickness t of the drift layer 1020 and the separation layer 1070 D and t Iso These will be shown.

[0302] In one example, the drift layer 1020 has a dielectric constant ε1 and a bandgap energy

[0303]

number

[0304] The separation layer 1080 has a dielectric constant ε1 and a band gap energy

[0305]

number

[0306] It has. In one example, the materials of the drift layer 1020 and the separation layer 1080 are

[0307]

number

[0308] It is selected in such a way that... Next, design principles that can be used to design the isolation layer and field plate described herein are explained. Consider a plane-parallel metal plate capacitor with a dielectric located between metal plates of area A, separated by thickness t and having a finite lateral extent. Capacitance C p C p =ε r It is defined as ε0A / t. Field plate overhang w FP Effective parasitic capacity C p To minimize low-k (i.e., low ε r )) Select the material, and the thickness of the separation layer t ISO This can be increased. Furthermore, low-k dielectric materials can be compared to Ga2O3 using the following relationship.

[0309]

number

[0310] When using thickness, (C p / A) = 89 fF / μm 2 This is the target value.

[0311]

number

[0312] To achieve a relative reduction in overhang capacity density up to that point, the device uses t low-k Al2O3 with a thickness of 640 nm can be used.

[0313] In one example, the field plate layer 1090 and the SB metal contact 1030 may be formed from the same metal, e.g., a high work function metal or alloy of Cu, Te, Be, Rh, Co, C, Ni, Au, Ir, Pd, Pt, Se, Os and combinations thereof (see Figure 11A). In another example, the metal layer 1030 may be formed from a high work function metal, including but not limited to Cu, Te, Be, Rh, Co, C, Ni, Au, Ir, Pd, Pt, Se, Os and combinations thereof, while the metal of the field plate layer 1090 may be selected from metals with lower work functions, such as Al, Ti, Mo, and W. High melting point metals can be advantageous for use in high-temperature operations (e.g., above 300°C).

[0314] Ohmic contacts to the substrate may also include metals with high work function to enable co-processing of the front and back surfaces of the device structure. For example, Ni can be used as the SB metal on the surface of the drift layer, but Ni can also function as an ohmic contact to a highly doped SiC substrate. Furthermore, silicides can be used to form low-resistance ohmic contacts to the substrate. Silicon can be removed from the SiC substrate by thermal annealing of the contact metal to form a silicide. For example, Ni x Si 1-x It can form Ti x Si 1-x It can form a SiC / Ti x Si 1-x Materials such as Ti / Al can form ohmic contacts with the substrate.

[0315] Some examples of the field plate metal layer 1090 / separation layer 1080 / Schottky barrier metal 1030 / wide bandgap oxide drift layer 1020 / substrate 1010 / ohmic contact layer structure are as follows: Al / Al2O3 / Al / Ni / Ga2O3 / 4H-SiC / Ni / Al Cu / Al2O3 / Al / Ni / Ga2O3 / 4H-SiC / Ni / Cu Cu / Al2O3 / Al / Ni / NiO / Ga2O3 / 4H-SiC / Ni / Cu Cu / Al2O3 / Al / Ni / Ni x Cu y O / Ga2O3 / 4H-SiC / Ni / Cu Al / Al2O3 / Al / Ni / Pd / Ga2O3 / 4H-SiC / Ni / Cu.

[0316] In one embodiment, the separation layer 1080 is formed from a material with a wider band gap than the drift layer 1020. In one example, the separation layer 1080 is formed from Al2O3. In another example, the separation layer 1080 is formed from SiO2.

[0317] In other examples, the separation layer can be a wide-bandgap oxide having a p-type conductivity. For example, the oxide of the separation layer may include nickel oxide, nickel-copper oxide, copper oxide, tellurium oxide, or osmium oxide. The separation layer may also include a portion of a metal oxide formed from an SB metal.

[0318] In other examples, the IL may also have p-type characteristics, with or without having a bandgap larger than the drift layer.

[0319] Figure 36 shows a plot of the electric field distribution 1110 of a simulation of a vertical multilayer semiconductor device with a configuration similar to the device 1000 shown in Figures 35A and 35B, incorporating the field plate arrangement described above (for example, the one in Figures 35A and 35B).

[0320] As can be seen from the inspection, the field plate layer 1090 has an outer diameter (for example, d in Figure 35B). FP ) and the overhang above the separation layer 1080 (for example, w in Figure 35B) FPThe low-k isolation layer 1080 also functions to reduce the concentration of electric field lines near the longitudinal boundaries or corners of the metal layer 1030 in contact with the drift layer surface. The equipotential lines 1110 between a portion of the interface of the contact metal 1030 and the drift layer 1020 are significantly flattened compared to the absence of the field plate layer 1090. The concentration of electric field lines 1115 is also significantly reduced near the contact region (metal layer 1030) in direct contact with the drift region 1020. The low-k isolation layer 1080 also functions to reduce the maximum electric field strength directly beneath the field plate layer 1090 by spreading the equipotential lines laterally. Furthermore, the conduction channel formed between the metal layer 1030 in contact with the drift region and the laterally oriented conductive substrate 1010 exhibits a substantially uniform electric field. Although not limited by theory, a decrease in electric field density in regions adjacent to the metal layer 1030 (particularly the angular regions near the interface between the drift layer 1020 and the metal layer 1030, such as the interface region 140 shown in Figure 1) can improve device performance by, for example, reducing the peak electric field within the device to a level far below the critical yield field of the host drift material.

[0321] In the case of a fixed vertical device configuration, the current-carrying capacity of the diode structure in Figure 1 can be increased by scaling the contact area 140 to a larger area or by multiplexing several parallel-connected diodes. By dividing the longitudinal current among several parallel interconnected diodes, trade-offs are possible between the consumed epitaxial area, maximum longitudinal current capacity, and thermal effects.

[0322] Figures 37A and 37B show transverse and longitudinal cross-sectional views, respectively, of a composite diode device 1200 having multiple unit cells 1250 similar to the vertical multilayer semiconductor diode device 1000 shown in Figures 35A and 35B. The top cross-section of Figure 37A is taken along section AA and represents a plane parallel to the substrate surface where the circular metal layer 1030 and the isolation layer 1080 intersect. The longitudinal cross-section of Figure 37B relates to the feature of an optional continuous top contact metal 1220 interconnecting multiple Schottky barrier metal contacts 1030, the top contact metal 1220 functioning as a top field plate 1090. The drift layer 1020 is located on the substrate 1010 as well as on the ohmic contacts 1240. The metal layer 1030 contains several circular metal regions. The isolation layer 1080 extends across the composite diode device 1200 and surrounds each of the circular metal regions of the metal layer 1030. A drift layer (e.g., drift layer 1020 in Figure 35B) can be located between the metal layer 1030 and the substrate (e.g., substrate 1010 in Figure 35B) and can extend across the composite diode device 1200. A field plate layer 1220 (e.g., 1090 in Figure 35B) can be formed above the metal layer 1030 and can also extend across the composite diode device 1200. Each unit cell 1250 has an outer periphery 1092, which can relate to the outer diameter and overhang dimensions of the field plate required for each unit cell to reduce electric field concentration in each of the circular regions of the metal layer 1030. Thus, in this example, the dimensions of the field plate layers 1090 / 1220 are limiting factors regarding the number of unit cells that can be arranged within a given surface area.

[0323] In various examples, each unit cell may have a width ranging from 1 micron to 100 microns, or from 100 microns to 1 cm. In one example, each unit cell shares a common substrate (1010) and a drift layer 1020. In these examples, high-resistance edge termination regions can be formed between each unit cell. In one example, the termination region is formed as a physical trench or channel, extending downward and entering the drift layer 120, forming a boundary between each unit cell 1250. In another example, the termination region can be formed by ion implantation, where a resistive trench or channel region is formed within the oxide material of the drift layer 1020.

[0324] In various embodiments, a metal layer (e.g., metal layer 130 in Figure 1, or metal layer 1030 in Figures 35A and 35B) is deposited using a metal deposition process (such as sputtering, thermal deposition, electron beam deposition, or electrodeposition) within any further epitaxial layer formed above an epitaxial drift layer (e.g., drift layer 120 in Figure 1, or drift layer 1020 in Figures 35A and 35B), following the formation of an epitaxial drift layer. That is, the metal deposition process is carried out separately from the epitaxial oxide deposition. As understood, this requires a process change from the epitaxial oxide layer deposition process to the metal deposition process. The final deposited epitaxial oxide surface can be protected by limiting its exposure to a contaminating environment before metal deposition. This can be achieved by configuring a separate deposition chamber with a vacuum wafer transport mechanism. Alternatively, metal deposition can be performed within the same process chamber as oxide deposition, once undesirable species have been removed from the chamber. In some cases, as further described herein, metals can be epitaxially deposited within an epitaxial oxide deposition chamber.

[0325] Figures 38A–38C show process flows for forming vertical multilayer semiconductor devices, including a metal layer and an epitaxial drift layer of oxide material forming a Schottky barrier junction, according to several embodiments. The metal layer 1330 can be an epitaxial metal layer (e.g., formed using MBE, ALD, or MOCVD) or a non-epitaxial metal layer (e.g., formed using sputtering, pulsed laser deposition, or thermal deposition of metal). Each process block (or unit operation) of the process produces the intermediate products shown in Figures 38A–38C.

[0326] In one stage / block of the process, an epitaxial drift layer 120 is formed on the substrate 110, as shown in the intermediate product 1310 in Figure 38A.

[0327] In another block of the process, an (epitaxial) metal layer 1330 is formed on the drift layer 120, as shown in the intermediate product 1340 in Figure 38B. Lattice constant and / or crystal structure mismatch between a particular metal and the final surface reconstruction of the oxide surface plays a crucial role in the quality of the metal-oxide interface. Methods for forming a favorable metal-oxide interface are disclosed later in this disclosure. In other examples, the (epitaxial) metal layer 1330 may be formed on any intervening or intermediate epitaxial deposited layer formed on the drift layer 120. In one example, the thickness of the (epitaxial) metal layer 1330 is between 1 angstrom and 100 angstroms. The epitaxial metal or the first deposited metal layer may be relatively thin, and then another metal layer may be deposited to increase the total layer thickness. The second metal deposition step may contain a different metal composition from the first metal, or the same metal.

[0328] In another block of the process, the metal layer 1330 may be patterned, as shown in the intermediate product 1370 in Figure 38C. The intermediate product 1370 may be generated by photolithographic patterning of a mask followed by selective material removal by a physical etching process. The etching process may be at least one of a dry reactive gas plasma process, a wet etching process, or other processes. The device may be further processed as needed to form the vertical multilayer semiconductor diode device according to the present disclosure. For example, a patterned contact layer 1351 may be included on top of the epitaxial metal layer. In some cases, a non-epitaxial metal layer may be used to form a Schottky barrier junction with an epitaxially deposited drift layer 120. In some cases, a transition layer (e.g., shown in structure 400 in Figure 4 and described above) may be deposited between the substrate 110 and the drift layer 120. In some cases, an intermediate layer (e.g., shown in structure 800 of Figure 8 and described above) can be deposited between the drift layer 120 and the (epitaxial) metal layer 1330. In some cases, several layers are patterned (e.g., using wet etching, plasma etching, and / or photolithography) to form the structures described herein. Optionally, the oxide surface exposed by the metal patterning 1335 may be treated to reduce surface damage, reduce surface leakage, and deactivate the surface.

[0329] Any of the device structures described herein (for example, structure 100 in Figure 1, 300 in Figures 3A and 3B, 400 in Figure 4, 600 in Figure 6, 800 in Figure 8, 1000 in Figures 35A and 35B, and 1200 in Figure 37A) can be fabricated using the above process.

[0330] Figures 39A–39G show a process flow for forming a vertical multilayer semiconductor diode device according to another exemplary embodiment, which includes an epitaxial drift layer of oxide material forming a metal layer and a Schottky barrier junction. The metal layer 1430 in this process can also be an epitaxial metal layer (e.g., formed using MBE or MOCVD) or a non-epitaxial metal layer (e.g., formed using sputtering, pulsed laser deposition, or thermal deposition of metal). Each process block (or unit operation) of the process produces the intermediate products shown in Figures 39A–39G.

[0331] In one block of the process, an epitaxial drift layer 1420 containing a semiconductor oxide material is formed on the SiC substrate 1410, as shown in the intermediate product 1401 shown in Figure 39A. In some cases, the SiC substrate 1410 is a composite substrate including a bulk substrate layer and a surface layer (e.g., the bulk substrate layer 112 and surface layer 114 of substrate 110 in Figure 1), the surface layer containing single-crystal SiC.

[0332] In another block of the process, a separation layer 1480 is formed on the drift layer 1420, as shown in the intermediate product 1402 in Figure 39B. In one example, the separation layer 1480 is formed from a suitable oxide material such as Al2O3, NiGa2O4, AlCu2O4, GaCu2O4, MgO, ZnGa2O4, or SiO2. In one example, the separation layer 1480 is formed on the drift layer 1420 by a conformal deposition process such as atomic layer deposition (ALD). In another example, the separation layer 1480 is an epitaxial layer formed using an epitaxial deposition process (e.g., MBE or MOCVD). In one example, the separation layer 1480 is formed to have a layer thickness of 100 nm to 300 nm.

[0333] In another block of the process, the opposing in-device field termination region 1471 and the opposing inter-device isolation region 1475 are formed by physically removing portions of the separation layer 1470 and the drift layer 1420, respectively, as shown in the intermediate product 1403 in Figure 39C. Alternatively, selective physical modification of area and depth can be achieved by an ion implantation process. Furthermore, the central contact area region 1477 is formed by removing the separation layer 1480 and exposing the drift layer 1420. The opposing in-device field termination region 1471 and the opposing inter-device isolation region 1475 can be formed by patterning and etching the separation layer 1480 and the drift layer 1420 (e.g., using wet etching, plasma etching, and / or photolithography). In one example, these portions are removed by etching after coating with photoresist.

[0334] In another block of the process, as shown in the intermediate product 1404 in Figure 39D, an upper metal layer is deposited, in this example forming the metal layer 1430 and the field plate layer 1490. In some cases, the metal layer 1430 is thinner than the field plate layer 1490. For example, the metal layer 1430 can be deposited using epitaxial techniques and can be thinner than the field plate layer 1490, which can be deposited using faster growth methods (e.g., sputtering or thermal deposition). In this example, a guard ring 1495 is formed on the isolation layer 1480 outside the field termination region 1471. The guard ring 1495 can supply a reference voltage and reduce parasitic currents and voltages. In various examples, the top metal layers (e.g., 1430, 1490 and / or 1495) may be formed from Ti / Al, Al, Ni, Mo, Pd, or combinations thereof. In some cases, the device may not include an intermediate layer (for example, as shown in structure 100 in Figure 1 or structure 400 in Figure 4), and the guard ring 1495 can be deposited on the epitaxial oxide layer. Parts of the upper metal layers corresponding to the field-terminated region 1471 and the isolation region 1475 (e.g., 1430, 1490, and / or 1495) are also removed, for example, using patterning and plasma etching processes. In another example, a patterning and metal lift-off (MLO) process is used.

[0335] In another block of the process, a top passivation layer 1476 is formed over the entire device, as shown in the intermediate product 1405 in Figure 39E. In one example, the top passivation layer 1476 is formed from a suitable oxide material such as Al2O3 or SiO2.

[0336] In another block of the process, a lower contact layer 1452 is formed on the back surface of the substrate 1410, as shown in the intermediate product 1406 in Figure 39F. The lower contact layer 1452 can form an ohmic contact with the substrate 1410 and can be deposited using any of the metal deposition techniques described herein.

[0337] In another block of the process, the metal layer 1430, which in this example also forms the upper contact, is exposed by a further etching process that removes part of the passivation layer 1476, as shown in the intermediate product 1407 shown in Figure 39G.

[0338] Figure 40 shows an example of a schematic cross-sectional view of a vertical multilayer semiconductor diode device configuration Y100 used to simulate the thermal heating effect. In this example's thermal model, the semiconductor diode device configuration Y100 is assumed to be continuous from left to right (i.e., semi-infinite) without lateral boundary conditions.

[0339] Moving roughly upwards (in the positive Z direction) from the bottom of Figure 40, the semiconductor device configuration Y100 has its lower surface (i.e., S1) at temperature T S1 It includes a horizontally extending back-drain metal ohmic contact layer F1 (cathode) held in place. The next layer includes substrate Y110 (F5). In the various examples shown below, thermal modeling is performed to compare different substrate materials such as highly doped (n-type or p-type) SiC or Ga2O3. Firstly, the doping level and type do not significantly alter the thermal conductivity of the host material.

[0340] Above substrate Y110, an epitaxial drift layer Y120 (F6+F7+F8) containing semiconductor oxide material is formed, which in this example is modeled as three regions including a central region F8 and opposing boundary regions F6 and F7. By dividing the epitaxial drift layer Y120 into three regions in this way, the temperature performance characteristics of the central region F8 can be individually characterized (see, for example, Figure 44 below). The central region F8 is where the most ohmic heating occurs due to the large forward conduction channel. Regions F7 and F6 represent semiconductor regions with little or no longitudinal current flow.

[0341] Above the central region F8 of the epitaxial drift layer Y120, there is a Schottky barrier metal layer Y130 (within region F3) that forms a Schottky barrier junction between the metal layer Y130 and the central region F8 of the epitaxial drift layer Y120.

[0342] Above the boundary regions F6 and F7 of the epitaxial drift layer are the boundary regions F2 and F4 of the separation layer Y180, which is formed from a material with a wider band gap compared to the semiconductor oxide material forming the epitaxial drift layer Y120, respectively. Generally, the separation layer regions F2 and F4 may contain compositions with lower thermal conductivity than the drift layer Y120 (F7, F8, and F6). Extending above the Schottky barrier metal layer Y130 and partially above regions F2 and F4 of the separation layer Y180 is the field plate layer Y190 (within region F9), formed from a low, medium, or high work function metal. The centrally located metal interconnect F10 extends upward from the field plate layer Y190, overlapping and extending horizontally to the top contact bus metal layer F11 (anode). In one example, the field plate layer Y190, the metal interconnect F10, and the top contact metal layer F11 may be formed of Al. In another example, the electrical conduction type can be changed to the opposite conduction type, in which case the top bath metal layer F11 functions as a cathode. As understood, the thermal conductivity performance is equivalent.

[0343] In this example, the exposed bottom surface of the upper contact bus metal layer F11, the exposed side surface of the interconnection section F10, the exposed side surface and outermost surface of the field plate layer Y190, and the exposed outermost surfaces of the boundary regions F2 and F4 of the separation layer Y180 (see Figure 40) are all at ambient air temperature T aIt is assumed that these exposed surfaces are located in such a way that they allow convective transfer of heat generated by the device configuration Y100 to the "air". This would be considered a worst-case scenario, as in other examples the "air" region is a thermally insulating dielectric material (e.g., a polymer planarization layer) and also minimizes heat transfer from the device configuration Y100 (e.g., the interconnect F10 implemented as a wire bond connected to the contact bus metal layer F11 in the form of a bond pad). Furthermore, the lower surface S1 of the metal contact region F1 is at temperature T S1 It is assumed that the metal contact bus region F11 is held at a temperature T S2 It is assumed that it will be held there.

[0344] Figure 41 shows a plot Y200 of the thermal conductivity of various semiconducting materials as a function of temperature, which can be used to model the temperature of the vertical multilayer semiconductor device configuration Y100 described later. The plot shows the thermal conductivity curves of semiconducting materials, including not only the thermal conductivity curves of the potential substrate material 4H-SiC Y210 and n+-doped (Sn)Ga2O3Y220, but also the thermal conductivity curve of intentionally undoped Ga2O3Y230, which can be used as an example to form the epitaxial drift layer Y120 of the device configuration Y100 shown in Figure 40.

[0345] As can be seen from the tests, the thermal conductivity of all the materials depicted decreases with increasing temperature. At an operating temperature of 200°C, the thermal conductivity of SiC is at least five times higher than that of the Ga2O3-based materials shown. This aspect represents one of the main advantages of the hybrid approach disclosed herein.

[0346] In one example, the thermal modeling involves simulating the voltage initially applied to a central region of approximately 1 μm of the upper contact layer F11, with the drain contact layer F1 held at ground potential. In this example, the simulated applied voltage corresponds to an initial current of 65 amperes conducted between the upper contact layer F11 and the drain contact layer F1 by the model configuration Y100. Furthermore, the temperature T of the surface S1 of the configuration model Y100 is also simulated. S1 The temperature is set to 25°C, and the temperature of the surface S2 is T S2 The temperature is set to 75°C. The model then becomes capable of reaching an equilibrium state in which a steady-state forward current is conducted by the semiconductor device configuration Y100.

[0347] The model is computed using the finite element method to construct the spatial distribution of material properties in a high-density tensor mesh. Heat transfer across the entire 2D model structure is applied and solved using parabolic partial differential equations.

[0348]

number

[0349] In the formula, Q is heat transfer, T is temperature, and C h ρ is the specific heat, κ is the thermal conductivity, and ρ is the density of the material. Each parameter is a function of time and the spatial position (t,x,y) of each element.

[0350] The simulation workflow includes (i) a step or block to create a 2D physical model for steady-state or transient state simulation, (ii) a step or block to discretize the model by applying a spatial mesh algorithm, and (iii) a matrix element C hThis includes (iv) a step or block to assign (t=0,x,y), ρ(t=0,x,y), and κ(t=0,x,y); (iv) a step or block to specify an internal heat source Q within the geometry; (v) a step or block to specify the temperature on the boundary or the heat flux through the boundary, T(t=0,x,y); (v) a step or block to specify the ambient temperature, the convective heat transfer coefficient, and the radiant heat flux; and (vi) a step or block to specify the emissivity ε and the Stefan-Boltzmann constant σ for each material in the structure. Once the model is fully specified, the simulation heat flow algorithm is initialized with the initial temperature or initial estimate.

[0351] Referring to Figure 42, a temperature contour shaded plot Y300 is shown, which in this example shows the steady-state temperature distribution resulting after thermal modeling of a semiconductor device configuration Y100 consisting of a highly doped Ga2O3 substrate Y110 (e.g., material Y220 in Figure 41) and a Ga2O3 epitaxial drift layer Y120 (e.g., material Y230 in Figure 41). The Schottky barrier metal layer Y130 is selected to be a metal with a high work function, such as Ni, and the Ga2O3-based epitaxial drift layer Y120 is n - It is doped. In other examples, the Schottky barrier metal layer Y130 can be selected from other metals with high work functions, such as Pt, Pd, Cu, or Os. In alternative configurations, the Ga2O3 epitaxial oxide layer is p - The doped Schottky barrier metal layer Y130 can be selected from metals with low work functions such as Al or Ti. The thermal conductivity of most selected metals does not significantly alter the conclusions herein. The internal heat source within structure Y300 is generated by the resistive heating effect due to a longitudinal current (e.g., constant current) flowing within region F8 of drift region Y120.

[0352] As can be seen from Figure 42, the maximum temperature region Y310 is located within the central region F8 of the drift layer Y120, at approximately 400°C, and the temperature gradient extends laterally into the contact and field plate Y190. The top contact and separation layer are bonded to an open surface for air convection. Nevertheless, the top contact Y190 rises to approximately 300°C, meaning that a refractory metal may be required for stability (or reliability, or durability). In general, metal bonding temperatures above 250°C are problematic for high-power and high-reliability applications. For this exemplary model, it can be concluded that the material, including the Schottky barrier metal layer Y130, separation layer Y180, and field plate layer Y190, must operate at temperatures in the 250°C–300°C range, where reliability is expected to be negatively affected.

[0353] The operation of a forward-biased diode is modeled as the central epitaxial drift layer Y130 region F8 conducting current as a "filament," and the heating power is IR 2 According to the relationship, I is the current flowing through the region, and R is the effective resistance of the region, which is determined by the doping concentration.

[0354] Referring again to Figure 42, it can be seen that the steady-state temperature of the interface between the Ga2O3 drift region and the substrate junction is approximately 350°C, and that a gradient extends toward the rear contact, which is maintained at 25°C. The low thermal conductivity of the Ga2O3 substrate causes a self-heating effect in the drift region.

[0355] In contrast to the structure in Figure 42, here it is replaced with a high thermal conductivity substrate as shown in Figure 43. Except that a SiC substrate (see, for example, material Y210 in Figure 41) is used instead of the Ga2O3 substrate in the structure adopted in Figure 42, a temperature contour shaded plot Y400 is shown, which represents the temperature distribution obtained as a result of thermal modeling of the semiconductor device configuration Y100 modeled in Figure 42.

[0356] In contrast to the modeling results shown in Figure 42, the results in Figure 43 show that the maximum temperature Y410 of the central region F8 has a maximum temperature in the range of 200°C to approximately 220°C, which is significantly lower than the maximum temperature of the structure with the Ga2O3 substrate modeled in Figure 42. The same thermal heat source is applied to both Figure 42 and Figure 43. Furthermore, the material including the Schottky barrier metal layer Y130, the isolation layer Y180, and the field plate layer Y190 operates at a temperature of approximately 175°C, which is more advantageous than conventional heat dissipation methods. The SiC substrate with high thermal conductivity provides an efficient heat sink in the drift region and offers lateral thermal management throughout the structure. The temperature reduction enabled by the improved thermal management described herein also relaxes the constraints on the type of metal that can be used, which has a favorable impact on the reliability of the device.

[0357] Many material parameters are temperature-dependent. Thermal conductivity, heat capacity, and bandgap energy generally decrease as the temperature rises. Also, thermal activation of carrier generation increases the number of free carriers, reducing the electrical resistance of semiconductors. Conversely, in metals, electrical resistance usually increases with increasing temperature. Therefore, the self-heating effect disclosed in Figure 42 can cause thermal "runaway," and if heat dissipation is limited, it can lead to premature yielding of the device.

[0358] The transient thermal response of the model reveals further advantages and disadvantages of the oxide drift region coupled to high and low thermal conductivity substrates.

[0359] Referring to Figure 44, the transient responses of device models Y300 and Y400 for two current pulse periods occurring within the current filament region F8 are shown. A plot of the integrated thermal intensity β(t) of region F8 with drift layer Y120 as a function of time (in microseconds) Y500 is shown for the two device configurations shown in Figure 42 (Ga2O3 substrate) and Figure 43 (SiC substrate), assuming a pulsed current input to region F8 with an on period of 5 μs and an off period of 5 μs (duty cycle 50%). Upon examination, the maximum thermal intensity Y510 of the SiC substrate-based device is approximately one-third lower than the maximum thermal intensity Y520 of the Ga2O3 substrate-based device, despite both devices having the same Ga2O3 drift layer and top contact structure. Furthermore, the thermal intensity of the SiC substrate-based device can recover to zero Y530 before the start of the second pulse in the next 5 μs, which is in contrast to the recovery Y540 of the Ga2O3 substrate-based device.

[0360] As is understood, the time required for Ga2O3 substrate-based diode devices to dissipate heat increases, which in turn increases the minimum dwell time required for any switching application compared to SiC substrate-based diode devices. Alternatively, if such a minimum dwell time (or off-period duration) is not long enough, Ga2O3 substrate-based devices may suffer from thermal "runaway."

[0361] Figure 45 shows a schematic cross-sectional view of a vertical multilayer semiconductor diode device configuration Y600, which was used to simulate the thermal performance of a mesa-type semiconductor device. In this example, the epitaxial drift layer Y620 (F6+F7+F8) of the device model configuration Y600 is formed as a mesa structure with angled walls extending upward from the substrate Y610 (F5), and the region outside the mesa is at ambient air temperature T a This is assumed (see Figure 45).

[0362] Moving roughly upwards from the bottom of Figure 45, the device model configuration Y600 has its bottom surface (i.e., S1) at temperature T S1 It includes a horizontally extending back-drain metal ohmic contact layer F1 (cathode) held in place. The next layer includes the substrate Y610 (F5). Above the substrate F5, an epitaxial drift layer Y620 containing a semiconductor oxide material is formed, which is remodeled as three regions including the central region F8 and boundary regions F6 and F7 facing the central region F8, in order to enable characterization of the central region F8. Above the central region F8 of the epitaxial drift layer Y620 lies a Schottky barrier metal layer Y630 (F3) that forms a Schottky barrier junction between the metal layer Y630 (F3) and the central region F8 of the epitaxial drift layer Y620. In this example, the metal layer Y630 also forms an upper contact layer, and its upper surface is at temperature T S2 It is assumed that it will be held at (for example, the top surface at temperature T S2 (It is coupled to the heat sink.)

[0363] In this example, the thermal modeling involves simulating the voltage initially applied to a central region of approximately 1 μm of the Schottky barrier metal layer Y630, with the drain contact layer F1 held at ground potential. In this example, the simulated applied voltage corresponds to an initial current of 65 amperes conducted between the Schottky barrier metal layer Y630 and the drain contact layer F1 by the model configuration Y600. Furthermore, the temperature T of the surface S1 of the configuration model Y600 is also simulated. S1 The temperature is set to 25°C, and the temperature of the surface S2 is T S2 The temperature is set to 75°C. The model then becomes capable of reaching an equilibrium state in which the steady-state forward current is conducted by the device configuration Y600.

[0364] Referring here to Figure 46, a steady-state temperature contour shaded plot Y700 is shown, which in this example shows the resulting temperature distribution after thermal modeling of configuration Y600, consisting of a highly doped Ga2O3 substrate (e.g., see material Y220 in Figure 41) and a Ga2O3 epitaxial drift layer (e.g., see material Y230 in Figure 41). The Schottky barrier metal layer Y630 is selected to be a metal with a high work function, such as Ni, and the Ga2O3 epitaxial oxide layer is n - It is doped. In other examples, the Schottky barrier metal layer Y630 can be selected from other metals with high work functions, such as Pt, Pd, or Os. In alternative configurations, the Ga2O3 epitaxial oxide layer is p - The doped Schottky barrier metal layer Y630 can be selected from metals with low work function, such as Al.

[0365] Similar to the modeling results in Figure 42, as can be seen from the modeling results shown in Figure 46, the maximum temperature Y710 of the central region F8 is approximately 350°C, again far exceeding the desired operating temperature of 200°C to 220°C for semiconductor diode devices. Furthermore, the extended region of the epitaxial drift layer Y620 needs to operate at temperatures in the range of 250°C to 300°C, which is expected to affect reliability.

[0366] Referring now to Figure 47, we see a steady-state temperature contour shaded plot Y800 showing the resulting temperature distribution after thermal modeling of the semiconductor device configuration Y600 modeled in Figure 46, except that a SiC substrate (see, for example, material Y210 in Figure 41) is used instead of a Ga2O3 substrate. In contrast to Figure 46, the maximum temperature Y810 in the central region F8 has a maximum temperature in the range of 200°C to 220°C, which is significantly lower than the maximum temperature of the Ga2O3 substrate-based device shown in Figure 46. Furthermore, the epitaxial drift layer Y620 considered in total has an overall operating temperature of about 150°C, which is sufficient within the conventional operating temperature range of these types of diode devices.

[0367] The thermal models described herein demonstrate the advantageous hybrid integration of oxide drift layers on high thermal conductivity SiC substrates to dramatically improve steady-state and transient device performance, which can be applied to high-power switching.

[0368] Next, further detailed embodiments and manufacturing methods of hybrid metal oxide semiconductor and SiC substrate device architectures will be described.

[0369] Figure 48 shows the electron affinity of crystal surface orientation (χ) on a vacuum-referenced absolute energy scale for a slightly sloped surface of β-Ga2O3 labeled with Miller indices (hkl) and a (000±1) surface of 4H-SiC (i.e., a Si polar surface and a C polar surface). A The plot of Z1-1000 is shown. The band gap of each material is represented by a shaded box, the outermost surface level represents the conduction band edge, and the lower boundary of each box represents the valence band edge. Figure 48 shows the band gap and (χ A The results were calculated using density functional theory (DFT) for crystalline slabs of specific materials.

[0370] In particular, the Si polar 4H-SiC(0001) surface is favorable for the epitaxial deposition of β-Ga2O3(-201) aligned films. Assuming an undoped material, the electron affinity of β-Ga2O3(-201) is given as Z1-1010, and the electron affinity of 4H-SiC(0001) is given as Z1-1020.

[0371] The interface between the epitaxially grown β-Ga2O3(-201) layer and the 4H-SiC(0001) layer results in an energy band lineup as shown in Figure 49. The conduction band edge Z2-2020 is shown along the device growth direction in Figure 9C at the heterointerface junction. The drift region is n-type (5e16cm). -3 ) and the n-type 4H-SiC region is 1e19cm -3As shown, this results in a discontinuity in the conduction band, inducing a triangular potential well on the Ga2O3 side. Furthermore, the device configuration in Figure 9C shows that the first quantization energy level in the potential well falls below the Fermi energy, inducing a two-dimensional electron gas (2DEG) in the heterojunction. An example of a 2DEG localized in the heterojunction, the lowest energy quantization electron wavefunction, is shown as Z2-2010. The presence of the 2DEG is advantageously used in this disclosure to form an electrical contact between the two regions, effectively pinning the conduction band locally.

[0372] The devices, structures, and methods described herein may include crystallographic matching of two different crystalline space groups (SGs), including Ga2O3 (SG=C2m) and 4H-SiC (SG=P63mc).

[0373] Figures 50 and 51 show the detailed atomic arrangement of Si and C atoms in a single-crystal 4H-SiC polytope, oriented along the C direction Z3-3020, respectively. Figure 50 shows the single-crystal unit lattice Z3-3010 containing a wurtzite-like hexagonal atomic arrangement. The polarity orientation refers to Si-C bonds oriented along the

[0001] or [000-1] axis, as is evident from the Si and C planes shown. C-plane (i.e., (0001) or (000-1)) oriented surfaces with in-plane Si-Si and CC lattice spacings a(Si-Si) = 3.095 Å are shown in Figure 51. The stacking order along the Si polarity direction is (ABCBABCB-...) with an equal number of cubic and hexagonal bonds.

[0374] Epitaxial bonding of single-crystal Ga2O3 compositions is possible on different SiC surfaces, but Ga2O3 can be formed in various polytopes exhibiting distinct symmetry groups selected from monoclinic (C2m), rhombohedral (R3c or R3m), orthorhombic (Pna21), cubic (Fm3m), and even hexagonal (P63mc). Ideally, a single, uniform polytope is desirable for the epitaxial layer to achieve the best electronic performance in this application. Mixed polytope epitaxial layer compositions are possible, but may produce lower quality materials and devices. The stability of a given polytope epitaxially formed on a SiC surface is governed not only by several factors, namely (i) in-plane lattice mismatch between different crystal symmetry space groups of the epitaxial layer and the substrate relative to a given crystal orientation plane and epitaxial layer, (ii) surface energy of the SiC surface, (iii) first bonding species of the SiC surface to a first complementary species of Ga2O3 (i.e., Ga or O), and (v) the relative ratio of incident flux Ga and active O atoms chemiadsorbed and physiadsorbed at a given surface deposition temperature, but also by other factors.

[0375] The devices, structures, and methods described herein may include a beta-phase monoclinic form of Ga2O3 that can be stabilized to a wide growth window by selective deposition on a prepared C-plane surface of 4H-SiC. Furthermore, as shown in Figure 52, the β-Ga2O3 film is epitaxially formed in a layered growth mode oriented in the [-201] crystal direction Z4-4020. In monoclinic Ga2O3, 50% of the Ga-O bonds are tetrahedral and the remaining 50% are octahedral. The coordination of the O-terminated SiC surface, along with its influence on the stacking order of the Ga2O3 epitaxy, will be discussed later. Of interest is the stacking order of Ga atoms and O atoms along the epitaxial growth direction Z4-4020. The atomic plane consists of a buckled Ga-Ga layer followed by a substantially planar two-dimensional O lattice, a substantially planar two-dimensional Ga lattice, and again a substantially planar two-dimensional O lattice, and this order is repeated along the growth direction. During the simultaneous deposition of Ga and O species, self-assembly of the crystal structure occurs. An optional final surface on the (-201) plane is shown as the oxygen-terminated surface Z4-4030. This can be achieved after epitaxial deposition by exposing its surface to active O species (or only active O species). In Figure 53, the surface reconstruction of the O-terminated surface is shown, indicating a hexagonal arrangement of O atoms Z4-4010.

[0376] Figure 54 shows a further simplified lattice model for evaluating the lattice mismatch of the first Si-terminated or C-terminated surface of the axial C-plane oriented 4H-SiC of Figure 54, which has a planar hexagonal system with interatomic distances a(Si-Si)=a(CC)=3.095 Å.

[0377] Figure 55 shows the oxygen hexagonal lattice on the oxygen-terminated (-201) oriented β-Ga2O3 surface. The O lattice is a modified hexagon with a range of 2.985 ≤ a(OO) ≤ 3.083 Å. This allows us to estimate the range of the in-plane lattice constant mismatch (LM) as follows:

[0378]

number

[0379] In practice, LM < 5% is desirable for epitaxial layers with low defect density, indicating that the O lattice can respond elastically to in-plane compressive strain.

[0380] Figure 56 schematically shows possible epitaxial orientations for manufacturing oxide-SiC articles. A C-plane cut 4H-SiC substrate Z9-9030 can be oriented to present either a Si plane or a C plane for epitaxial deposition. The intrinsic polarity Z9-9040 of 4H-SiC affects the surface electron affinity (shown in Figure 48) and, consequently, the heterojunction band alignment with the epitaxial oxide. If the 4H-SiC is oriented with a surface normal Z9-9010, this defines the epitaxial growth direction Z9-9010. The epitaxial layer may also be grown / organized at an angle such that the surface normal does not perfectly coincide with the epitaxial layer crystal plane. For example, the semiconducting oxide Z9-9020 may be β-Ga2O3. The first surface of the epitaxial layer Z9-9050 can be predetermined by the growth sequence in which the epitaxy process is initiated. Furthermore, the final epitaxial layer surface Z9-9060 may also be predetermined by the growth process.

[0381] Further analysis of the C-plane oriented surface structure of 4H-SiC is shown in Figures 57A, 57B, 57C, and 57D.

[0382] Figure 57A shows a cross-sectional view of the atomic arrangement of a prepared C-plane 4H-SiC crystal with Si polarity Z10-10010, presenting the final surface having the outermost Si atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing at up to approximately 1000°C. If desired, exposure of low-flux Si atoms impacting the surface can also ensure the final Si surface state after the desorption of native silicon oxycarbide. Exposure of the Si-terminated surface by the active species of oxygen can self-limit the surface to have an O-terminated surface. In that case, the stacking order is -O-Si-C-Si-C- from the surface downwards.

[0383] Figure 57B shows a cross-sectional view of the atomic arrangement of a prepared C-plane 4H-SiC crystal with C polarity Z10-10020, presenting the final surface having outermost Si atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing at up to approximately 1000°C. Optionally, exposure of low-flux Si atoms impacting the surface can also ensure the final Si surface state after the desorption of native silicon oxycarbide. Exposure of the Si-terminated surface by the active species of oxygen can self-limit the surface to have an O-terminated surface. In that case, the stacking order is -O-Si-C-Si-C- from the surface downwards.

[0384] A comparison of Figure 57A and Figure 57B reveals oxygen bonds between surface O-Si atoms with distinct bond symmetries that indicate the preferred next adsorbed atomic layer in the Ga configuration (see Ga and O configurations in Figure 52).

[0385] Oxygen can bond to either Si or C in terms of bond strength: E 結合 (Si-O) = 452 kJ / mol, E 結合 (Si=O)=590kJ / mol, E 結合 (CO) = 360 kJ / mol, and E 結合 (C=O)=715kJ / mol Figures 57C and 57D show alternative first oxygen bond configurations to the carbon outermost surface constructed on Si-polar or C-polar 4H-SiC surfaces, respectively.

[0386] Figure 57C shows a cross-sectional view of the atomic arrangement of a prepared C-plane 4H-SiC crystal with Si polarity Z10-10030, presenting the final surface with outermost C atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing above approximately 1000°C. Optionally, exposure of low-flux C atoms impacting the surface can also ensure the final C surface state after desorption of native silicon oxycarbide. Exposure of the C-terminated surface by the active species of oxygen can self-limit the surface with an O-terminated surface. In this case, the stacking order is -OC-Si-C- from the surface downwards. Further crystal growth is shown with an additional Ga adsorption layer, where the tetragonal bonding arrangement is shown to form the order -Ga-OC-Si-C-.

[0387] Figure 57D shows a cross-sectional view of the atomic arrangement of a prepared C-plane 4H-SiC crystal with C polarity Z10-10040, presenting the final surface with outermost C atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing above approximately 1000°C. Optionally, exposure of low-flux C atoms impacting the surface can also ensure the final C surface state after desorption of native silicon oxycarbide. Exposure of the C-terminated surface by the active species of oxygen can self-limit the surface with an O-terminated surface. In this case, the stacking order is -OC-Si-C- from the surface downwards. Further crystal growth is shown with an additional Ga adsorption layer, where tetragonal or octagonal bonding arrangements are shown to form the order -Ga-OC-Si-C-.

[0388] Preparation of the SiC surface is a crucial step in realizing a high-quality single-crystal β-Ga2O3(-201) oriented epitaxial layer using the methods and structures disclosed herein.

[0389] Figures 57E and 57F show the effect of a misoriented C-plane 4H-SiC surface (i.e., miscut at an angle > 0 from the axial surface) on the epitaxial layer growth of Ga2O3.

[0390] Figure 57E shows a cross-sectional view of a Si polar 4H-SiC crystal along the

[0001] direction Z10-10010, having a miscut surface Z10-10070 tilted at an angle q from the on-axial c-plane surface Z10-10050. Z10-10065 is the miscut direction perpendicular to the substrate surface, and direction Z10-10060 is the c-axis of SiC. The angle q (or miscut angle) in Figure 57E is not drawn to scale. In some cases, q is 2 to 6 degrees, or about 4 degrees. Below the plane of the miscut surface Z10-10070, the SiC crystal is included, and above it, epitaxial Ga2O3 growth is included. The epitaxial layer can grow either along the Z10-10060 direction with stacking faults, or tilted at a substantially directed inclination at the epitaxial layer crystal plane Z10-10055. Figure 57F schematically shows the growth of an epitaxial layer crystal plane having a step-terrace surface Z10-10080 on a 4H-SiC crystal Z10-10080, with an inclined plane Z10-10055.

[0391] Figure 57G further discloses an exemplary process flow Z10G-1000 for manufacturing the structural template surfaces disclosed in Figures 57A, 57B, 57C, and 57D, which can be further incorporated into the structures and devices disclosed herein.

[0392] The integration of two different crystal symmetry groups (SGs) begins with epitaxial deposition of an oxide having symmetry group SG-2 (e.g., monoclinic Ga2O3) onto a substrate having symmetry group SG-1 (e.g., hexagonal 4H-SiC). Favorable alignment of SG-2 and SG-1 can be achieved by carefully selecting the crystal planes of the substrate to match the possible epitaxial planes of the SG-2 oxide. For example, the Si polar planes of the C-plane 4H-SiC can be terminated with Si sublattice planes. The Si sublattice can be terminated with an oxygen adsorption layer, thereby forming a coupling layer with the Ga adsorption atomic layer.

[0393] The final surface of the oxide epitaxial layer (e.g., β-Ga2O3) can also be terminated with a surface type and species suitable for the subsequent formation of a high-quality first metal layer. The thickness of the first metal layer can be approximately 1-10 nm or more, followed by another second metal layer.

[0394] Figure 57H shows another example of a manufacturing process flow for epitaxial deposition of a thick oxide film on a SiC substrate. The growth conditions required for Ga and O to self-assemble into a specific Ga2O3 polytope (e.g., monoclinic) can be achieved by providing the growth temperature, a predetermined incident flux, and the ratio of co-deposited Ga to reactive oxygen species. Stacking faults and other crystal misalignments and coordinations may occur and can accumulate as a function of film thickness. An exemplary method for achieving thick epitaxial films beyond a certain co-deposit thickness limit is to interrupt growth to stop film growth and restore surface quality. For example, epitaxial growth of β-Ga2O3(-201) can be interrupted after approximately 100 nm of growth and annealed in an oxygen environment by stopping the Ga flux. Surface improvement can be demonstrated by in-situ diagnostics. Epitaxial growth can be restarted for a predetermined time or at a performance index indicating film quality. This cycle can be repeated multiple times until the desired thickness is achieved. In some cases, growth interruption introduces non-growing species such as nitrogen, atomic nitrogen, surfactants (e.g., bismuth, or zinc, or magnesium, or germanium), hydrogen, or atomic hydrogen.

[0395] Figure 58 shows experimental data for epitaxial β-Ga2O3(-201) films directly deposited on the surface of a prepared axial n-type 4H-SiC(0001) oriented substrate. Atomic beam epitaxy was performed in an ultra-high vacuum deposition chamber using pure Ga metal and an activated oxygen source from a high-power quartz valve inductively coupled RF plasma source. In some exemplary growths, O2, N2, and N2O were co-supplied to one or more RF plasma sources. Epitaxy systems and methods are described, for example, in U.S. Patents 10,964,537, 11,282,704, 11,342,484, and 11,670,508, which are incorporated herein by reference.

[0396] The 4H-SiC substrate in the example shown in Figure 58 was directly heated with a high-temperature or mid-infrared emissivity SiC heater. The wafer was rotated and positioned relative to the source during growth to allow for the deposition of a very uniform film on a 4” diameter wafer. The substrate growth temperature ranged from 500 to 1000°C, depending on the resistivity of the SiC substrate. N-type 4H-SiC(0001) substrates were grown at approximately 500–700°C without back coating, due to the direct match of emissivity between the heater and the substrate. Semi-insulating 4H-SiC substrates were grown at approximately 700–950°C without back coating, due to the direct match of emissivity between the heater and the substrate. In several exemplary epitaxial growths, it was found that the highest quality single-crystal films were obtained from higher substrate deposition temperatures.

[0397] Reflected high-energy electron diffraction (RHEED) is an essential in-situ diagnostic for direct and real-time evaluation of the quality and crystal structure of epitaxial layers. Figure 58 shows a RHEED image at high symmetry points as a function of azimuth rotation of the substrate around the surface normal of a β-Ga2O3(-201) epitaxial layer approximately 2 microns thick grown on the n-type 4H-SiC(0001)Si polar axis. Excellent single-crystal quality is evidenced by long, sharp RHEED diffraction streaks indicating an atomically flat film. RHEED streaks were monitored and maintained throughout the film growth process. The (-201) oriented film exhibits a 60-degree periodicity as expected and shows no polycrystalline arc or pyramidal surface features as spots.

[0398] Figure 59 shows a RHEED image of a thick β-Ga2O3(-201) epitaxial layer grown on an n-type 4H-SiC(0001)Si polar substrate that was intentionally miscut 4 times from the on-axial surface toward plane A. Sharp and strong streaks are also shown, which are curved due to the miscut of the substrate. Spots overlap the streaks, indicating that the incident RHEED electron beam is partially transmitted through the terrace steps. In this disclosure, it is determined that growth on a miscut SiC surface can give excellent Ga2O3 film quality with respect to rotational domains that are capable of (-201) reconstruction.

[0399] Figures 60A and 60B show in-situ oblique incidence laser reflectance at wavelength λ=405nm (see Figure 60A for instrument setup), providing further evidence of the high crystalline and optical quality of the epitaxial layer Ga2O3 grown on a SiC substrate. The high initial reflectance from the bare SiC surface (plot in Figure 60B) decreases with the deposition of the Ga2O3 film, and oscillations in optical thickness appear every λ / 2n (n(Ga2O3)=1.9). Growth rates (GR) between 0.1 and 4 angstroms per second are possible. Higher growth rates are also possible with scaled elemental sources and chamber characterization.

[0400] Figure 61A shows a wide-angle dicrystalline diffraction Ω-2θ symmetric scan of a Ga2O3 epitaxial layer on a SiC substrate. Sharp and strong Bragg peaks of β-Ga2O3n(-2 0 1) (n=1, 2, 3, 4, and 5) are shown, and there is no evidence of parasitic polytopes.

[0401] Figures 61B and 61C show the asymmetric X-ray diffraction reciprocal lattice maps near two Bragg peaks centered on 4H-SiC(107) and βGa2O3(-403) for a heteroepitaxial structure formed as a 2 μm thick βGa2O3(-201) / / 4H-SiC(0001)0-deg miscut. The RSM maps indicate that the oxide film is a single crystal of high quality and that different crystal symmetry space groups can be fitted to it.

[0402] In another example, Ga2O3 epitaxial layers can have other pure polytopes when deposited on alternating SiC surface orientations. For example, Figure 62 shows the crystal structure of alpha-phase Ga2O3 (SG=R3c), which is similar to sapphire and can form on AR- or M-plane SiC (2H-, 4H-, or 6H-). Figure 63 also shows a possible wurtzite-type crystalline polytope of Ga2O3 having SG=P63mc, which can form on several SiC substrate orientations. Other polytopes, e.g., SG=Pna21 or cubic (defective SG=Fm3m), are also possible. Of particular interest are the Pna21 and P63ms space groups, due to their intrinsic property of being polar crystals. This disclosure determines that new electronic devices can potentially be constructed using spontaneous and piezoelectric polarization-induced carrier doping by forming Ga-polar or O-polar Ga2O3 films (e.g., including Pna21 and P63ms space groups) on Si-polar or C-polar SiC.

[0403] Figure 64 schematically illustrates a novel embodiment of this disclosure aimed at pre-determining the electronic properties of the final surface of an oxide epitaxial film. It has been found that β-Ga2O3(-201) surfaces possess electron affinities sensitive to deposition conditions, post-deposition conditions, thermal annealing, annealing in oxygen, and other environmental exposures. Furthermore, it has been found that hydrogen can play a significant role in controlling the final state of surface electron affinities. Bulk regions of a β-Ga2O3 film or substrate, which may already incorporate hydrogen (or hydrogen-containing) impurities Z17-17020 dispersed throughout the bulk or within a thickness Z17-17030, are indicated as Z17-17010. For example, a bulk-grown Ga2O3 substrate exhibits high-level hydrogen-like impurities. These hydrogen-like impurities may be released from the surface region Z17-17040 by heat or chemical treatment Z17-17050, and the hydrogen-like (or hydrogen-containing) particles Z17-17045 may diffuse or migrate onto the surface Z17-17055 and be removed from the structure Z17-17060. Therefore, the outermost surface portion with a thickness of Z17-17035 may be different from the bulk region Z17-17030.

[0404] Conversely, the surface region Z17-17040 can be chemically or thermally treated in process Z17-17050, which introduces hydrogen-like species to a depth of Z17-17035 within the surface region Z17-17040. In one example, high-temperature epitaxial growth of an oxide layer is completed, and despite the growth temperature ramping down to ambient temperature over time (t), it is subjected to a large oxygen partial pressure. Oxygen annealing during the substrate temperature ramp-down after the growth of the epitaxial layer may induce an effect that selectively depletes the surface region Z17-17040 of impurities or depletes the surface of charge carriers. Such techniques can be useful, for example, if the epitaxial layer is co-doped with Si, Ge or Sn during epitaxy, the final surface region Z17-17040 may have significantly lower doping than the bulk region Z17-17010. Such depleted surfaces, if left unmodified, directly affect Schottky barrier formation, as discussed herein.

[0405] Figure 65 shows the effect on the surface of a highly doped n+ layer or a β-Ga2O3(-201) oriented epitaxial layer deposited as an n-type drift layer on a substrate. Conduction band edge E C (z) and valence band edge E V (z) is shown as a separated portion. In this example, Si-doped Ga2O3 by impurity donor doping is shown in the epitaxial layer ("epi") N ドリフト = 5e16cm -3 It is used.

[0406] If the surface after epitaxial growth is intentionally exposed to hydrogen and atomic hydrogen, a neutral surface can be created. However, as the substrate temperature rises, hydrogen exposure causes a layer to form within the epitaxial layer at a depth of Z. 蓄積 (Z 空乏、蓄積 A surface electron storage layer can be created that penetrates to the ) layer. Conversely, when the surface of the grown epitaxial layer is exposed to oxygen by increasing the temperature, a depletion surface is created. Possible scenarios of surface band curvature are shown in Figure 65 as “depletion surface” or “charge storage surface”.

[0407] Figures 65, 66A, and 66B show the effect of surface modification on the β-Ga2O3(-201) drift layer of a device similar to the one shown in Figure 9B, using Ni metal contacts. The SB potential on the neutral drift layer surface is φ SB = 1.05 eV, and a high barrier φ is present at the heterointerface on the depletion surface. SB = 1.3eV, but if surface charge is accumulated, φ SB This results in 0.85eV. The results for the forward bias IV are shown in Figure 66A (semi-logarithmic) and Figure 66B (linear) plots.

[0408] The plot shows that the surface state of the drift layer after growth directly affects the diode's turn-on voltage and subthreshold slope.

[0409] Figure 67 shows a comparison of the "clean" and "depleted" surfaces of the β-Ga2O3(-201) drift layer for a device structure similar to that shown in Figure 9B (but with a different contact metal), using various high-work-function metals. The clean surface is treated with hydrogen by heating, while the depleted surface is annealed in oxygen.

[0410] Figure 67 shows the large variation in the possible forward IV curves when metals with various high work functions are deposited on two types of surfaces (depleted or clean). This helps to explain the variation in experimental results for various devices and processing methods.

[0411] Figures 68A and 68B show exemplary process flows for manipulating the surface charge state of the final surface of an epitaxial oxide layer. The epitaxial oxide layer is grown at a high growth temperature T_growth in a highly oxidizing environment designed to form a metal oxide composition. After the growth of the epitaxial layer, the metal source is abruptly removed from the growth region, indicated as a “stop growth” step. Oxygen and reactive oxygen species in the growth chamber can range from 1e-6 to 1e-4 torr, and a finite amount of time is given to evacuate them from the chamber so that the epitaxial layer surface does not substantially interact. The substrate can be cooled to a lower or higher temperature at a ramp rate. In one example, the growth temperature is reduced to a lower idle value while the ambient gas environment is substantially oxygen.

[0412] In this example, the epitaxial layer surface may be modified to exhibit a depletion surface charge density. In another example, once the growth of the epitaxial layer is stopped, the oxidizing gas is removed and replaced with an alternative gas species, or the surface is left gasless. The alternative gas species may be nitrogen or argon, thereby ensuring that the surface does not substantially interact with the gas during the ramp to idle temperature. In yet another example, the grown epitaxial layer is held at a high or low temperature while the chamber gas is simultaneously replaced with a non-oxidizing hydrogen species such as hydrogen, a forming gas, or hydrogen plasma, or methane. In yet another example, the surface may be exposed to hydrogen and oxygen, or hydrogen peroxide, or hydrocarbons. During the ramp to idle temperature, the hydrogen species may be maintained or evacuated.

[0413] After the surface charge state is achieved, the epitaxial layer article can be transferred to another chamber under vacuum, or it can remain in the growth chamber for subsequent in-situ direct metal deposition. The metal deposition can be a high work function metal deposited directly onto the epitaxial layer surface whose charge state has been altered. In one example, a nickel efflux source is used to deposit pure Ni directly onto a β-Ga2O3(-201) surface under a UHV environment. In one example, the Ni can be epitaxial and directly form a first Ni(111) oriented metal layer on a hexagonal β-Ga2O3(-201) surface. The surface charge of β-Ga2O3(-201) can be maintained by the in-situ Ni(111) cap. Subsequent in-situ extraprocessing may deposit additional metal(s) to increase the thickness of the contact layer and improve mechanical strength and / or conductivity.

[0414] In some cases, a Ni oxide layer can be directly formed on the oxygen-terminated β-Ga2O3(-201) surface before forming the Ni metal cap.

[0415] Figure 69 illustrates the direct deposition of an epitaxial Ni metal contact layer (SB) onto a semiconducting β-Ga2O3(-201) surface ("Semi"). A monolayer of oxygen (OI) can be used on the O-terminal surface to form a linkage bond to the nickel (M) metal contact (SB). In some cases, a thick, intentional deposition of NiO can be formed before the Ni metal cap is formed. Structures similar to those shown in Figure 69 are also possible. In some cases, any of the metallic materials used for Schottky metals as described herein can form an oxide at the interface between the drift layer and the Schottky metal layer. For example, any of the metallic materials in Figure 11A can form an oxide containing the metal species and oxygen (e.g., PtO2) at the interface between the drift layer (e.g., including Ga2O3 or other epitaxial oxide materials) and the metal layer (Schottky contact). In some cases, the metal oxide forming the Schottky barrier can form an intermediate layer as described herein. In some cases, the metal oxide forming the Schottky barrier may be thicker than the example shown in Figure 69. For example, it may have a thickness within the range of intermediate layers described herein.

[0416] The devices, structures, and methods described herein may include in-situ single-crystal Ni(111) oriented films deposited directly onto a β-Ga2O3(-201) surface under low temperature and high vacuum (<1e-8 torr).

[0417] Furthermore, many other possible configurations exist for implementing an intermediate layer (IL) or drift layer containing a UWBG oxide composition.

[0418] Figures 70A to 70G show experimental examples of epitaxial structures including an epitaxial β-Ga2O3(-201) layer and an epitaxial Ni(111) layer formed on a SiC(0001) substrate. The Ni(111) layer in this example was 20 nm thick. The epitaxial structure in this example was formed by MBE using the techniques described herein, for example, method Z10G-10000 in Figure 57G, or methods Z21-21010 and Z21-21020 in Figures 68A to 68B.

[0419] Figure 70A schematically shows a multilayer epitaxial structure 70100, which includes a SiC substrate 70105, an epitaxial semiconducting oxide layer 70110, an epitaxial metal layer 70115, an optional further contact layer 70120 to the metal layer 70115, and an optional contact layer 70125 to the substrate 70105.

[0420] Figure 70B shows the highly symmetric in-plane azimuth (φ=203) of structure 70205, which includes a single-crystal epitaxial β-Ga2O3(-201) oriented layer formed on a 4-degree miscut n-type Si polar 4H polytope SiC(0001) substrate on its outermost surface. o The RHEED image 70200 of the diffraction pattern is shown. The single-crystal high-quality oxide film is shown by elongated, thin RHEED streaks in Figure 70B.

[0421] Figure 70C shows the in-plane azimuth (φ=203) of structure 70215, which contains a single-crystal epitaxial metallic Ni(111) oriented layer directly deposited on the single-crystal epitaxial β-Ga2O3(-201) oriented surface of structure 70205. o The RHEED image 70210 of the diffraction pattern is shown. The single-crystal high-quality metal film is shown by elongated, thin RHEED streaks in Figure 70C.

[0422] Figure 70D shows a highly symmetrical surface with an in-plane azimuth (φ=203) of the same structure as Figure 70B, including a single-crystal epitaxial β-Ga2O3(-201) oriented surface directly deposited on a 4-degree miscut n-type Si polar 4H polytope SiC(0001) substrate. oThe RHEED image of the diffraction pattern 70300 is shown. The single-crystal high-quality oxide film is again shown by elongated, thin RHEED streaks as indicated.

[0423] Figure 70E shows the same highly symmetric in-plane azimuth (φ=203) of structure 70215, which includes a single-crystal epitaxial metallic Ni(111) oriented surface directly deposited on the single-crystal epitaxial β-Ga2O3(-201) oriented surface of structure 70205. o The RHEED image 70310 of the diffraction pattern is shown. The single-crystal high-quality metal film is again shown by elongated, thin RHEED streaks as indicated.

[0424] The RHEED results shown in Figures 70C and 70E indicate that the periodicity of the surface azimuth RHEED diffraction pattern is Δφ = 60. o We have confirmed that this occurs in each instance, indicating a Ni(111) orientation film containing face-centered cubic crystals.

[0425] Figures 70F and 70G show wide-angle X-ray diffraction plots 70400 and high-resolution X-ray diffraction plots 70500, respectively, of the completed multilayer structure 70215, which includes an epitaxial Ni(111) layer formed on an epitaxial β-Ga2O3(-201) layer formed on a Si polar 4H polytope SiC(0001) substrate. Inset 70505 shows the atomic structure of the Ni(111) oriented surface. The high-resolution X-ray diffraction plot 70500 in Figure 70G includes thickness fringes of the Ni(111) peak, indicating a high-quality interface and a low-surface-roughness structure 70215.

[0426] Figures 70B to 70G clearly show Bragg diffraction patterns of phase-pure (or single-phase) semiconducting oxides and Ni metals, which exhibit consistent epitaxial relationships between the deposited layers, as observed in the RHEED and X-ray diffraction results.

[0427] Figures 71A, 71B, 72, and 73 disclose a range of suitable UWBG semiconducting oxide compositions that are possible and advantageous for improving the performance of semiconductor devices, such as high-power devices and diodes.

[0428] In general, any material described herein (for example, any composition of material 1 to 7, (Mg x Zn 1-x )(Al y Ga 1-y )2O4 (wherein 0≦(x,y)≦1), or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein the formula 0≦(x,y,z)≦1), or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4(wherein 0≦(x,y,z)≦1), or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦(p,x,y,z)≦1) can be used for drift layers, intermediate layers, and other layers of the devices, structures, and methods described herein.

[0429] For example, Figure 71A discloses possible bandgap ranges for compositions in the form of zinc-gallium oxide and zinc-aluminum oxide. ZnGa2O4 and ZnAl2O4 in spinel structures exhibit SG=Fd3m and are deposited as (111)-oriented films on β-Ga2O3(-201) or C-plane 4H-SiC.

[0430] In another example, Figure 71B discloses possible bandgap ranges for compositions in the form of magnesium-gallium oxide and magnesium-aluminum oxide. Spinel structures of MgGa2O4 and MgAl2O4 exhibit SG=Fd3m and are deposited as (111)-oriented films on β-Ga2O3(-201) or C-plane 4H-SiC.

[0431] In other examples, Figures 72 and 73 show quaternary composition oxide materials that can be used for drift layers, intermediate layers, and other layers in the devices, structures, and methods described herein.

[0432] Figure 73 shows the possible band gap variations for magnesium-zinc-gallium oxide and magnesium-zinc-aluminum oxide.

[0433] Figure 74 shows the possible band gap variations for magnesium-aluminum-gallium oxide and zinc-aluminum-gallium oxide.

[0434] In some cases, the drift layer, intermediate layer, and other layers of the devices, structures, and methods described herein may be of the spinel type (SG=Fd3m) (Mg x Zn 1-x )(Al y Ga 1-y )2O4 (wherein 0≦(x,y)≦1) can be included, and the composite oxide formed thereby can be realized as intrinsic, p-type, or n-type conduction (without impurity doping), thereby eliminating the need for impurity doping. In another form, spinel can be deposited as a (111) oriented film on β-Ga2O3(-2O1) or C-plane 4H-SiC.

[0435] In one example, (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4 (wherein 0≦(x, y, z)≦1), or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2zA composite oxide formed by (wherein 0≦(x,y,z)≦1) (for example, having a spinel form (SG=Fd3m)) can be used in the structures and devices described herein as intrinsic, p-type, or n-type conducting (without impurity doping), thereby eliminating the need for impurity doping. In another embodiment, spinel can be deposited as a (111)-oriented film on β-Ga2O3(-201) or C-plane 4H-SiC in the structures and devices described herein.

[0436] Other SG forms of Ga2O3 (e.g., α-phase or β-phase), (Al x Ga 1-x )2O3 (e.g., α-phase or β-phase) (wherein 0≦x≦1), Mg x Ga 2(1-x) O 3-2x (in the formula, 0≦x≦1), Mg x Al 2(1-x) O 3-2x (In the formula, 0≦x≦1), (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Ga y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Al y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Mg x Ga y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Mg x Al y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Ni x Ga y O z (In the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Ni x Al y O z(wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (wherein 0<x<1, and 0<y<1), or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4 (wherein 0≦(x, y, z)≦1), or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦(p, x, y, z)≦1) can also be used in the materials, structures, and devices described in the present specification.

[0437] Yet another aspect of the heterojunction β-Ga2O3(-201) / 4H-SiC(0001) associated with the doping density of SiC is disclosed.

[0438] As shown in Figure 74 and Figure 75, considering the diode formed as structure 75-28010, an anode contact (A) and a β-Ga2O3(-201) epilayer deposited on a 4H-SiC(0001) layer or substrate on the Si polarity axis with a cathode contact (K) are shown. Further, the oxide is n-type and is doped to a concentration of 1e17cm-3, but the n-type doping concentration of the 4H-SiC layer varies

[0439] [Equation]

[0440] is considered. Figure 74 shows the complete conduction and valence band structure as a function of the growth direction. The conduction band heterointerface is magnified in Figure 75, showing the depletion effect in the junction extending within the SiC region. In this case, low

[0441]

number

[0442] For example, in the diode structure shown in Figure 9C, a large potential barrier is generated, which can significantly affect device performance.

[0443] Therefore, it can be advantageous to control the doping density of the SiC (substrate or layer) by controlling the epitaxy process used to fabricate the structure. For example, a highly conductive 4H-SiC substrate can be prepared for epitaxial oxide growth. While the SiC substrate is heated in a vacuum to the required growth temperature, the surface of the SiC substrate may change its surface charge density and desorb potential impurity dopants. This can significantly reduce the 4H-SiC surface donor density, potentially creating a remarkably large depletion region extending within the SiC material. As a result, the on-resistance of the diode may become higher, and electrical losses may increase.

[0444] In some cases, the SiC substrate is heated to the required growth temperature in an environment that avoids changes in surface charge density. For example, the SiC substrate may be heated in an inert environment or under a Si flux to prevent Si desorption.

[0445] Those skilled in the art may not fully understand that heterojunctions formed at the interface between two different oxide materials can also form complex interactions. Metal-[oxide-semiconductor] junctions, as described above, can form Schottky barrier contacts or ohmic contacts. Heterojunctions between two oxides with different bandgap energies, compositions, electron affinities, and even different dielectric constants directly affect the properties near the heterojunction.

[0446] FIG. 76 shows a simplified cross-sectional physical structure of a drift oxide semiconductor with a portion of the drift oxide surface having metal deposited along the A-A' direction parallel to the growth direction z. Similarly, the aforementioned isolation layer (see FIG. 79 to FIG. 86) functioning as a dielectric insulator between the field plate and the oxide drift layer is also formed along a portion of the oxide drift surface along the B-B' direction, as shown. Isolation layer (ISO) t isо and the thickness of the drift layer t ドリフト are indicated. Assuming that the isolation layer further comprises an oxide material composition having a wider bandgap energy than the oxide composition of the drift layer, E g1 <E g2 , and the equivalent energy band diagram along the B-B' direction is shown in FIG. 77.

[0447] FIG. 77 is a plot of a spatial energy band diagram of a heterojunction formed between an oxide semiconductor drift and a dissimilar oxide or material region forming an isolation region. The left side of the spatial conduction band diagram E C (z) corresponds to the drift layer, the right side corresponds to the isolation layer, and the position of the equilibrium Fermi energy E F is between two possible first electron quantization states in the inversion potential well located at the heterointerface.

[0448] E F is located above the first quantized electron state, a heterointerface two-dimensional electron gas with surface charge N s int >0 may exist, which forms a negatively charged sheet at the interface. This charge sheet may be continuous or discontinuous depending on the surface roughness at the interface, which represents a surface leakage path that is detrimental to vertical conduction device operation. This can be utilized in lateral transport devices.

[0449] Conversely, when E F is located below the first quantized electron state, the heterointerface does not accumulate surface charge (N SSince it is (=0), it can potentially function as a suitable blocking barrier.

[0450] A further aspect unique to the interaction between steep interfaces between different oxide material compositions is the possible large variation in dielectric constant and the resulting large discontinuity of dielectric constant at the heterointerface Δε=ε ドリフト -ε iso The dielectric confinement (deconfinement) effect can increase (decrease) the Coulomb interaction between charge carriers located in discontinuity or near discontinuity.

[0451] For example, if the drift layer is Ga2O 3を含み、 If the separation layer contains a low-k dielectric material, then Δε = ε ドリフト -ε iso >0. Alternatively, in another example, if the drift layer contains Ga2O3 and the separation layer contains a high-k dielectric material, then Δε = ε ドリフト -ε iso It becomes < 0.

[0452] Figure 78A shows a table of calculated static and optical dielectric constants for several exemplary UWBG oxide materials suitable for application to this disclosure. Some materials exhibit properties that depend on the crystal orientation.

[0453] The concepts of dielectric confinement and screening are treated herein with specific reference to the boundary between two slabs of oxide materials with dissimilar dielectric constants.

[0454] Figures 78B and 78C plot electrostatic equipotential lines between two equal-quantity, opposite-sign charge regions placed in slabs of different dielectric constants of the host material, separated by a distance of 0.5 units in the x-direction. Figure 78B shows the case where the dielectric constants of both the left slab (ε1) and the right slab (ε2) are equal. Symmetrical equipotential lines are shown. However, when the ratio ε2 / ε1 = 10 is shown, in Figure 78C, the equipotential lines are highly asymmetric across the heterodielectric interface with respect to the potential screened in the slab of the higher dielectric constant.

[0455] From Figures 78B and 78C, the electric field strengths shown in the contour plots of Figures 78D and 78E, respectively, are calculated. The electric field screening effect in the high-dielectric region is shown. The quantitative value of the electric field vector is calculated near the heterodielectric interface and is shown in Figures 78F and 78G.

[0456] Figure 78F shows the electric field E X (E Y This shows the spatial variation of the x and y components of ). When both halves of the structure have equal dielectric constants, i.e., ε² / ε¹ = 1, E along the interface X and E Y The symmetry of the components is shown for three cases: the interface x=0 and small amounts on both sides (x=+ / -0.005 units). As expected, the symmetry of the curve reflects equiquantity of oppositely charged charges.

[0457] Figure 78G shows a simulation for the case ε2 / ε1=10, where the electric field in the high dielectric region is substantially screened as shown. This phenomenon can be utilized in this disclosure to engineer the maximum electric field generated within the device structure due to manufacturing-induced geometric shape effects. For example, sharp edges typically formed around metal contacts by photolithography, lift-off, or etching can generate unfavorable fringing electric fields. Therefore, it is desirable to control these fringing electric fields with sharp metallic features, as the electric field may exceed the yield strength of the oxide electric field.

[0458] Figures 79 and 80 show two-dimensional electrostatic models of two types of vertical multilayer semiconductor devices used to form Schottky barrier diodes.

[0459] Two similar structures are shown, distinguished by the thickness between the field plate (FP) overhang region and the final surface (F4) of the drift region. The SiC substrate F3 is electrically conductive, while the isolated region F2 is given the property of having a dielectric constant that can be selected differently from the drift layer, although it has a bandgap energy beyond the drift region. Region F1 is taken as air, and the drift region F4 is Ga2O3 with a low charge density. The gap between the FP and the drift region is 0.4 units in the longitudinal direction of the model in Figure 79 and 0.05 units in the longitudinal direction of the model in Figure 80. Furthermore, the Schottky metal contact is depicted as a split field plate, with the left side having no field plate overhang. This allows for comparison of designs with and without a field plate in the same simulation. The contribution of the FP to the overall device capacitance is greater in small gap configurations, which is important for high-speed switching applications.

[0460] Figures 81 and 82 show the magnitude of the spatial electric field calculated as contour lines between a thin FP biased at +1000V and the rear contact at -1000V. The dielectric constant of all regions is considered, and in Figure 81, ε ISO / ε ドリフト = 0.2, and in Figure 82, ε ISO / ε ドリフト = 3.

[0461] Figures 83 and 84 show enlarged views of the “thick” FP (Functional Product) of the electrostatic field contour lines for low-k and high-k, respectively.

[0462] Figures 85 and 86 show magnified views of the "thin" FP (Functional Product) of the electrostatic field contour lines for low-k and high-k, respectively.

[0463] The quantitative potential energy near the horizontal interface of the drift layer in contact with the metal contact and the separation layer was calculated. Figures 87 and 88 plot the cases of thin FPs with low-k and high-k separation materials, respectively. The potential is maximum at the metal interface, slightly lower near the contact, but located slightly below the interface. The lateral magnitude of the FP indicates that the potential is maintained for high-k separation materials, but decreases rapidly for low-k separation materials.

[0464] The spatial magnitude of the electric field near the interface is plotted in Figures 89 and 90 for thin fission products (FPs) with low-k and high-k separating materials, respectively. The large peak in the electric field located at the metal contact corner and the effect of lateral FPs are clearly evident. The results indicate that the high-k separating layer is effective in reducing the peak electric field at the metal contact critical point.

[0465] Further analysis of the split FP structure allows for a direct comparison of the maximum electric field generated at the interface between the drift layer and the metal contact.

[0466] Figures 91 and 92 are plots of the spatial variation of the magnitude of the electric field generated at the heterointerface within the structure of three horizontal planes slightly above and below the heterointerface between the drift layer and the separation layer. The device structure is the spacing between the thin field plate / separation layer / drift layer.

[0467] Figure 91 shows the maximum electric field within the structure at the drift layer and metal contact interface region, for "without field plate" and "with field plate," as a function of the dielectric constant used in the separation material. It is shown that FP reduces the maximum electric field in all cases, regardless of whether the dielectric constant of the separation layer is lower or higher than that of the drift layer material. ε of FP ISO / ε ドリフトWhen the value exceeds 4, the diminishing returns effect appears, but in another example, combining a conformal high-k dielectric with a simple metal mesa contact may provide excellent performance. It is also possible to deposit a high-k isolation layer and then etch the region for defining the Schottky metal contact. Figure 92 further investigates the ratio γ of the maximum electric field with and without FP by defining it as follows.

[0468]

number

[0469] In Figure 92, when the dielectric constant ratio of the isolation layer and the drift layer is in the range of approximately 0.5 ≤ κ ≤ 2.0, the greatest advantage of Fp is observed at the smallest ratio γ. In this range, it is possible to reduce the maximum electric field by approximately 45%. For high-k (i.e., κ > 3.0) isolation materials, dielectric confinement and screening become dominant, and simple metal mesa-type contacts become efficient, thus reducing the usefulness of FP.

[0470] In various embodiments, the results of the above investigations of the isolation layer material and the effects of FP may be taken into consideration when optimizing the diode design according to this disclosure.

[0471] Figure 93 shows a two-dimensional electrostatic model used to investigate simple metallic mesa-type Schottky contacts embedded in isolation materials of various dielectric constants.

[0472] Figure 94 plots the results of calculations for drift and the maximum surface electric field strength at the metal / separation layer interface. By utilizing a separation layer material selected for its high dielectric constant, the peak surface electric field can be reduced by an order of magnitude. High dielectric materials with a band gap larger than the drift regi...

Claims

1. A method for manufacturing an integrated circuit, wherein the method is A composite substrate is prepared having an upper substrate layer containing single-crystal silicon carbide and a lower substrate layer containing polycrystalline silicon carbide. The process involves epitaxially growing an active layer on the aforementioned upper substrate layer, The active elements are formed in and on the active layer, The handle is joined to the upper surface of the active element, The method comprising removing the lower substrate layer.

2. The method according to claim 1, wherein the active element is a vertical insulated gate bipolar transistor.

3. The method according to claim 1, wherein the active element is a vertical MOSFET.

4. The method according to claim 1, wherein the active element includes a silicon carbide layer.

5. The method according to claim 1, wherein the active element includes a gallium oxide layer.

6. The method according to claim 1, wherein the upper substrate layer is formed on the lower substrate layer by a layer transfer process.

7. The further includes forming a heat sink on the back of the integrated circuit, The method according to claim 1, wherein the heat sink is not directly adjacent to the channel region of the active element.

8. A drilled region is formed in the active layer that exposes the first portion of the active element from the back surface of the integrated circuit. The method further includes depositing an electrically insulating heat dissipation layer on the excavated area, The method according to claim 1, wherein the excavation area defines the remaining portion of the material having the same lateral extent as the second portion of the active element.

9. The method according to claim 1, further comprising removing part or all of the upper substrate layer.

10. The active element has a gate region, a source region, a drain region, and a channel region. The method according to claim 1, wherein the channel region is located below the gate region and between the source region and the drain region.

11. The active element is a vertical diode device having an anode contact region, an upper contact region, a drift region, and a cathode contact region. The upper contact region is located below the anode contact region. The drift region is located below the upper contact region. The method according to claim 1, wherein the cathode contact region is located below the drift region.

12. The method according to claim 1, wherein the active element is a vertical transistor device, a vertical bipolar device, or a vertical unipolar device.

13. The active element is a vertical multilayer semiconductor diode device having an epitaxial drift layer formed on the active layer on the composite substrate, a metal layer formed on the epitaxial drift layer, and a field plate layer formed on the metal layer. The method according to claim 1, wherein the metal layer and the epitaxial drift layer form a Schottky barrier junction.

14. The active element is a T-channel vertical multilayer semiconductor diode device having an oxide semiconductor drift layer formed on the active layer on the composite substrate, an oxide semiconductor channel region formed on the oxide semiconductor drift layer, and a Schottky metal layer formed on the oxide semiconductor channel region. The method according to claim 1, wherein the Schottky metal layer and the oxide semiconductor channel region form a Schottky junction.

15. A method for manufacturing an integrated circuit, wherein the method is Prepare a substrate containing single-crystal silicon carbide, Epitaxial growth of an active layer containing an oxide on the aforementioned substrate, The active elements are formed in and on the active layer, The handle is joined to the upper surface of the active element, The method comprising removing at least a portion of the substrate from the back surface of the integrated circuit.

16. The method according to claim 15, wherein the active element is a vertical insulated gate bipolar transistor.

17. The method according to claim 15, wherein the active element is a vertical MOSFET.

18. The channel region is formed by a first ion implantation into the active layer, Forming a source region by a second ion implantation into the active layer, Forming a drift region in the active layer, The method according to claim 16, further comprising forming a drain region on the back surface of the integrated circuit.

19. The method according to claim 15, wherein the oxide is gallium oxide.

20. The substrate is a composite substrate having a first portion and a second portion formed on the first portion. The first portion contains polycrystalline silicon carbide, The second portion contains single-crystal silicon carbide, The method according to claim 15, wherein by removing at least a portion of the substrate, most or all of the first portion of the substrate is removed.

21. A method for manufacturing an integrated circuit, wherein the method is A composite substrate is prepared having an upper substrate layer containing single-crystal silicon carbide and a lower substrate layer containing a sacrificial material capable of forming structural support for integrated circuit device formation. Forming a single-crystal transition layer on the upper substrate layer, The process involves epitaxially growing an active layer on the aforementioned single-crystal transition layer, The active elements are formed in and on the active layer, The handle is joined to the upper surface of the active element, The method comprising removing the lower substrate layer.

22. The method according to claim 21, wherein the single-crystal transition layer comprises n-type or p-type SiC.

23. The single crystal transition layer is n-type Ga ２ O ３ The method according to claim 21, including the method described in claim 21.

24. The method according to claim 21, wherein the handle comprises polycrystalline SiC, sintered ceramic, alumina, high-melting-point metal, BN, graphite, or a diamond-like material.

25. The method according to claim 21, wherein the upper substrate layer is formed by layer transfer from a bulk crystal starting material to the lower substrate layer.

26. The method according to claim 25, wherein the outermost surface of the layer-transferred upper substrate layer is configured for the subsequent epitaxial formation of the single-crystal transition layer.

27. The method according to claim 21, wherein the lower substrate layer is removed chemically or mechanically in order to expose the back surface of the upper substrate layer.

28. The method according to claim 27, wherein the back surface of the upper substrate layer is configured for the subsequent formation of an ohmic contact region on the back surface.

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