semiconductor devices

Abstract

A multilayer semiconductor diode device may comprise a substrate containing silicon carbide (SiC) and an epitaxial drift layer containing a first semiconductor oxide material above the silicon carbide (SiC) substrate in the direction of growth. The multilayer semiconductor diode device may further comprise a polar nitride layer containing a polar semiconductor nitride material above the epitaxial drift layer in the direction of growth and a metal layer above the polar nitride layer in the direction of growth.

Description

[Technical Field]

[0001] Related applications This application is a continuation-in-part application of U.S. Application No. 18 / 628,178, filed on April 5, 2024, titled “SEMICONDUCTOR DEVICE,” which is a continuation-in-part application of U.S. Application No. 18 / 394,688, filed on December 22, 2023, which claims the interests of U.S. Provisional Patent Application No. 63 / 584,661, filed on September 22, 2023, titled “SEMICONDUCTOR DEVICE,” and was issued on August 27, 2024, as U.S. Patent No. 12,074,195, also titled “SEMICONDUCTOR DEVICE,” all of which are incorporated herein by reference for any purpose. [Background technology]

[0002] High-power semiconductor devices operating at high voltages (e.g., over 1.3kV) have been fabricated using various types of semiconductor materials. For example, Schottky diodes using silicon carbide (SiC) material have replaced silicon (Si) in high-power applications such as power conversion and automotive electronics. Recently, beta-phase gallium oxide (β-Ga2O3) has become available as a standalone technology and is being used to form high-power Schottky diodes (potentially with improved performance and lower cost) as an equivalent SiC alternative. SiC is a wide-bandgap (WBG) semiconductor compared to Si. By leveraging the fundamental advantages gained by WBG, it can be engineered to improve high-power performance. Similarly, semiconductors can potentially outperform SiC and further improve device performance as the bandgap increases. Various polytopes of gallium oxide (Ga2O3) semiconductors have bandgap ranges of 4.5eV to 5.0eV (E) compared to the bandgap of SiC (approximately 3.2eV) and Si (approximately 1.1eV). gThis increased band gap can be advantageously used to improve the on-state resistance of the diode (i.e., reduce losses) and increase the blocking voltage capability (i.e., improve isolation). [Overview of the project] [Problems that the invention aims to solve]

[0003] Despite intensive development of high-voltage β-Ga2O3 diodes and transistors, fundamental limitations still exist for widespread acceptance in high-power applications. [Means for solving the problem]

[0004] In some embodiments, the technology described herein relates to a multilayer semiconductor diode device, which comprises a substrate containing silicon carbide (SiC), an epitaxial transition layer containing a first semiconductor oxide material or SiC, located on the substrate, an epitaxial transition layer containing a second semiconductor oxide material, located on the epitaxial transition layer, and a metal layer located above the epitaxial drift layer, wherein the metal layer and the epitaxial drift layer form a Schottky barrier junction.

[0005] In some embodiments, a method for forming a multilayer semiconductor diode device includes providing a substrate containing silicon carbide (SiC), forming an epitaxial transition layer containing a first semiconductor oxide material or SiC on the substrate, forming an epitaxial drift layer containing a second semiconductor oxide material on the epitaxial transition layer, and forming a metal layer above the epitaxial drift layer, wherein the metal layer and the epitaxial drift layer form a Schottky barrier junction.

[0006] In some embodiments, the technology described herein relates to a multilayer semiconductor diode device comprising a substrate containing silicon carbide (SiC), an epitaxial drift layer containing a first semiconductor oxide material located on the substrate, an epitaxial channel layer containing a second semiconductor oxide material located on the epitaxial drift layer, a Schottky metal layer located above the epitaxial channel layer, the Schottky metal layer and the epitaxial channel layer forming a Schottky barrier junction, the epitaxial channel layer and the Schottky metal layer being formed within a first mesa-type structure, and a sidewall layer containing a dielectric material located on the epitaxial drift layer and in contact with the wall portion of the first mesa-type structure.

[0007] In some embodiments, the techniques described herein relate to a method for forming a multilayer semiconductor diode device, the method comprising: providing a substrate containing silicon carbide (SiC); forming an epitaxial drift layer on the substrate containing a first semiconductor oxide material; forming an epitaxial channel layer on the epitaxial drift layer containing the first semiconductor oxide material; forming a metal layer on the epitaxial drift layer, wherein the metal layer and the epitaxial drift layer form a Schottky barrier junction; etching the epitaxial channel layer and the metal layer to form a mesa-type structure; and forming a sidewall layer containing a dielectric material, wherein the sidewall layer is on the epitaxial drift layer and in contact with the wall portion of the mesa-type structure.

[0008] In some embodiments, the technology described herein relates to a multilayer semiconductor diode device comprising a substrate containing silicon carbide (SiC), an epitaxial drift layer containing a first semiconductor oxide material and located above the substrate with respect to the growth direction, a polar nitride layer containing a polar semiconductor nitride material and located above the epitaxial drift layer with respect to the growth direction, and a metal layer located above the polar nitride layer with respect to the growth direction.

[0009] In some embodiments, the techniques described herein relate to a method for forming a multilayer semiconductor diode device, the method comprising providing a substrate containing silicon carbide (SiC), forming an epitaxial drift layer on the substrate containing a first semiconductor oxide material, forming an epitaxial polar nitride layer on the epitaxial drift layer containing a polar semiconductor nitride material, and forming a metal layer on the epitaxial polar nitride layer, wherein the metal layer and the epitaxial polar nitride layer form a Schottky barrier junction.

[0010] In some embodiments, the technology described herein relates to a multilayer semiconductor diode device comprising a substrate containing silicon carbide (SiC), an epitaxial drift layer containing a first semiconductor oxide material, the epitaxial drift layer being above the substrate with respect to the growth direction and doped in the n-type, a template layer containing a nitride template material and in contact with the epitaxial drift layer, a polar nitride layer containing a polar semiconductor nitride material, the polar nitride layer being in contact with the template layer, the polarization axis of the polar semiconductor nitride material being aligned with the growth direction such that the polar nitride layer contains p-type charges, and the polar nitride layer and the epitaxial drift layer forming a p / n junction, and a metal layer above the polar nitride layer.

[0011] Embodiments of this disclosure will be described with reference to the accompanying drawings. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic cross-sectional view of a vertical multilayer semiconductor diode device according to an exemplary embodiment. [Figure 2A] This is a simplified band diagram of a vertical multilayer semiconductor diode device according to several embodiments. [Figure 2B] This is a plot of the trend of the critical electric field that can be supported with respect to the semiconductor bandgap energy. [Figure 2C] This is a plot of specific on-resistance versus breakdown voltage for silicon, silicon carbide, and gallium oxide semiconductors. [Figure 3] A and B are schematic diagrams of the substrate and drift layer of a vertical multilayer semiconductor diode device, as shown in Figure 1, according to several embodiments, and corresponding plots of exemplary variations in doping concentration (i.e., doping density) as a function of vertical height. [Figure 4] This is a schematic cross-sectional view of a vertical multilayer semiconductor diode device according to another exemplary embodiment. [Figure 5] Figure 4 shows schematic diagrams of the substrate, transition layer, and drift layer of a vertical multilayer semiconductor diode device, as shown in several embodiments, and a corresponding plot of exemplary variations in doping concentration as a function of vertical height. [Figure 6] Figure 4 shows schematic diagrams of the substrate, transition layer, and drift layer of a vertical multilayer semiconductor diode device, as shown in several embodiments, and a related plot of another exemplary variation in doping concentration as a function of vertical height. [Figure 7] Figure 4 shows schematic diagrams of the substrate, transition layer, and drift layer of a vertical multilayer semiconductor diode device as shown in several embodiments, along with related plots of another exemplary variation in doping concentration as a function of vertical height, and further, related plots of an exemplary variation in composition as a function of vertical height. [Figure 8A]This is a schematic cross-sectional view of a vertical multilayer semiconductor diode device according to another exemplary embodiment. [Figure 8B] This is a schematic cross-sectional view of a vertical multilayer semiconductor diode device according to another exemplary embodiment. [Figure 8C] The table shows combinations of n-type and p-type layers having ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 8D] The table shows combinations of n-type and p-type layers having ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 8E] The table shows combinations of n-type and p-type layers having ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 8F] The table shows combinations of n-type and p-type layers having ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 9A] This is an exemplary process flow for designing a vertical multilayer semiconductor diode device according to several embodiments. [Figure 9B] This shows the spatial variation of the conduction and valence band edge energy diagrams of a vertical multilayer semiconductor device oriented along the growth direction, according to an exemplary embodiment. [Figure 9C] This is a spatial variation of the conduction band edge energy diagram of a vertical multilayer semiconductor device oriented along the growth direction, according to an exemplary embodiment. [Figure 10] This is a plot of the breakdown voltage of β-Ga2O3 versus the variation in drift region donor doping concentration for several film thicknesses according to several embodiments. [Figure 11A]This is a plot of the metallic work function energy of a selected metal and the corresponding Schottky barrier energy for the (-201) oriented plane of β-Ga2O3, according to several embodiments. [Figure 11B] This is a semi-logarithmic-linear forward bias current-voltage of a Schottky barrier diode according to several embodiments. [Figure 11C] This is a linear-linear forward bias current-voltage of a Schottky barrier diode according to several embodiments. [Figure 12] This is a plot of the spatial variation of the conduction band energy of the Schottky barrier formed between nickel and the (-201) oriented plane of β-Ga2O3, as a function of the drift donor carrier concentration, according to several embodiments. [Figure 13] This is a plot of the spatial variation of the conduction band energy of the Schottky barrier formed between nickel, the MgO intermediate layer, and the (-201) oriented plane of β-Ga2O3, as a function of the drift donor carrier concentration, according to several embodiments. [Figure 14] This is a schematic cross-sectional view of a vertical multilayer semiconductor structure that forms a Schottky barrier diode containing alpha-phase Ga2O3 and alpha-phase (AlxGa1-x)2O3 epitaxially formed on SiC substrates of A-plane, R-plane, and M-plane according to several embodiments. [Figure 15] This is a schematic cross-sectional view of a vertical multilayer semiconductor structure that forms a Schottky barrier diode containing beta-phase Ga2O3 and beta-phase (AlxGa1-x)2O3 epitaxially formed on a C-plane SiC substrate, according to several embodiments. [Figure 16] This is a plot of the spatial variation of the conduction band energy of a Schottky barrier formed between nickel, a 5 nm thick MgO intermediate layer, and a (-201) oriented plane of β-Ga2O3, as a function of drift donor carrier concentration, according to several embodiments. [Figure 17]This is a plot of the spatial variation of the conduction band energy of the Schottky barrier formed between nickel, a 15 nm thick MgO intermediate layer, and a (-201) oriented plane of β-Ga2O3, as a function of the drift donor carrier concentration, according to several embodiments. [Figure 18] This is a schematic current-voltage plot of a vertical multilayer semiconductor Schottky barrier diode, illustrating the characteristics associated with reverse and forward bias operation in several embodiments. [Figure 19A] This is a plot of the quantum mechanical tunneling probability (coefficient) of electron transport in the conduction band, calculated as a function of incident electron energy for a Schottky barrier with a [Ni / β-Ga2O3] multilayer structure, according to several embodiments. [Figure 19B] This is a plot of the quantum mechanical tunneling probability (coefficient) of electron transport in the conduction band, calculated as a function of incident electron energy for a Schottky barrier with a [Ni / MgO / β-Ga2O3] multilayer structure, according to several embodiments. [Figure 19C] This is a plot of spatial variations at the conduction and valence band edges along the growth direction of a multilayer diode structure containing [Ni / ZnGa2O4 intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate] in several embodiments. [Figure 19D] This is a plot of spatial variations at the conduction and valence band edges along the growth direction of a multilayer diode structure containing [Ni / ZnGa2O4 intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate], shown near the depletion region formed by the Schottky barrier, according to several embodiments. [Figure 19E] This is an IV plot of a simulation of a multilayer semiconductor Schottky barrier diode under forward bias conditions, according to several embodiments. [Figure 19F] This is an IV plot of a simulation of a multilayer semiconductor Schottky barrier diode under forward bias conditions, according to several embodiments. [Figure 20]The following schematic diagrams illustrate distinct functional regions of a vertical multilayer semiconductor device, including a Schottky metal, an intermediate region, a drift region, a transition region, a substrate, and a rear contact (not shown), according to several embodiments, where the intermediate region and the transition region are formed as multiple semiconductor layers. [Figure 21A] The plots show the spatial variations at the conduction and valence band edges along the growth direction of multilayer diode structures including [Ni / superlattice intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate] in several embodiments, where the finite-period superlattice intermediate layer includes, for example, a two-layer pair of [ZnGa2O4 / Ga2O3]. [Figure 21B] The plots show the spatial variations at the conduction and valence band edges along the growth direction of multilayer diode structures including [Ni / superlattice intermediate layer / β-Ga2O3 drift layer / 4H-SiC substrate] in several embodiments, where the finite-period superlattice intermediate layer includes, for example, a two-layer pair of [ZnGa2O4 / Ga2O3]. [Figure 21C] Schematic space band energy diagrams of metal-oxide-metal (MOM) heterostructures in several embodiments are shown, illustrating the band bending due to high field effects for biased MOM structures. [Figure 22] This is a plot of spatial variations at the conduction and valence band edges along the growth direction of a multilayer diode structure, including an exemplary [Ni / β-Ga2O3 drift layer / 4H-SiC substrate], as a function of the applied reverse bias, including a barrier degrading effect resulting from the surface electric field being generated across the Schottky barrier potential in several embodiments. [Figure 23] The plots show the spatial variation at the conduction band edge along the growth direction of a multilayer diode structure, including an exemplary [Ni / β-Ga2O3 drift layer / 4H-SiC substrate], as a function of the applied reverse bias, including a barrier reduction effect resulting from the surface electric field being generated across the Schottky barrier potential, where the surface electric field varies from 0 MV / cm to 1 MV / cm, showing variations in the height and width of the Schottky barrier. [Figure 24]The plots of the calculated effective barrier width and potential energy height of a Schottky heterojunction as a function of the applied reverse bias and therefore the surface electric field are shown for several embodiments. [Figure 25] The quantum mechanical tunneling coefficients calculated as a function of the surface electric field for the incident electron energy across the Schottky barrier formed by the [Ni / β-Ga2O3 / 4H-SiC] structure are shown for several embodiments. [Figure 26] The quantum mechanical tunneling coefficients calculated as a function of the surface electric field for the incident electron energy across the Schottky barrier formed by the [Ni / 5nm MgO / β-Ga2O3 / 4H-SiC] structure are shown for several embodiments. [Figure 27] In several embodiments, the calculated component contributions of thermionic emission current and quantum mechanical tunneling current to the applied surface electric field are plotted as a function of several substrate temperatures, and the device structure includes a vertical multilayer semiconductor structure [Ni / β-Ga2O3 / 4H-SiC]. [Figure 28] In several embodiments, the calculated component contributions of thermionic emission current and quantum mechanical tunneling current to the applied surface electric field are plotted as a function of several substrate temperatures, and the device structure includes a vertical multilayer semiconductor structure [Ni / 5nm MgO / β-Ga2O3 / 4H-SiC]. [Figure 29A] Plots of static and optical (high-frequency) dielectric constants calculated for the selection of semiconductor and oxide materials in several embodiments are shown, and the trend of dielectric constant versus material bandgap energy is disclosed. [Figure 29B] Figure 29A shows plots of field-induced conduction band edge barrier drop energy versus material bandgap energy using the optical dielectric constant calculated in several embodiments, with three exemplary field intensities plotted for a 5 μm slab. [Figure 29C] The empirical trends of interface state parameters and minimum surface density of states, which vary as a function of material bandgap energy, are plotted for several embodiments. [Figure 30] The top figure shows a plot of spatial variation of conduction band edges along the growth direction of a superlattice delta-doped drift region using an exemplary Ga2O3 host layer bonded to a Ni Schottky barrier and deposited on a SiC substrate, according to several embodiments, while the bottom figure shows a periodic doping layer interspersed with intentionally undoped regions. [Figure 31] The plots of the effective donor doping concentration of the delta-doped superlattice drift region against the thickness ratio γ in several embodiments are shown. [Figure 32] A and B are plots of the forward bias IV curves for two configurations of a vertical multilayer Schottky barrier diode containing a delta-doped SL Ga2O3 drift region, according to several embodiments. [Figure 33] A and B plot the spatial variation of the conduction band edge along the growth direction of a double barrier intermediate region containing [ZnGa2O4 / Ga2O3 / ZnGa2O4] formed between the Ni metal and the Ga2O3 drift region according to several embodiments, and show the quantized electronic energy states for zero and high surface electric fields applied to this structure. [Figure 34] The calculated electrostatic potential and field lines are plotted for exemplary [metal / Ga2O3 / SiC] vertical structures with outermost Ni contacts surrounded by a separator layer dielectric material, according to several embodiments. [Figure 35A] The image shows a top view of an example of a diode formed on a Ga2O3 / SiC multilayer structure using a circular Schottky barrier metal and a circular field plate metal contact, according to several embodiments. [Figure 35B] The cross-sectional view shows an example of a diode formed on a Ga2O3 / SiC multilayer structure using a circular Schottky barrier metal and a circular field plate metal contact, according to several embodiments, where the top field plate contact is separated from the surface of the Ga2O3 drift layer using a separation layer. [Figure 36]The calculated electrostatic potential and field lines are plotted for exemplary [metal / Ga2O3 / SiC] vertical structures with an outermost Ni contact surrounded by a separator layer dielectric material and a further field plate located on the separator layer, and electrically in contact with a Schottky barrier contact, according to several embodiments. [Figure 37A] A schematic top view of multiple close-packed circular Schottky barrier metal contacts separated by a fixed radius, according to several embodiments, is shown. [Figure 37B] Figure 37A is a cross-sectional view of the structure showing the relationship between the Schottky barrier metal, the field plate contact, the separation layer, the drift layer, the substrate, and the rear ohmic contact according to several embodiments. [Figure 38] Figures A, B, and C schematically illustrate the process flow for forming a top Schottky metal mesa-type region on an epitaxial drift layer formed on a substrate, according to several embodiments. [Figure 39A] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39B] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39C] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39D] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39E] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39F] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 39G] A schematic diagram of the manufacturing process flow for a vertical conduction multilayer semiconductor diode structure according to an exemplary embodiment is shown. [Figure 40]This is a two-dimensional thermal model of a vertical multilayer semiconductor diode used to solve conduction-dominant heat transfer due to convection and radiation occurring at the boundary, according to several embodiments. [Figure 41] This is a plot of the temperature-dependent thermal conductivity of single-crystal SiC and Ga2O3 materials according to several embodiments. [Figure 42] This is a steady-state thermal distribution contour map of a 2D diode model composed of a Ga2O3 drift layer and a Ga2O3 substrate with electrical conductivity and low thermal conductance. The steady-state current induces ohmic heating within region F8, and the metal contacts are connected to a thermal reservoir. [Figure 43] The steady-state thermal distribution contour plots of several embodiments of a 2D diode model composed of a Ga2O3 drift layer and an electrically conductive and high thermal conductance SiC substrate are shown, where the steady-state current induces ohmic heating within region F8, and the metal contacts are connected to a thermal reservoir. [Figure 44] The following are plots of transient heat transfer and dissipation rates in multilayer semiconductor diodes with respect to forward bias current pulses in several embodiments, comparing Ga2O3 and SiC substrate configurations. [Figure 45] This is a two-dimensional thermal model of a vertical multilayer semiconductor diode, configured as a mesa-type drift region and used to resolve conduction-dominant heat transfer due to convection and radiation occurring at the boundary, according to several embodiments. [Figure 46] These are steady-state thermal distribution contour plots of a 2D diode model composed of a mesa-type Ga2O3 drift layer and a Ga2O3 substrate with electrical conductivity and low thermal conductance, according to several embodiments. The steady-state current induces ohmic heating within region F8, and the metal contacts are connected to a thermal reservoir. [Figure 47] The steady-state thermal distribution contour plots of several embodiments of a 2D diode model composed of a mesa-type Ga2O3 drift layer and an electrically conductive and high-thermal-conductance SiC substrate are shown, where the steady-state current induces ohmic heating within region F8, and the metal contacts are connected to a thermal reservoir. [Figure 48] The absolute energy alignment of the conduction band and valence band with respect to vacuum energy is plotted for the surface orientation dependence of β-Ga2O3 and the C-plane surface of Si-polar and C-polar 4H-SiC according to several embodiments. [Figure 49] The following are plots of spatial conduction band energy diagrams near the β-Ga2O3 / Si polar 4H-SiC heterojunction in several embodiments, where the lowest energy quantum confinement electron wavefunction lies below the Fermi energy level. [Figure 50] The cross-sections of the atomic crystal structure of a 4H-SiC polytope along the

[0001] direction according to several embodiments are shown. [Figure 51] The atomic crystal structure configurations of 4H-SiC polytopes shown on C-plane hexagonal surfaces according to several embodiments are shown. [Figure 52] Cross-sectional views of the monoclinic β-Ga2O3 crystal structure along the [-201] direction are shown according to several embodiments. [Figure 53] The oxygen sublattice arrangement on the (-201)β-Ga2O3 surface according to several embodiments is shown. [Figure 54] Several embodiments show a Si or C hexagonal sublattice on a 4H-SiC(0001) surface. [Figure 55] Several embodiments show the oxygen hexagonal sublattice on the surface of (-201)β-Ga2O3. [Figure 56] The surface orientation and polarity of two slabs containing (-201) oriented β-Ga2O3 and 4H-SiC as Si-polar or C-polar are shown according to several embodiments. [Figure 57A] The atomic arrangements of bulk 4H-SiC crystals having a Si polar surface and a SiC surface, which are preferentially terminated with Si atoms comprising a first oxygen adsorption atomic layer, are shown according to several embodiments. [Figure 57B] The atomic arrangements of bulk 4H-SiC crystals having a C polar surface and a SiC surface, preferentially terminated with Si atoms comprising a first oxygen adsorption atomic layer, are shown according to several embodiments. [Figure 57C]The atomic arrangements of bulk 4H-SiC crystals having a Si polar surface and a SiC surface, preferentially terminated with C atoms, comprising a first oxygen adsorption atomic layer and a second Ga adsorption layer, are shown according to several embodiments. [Figure 57D] The atomic arrangements of bulk 4H-SiC crystals having a C polar surface and a SiC surface, preferentially terminated with C atoms, comprising a first oxygen adsorption atomic layer and a second Ga adsorption layer, are shown according to several embodiments. [Figure 57E] Several embodiments demonstrate possible atomic arrangements on a deliberately miscut 4H-SiC(0001) surface as a template for further Ga2O3 film growth, and the subsequent formation of epitaxial Ga-O bonds. [Figure 57F] The images show a cross-section of a miscut 4H-SiC(0001) crystal that creates a film-forming surface tilted with respect to the 4H-SiC crystal axis, using multiple steps according to several embodiments, and creating a ledge on the SiC surface. [Figure 57G] The following are exemplary process flows for heterogeneous deposition of oxide semiconductors in pre-selected surface orientations on a SiC substrate, according to several embodiments, illustrating process steps for manipulating the substrate and / or oxide semiconductor surface species and states in the preparation of oxide epitaxy and / or metal deposition sequences of a device structure. [Figure 57H] This is an exemplary process flow for heterogeneous deposition of oxide semiconductors using growth interruption methods to improve film quality, according to several embodiments. [Figure 58] The images show a complete series of reflectance high-energy electron diffraction (RHEED) images due to azimuth rotation around the rotation axis of epitaxial growth in several embodiments. The long, sharp RHEED streaks indicate atomically flat and highly crystalline 2 μm Si-doped β-Ga2O3(-201) oriented films deposited on a 0-degree miscut n+4H-SiC(0001) substrate. [Figure 59]These are a series of RHEED images resulting from azimuth rotation around the rotation axis of epitaxial growth. The long, sharp RHEED streaks indicate the atomically flat and highly crystallinity of a 2 μm Si-doped β-Ga2O3(-201) oriented film deposited on a 4-degree miscut n+4H-SiC(0001) substrate, as in several embodiments, and the RHEED dots represent electron beam transmission through the step edge. [Figure 60] Figures A and B show the in-situ laser reflectances used for epitaxial deposition of β-Ga2O3(-201) aligned films on n+4H-SiC(0001) substrates in several embodiments. The periodic thickness oscillations shown in the experimental data for B are a result of the constant growth rate of the Ga2O3 initially deposited on the bare n+SiC substrate. [Figure 61A] This is a plot of the X-ray diffraction symmetric double crystal rocking curve of a single crystal β-Ga2O3(-201) oriented film on an n+4H-SiC(0001)_0deg miscut, where the sharp β-Ga2O3 peak indicates beta-phase pure growth conditions. [Figure 61B] These are contour plots of the reciprocal space map of a β-Ga2O3(-201) oriented film on an n+4H-SiC(0001)_0deg miscut according to several embodiments, showing the reciprocal space map (RSM) of the asymmetric Bragg SiC(107) peak. [Figure 61C] Contour plots of the reciprocal space map of β-Ga2O3(-201) oriented films on n+4H-SiC(0001)_0deg miscuts according to several embodiments, showing the RSM of the asymmetric Bragg β-Ga2O3(-403) peak. [Figure 62] This is a top view of the atomic arrangement of a Ga2O3 crystal showing the (0001) plane and a hexagonal oxygen sublattice according to several embodiments. [Figure 63] This is a top view of the atomic arrangement of a wurtzite-type phase Ga2O3 crystal exhibiting a (0001) plane and a hexagonal oxygen sublattice according to several embodiments. [Figure 64]These are schematic diagrams of the bulk and surface regions of an oxide epitaxial layer according to several embodiments, in which hydrogen-like (hydrogenic) impurities are arranged within the structure. [Figure 65] This is a plot of the spatial energy band diagrams of Ga2O3 multilayer structures showing the surface depletion effect and the accumulation effect at its surface, according to several embodiments. [Figure 66] Figures A and B are plots of calculated forward bias IV curves for Schottky barrier diodes containing Ni / β-Ga2O3 / 4H-SiC, showing three cases of surface modification of β-Ga2O3 semiconductors according to several embodiments, and their effect on the diode's turn-on voltage. [Figure 67] This is a plot of forward bias IV curves calculated for a series of Schottky barrier diodes, including [high work function metal / β-Ga2O3 / 4H-SiC], showing the effect of two cases of surface modification (clean and depletion type) of β-Ga2O3 semiconductors according to several embodiments, and their impact on the diode's turn-on voltage. [Figure 68A] This is an exemplary process flow sequence, according to several embodiments, in which an oxide semiconductor region is fabricated, followed by surface modification, and then favorably capped with a high work function metal. [Figure 68B] This is an exemplary process flow sequence for manufacturing, according to several embodiments, for further processing steps following the in-situ deposition of a first metal layer onto a modified surface of an epitaxial oxide layer. [Figure 69] Possible atomic arrangements near metal oxide heterojunctions according to several embodiments are shown, and the surface portion of a single-crystal β-Ga2O3 region having epitaxial coordination in the epitaxial metal region is shown together with the interfacial oxygen-terminated layer. [Figure 70A] Several embodiments of a multilayer epitaxial structure, comprising a SiC substrate, an epitaxial semiconducting oxide layer, and an epitaxial metal layer, are schematically shown. [Figure 70B]The RHEED images of highly symmetrical surface diffractograms of the structure shown in Figure 70A are shown for several embodiments. [Figure 70C] The RHEED images of highly symmetrical surface diffractograms of the structure shown in Figure 70A are shown for several embodiments. [Figure 70D] The RHEED images of highly symmetrical surface diffractograms of the structure shown in Figure 70A are shown for several embodiments. [Figure 70E] The RHEED images of highly symmetrical surface diffractograms of the structure shown in Figure 70A are shown for several embodiments. [Figure 70F] Figure 70A shows wide-angle X-ray diffraction plots of the completed multilayer structures according to several embodiments. [Figure 70G] High-resolution X-ray diffraction plots of the completed multilayer structure in Figure 70A are shown according to several embodiments. [Figure 71A] The bandgap energy variations with respect to composition of binary and ternary compositions in the form of (Ga2O3)x(ZnO)1-x and (Al2O3)x(ZnO)1-x, suitable for integration with the vertical multilayer semiconductor devices disclosed herein, are plotted according to several embodiments. [Figure 71B] The bandgap energy variations with respect to composition of binary and ternary compositions in the form of (Ga2O3)x(MgO)1-x and (Al2O3)x(MgO)1-x, suitable for integration with the vertical multilayer semiconductor devices disclosed herein, are plotted according to several embodiments. [Figure 72] The bandgap energy variations with respect to composition of ternary and quaternary compositions in the form of (ZnxMgO1-x)Ga2O4 and (ZnxMgO1-x)Al2O4, suitable for integration with the vertical multilayer semiconductor devices disclosed herein, are plotted according to several embodiments. [Figure 73]The bandgap energy variations with respect to composition of ternary and quaternary compositions in the form of (AlxGaO1-x)2ZnO4 and (AlxGaO1-x)2MgO4, suitable for integration with the vertical multilayer semiconductor devices disclosed herein, are plotted according to several embodiments. [Figure 74] This is a spatial energy band diagram of a [metal / n+Ga2O3 / 4H-SiC / metal] multilayer structure, showing the effect of donor doping concentration in the 4H-SiC region according to several embodiments. [Figure 75] This is a spatial energy band diagram of a [metal / n+Ga2O3 / 4H-SiC / metal] multilayer structure, showing the effect of donor doping concentration in the 4H-SiC region according to several embodiments. [Figure 76] This is a cross-sectional view of a portion of a device, including an epitaxial oxide region, a Schottky metal contact, and a dielectric isolation region, according to several embodiments. [Figure 77] This is a plot of the spatial energy band diagram of a heterojunction formed between an oxide semiconductor drift region and a heterogeneous oxide film or material region forming a separation region, according to several embodiments. [Figure 78A] This is a table of calculated dielectric constants for a series of exemplary oxide and fluoride materials compatible with the vertical multilayer device structures disclosed herein, according to several embodiments. [Figure 78B] This is a model of electrostatic interaction between equal but oppositely charged charges located separately in two different dielectric materials, according to several embodiments. It shows symmetric equipotential lines distributed between +Q and -Q charges in the case of equal dielectric material slabs. [Figure 78C] This is a model of electrostatic interaction between equal but oppositely charged charges located separately in two different dielectric materials, according to several embodiments. It shows asymmetric equipotential lines distributed between +Q and -Q charges in the case of slabs made of different dielectric materials. [Figure 78D]This is a model of electrostatic interaction between equal but oppositely charged charges located separately in two materials, according to several embodiments. It shows a symmetrical distribution of the electric field magnitude as a line distributed between the +Q and -Q charges in the case of equal dielectric constant material slabs. The concept of dielectric screening is demonstrated to this disclosure using UWBG materials with different dielectric constants. [Figure 78E] This is a model of electrostatic interaction between equal but oppositely charged charges located separately in two materials, according to several embodiments. It shows the asymmetric distribution of the electric field magnitude as a line distributed between +Q and -Q charges in the case of slabs of materials with different dielectric constants. The concept of dielectric screening is demonstrated to this disclosure using UWBG materials with different dielectric constants. [Figure 78F] Figure 78D shows plots of the parallel EY and perpendicular EX electric field components near the heterointerface of the electrostatic model structure in several embodiments. [Figure 78G] Figure 78E shows plots of the parallel EY and perpendicular EX electric field components near the heterointerface of the electrostatic model structure in several embodiments. [Figure 79] This is a two-dimensional electrostatic model of an exemplary multilayer semiconductor diode structure, including a lower electrode, a substrate, a drift layer, and a field plate electrode embedded within an isolation region dielectric, according to several embodiments. The field plate electrode is drawn asymmetrically around the longitudinal centerline of the structure, simultaneously simulating a structure without a field plate on the left and a structure with a field plate on the right. The isolation layer dielectric is thick, representing a field plate isolated from the drift region. [Figure 80] This is a two-dimensional electrostatic model of an exemplary multilayer semiconductor diode structure, including a lower electrode, a substrate, a drift layer, and a field plate electrode embedded within an isolation region dielectric, according to several embodiments. The field plate electrode is drawn asymmetrically around the longitudinal centerline of the structure, simultaneously simulating a structure without a field plate on the left and a structure with a field plate on the right. The isolation layer dielectric is thin, representing a field plate isolated from the drift region. [Figure 81]The following are electrostatic simulations of split-field plate designs with thin dielectric spacing according to several embodiments, and the resulting spatial variations in electric field strength, comparing the isolation layers in two cases: low-k dielectric (Figure 81) and high-k dielectric (Figure 82). [Figure 82] The following are electrostatic simulations of split-field plate designs with thin dielectric spacing according to several embodiments, and the resulting spatial variations in electric field strength, comparing the isolation layers in two cases: low-k dielectric (Figure 81) and high-k dielectric (Figure 82). [Figure 83] The following are electrostatic simulations of split-field plate designs with thick dielectric spacing according to several embodiments, and the resulting spatial fluctuations of the electric field strength near the interface between the drift region and the isolation region, comparing the isolation layer in two cases: low-k dielectric (Figure 83) and high-k dielectric (Figure 84). [Figure 84] The following are electrostatic simulations of split-field plate designs with thick dielectric spacing according to several embodiments, and the resulting spatial fluctuations of the electric field strength near the interface between the drift region and the isolation region, comparing the isolation layer in two cases: low-k dielectric (Figure 83) and high-k dielectric (Figure 84). [Figure 85] The following are electrostatic simulations of split-field plate designs with thin dielectric spacing according to several embodiments, and the resulting spatial fluctuations of the electric field strength near the interface between the drift region and the isolation region, comparing the isolation layer in two cases: low-k dielectric (Figure 85) and high-k dielectric (Figure 86). [Figure 86] The following are electrostatic simulations of split-field plate designs with thin dielectric spacing according to several embodiments, and the resulting spatial fluctuations of the electric field strength near the interface between the drift region and the isolation region, comparing the isolation layer in two cases: low-k dielectric (Figure 85) and high-k dielectric (Figure 86). [Figure 87]This is a plot of the magnitude of the electric field generated within the structure at the heterointerface between the drift layer and the isolation layer, extending laterally along the x-direction. The device structure has a thin field plate / isolation layer / drift layer spacing according to several embodiments. Figure 87 is for the low-k dielectric case, and Figure 88 is for the high-k dielectric isolation layer. [Figure 88] This is a plot of the magnitude of the electric field generated within the structure at the heterointerface between the drift layer and the isolation layer, extending laterally along the x-direction. The device structure has a thin field plate / isolation layer / drift layer spacing according to several embodiments. Figure 87 is for the low-k dielectric case, and Figure 88 is for the high-k dielectric isolation layer. [Figure 89] These are plots of the spatial variation of potential energy occurring within the structure at the heterointerface, across three horizontal planes, namely slightly above and below the heterointerface between the drift layer and the isolation layer. The device structure is a thin field plate / isolation layer / drift layer spacing, depending on several embodiments. Figure 89 shows the case for a low-k dielectric, and Figure 90 shows the case for a high-k dielectric isolation layer. [Figure 90] These are plots of the spatial variation of potential energy occurring within the structure at the heterointerface, across three horizontal planes, namely slightly above and below the heterointerface between the drift layer and the isolation layer. The device structure is a thin field plate / isolation layer / drift layer spacing, depending on several embodiments. Figure 89 shows the case for a low-k dielectric, and Figure 90 shows the case for a high-k dielectric isolation layer. [Figure 91] This is a simulation plot investigating the effect of the dielectric constant of the isolation layer on the dielectric constant of the drift region, applicable to thin field-plate isolation in several embodiments. The top electrode structure includes a right side (rhs) with a field plate and a left side (lhs) without a field plate. The maximum electric field at the heterointerface between the drift layer and the top electrode (or isolation layer) is calculated for the rhs and lhs portions of the electrode as a function of the dielectric constant of the isolation layer. [Figure 92]The plots in Figure 91, obtained from calculations in several embodiments, show the ratio γ of the maximum electric field with a field plate to that without a field plate. [Figure 93] A two-dimensional electrostatic model is shown, used to simulate the effect of the dielectric constant of the separation layer in the case of a simple top metal mesa-type contact, according to several embodiments. [Figure 94] In some embodiments, the plot of the maximum surface electric field at the heterointerface between the isolation layer (or top metal) and the drift layer surface is shown as a function of the dielectric constant of the isolation layer, illustrating the electric field screening effect of the high-k dielectric isolation layer. [Figure 95] This is a photograph of a fabricated wafer containing multiple vertical device structures showing Ni Schottky barrier metal patterns used in exemplary designs according to several embodiments. The rear contacts are not processed in this stage and exhibit the transparent properties of the material. [Figure 96A] In some embodiments, alternative device designs, referred to herein as "T-channel" designs, are presented. [Figure 96B] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96C] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96D] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96E] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96F] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96G]The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 96H] The following shows a modeled (or calculated) spatial electric field in a device having a structure such as that shown in Figure 96A, according to several embodiments. [Figure 97] The following are exemplary device configurations according to several embodiments, and the device configuration shown in Figure 96A is repeated to form an array of devices on a common SiC substrate. [Figure 98A] Examples of devices having the “T-channel” design described with respect to Figure 96A, with the addition of a transition layer, an intermediate layer, or both, are shown according to several embodiments. [Figure 98B] Examples of devices having the “T-channel” design described with respect to Figure 96A, with the addition of a transition layer, an intermediate layer, or both, are shown according to several embodiments. [Figure 98C] Examples of devices having the “T-channel” design described with respect to Figure 96A, with the addition of a transition layer, an intermediate layer, or both, are shown according to several embodiments. [Figure 99] This is a comparison of the absolute energy scales of conduction and valence electron edge energy alignments for N-polar and Ga-polar GaN surfaces, Ga-polar and O-polar Pna21 Ga2O3 surfaces, monoclinic β-Ga2O3(-201) surfaces, and SI-polar and C-polar 4H-SiC surfaces according to several embodiments. [Figure 100] A to D show possible combinations of polarity-mixed multilayer semiconductor structures containing [GaN / Ga2O3 / 4H-SiC] according to several embodiments. [Figure 101A] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101B] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101C]Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101D] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101E] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 101F] Examples of device structures including a vertical multilayer semiconducting structure comprising an epitaxial oxide layer and an epitaxial nitride layer are shown according to several embodiments. [Figure 102A] A table is shown illustrating combinations of n-type and p-type layers with ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 102B] A table is shown illustrating combinations of n-type and p-type layers with ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 102C] A table is shown illustrating combinations of n-type and p-type layers with ohmic contacts to a SiC substrate and ohmic or Schottky contacts to an epitaxially grown semiconductor layer, according to several embodiments. [Figure 103] This is an exemplary manufacturing process flow for several embodiments, which involves fabricating an epitaxial Ga2O3 layer on a SiC substrate, followed by the fabrication of a GaN template layer and the growth of an optional GaN epitaxial layer. The structure is then processed to form a Schottky metal electrode(s) according to several embodiments. [Figure 104]This is a plot of double-crystal X-ray diffraction showing a symmetric Ω-2θ scan of an epitaxial multilayer structure in which Ga polar wurtzite-type GaN is formed on the final surface of a β-Ga2O3(-201) epitaxial layer formed on a SiC or sapphire C-plane substrate, according to several embodiments. [Figure 105A] The plots of the spatial energy band diagrams for vertical multilayer semiconductor devices containing [Ni / Ga polar GaN / β-Ga2O3(-201)N drift / n+4H-SiC] in several embodiments are shown, where polarization-induced band curvature is attributed to the thickness of the top layer of Ga polar GaN and is simulated for three GaN layer thicknesses. [Figure 105B] The plots of the spatial energy band diagrams for vertical multilayer semiconductor devices containing [Ni / Ga polar GaN / β-Ga2O3(-201)N drift / n+4H-SiC] in several embodiments are shown, where polarization-induced band curvature is attributed to the thickness of the top layer of Ga polar GaN and is simulated for three GaN layer thicknesses. [Figure 105C] This is a plot of spatial valence band energy profiles near the [Ni / Ga polar GaN / β-Ga2O3] region, showing the quantum confinement wavefunction states of the lower eight energy levels of heavy holes generated in GaN at the heterointerface, according to several embodiments. [Figure 105D] This is a plot of a series of simulations of the spatial conduction band energy near the [Ni / Ga polar GaN / β-Ga2O3] region, showing the variation in electron barrier height as a function of GaN layer thickness in several embodiments. [Figure 105E] These are plots of the maximum conduction energy barrier height calculated as a function of the GaN layer thickness for the device structures shown in Figures 55 to 58, according to several embodiments. [Figure 106A] This is a schematic cross-section of a vertical multilayer semiconductor stack. The outermost surface portion of the oxide layer, which indicates surface roughness, is shown. [Figure 106B] This is a schematic cross-section of a vertical multilayer semiconductor stack. It shows the outermost surface portion of the oxide layer, planarized after epitaxial growth to demonstrate a lower surface roughness, according to several embodiments. [Modes for carrying out the invention]

[0013] In the following description, similar reference numerals indicate the same or corresponding parts throughout the drawings.

[0014] This disclosure describes a semiconductor diode device comprising at least one type of epitaxial oxide material deposited on a silicon carbide (SiC) substrate, wherein the epitaxial oxide material forms an epitaxial oxide layer (or drift layer) and a metal layer (e.g., an epitaxial metal layer) on the epitaxial oxide layer. In some embodiments, the materials of the metal layer and the epitaxial oxide layer are selected to form a Schottky junction. The epitaxial oxide material has a wide band gap (e.g., about 2.5 eV to about 10 eV, or about 3 eV to about 10 eV, or about 4.5 eV to about 7 eV).

[0015] In some embodiments, the semiconductor devices described herein include layers in addition to the epitaxial oxide layer (or drift layer) on the SiC substrate. For example, an epitaxial transition layer can be formed between the SiC substrate and the epitaxial oxide layer. In some cases, the transition layer can provide intermediate level doping between the substrate and the epitaxial oxide layer and / or control interfacial strain, thereby affecting the electronic and structural properties of the semiconductor diode device, as further described herein. In another example, an intermediate layer can be formed between the epitaxial oxide layer and a metal layer. The intermediate layer can affect the electronic properties of the semiconductor diode device, such as turn-on voltage and / or reverse breakdown voltage, by altering the Schottky barrier properties, as further described herein. In some cases, the structure can include both a transition layer and an intermediate layer. The intermediate layer and the transition layer can each be a single layer, or they can each include multiple material layers, such as a superlattice layer or a chirp layer.

[0016] Furthermore, in some cases, the semiconductor diode devices described herein may include an isolation layer surrounding the metal layer. The isolation layer may be advantageous in reducing surface current and controlling the electrostatic vector field of the device described herein. The isolation layer may include a material having a higher band gap than the material of the epitaxial oxide layer (or drift layer), and may be crystalline (e.g., an epitaxial material), amorphous, or polycrystalline. The dielectric constant of the isolation layer material may be lower or higher than that of the epitaxial oxide layer (or drift layer). In some cases, the isolation layer is an oxide. In some cases, the isolation layer is an epitaxial layer formed on the epitaxial oxide layer (or drift layer).

[0017] The materials, structures, and methods described herein can be used in two-terminal, three-terminal, or other multi-terminal semiconductor devices, such as Schottky barrier (SB) diodes, p / n junction diodes, PIN diodes, transistors, switches, high-power switches, RF switches, varactors, light-emitting devices, semiconductor devices having quantum wells or superlattices, and semiconductor devices having composition (or doping density) gradients.

[0018] The semiconductor devices described herein (e.g., vertical semiconductor diode devices) enable high dielectric breakdown voltages in the off or blocking state (i.e., high breakdown voltages can be greater than 50V, greater than 100V, or between 50V and 10,000V). Essentially, power P is the product of voltage (V) and current (I). For a given operating power, a decrease in current results in the ability to utilize higher voltages. Generally, since current scales with respect to the cross-sectional area of ​​the device or conductor, higher operating voltages result in lower ohmic heating losses (I). 2 R on Lowering the on-resistance (R) makes it possible to miniaturize the device. on Reducing ) further reduces losses.

[0019] As requirements for high-power semiconductor devices operating above 1.3kV become more stringent, there is a need for improved simultaneous size-weight and power (SWaP) metrics. Compact, high-power-density SWaP power conversion configurations present challenges to conventional technologies. Semiconductor devices containing Ga2O3 have been proposed, but this material has low thermal conductivity, meaning that heat, once generated, must often be dissipated using complex thermodynamic arrangements. On the other hand, all-SiC devices currently available exhibit lower breakdown voltages compared to equivalent devices containing Ga2O3 of the same thickness and doping concentration (or conductivity). The terms “doping concentration” and “doping density” are used interchangeably herein.

[0020] This disclosure provides solutions to the above problems and means for dramatic improvement, including a hybrid approach involving a silicon carbide (SiC) substrate, which, compared to devices with a SiC epitaxial layer on a SiC substrate, provides an increased breakdown voltage V for a given longitudinal thickness and doping concentration (or conductivity). br When combined with layers of a semiconducting device formed from an epitaxially deposited oxide material (e.g., Ga2O3), it exhibits good thermal and electrical conductivity. A further advantage of bonding the oxide semiconducting active region to SiC is the improved flexibility of possible device configurations (i.e., heterojunction engineering). The structures and methods described herein can also enable a reduction in manufacturing costs.

[0021] In some examples of semiconductor diode devices including an epitaxial oxide layer on a silicon carbide (SiC) substrate, the SiC substrate can be made from a crystal polytype of 4H-SiC, 2H-SiC, 6H-SiC, or 3C-SiC. The orientation of the SiC substrate can be C-plane SiC (0001), A-plane SiC (11-20), R-plane SiC (10-12), or M-plane SiC (1-100). Single-crystal SiC has a thermal conductivity of about 300 to 500 W / (m-K), which is significantly higher than other semiconductor substrate materials such as Ga2O3 (about 20 to 30 W / (m-K)) or Si (about 100 to 150 W / (m-K)). The high thermal conductivity of SiC is advantageous for high-power electronic device structures epitaxially formed on SiC substrates, as it improves heat dissipation through the substrate.

[0022] In some examples of semiconductor diode devices on a silicon carbide (SiC) substrate, the epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or isolation layer are made of Ga2O3 (e.g., α-phase or β-phase); (Al x Ga 1-x )2O3 (e.g., α-phase or β-phase) (0≦x≦1); Mg x Ga 2(1-x) O 3-2x (0≦x≦1); Mg x Al 2(1-x) O 3-2x (0≦x≦1); (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (0≦x≦1, 0≦y≦1, and 0≦z≦1); Zn x Ga y O z (0≦x≦1, 0≦y≦1, and 0≦z≦1); Zn x Al y O z (0≦x≦1, 0≦y≦1, and 0≦z≦1); Mg x Ga y O z (0≦x≦1, 0≦y≦1, and 0≦z≦1); Mg x Aly O z (0≦x≦1, 0≦y≦1, and 0≦z≦1); Ni x Ga y O z (0≦x≦1, 0≦y≦1, and 0≦z≦1); Ni x Al y O z (0≦x≦1, 0≦y≦1, and 0≦z≦1); (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (0<x<1 and 0<y<1); or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (0≦x≦1, 0≦y≦1, and 0≦z≦1), or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )₂O₄ (0≦(x,y,z)≦1, or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (0≦(p,x,y,z)≦1) can include one or more of them.

[0023] The oxygen content of the epitaxial oxide materials described herein (e.g., the aforementioned epitaxial oxide materials) can vary in some embodiments. For example, the different crystal symmetries of the aforementioned epitaxial oxide materials can have compositions with varying oxygen content (e.g., having a lower or higher oxygen fraction) compared to the recited compositions. In some cases, the ratio of metal atoms to oxygen atoms may be smaller or larger than that in the compounds described herein due to defects in the material (e.g., oxygen or metal vacancies and / or interstitial atoms).

[0024] The epitaxial oxide materials (e.g., epitaxial oxide layers (or drift layers), transition layers, intermediate layers, and / or separation layers) described in this specification can be doped p-type or n-type. For example, (Al x Ga 1-x )2O3 and other epitaxial oxides can be doped n-type using extrinsic dopants such as Si, Ge, or Sn. In various examples, dopants may be spatially confined (e.g., in one or more doping layers within a given region). In one example, dopants may be confined in two or more spatially separated doping layers within a region (e.g., two spatially separated doping layers within a transition layer), or in other examples, the doping layers may extend across a region or a portion of a region.

[0025] In some embodiments, any of the epitaxial layers of the structures and devices described herein (e.g., epitaxial oxide layers (or drift layers), transition layers, intermediate layers, and / or separation layers) can include the following. (A2O3) x (BO) 1-x ≡A 2x B 1-x O 2x+1 (Material 1) In Material 1, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1. These ranges differ from each other, for example, because some embodiments of Material 1 (represented by the formula above) include binary materials, and other embodiments include binary or ternary materials. Elsewhere in this specification, subscripts in material formulas can include or exclude zero and / or one to distinguish binary, ternary, quaternary, or other materials. The atomic species of Material 1 can be selected from trivalent A={Al, Ga, RE, Bi, B', In} and divalent B={Ni, Mg, Zn}, where O=oxygen, Al=aluminum, Ga=gallium, RE=at least one rare earth (e.g., lanthanide), Bi=bismuth, B'=boron, In=indium, Zn=zinc, Mg=magnesium, and Ni=nickel.

[0026] For example, in the above formula for material 1, if x = 1 / 2, the epitaxial layer of the structure or device described herein may include A2B1O4. Some examples of such materials are Al2Mg1O4, Ga2Mg1O4, Al2Zn1O4, Ga2Zn1O4, Al2Ni1O4, Ga2Ni1O4, and RE2Zn1O4.

[0027] In another example, if x = 1 / 3 in the above formula for material 1, the epitaxial layer of the structure or device described herein may include A2B2O5. Some examples of such materials are Al2Mg2O5, Ga2Mg2O5, Al2Zn2O5, Ga2Zn2O5, Al2Ni2O5, and Ga2Ni2O5.

[0028] In another example, if x = 1 / 4 in the above formula for material 1, the epitaxial layer of the structure or device described herein may include A2B3O6. Some examples of such materials are Al2Mg3O6, Ga2Mg3O6, Al2Zn3O6, Ga2Zn3O6, Al2Ni3O6, and Ga2Ni3O6.

[0029] In another example, if x = 1 / 5 in the above formula for material 1, the epitaxial layer of the structure or device described herein may include A2B4O7. Some examples of such materials are Al2Mg4O7, Ga2Mg4O7, Al2Zn4O7, Ga2Zn4O7, Al2Ni4O7, and Ga2Ni4O7.

[0030] In another example, in the above equation, if x = 3 / 4, the epitaxial layer of the structure or device described herein is A6B1O 10 It can include. Some examples of such materials are Al6Mg1O 10 Ga6Mg1O 10 Al6Zn1O 10 Ga6Zn1O 10 Al6Ni1O 10 Ga6Ni1O 10 , and RE6Zn1O 10is.

[0031] In another example, in the above formula for Material 1, x can be any of the values 0≦x≦1, 0<x≦1, 0≦x<1, and 0<x<1. More dilute compositions are also possible, such as for example in the case of 0≦x≦0.1, or 0.9≦x≦1.0.

[0032] In some embodiments, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein can include the following. ((A y C 1-y )2O3) x (BO) 1-x ≡(A y C 1-y ) 2x B 1-x O 2x+1 (Material 2) For Material 2, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1; and 0≦y≦1, 0<y≦1, 0≦y<1, or 0<y<1. The atomic species of Material 2 can be selected from trivalent A and C selected from two of {Al, Ga, RE, Bi, B', In}, and divalent B={Ni, Mg, Zn}, where O=oxygen.

[0033] For example, in the above formula for Material 2, when x=1 / 2 and y=1 / 10, the epitaxial layer of the structure or device described herein can include (A 0.1 C 0.9 )2B1O4. Some examples of such materials are (Al 0.1 Ga 0.9 )2Mg1O4, (Al 0.1 Ga 0.9 )2Ni1O4, (Bi 0.1 Ga 0.9 )2Mg1O4, (RE 0.1 Ga 0.9 )2Zn1O4, and (RE 0.1 Al 0.9 )2Zn1O4.

[0034] In some embodiments, any of the structures and epitaxial layers (e.g., epitaxial oxide layers (or drift layers), transition layers, intermediate layers, and / or separation layers) of the devices described herein can include the following. ((A y D z C 1-y-z )2O3) x (BO) 1-x ≡(A y D z C 1-y-z ) 2x B 1-x O 2x+1 (Material 3) In Material 3, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1; 0≦y≦1, 0<y≦1, 0≦y<1, or 0<y<1; and 0≦z≦1, 0<z≦1, 0≦z<1, or 0<z<1. The above formula for Material 3 is also constrained such that the sum satisfies y+z≦1. The atomic species of Material 3 can be selected from trivalent A, D and C selected from three of {Al, Ga, RE, Bi, B', In}, and divalent B={Ni, Mg, Zn}, where O=oxygen.

[0035] For example, in the above formula of Material 3, when x=1 / 2, y=18 / 20, and z=1 / 20, the epitaxial layer of the structure or device described herein can include (A 0.9 D 0.05 C 0.05 )2B1O4. Some examples of such materials are (Ga 0.9 Al 0.05 In 0.05 )2Mg1O4, (Ga 0.9 Al 0.05 In 0.05 )2Ni1O4, (B' 0.05 Bi 0.05 Ga 0.9 )2Mg1O4, (RE 0.05 In 0.05 Ga 0.9 )2Zn1O4, and (RE 0.05 Ga 0.9 Al 0.05 )2Zn1O4.

[0036] In some embodiments, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein can include the following. (A2O3) 1-x (B y C 1-y O) x ≡A 2(1-x) B xy C x(1-y) O 3-2x (Material 4) In Material 4, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1; and 0≦y≦1, 0<y≦1, 0≦y<1, or 0<y<1. The atomic species of Material 4 can be selected from trivalent A={Al, Ga, RE, Bi, B', In} and divalent B and C selected from at least two of {Ni, Mg, Zn}, where O=oxygen in the formula.

[0037] For example, in the above formula of Material 4, when x=1 / 2 and y=1 / 4, the epitaxial layer of the structure or device described herein can include A2B 0.25 C 0.75 O4. Some examples of such materials are Ga2Mg 0.25 Zn 0.75 O4, Al2Mg 0.25 Zn 0.75 O4, Ga2Mg 0.25 Ni 0.75 O4, and Ga2Zn 0.25 Mg 0.75 O4.

[0038] In some embodiments, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein can include the following. ((A z D 1-z )2O3) 1-x (B y C 1-y O) x ≡A2z(1-x) D 2(1-z)(1-x) B xy C x(1-y) O 3-2x (Material 5) For Material 5, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1; 0≦y≦1, 0<y≦1, 0≦y<1, or 0<y<1; and 0≦z≦1, 0<z≦1, 0≦z<1, and 0<z<1. The atomic species of Material 5 may be selected from trivalent A or D selected from at least two of {Al, Ga, RE, Bi, B', In}, and divalent B and C selected from at least two of {Ni, Mg, Zn}, wherein O = oxygen in the formula.

[0039] For example, in the above formula of Material 5, when x=1 / 2, y=1 / 2, and z=1 / 2, the epitaxial layer of the structure or device described herein may comprise A1D1B 0.5 C 0.5 O4. Some examples of such materials include Al1Ga1Ni 0.5 Mg 0.5 O4, In1Ga1Zn 0.5 O4, and RE1Al1Zn 0.5 Ni 0.5 O4.

[0040] In some embodiments, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described herein may include the following. (A2O3) x (BO2) 1-x ≡A 2x B 1-x O x+2 (Material 6) In Material 6, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1. The atomic species of Material 6 can be selected from trivalent A={Al, Ga, RE, Bi, B', In} and divalent B={Ge, Si, Sn}, where in the formula, O=oxygen, Al=aluminum, Ga=gallium, RE=at least one rare earth (e.g., lanthanide), Bi=bismuth, B'=boron, Ge=germanium, Si=silicon, and Sn=tin.

[0041] For example, in the above formula of Material 6, when x=1 / 2, the epitaxial layer of the structure or device described in the present specification may include A2B1O5. Some examples of such materials are Al2Si1O5, Ga2Ge1O5, Al2Ge1O5, RE2Sn1O5, B'2Ge1O5, and In2Ge1O5.

[0042] For example, in the above formula of Material 6, when x=3 / 4, the epitaxial layer of the structure or device described in the present specification may include A6B1O 11 . Some examples of such materials are Al6Ge1O 11 , RE6Ge1O 11 , and B'6Si1O 11 .

[0043] In some embodiments, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) of the structures and devices described in the present specification may include the following. (AO) x (BO2) 1-x ≡A x B 1-x O 2-x (Material 7) In Material 7, 0≦x≦1, 0<x≦1, 0≦x<1, or 0<x<1. The atomic species of Material 7 can be selected from trivalent A={Mg, Ni, Zn} and divalent B={Ge, Si, Sn}, where in the formula, O=oxygen, Mg=magnesium, Ni=nickel, Zn=zinc, Ge=germanium, Si=silicon, and Sn=tin.

[0044] For example, in the above formula for Material 7, when x=1 / 2, the epitaxial layer of the structure or device described herein can comprise A1B1O3. Some examples of such materials are Zn1Si1O3, Zn1Ge1O3, Ni1Ge1O3, Mg1Sn1O3, Mg1Zn1O3, and Ni1Sn1O3.

[0045] For example, in the above formula for Material 7, when x=2 / 3, the epitaxial layer of the structure or device described herein can comprise A2B1O4. Some examples of such materials are Zn2Si1O4, Mg2Ge1O4, Ni2Ge1O4, Mg2Sn1O4, Mg2Si1O4, and Ni2Si1O4.

[0046] It should be understood that for any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or isolation layer) of the structures and devices described herein, any compositional fraction (e.g., x, y and / or z) of any of the formulas of the materials described herein (e.g., Materials 1 to 7 described above) may vary within the layer from the exact amount. For example, the compositional fraction may vary due to crystal lattice defects (e.g., vacancies, antisite defects, and / or interstitial species) and random fluctuations within the physical composition. Accordingly, the compositional fractions of the formulas of the materials described herein can, in some cases, be considered the average composition of the layer.

[0047] Furthermore, any of the epitaxial layers (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or isolation layer) of the structures and devices described herein may have a stoichiometric composition of the materials described herein (e.g., Materials 1 to 7 above), for example, Ga2O3, or a non-stoichiometric composition, for example, Ga2O 3-p wherein 0<p<2 represents an oxygen-deficient or gallium-rich composition. Another example of a non-stoichiometric composition is Ga 2-qO3, where 0<q<1 in the formula represents a composition that is oxygen-rich and / or gallium-deficient. Any of the oxide compositions (e.g., Materials 1 to 7) described herein can be stoichiometric or non-stoichiometric in the present structures and devices.

[0048] Furthermore, any of the epitaxial layers of the structures and devices described herein (e.g., epitaxial oxide layer (or drift layer), transition layer, intermediate layer, and / or separation layer) can include a dilute alloy composition of any of the oxide compositions (e.g., Materials 1 to 7) described herein. A dilute alloy composition is one in which the dilute component of the material is present at a concentration of less than 0.1. For example, one of Materials 1 to 7 can include values of x, y, and / or z of less than 0.1, or less than 0.05, or less than 0.01. In some cases, dopant species (e.g., Si, Ge, or Sn) can be incorporated into the materials described herein (e.g., one of Materials 1 to 7 formed in the epitaxial layer) at a composition of less than 0.1, or less than 0.05, or less than 0.01.

[0049] The epitaxial oxide layer can also have crystal symmetry and orientation that enable epitaxial layer formation on a SiC substrate. In some examples, the epitaxial oxide material is selected to have a lattice mismatch with the SiC substrate of less than 10%, or less than 8%, or less than 6%, or less than 5%, or less than 2%. The thickness of the epitaxial oxide layer can be smaller than the critical layer thickness of the material (below this critical layer thickness, the epitaxial oxide layer may be elastically strained and substantially coherent with the substrate, and above this critical layer thickness, the epitaxial oxide layer relaxes or partially relaxes). For example, the thickness of the epitaxial oxide layer can be 1 nm to 100 microns, or 100 nm to 10 microns, or 1 nm to 1 micron, or 5 nm to 500 nm.

[0050] In some examples, the semiconductor diode devices disclosed herein include short-period superlattices (SPSLs). The epitaxial oxide layer may include an SPSL, and / or other layers of the device (e.g., a transition layer, or an intermediate layer) may include an SPSL. In some cases, the SPSL includes sub-layers of alternating wider bandgap material and narrower bandgap material (a barrier layer and a well layer, respectively). The thickness of the barrier or well sub-layer in the SPSL can be less than 1 monolayer (ML) to 5 ML, or less than 1 ML to 10 ML, or less than 1 ML to 20 ML. Barrier and / or well sub-layers having a thickness of less than 1 ML or 1 unit cell along the growth direction may be discontinuous in the lateral direction (i.e., parallel to the main surface of the layer).

[0051] In some examples, the semiconductor diode devices disclosed herein include a chirp layer. The epitaxial oxide layer may include a chirp layer, and / or other layers of the device (e.g., a transition layer, or an intermediate layer) may include a chirp layer. The chirp layer is similar to SPSL in that it also includes sublayers of alternating wider bandgap material and narrower bandgap material (a barrier layer and a well layer, respectively), but the chirp layer has sublayer properties that vary throughout the chirp layer. For example, the chirp layer may have two different compositions to form the barrier layer and the well sublayer (Al x Ga 1-x ) may include alternating sublayers of 2O3 (i.e., two different values ​​of x). The barrier sublayer and / or well sublayer vary in thickness through the chirp layer. In another example, the chirp layer is made of (Al to form the barrier sublayer and well sublayer. x Ga 1-x ) may include alternating sublayers of 2O3, and the barrier sublayer and / or well sublayers change composition through the chirp layer. In another example, the chirp layer is (Al to form the barrier sublayer and well sublayer. x Ga 1-xIt may include alternating sublayers of 2O3, and the barrier sublayers and / or well sublayers vary in thickness and / or composition through the chirp layer.

[0052] In yet another example, a bulk-like gradient band gap has a band gap energy E that varies along the growth direction z. g It may be incorporated into a device having (z). The variation can be linear or nonlinear, monotonic or non-monotonic along the growth direction. For example, (Al x Ga 1-x The gradient layers of 2O3 may be formed such that the alloy composition x is a function of the growth direction z, such as x(z).

[0053] Digital alloys formed using SPSL or bulk-like alloys are possible, and further variations in effective material properties can be given along the growth direction.

[0054] Methods for forming semiconductor diode devices disclosed herein, comprising an epitaxial oxide layer on a silicon carbide (SiC) substrate and a metal layer (such as an epitaxial metal layer) on the epitaxial oxide layer, are also described herein. Such methods may include forming highly crystalline and epitaxial oxide layers on a SiC substrate using epitaxial layer growth techniques, such as molecular beam epitaxy (MBE), gas-source molecular beam epitaxy (GS-MBE), plasma-source MBE (P-MBE), metal-organic vapor deposition (MOCVD), atomic layer deposition (ALD), vacuum laser ablation source, vapor deposition (VPE), gas source, sputtering source, electron beam deposition source, and plasma deposition. Other epitaxial layer growth techniques may also be applicable, ultimately resulting in a highly crystalline oxide film formed on the surface of the substrate.

[0055] In a typical embodiment, an in-situ (out-of-situ) metal layer can be formed (or deposited) on an epitaxial oxide layer. In another embodiment, the in-situ metal layer can be formed directly on the pristine final surface of the epitaxial oxide. Furthermore, the in-situ metal layer can be formed on a deliberately prepared final epitaxial oxide surface. Even further, the metal layer can be formed on a deliberately prepared final epitaxial oxide surface, a process that does not expose the structure or surface to a contaminating environment. Metal layers such as those of elements Ni, Cu, Al, Ti, Pd, Pt, Ir, Er, Gd, Mo, W, Os, and their alloys can be deposited to form a non-epitaxial metal layer using physical vapor deposition techniques, such as MBE, sputtering, pulsed laser deposition, or thermal deposition of metal. Alternatively, or further, an epitaxial metal layer can be formed on the epitaxial oxide layer using an epitaxial layer growth technique (e.g., MBE, MOCVD, or another epitaxial layer growth technique) to form a substantially crystalline first metal layer that is in direct contact with the epitaxial oxide layer to form a metal oxide heterojunction. Further metal or conductive layers may be formed on the final surface of the first metallic crystalline metal layer that forms the metal oxide heterojunction. In some cases, multiple epitaxial and / or non-epitaxial metal layers can be deposited. For example, epitaxial and / or non-epitaxial metal layers can be deposited in different areas of the device to perform different functions. The metal layer can also contain multiple epitaxial and / or non-epitaxial metal layers within the same area of ​​the device, for example, a first layer being a sticking layer and subsequent layers adhering to that sticking layer. In some cases, the metal layer may include a first epitaxial layer that forms a low-defect interface with the semiconductor layer below, and the non-epitaxial metal layer may be deposited on top of the epitaxial metal layer.

[0056] Metal-induced gap states (MIGS) are known in the prior art for metal contacts to semiconductor surfaces. Simply put, MIGS arise from a mismatch of different crystal structures, including metal-oxide semiconductor interfaces, resulting in unfavorable bonding configurations at metal-oxide heterointerfaces. The passivation of the aforementioned interfacial dangling bonds can be used to reduce the impact of MIGS on Schottky barrier reduction.

[0057] In some embodiments, the semiconductor devices disclosed herein involve a direct and bonding arrangement of bonds across a metal-oxide heterointerface, where a substantially epitaxial (i.e., crystalline) first metal layer is formed on an anionic or cationic oxide surface.

[0058] In some cases, a separation layer can be formed between an epitaxial oxide layer and a metal layer (e.g., an epitaxial metal layer) using epitaxial layer growth techniques (e.g., MBE, MOCVD, or another epitaxial layer growth technique). In some cases, a passivation layer can be formed on the device. The passivation layer may be made of, for example, aluminum oxide (Al2O3), magnesium oxide (MgO), or zinc-magnesium-gallium oxide (Zn x Mg 1-x )Ga2O4, Aluminum-gallium oxide (Al x Ga 1-x )2O3, Nickel-zinc-magnesium-gallium-aluminum oxide (Ni x Zn y Mg 1-x-y )(Ga p Al 1-p )O q Magnesium germanium oxide (Mg) x Ge y O z Alternatively, it may contain silicon dioxide (SiO2), where the subscripts x, y, z, p, and q indicate atomic fractions representing various crystalline, polycrystalline, or amorphous forms.

[0059] In some cases, one or more layers (e.g., an epitaxial oxide layer, an epitaxial metal layer or metal layer, a separation layer, and / or a passivation layer) can be patterned to form a device, for example, using photolithography and etching techniques (e.g., using photoresist, plasma etching, and / or metal lift-off processes). Alternatively, damascene metal patterning can be utilized, where the oxide is used as a trench and then chemically and mechanically polished as needed.

[0060] Figure 1 shows a schematic cross-sectional view of a vertical multilayer semiconductor diode device 100 according to an exemplary embodiment.

[0061] In this example, the semiconductor device 100 contains silicon carbide (SiC) and has a width w Sub , and thickness t Sub The substrate 110 includes a substrate having the following characteristics. In one example, the substrate 110 is formed from a 4H-SiC polytope of SiC. In another example, the substrate 110 is formed from 2H-SiC, 6H-SiC, or 3C-SiC.

[0062] In some cases, the substrate 110 is a bulk material, such as single-crystal SiC. In some cases, the substrate 110 may include an optional bulk substrate layer 112 and an optional surface layer 114. A substrate 110 including both a bulk substrate layer 112 and a surface layer 114 is referred to herein as a “composite substrate”. For example, the bulk substrate layer 112 may be polycrystalline SiC, and the surface layer 114 may be a single-crystal layer of SiC. In such a structure, the surface layer 114 may be a thin layer (e.g., 100 nm to 5 microns, or 100 nm to 1 micron) that serves as a template for epitaxial growth, and the bulk substrate layer 112 may be a material having high thermal conductivity and / or selected electrical conductivity (e.g., electrically conductive or insulating). For example, the surface layer 114 may include one or more single-crystal layers of 4H-SiC polytopes of SiC, or it may be 2H-SiC, 6H-SiC, or 3C-SiC. In other examples, the surface layer 114 is made of one or more single-crystal oxide materials (e.g., Ga2O3, Al2O3, or Al2O3). x Ga 1-x )2O3, where 0≦x≦1) may be included in the formula. For example, the surface layer 114 may include any of the oxide materials described herein, for example, any of the compositions of materials 1 to 7.

[0063] Such composite substrates can be formed, for example, by removing layer 114 from a single-crystal substrate (e.g., a single-crystal SiC substrate, or an oxide substrate) and bonding it to a bulk substrate layer 112 (e.g., a polycrystalline SiC, or a bulk layer of another material with high thermal conductivity). In such cases, the single-crystal substrate layer (e.g., SiC, Ga2O3, or Al2O3) can be removed and bonded to the bulk substrate layer 112. In other examples, an epitaxially grown layer (e.g., any of the compositions of materials 1-7, or epitaxially grown SiC) can be removed from the grown substrate and bonded to the bulk substrate layer 112. In some cases, the bulk substrate layer 112 can be formed from a material with high thermal conductivity and optionally high electrical conductivity, such as polycrystalline SiC, a metal (e.g., Ni, Al, or Cu), or a ceramic material (e.g., AlN or BN).

[0064] A method for transferring a single crystal surface layer 114 from a donor substrate to a bulk substrate layer 112 involves forming a weak or defective crystal layer beneath the surface layer 114 (e.g., the surface layer 114 of the donor substrate, or the surface layer 114 which is an epitaxial layer on the donor substrate) (e.g., H + Or He + This may include ion implantation (using Si+ or C ions). The ion-implanted surface can then be bonded to a bulk substrate layer 112. Heat and / or pressure can then be applied to form an optional bonding layer 116, as further described below. Force can then be applied between the donor substrate and the bulk substrate layer 112, so that the structure is separated at the ion-implanted layer (if it is the weakest layer), removing most of the donor wafer but leaving the surface layer 114 bonded to the bulk substrate layer 112. In some cases, the surface of the transferred surface layer 114 can then be smoothed, the composite substrate can be annealed, and / or other processes can be performed to prepare the composite substrate for epitaxial growth.

[0065] In other cases, the bulk substrate layer 112 may be single-crystal SiC, and the surface layer 114 may be a modified, thermally treated, or chemically treated surface region or near-surface region, for example, to reconfigure the surface for epitaxial growth, or to convert it to graphene or oxide on which an epitaxial oxide layer can be grown. The composite substrate may be advantageous because the bulk substrate layer 112 can be fabricated from a less restrictive material than the surface layer 114. To be used as a template for the epitaxial growth of the oxide layer, the surface layer 114 may be a single-crystal material with compatible lattice constants and crystal structure and may have sufficiently high material quality (e.g., may have a low concentration of threading dislocations). Since the bulk substrate layer 112 of the composite substrate does not need to be single-crystal, the surface layer 114 may be fabricated from an electrically and thermally conductive material to which it can be bonded. In this disclosure, substrates of various embodiments may utilize the composite substrate shown in Figure 1.

[0066] In some cases, a thin bonding layer 116 is formed between the bulk substrate layer 112 and the surface layer 114. For example, the bonding layer 116 is made of a metallic or metalloid material (e.g., metallic or metalloid Si, C, or Si × C y It may include compounds. In some cases, the bonding layer 116 may be thermally and electrically conductive. For example, a metallic or semimetallic bonding layer may be formed between a surface layer 114 (e.g., single-crystal SiC) and a bulk substrate layer 112 (e.g., polycrystalline SiC) as a result of surface activation and thermal bonding.

[0067] In some cases, the bulk substrate layer 112 may be thinned after device manufacturing (e.g., by mechanical processes, etching processes, or chemical mechanical polishing) to further reduce the effective electrical and / or thermal resistance of the bulk substrate layer 112. This can be advantageous because the cost of layer 112 can be significantly lower than the cost of the single-crystal high-quality surface layer 114.

[0068] The longitudinal direction of the multilayer semiconductor device 100 is defined to be approximately perpendicular to the outermost surface 111 of the substrate 110, as indicated by the arrows with a dimension "z" that increases upward in the longitudinal direction. Above the SiC substrate 110, and in this example on the outermost surface 111 of the substrate 110, an epitaxial drift layer 120 is formed, with a layer thickness t D The material includes a semiconductor oxide material having an epitaxial drift layer 120, which itself has an outermost surface 121. A metal layer 130 is formed above the epitaxial drift layer 120, in this case on the outermost surface 121 of the epitaxial drift layer 120. In some embodiments, the material properties of the drift layer 120 and the metal layer 130 are selected to form a Schottky potential barrier in the interface region 140 between the metal layer 130 and the epitaxial drift layer 120. In other embodiments, the material properties of the metal layer 130 are selected to form an ohmic contact with the semiconductor device 100. The metal layer 130 can be either an epitaxial metal layer or a non-epitaxial metal layer with the drift layer below it. In some cases, the metal layer 130 is an epitaxial metal layer that forms a low-defect interface with the epitaxial oxide layer 120 (compared to the interface formed between the epitaxial oxide layer 120 and the non-epitaxial metal layer) to form a Schottky barrier junction. The second metal layer 132 forms an ohmic (or nearly ohmic) electrical contact with the substrate 110 on the back surface opposite the outermost surface 121.

[0069] The layer thickness is not shown to scale in Figure 1 or any other figure in this specification showing a schematic cross-sectional view of a vertical multilayer semiconductor diode device. For example, the thickness of the substrate t sub The thickness of the drift layer 120 is t DIt can be much thicker. In some cases, the thickness of the substrate t sub The thickness of the drift layer 120 can be 1 mm to 3 mm, or 100 microns to 1 mm, or 10 microns to 500 microns. D This can be 10 nm to 100 microns, or 1 micron to 100 microns.

[0070] As shown in Figure 1, the device 100 may include an ohmic anode contact region 151 ("A") and an ohmic cathode contact region 152 ("C"), which may be formed on or within the metal layer 130 and on or within the metal layer 132, respectively. In one example, the ohmic anode contact region 151 includes the metal layer 130. In one example, the ohmic cathode contact region 152 includes the metal layer 132.

[0071] In one example, the SiC substrate 110 may be doped to be n-type or p-type, thereby conferring a conduction type determined by the charge carriers, either electrons or holes. If the substrate 110 is a composite substrate, the bulk substrate layer 112 and / or surface layer 114 may be doped to be n-type or p-type, thereby conferring a conduction type determined by the charge carriers, either electrons or holes.

[0072] In some cases, the epitaxial drift layer 120 includes a semiconductor oxide material. The epitaxial drift layer 120 may include any of the oxide materials described herein, for example, any of the compositions of materials 1 to 7.

[0073] In various examples, the epitaxial drift layer 120 is made of Ga2O3 or (Al x Ga 1-x It is a semiconductor oxide material in the form of 2O3 (wherein the formula 0≦x≦1).

[0074] In another form, the epitaxial drift layer 120 is Mg x Ga 2(1-x) O 3-2x (wherein the formula 0≦x≦1), or Mgx Al 2(1-x) O 3-2x which is a semiconductor oxide material in the form of a ternary oxide, including but not limited to (wherein 0≦x≦1).

[0075] In another form, the epitaxial drift layer 120 is (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z which is a semiconductor oxide material in the form of (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1).

[0076] In another form, the epitaxial drift layer 120 is (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z which is a semiconductor oxide material in the form of (wherein 0≦x≦1, 0≦y≦1, and 0≦z<1).

[0077] In another form, the epitaxial drift layer 120 is (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z which is a semiconductor oxide material in the form of (wherein 0<x<1, 0≦y≦1, and 0≦z<1).

[0078] In some examples, the epitaxial drift layer 120 is Ga₂O₃ (e.g., α phase or β phase); (Al x Ga 1-x )₂O₃ (e.g., α phase or β phase) (wherein 0≦x≦1); Mg x Ga 2(1-x) O 3-2x (wherein 0≦x≦1); Mg x Al 2(1-x) O 3-2x (wherein 0≦x≦1); (Mg x Zn 1-x )z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Zn x Al y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Mg x Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Mg x Al y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Ni x Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Ni x Al y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (wherein 0<x<1 and 0<y<1); or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1, or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4 (wherein 0≦(x,y,z)≦1), or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦(p,x,y,z)≦1) can include one or more of them.

[0079] In other examples, the epitaxial drift layer 120 is doped to be n-type or p-type. In some cases, one or more impurity species may be added to the epitaxial drift layer 120 to exogenously dope the layer. In some cases, the epitaxial drift layer 120 may be a polar material doped via polarization doping.

[0080] In another example, the epitaxial drift layer 120 is formed from β-Ga2O3(-201), and the substrate 110 is formed from C-plane SiC(0001). If the substrate 110 is a composite substrate, the surface layer 114 may include C-plane SiC(0001), and the bulk substrate layer 112 may include polycrystalline SiC.

[0081] In another example, the epitaxial drift layer 120 is formed from β-Ga2O3(-201), the substrate 110 is formed from C-plane SiC(0001), and the oxide is formed on the silicon polar (Si polar) SiC surface.

[0082] Another example has an epitaxial drift layer 120 formed from β-Ga2O3(-201), the substrate 110 is formed from C-plane SiC(0001), and the oxide is formed on the carbon polar (C polar) SiC surface.

[0083] In one example, the epitaxial drift layer 120 is formed entirely or partially from alpha-phase α-Ga2O3 having crystal symmetry group R3m, and the substrate 110 is formed from 4H-SiC. The epitaxial oxide α-Ga2O3 is formed mainly as an A-plane oriented epitaxial film on A-plane oriented 4H-SiC(11-20), R-plane 4H-SiC(10-12), or M-plane 4H-SiC(10-10) surfaces. That is, an A-plane α-Ga2O3 oriented epitaxial film is possible on A-plane, R-plane, and M-plane 4H-SiC surfaces. The SiC surface can be selected from silicon polarity or carbon polarity orientation. The polarity of the surface directly affects the heterojunction formed with the epitaxial oxide, and this epitaxial oxide can be used as a form of polarization control at the interface, and polarization doping can also be easily performed. The epitaxial oxide of the epitaxial drift layer 120 may be nonpolar, semipolar, or polar, depending on the oxide crystal symmetry group and film orientation relative to the substrate surface.

[0084] In one example, the epitaxial drift layer 120 is β-(Al) at 0≦x≦1. x Ga 1-x ) is formed from 2O3. In another example, the epitaxial drift layer 120 is β-(Al) at 0≦x≦0.3. x Ga 1-x The substrate 110 is formed from C-plane SiC(0001) and is formed from 2O3. The SiC substrates described herein can be silicon-polar or carbon-polar. In the case of a composite substrate, the surface layer 114 can be silicon-polar or carbon-polar single-crystal SiC, and the bulk substrate layer 112 can be another material. This is a potential advantage of composite substrates because the surface layer 114 can be a material that can be used as a template for the epitaxial growth of the oxide layer, and the bulk substrate layer 112 can be made from a less restrictive material.

[0085] Furthermore, SiC substrates may be prepared to be intentionally miscut within the surface to expose multiple atomic steps and terraces. For example, a miscut C-plane 4H-SiC(0001) oriented surface may be prepared to form a miscut angle between 0 and 6 degrees oriented toward the A-plane(11-20). A 4-degree miscut is a standard type of substrate used in conventional techniques for growing epitaxial SiC films on n-type doped 4H-SiC substrates. Several examples of this disclosure provide insight that 4-degree miscut 4H-SiC may be advantageous for improving the crystallographic quality of epitaxial oxides.

[0086] In some cases, the SiC substrate is not miscut, meaning that the surface orientation plane of the substrate is approximately parallel to the crystal plane of the SiC in the substrate. For example, an unmiscut substrate can have an angle between 0 and 1 degree between the surface orientation plane of the substrate and the crystal plane of the SiC in the substrate. For instance, an unmiscut substrate can have a C-plane 4H-SiC(0001) oriented surface with a miscut angle between 0 and 1 degree that is oriented towards the A-plane (11-20).

[0087] In one example, the epitaxial drift layer 120 is α-(Al) at 0≦x≦1. x Ga 1-x Formed from 2O3, the substrate 110 is formed from A-plane SiC (1-100), R-plane SiC (2100), or M-plane SiC (1-100). Furthermore, the surface orientation of the SiC substrate having these orientations may be miscut by approximately 0-6 degrees to improve the crystalline properties of the epitaxial oxide. In other cases, the SiC substrate may not be miscut (i.e., have a miscut angle of 0-1 degree).

[0088] In some examples, the composition of the epitaxial drift layer 120 varies in the longitudinal direction. Similarly, the doping concentration may also vary in the longitudinal direction. In various examples, the drift layer 120 may have a combination of (i) a constant doping concentration and a constant composition in the longitudinal direction, (ii) a gradient doping concentration and a constant composition in the longitudinal direction, (iii) a constant doping concentration and a gradient composition in the longitudinal direction, or (iv) a gradient doping concentration and a gradient composition in the longitudinal direction.

[0089] In some embodiments, the epitaxial drift layer 120 may be formed as a superlattice comprising several different or dissimilar oxide materials. In some embodiments, the drift layer 120 may be formed as a chirp layer comprising several oxide materials, the chirp layer being similar to a superlattice with layers whose thickness varies through the drift layer 120. The superlattice or chirp layer may include a wider bandgap material and a narrower bandgap material, respectively, forming a potential energy barrier and a well layer. In some cases, the superlattice or chirp layer of the drift layer 120 may have, longitudinally, (i) a constant doping concentration and a constant composition, (ii) a graded doping concentration and a constant composition, (iii) a constant doping concentration and a graded composition, or (iv) a combination of a graded doping concentration and a graded composition. When the doping and / or composition is graded, the changes in doping and / or composition may be formed by varying the barrier and / or well layer through the drift layer 120. For example, the thickness of the barrier layer and / or well layer can be varied to form a gradient composition through the drift layer 120. In another example, the doping concentration of the barrier layer and / or well layer can be varied to form a gradient doping profile through the drift layer 120. In some cases, the doping concentration, thickness, and / or composition can be varied within one or more barrier layers and / or well layers of the superlattice or chirp layer of the drift layer 120 to form a gradient doping concentration and / or gradient composition.

[0090] In some examples, the configuration may be maintained in which the epitaxial drift layer 120 is formed above the substrate 110, even though one or more layers formed from non-semiconductor oxide materials or non-SiC materials may be formed between the substrate 110 and the drift layer 120. For example, a single-crystal metal layer, a semimetallic layer, or an insulating layer can be formed between the substrate 110 and the drift layer 120. Such layers can be useful for improving contact resistance or for providing a tunnel barrier within the low-resistance (or ohmic) contact between the substrate 110 and the drift layer 120.

[0091] Figure 2A shows a simplified electron energy band diagram 200 of a vertical multilayer semiconductor diode device, where the direction of increasing "z" corresponds to vertical upward movement as shown in Figure 1. In this example, the band diagram 200 shows the Schottky barrier junction (SBJ) region 210, the drift region 220, the n-type doped substrate 225, and the ohmic junction region 230 corresponding to the ohmic contact (OC) region of the diode device 100, where the drift layer is an n-type doped semiconductor oxide material. Schottky metal (SM) and ohmic metal (OM) are, respectively, high potential energy barriers φ SB And, low-energy barrier φ C Selected to achieve this. SM and OM may be different metals or the same metal. Valence band E as a function of longitudinal distance z. v (z) and conduction band E c The energy of (z) is shown, and the band gap energy E g This is also shown.

[0092] As can be seen by inspection, at the interface between the epitaxial metal layer 130 and the epitaxial drift layer 120 in equilibrium state, the Fermi energy level E F The Schottky potential barrier φ coincides across the interface. SB The depletion zone is located at a distance z downward within the epitaxial drift layer. depl It is formed in a state where it is only extended.

[0093] Figure 2B shows the electron energy band gap E g A critical field E can be supported by various semiconductors having crit This shows the empirically derived relationship between the two. The avalanche breakdown process by energy carrier-induced impact ionization determines the maximum sustainable electric field that can be supported by the host semiconductor (i.e., the critical or breakdown voltage over the entire finite thickness of the semiconductor is V). br (As defined). The maximum electric field at breakdown (also known as the critical electric field, E) crit (also known as) is the semiconductor bandgap E g It is known that this increases as the bandgap widens. Figure 2B shows selected data and fitted relationships for non-intentionally doped (NID) semiconductors ranging from small ("NBG", e.g., InAs, InP, GaAs, InGaP) to wide ("WBG", e.g., GaN, ZnO, SiC) and ultra-wide bandgap ("UWBG", e.g., diamond, Ga2O3, AlN, ZnGaO). The dashed line 250 is the fit to the data, yielding the power law shown. The solid line 255 is the preferred fit to the WBG and UWBG data, yielding the power law shown. This dependency (solid line 255) is a major determinant for the adoption of wide bandgap (WBG) semiconductors for high-power electronic devices, and, in this disclosure, ultra-wide bandgap (UWBG) semiconductors.

[0094] Figure 2C plots key relationships between merit indices that describe a given semiconductor. The specific on-resistance per unit thickness of the material.

[0095]

number

[0096] This determines the efficiency or loss of the diode in the conduction state.

[0097]

number

[0098] V br The plot shows the fundamental trends of a given semiconductor technology. The plot shows that both WBG 4H-SiC and UWBG β-Ga2O3 are significantly more advantageous than bulk Si, with on-resistance reduced by 3 to 4 orders of magnitude for a given maximum operating voltage. In particular, the devices of this disclosure leverage the advantages of UWBG Ga2O3 to further expand the possible improvements in high-power device design compared to WBG SiC. Shaded bands represent variations in possible material properties such as crystallinity, defects, and carrier mobility. Figure 2C can be used as a guide for designing high-power diode operation and shows the trade-off between low loss and high-voltage operation.

[0099] Figure 3A shows a schematic representation of the substrate 110 and drift layer 120 of a vertical multilayer semiconductor diode device as shown in Figure 1, and the doping concentration N as a function of the vertical height z. A,D The diagram shows the corresponding plot 301 of exemplary variations in (A and D refer to the donor site and acceptor site, respectively). For example, a highly doped n-type (e.g., n + The doped substrate 110 has a high N D Concentration (for example, 10 18 cm -3 ~10 20 cm -3 , or 10 19 cm -3 ~10 20 cm -3 ) also has a highly doped p-type (e.g., p + The doped substrate 110 has a high N A Concentration (for example, 10 18 cm -3 ~10 20 cm -3 , or 10 19 cm -3 ~10 20 cm -3) has. In this example, there is a discrete change between the drift layer doping concentration 320 and the substrate doping concentration 310 that occurs at the interface 111 between the substrate layer 110 and the drift layer 120. In this example, the drift layer 120 has a lower dopant concentration than the substrate 110. For example, the doped n-type drift layer 120 has 10 15 cm -3 ~10 18 cm -3 N D The doped p-type drift layer 120 may have a concentration of 10 15 cm -3 ~10 18 cm -3 N A It may have a concentration. In some embodiments, both the substrate 110 and the drift layer 120 are doped n-type, or both are doped p-type.

[0100] Figure 3B shows a schematic representation of the substrate 110 and drift layer 120 of a vertical multilayer semiconductor diode device as shown in Figure 1, and the doping concentration N as a function of the vertical height z. A,D The diagram shows the corresponding plot 303 of exemplary variation at the donor site and acceptor site (A and D refer to the donor site and acceptor site, respectively). In this example, the p-type SiC substrate 110 is N A Concentration 312 (for example, about 10 17 cm -3 ~about 10 20 cm -3 , or about 10 19 cm -3 ~about 10 20 cm -3 ) has, and the n-type drift layer doping concentration 320 is N D Concentration (for example, about 10 15 cm -3 ~about 10 20 cm -3 , or about 10 17 cm -3 ~about 10 20 cm -3 , or about 10 15 cm -3 ~about 10 18 cm -3) has. In such embodiments, a p / n junction is formed between the SiC substrate 110 and the drift layer 120. For example, the drift layer 120 may include epitaxial Ga2O3. In such an example, the metal contact 130 in Figure 1 may be a metal that forms an ohmic contact with the drift layer 120. When the SiC substrate 110 is doped to the p type, the metal 130 may be a metal selected from Ti, Al, Ni, Au, Pt, Mo, and / or Ta, as well as their alloys and layered stacks. The thickness of the drift layer 120 can be about 100 nm to 100 microns, or about 500 nm to about 5 microns, or about 1 micron to about 15 microns, or about 3 microns to about 5 microns. The SiC substrate 110 may be Si polar or C polar and may optionally have a miscut oriented surface to modify the material quality of the oxide. In some examples, the miscut angle can be in the range of 0.5 to 10 degrees, or 1 to 5 degrees, or 1 to 4 degrees. The substrate miscut may be selected to provide steps and terraces to aid oxide epitaxy.

[0101] Figure 4 shows a schematic cross-sectional view of a vertical multilayer semiconductor diode device 400 according to an exemplary embodiment. The device 400 in this example is similar to the device 100 in Figure 1, but the device 400 further includes a transition layer 160 positioned between the substrate 110 and the drift layer 120. In various examples, the intermediate transition layer 160 may be formed from SiC, a semiconductor oxide material, or a combination of both materials. The transition layer 160 has a layer thickness t T It holds.

[0102] In some cases, the transition layer 160 comprises a semiconductor oxide material. The transition layer 160 may include any of the oxide materials described herein, for example, any of the compositions of materials 1 to 7. The transition layer 160 may include a single semiconductor oxide composition, or more sublayers having different semiconductor oxide compositions, which can be selected from materials 1 to 7 (for example, the sublayers may form a double layer, a multilayer structure, a superlattice, or a chirp layer). In some cases, the transition layer 160 comprises a gradient composition (for example, a linear, stepwise, or chirp composition gradient) comprising one or more of materials 1 to 7. In some cases, the transition layer 160 comprises one or more of materials 1 to 7 that are doped with a single dopant concentration or with a dopant concentration that varies with depth in the transition layer 160.

[0103] In some examples, the transition layer 160 is Ga2O3 (e.g., α-phase or β-phase); (Al x Ga 1-x )2O3 (for example, α-phase or β-phase) (wherein 0≦x≦1); Mg x Ga 2(1-x) O 3-2x (In the formula, 0≦x≦1);Mg x Al 2(1-x) O 3-2x (In the formula, 0≦x≦1);(Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein the formula, 0≦x≦1, 0≦y≦1, and 0≦z≦1), Zn x Ga y O z (wherein the formula 0≦x≦1, 0≦y≦1, and 0≦z≦1);Zn x Al y O z (wherein the formula 0≦x≦1, 0≦y≦1, and 0≦z≦1); Mg x Ga y O z (wherein the formula 0≦x≦1, 0≦y≦1, and 0≦z≦1); Mg x Al y O z (wherein the formula 0≦x≦1, 0≦y≦1, and 0≦z≦1); Nix Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Ni x Al y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (wherein 0<x<1 and 0<y<1); or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4 (wherein 0≦(x,y,z)≦1), or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z wherein one or more of 0≦(p,x,y,z)≦1 can be included.

[0104] Figure 5 shows a schematic diagram 500 of the substrate 110, transition layer 160 and drift layer 120 of the vertical multilayer semiconductor diode device as shown in Figure 4, and an associated plot of exemplary variation of doping concentration N as a function of the vertical height z A,D .

[0105] In this example, the transition layer doping concentration 560 may have a doping concentration between the substrate doping concentration 510 and the drift layer doping concentration 520 due to discrete changes in the doping concentration between the substrate 110 and the transition layer 160, and between the transition layer 160 and the drift layer 120. In one example, the substrate 110 may be n + doped (i.e., 10 19~10 20 cm -3 The transition layer 160 has a doping concentration of n - It is okay to dope (i.e., about 10 18 cm -3 , or 10 17 cm -3 ~10 18 cm -3 (Having a doping concentration of n), the drift layer 120 is n -- It's okay to dope (i.e., 10 15 cm -3 ~10 17 cm -3 (having a doping concentration of ), as a result, it moves vertically upward from the substrate 110 to the drift layer 120, n + From the doping area n -- A transition can occur during the doping region. Similarly, a p-type device can be formed, and the substrate 110 is p + The transition layer 160 is doped with p - Doped, drift layer 120 is p -- These layers are doped with the above doping concentrations of the acceptor, not the donor. In other cases, the substrate 110 is n + or p + It can be doped, and the drift layer 120 is each n (to form a Schottky barrier junction) - or p - The transition layer 160 can be doped, and the transition layer 160 can have a doping concentration between the doping concentration of the substrate 110 and the doping concentration of the drift layer 120. For example, the transition layer 160 may be formed from SiC, and the drift layer 120 may be formed from a semiconductor oxide material. In another example, the transition layer 160 (TL) may be formed from a semiconductor oxide material, and the drift layer 120 may be formed from the same semiconductor oxide material as TL or a different oxide material. In one example, the transition layer 160 may be formed from a material selected to provide a structural matching region between the substrate 110 and the drift layer 120. For example, Mg x Zn y Ni z (Al p ,Ga1-p )O q The transition layer 160, which includes a semiconductor oxide material in the form of [a specific type of material], can be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 can be Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. Another example of a semiconductor oxide material is silicon oxycarbide Si x C y O z It is in the form of a transition layer 160 and can be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. Yet another example of a semiconductor oxide material is silicon oxynitride (Si). x N y O z It is in the form of a transition layer 160 and can be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. Another example of the transition layer 160 is silicon germanium carbide Si. x Ge y C z The material includes a transition layer 160, and therefore the interface strain formed between the SiC substrate 110 and the drift layer 120 can be controlled, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x Contains O3.

[0106] In some cases of structures 400 and 500, the transition layer 160 and the drift layer 120 contain n-type Ga2O3 (e.g., Ga2O3 deposited by single-crystal epitaxial deposition), and the transition layer doping concentration 560 is at least an order of magnitude higher than the drift layer doping concentration 520. The doping concentration in the transition layer 160 can be constant (as shown in Figure 5) or can be spatially variable in the growth direction (as shown in Figures 6 and 7, and further described later). The doping concentration of the transition layer 160 can be less than or equal to the doping concentration of the SiC substrate 110. The Ga2O3 transition layer 160 can have a thickness of about 10 nm to about 1 micron. The thickness of the Ga2O3 drift layer can be about 1 micron to 100 microns, or about 2 microns to about 15 microns, or about 3 microns to about 10 microns. The SiC substrate 110 can be Si polar or C polar and optionally may have a miscut oriented surface.

[0107] The surface of a SiC substrate or layer can be intentionally terminated with one or more species. For example, intentional surface termination of a SiC surface can substantially include silicon (Si), carbon (C), oxygen (O), or nitrogen (N) termination species. Termination with a single species (e.g., uniform termination) can be advantageously used to seed the epitaxial deposition of semiconductor oxides (or metal oxide films), resulting in interfacial bonding with a lower lattice mismatch (or reduced mismatch, or an acceptable mismatch) compared to when the surface is not terminated with a single species. For example, in a vacuum, a SiC surface can be prepared to form a Si-terminated surface. The Si-terminated surface can then preferentially react with reactive oxygen species to form a -C-Si-O- bond arrangement. Conversely, a C-terminated surface can be prepared so that the reaction with reactive oxygen produces a Si-CO- arrangement at the immediate interface. The oxygen can then readily bond with Ga (or another cation atom) to subsequently form a Ga2O3 single-crystal epitaxial layer.

[0108] Other possible interface layers can also be advantageously used. For example, silicon oxycarbide Si with a transition layer. x C y O z The interface surface including can also be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x Contains O3.

[0109] Alternatively, silicon carbon nitride (Si) can be included in the transition layer. x C y N z The interface surface including can also be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x Contains O3.

[0110] Germanium nitride Ge can be included in the transition layer 160. x N y The interface surface including can also be formed between the SiC substrate 110 and the drift layer 120, and the drift layer 120 is made of Ga2O3 or compositionally graded Al x Ga 1-x Contains O3.

[0111] Another example of a transition layer oxide is one in the form of magnesium oxide (MgO), which can be included in the transition layer 160 and formed between the SiC substrate 110 and the drift layer 120, where the drift layer 120 is Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. In the case of a 4H-SiC(0001) surface, the MgO(111) oriented transition layer may be only a few unit cells thick.

[0112] Another example of a transition layer oxide is a zinc gallium oxide (e.g., spinel crystal symmetry ZnGa2O4, e.g., having an Fd3m space group) which can be included in the transition layer 160 and formed between the SiC substrate 110 and the drift layer 120, where the drift layer 120 is Ga2O3 or compositionally graded Al x Ga 1-x It contains O3. In the case of a 4H-SiC(0001) surface, the ZnGa2O4(111) oriented transition layer may be thicker than the thickness of one or a few unit cells.

[0113] In other examples, one or more layers formed from non-semiconductor oxide materials or non-SiC materials may be formed between the substrate 110 and the transition layer 160, and / or between the transition layer 160 and the drift layer 120. For example, a single-crystal metal layer, a semimetallic layer, or an insulating layer can be formed between the substrate 110 and the transition layer 160. Such layers can be useful for improving contact resistance or for providing a tunnel barrier to form a low-resistance (or ohmic) contact between the substrate 110 and the transition layer 160.

[0114] Figure 6 shows a schematic diagram of the substrate 110, transition layer 160, and drift layer 120 of a vertical multilayer semiconductor diode device as shown in Figure 4, and the doping concentration N as a function of the vertical height z. A,D A related plot 601 of another exemplary variation in the same context is shown. Figure 6 shows an example in which the transition layer 160 has a variable doping density (i.e., doping concentration). The transition layer 160 may have a variable doping density that varies longitudinally, perpendicular to the outermost surface of the substrate. In some cases, the variable doping density of the transition layer 160 includes a doping density (e.g., the average doping density of the layer) that is between the doping density of the substrate and the doping density of the drift layer.

[0115] In this example, the transition layer doping concentration 660 has a monotonic gradient in the z direction, starting at a doping concentration lower than (i.e., less than) that of the substrate 110 and ending at a doping concentration approximately equal to that of the drift layer 120. In some cases, the transition layer doping concentration 660 has a monotonic variation, starting at a doping concentration approximately equal to that of the substrate or between the substrate doping concentration 610 and the drift layer doping concentration 620, and ending at a doping concentration approximately equal to that of the drift layer or between the substrate doping concentration 610 and the drift layer doping concentration 620. In one example, the transition layer doping concentration 660 may match the substrate doping concentration 610 at the interface between the substrate 110 and the transition layer 160, and then continuously change to match the drift layer doping concentration 620 at the interface between the transition layer 160 and the drift layer 120. In one example, the change in the transition layer doping concentration 660 may be substantially linear as a function of the vertical height z (for example, as shown in Figure 6). In another example, the transition layer concentration 660 may change continuously as a function of the vertical height z (i.e., without significant step changes, for example, monotonically or nonlinearly). In yet another example, the transition layer concentration 660 may change in a stepwise manner as a function of the vertical height z. The transition layer 160 in Figure 6 (for example, with respect to the transition layer 160 in Figure 4) may have any of the attributes of the transition layer 160 described above.

[0116] In one example, the initial transition layer doping concentration 660 at the interface between the substrate 110 and the transition layer 160 may differ from the substrate doping concentration 610 (for example, as shown in Figure 6). Similarly, in another example, the final transition layer doping concentration 660 (moving upward in the z direction) at the interface between the transition layer 160 and the drift layer 120 may differ from the drift layer doping concentration 620.

[0117] Referring back to Figure 1, discrete compositional changes, such as those occurring in the SiC substrate 110 and the oxide-based drift layer 120 (e.g., Ga2O3), can cause defects on the interface surface 111, which can affect carrier transport across the heterointerface between the substrate 110 and the drift layer 120 (e.g., discontinuities in the conduction and valence bands can lead to potential energy confinement or barrier and / or electrically active defects and / or crystallographic defects). In some cases, differences in the material properties of the substrate 110 and the drift layer 120 (e.g., lattice constants, crystal symmetry and / or orientation) can also cause through-dislocations to form in the drift layer 120, which can lead to defects at the interface 121 between the drift layer and the layer above it (e.g., the metal layer 130). Defects at interface 121 can affect carrier transport across the heterointerface between the drift layer 120 and the layer above it (e.g., the metal layer 130), potentially affecting, for example, the Schottky barrier diode properties.

[0118] Figure 7 shows a schematic diagram of the substrate 110, transition layer 160, and drift layer 120 of a vertical multilayer semiconductor diode device as shown in Figure 4. Figure 7 also shows the doping concentration N as a function of the vertical height z. A,D Related plot 701 of another exemplary variation in the composition, as well as an exemplary variation in the bandgap energy E as a function of vertical height z, which occurs by varying the composition. G Related plot 702 is also shown. In this example, the SiC substrate has a first bandgap energy of approximately 3.2 eV 770. As can be seen in this example, the bandgap energy of the transition layer 160 is 780 eV. G This value is close to the first bandgap energy of substrate 110, which is 770, and the bandgap energy of drift layer 120 is 790E. G It increases substantially linearly as a function of vertical height up to a value close to . In another example, the changing composition of the transition layer 160 is such that the bandgap energy of the drift layer 120 is 790E from the bandgap energy of the substrate 110. G It can be selected to cause a stepwise increase.

[0119] In this example, the transition layer doping concentration of 760 is the same as the transition layer doping concentration of 660 in Figure 6, and can have all the same characteristics as described above. Figure 7 shows an example in which the transition layer doping concentration of 760 starts at a doping concentration approximately equal to that of the substrate 110 (substrate doping concentration 710) and ends at a doping concentration approximately equal to that of the drift layer 120 (drift layer doping concentration 720).

[0120] In some cases of structures 400, 600, and 700, the transition layer 160 and the drift layer 120 contain n-type Ga2O3 (e.g., Ga2O3 deposited by single-crystal epitaxial deposition). In some such cases, the doping concentration 660 or 760 in the transition layer 160 is at least an order of magnitude higher than the drift layer doping concentration 620 or 720. The doping concentration 660 or 760 in the transition layer 160 can be constant (as shown in Figure 5) or can be spatially variable in the growth direction (as shown in Figures 6 and 7). If the doping concentration is spatially variable within the transition layer 160, at least one of the values ​​of the doping concentration 660 or 760 in the transition layer 160 is at least an order of magnitude higher than the drift layer doping concentration 620 or 720. For example, the transition layer 160 may include a doping concentration gradient of 660 or 760, and a doping concentration equal to or similar to the drift layer doping concentration of 620 or 720 at the interface between the transition layer 160 and the drift layer 120. In such a case, the doping concentration gradient of 660 or 760 can be increased between the drift layer 120 and the SiC substrate 110 until it is at least an order of magnitude greater than the doping concentration of 720 in the drift layer 120. In other examples, the doping concentration of the transition layer 160 may be higher than the doping concentration of the drift layer 120, and there may be a discrete variation in the doping density between the transition layer 160 and the drift layer 120. In such a case, there may be spatially variable doping concentrations within the transition layer 160 such that some or all of the doping concentrations in the transition layer 160 are at least an order of magnitude higher than the doping concentrations in the drift layer 120. The doping concentration of the transition layer 160 may be less than or equal to the doping concentration of the SiC substrate 110. The Ga2O3 transition layer 160 can have a thickness of approximately 10 nm to approximately 1 micron. The thickness of the Ga2O3 drift layer 120 can be approximately 1 micron to 100 microns, or approximately 2 microns to approximately 15 microns, or approximately 3 microns to approximately 10 microns. The SiC substrate 110 can be Si polar or C polar and optionally may have a miscut oriented surface.

[0121] Figure 8A is a schematic cross-sectional view of a vertical multilayer semiconductor device 800 according to an exemplary embodiment, comprising a substrate 110, a drift layer 120, an intermediate layer 170, and a metal layer 130. In this example, device 800 is similar to device 100 in Figure 1, but further includes an intermediate layer 170 formed from a semiconductor oxide and disposed between the drift layer 120 and the metal layer 130. The intermediate layer 170 has a layer thickness t I In this example, the intermediate layer 170 is formed directly on the outermost surface 121 of the drift layer 120, and the metal layer 130 is formed on the outermost surface 171 of the intermediate layer 170.

[0122] In some cases, the intermediate layer 170 may contain a high carrier concentration to form an ohmic contact between the drift layer 120 and the metal layer 130. For example, if the drift layer 120 is n-type, the intermediate layer 170 may contain a high n-type doping concentration (e.g., N D about 10 19 cm -3 Or 10 20 cm -3 ), or if the drift layer 120 is p-type, a high p-type doping concentration (e.g., N A about 10 19 cm -3 Or 10 20 cm -3 ) may include. In such cases, the doping concentration in the drift layer is lower (e.g., about 10%). 15 cm -3 ~about 10 18 cm -3 , or 10 15 cm -3The doping concentration of the intermediate layer 170 may be at least an order of magnitude higher than the doping concentration of the drift layer 120 to form an ohmic contact with the metal layer 130. Such an ohmic contact may be useful, for example, if a p / n junction exists between other layers of the structure. For example, a p / n junction can be formed using a p-type SiC substrate 110 and an n-type drift layer 120 (e.g., including epitaxial Ga2O3), or between an n-type drift layer and a p-type epitaxial layer, as further described herein. The thickness of the drift layer 120 can be about 1 to 100 microns, or about 3 to 15 microns, or about 3 to 5 microns. The SiC substrate 110 can be Si-polar or C-polar and optionally may have a miscut oriented surface.

[0123] Figure 8B shows a schematic cross-sectional view of a vertical multilayer semiconductor diode device 802 according to an exemplary embodiment. In this example, device 802 is similar to device 800 but further includes a transition layer 160 disposed between the substrate 110 and the drift layer 120, similar to device 400 in Figure 4.

[0124] A further advantage of the epitaxial oxide-SiC hybrid structures described herein is the availability of additional doping methods to form doping regions (e.g., planar doping regions, selective area doping regions, or doping regions via layer depth or thickness) within the host oxide region. For example, SiC can be effectively doped to p-type or n-type using in-situ epitaxial layer growth or post-epitaxial layer growth ion implantation followed by high-temperature recrystallization annealing. Diffusion doping of SiC is not an effective method for post-growth doping and / or selective area doping due to the high SiC bond energy that hinders doping of favorable activated impurity species. In contrast, post-growth diffusion doping can be used to dope oxides (e.g., Ga2O3) and can be very effective. As an example, spin-on-glass dopants can be selectively applied to the surface of Ga2O3 as a blanket layer, or to selected areas, and impurity species can be transported into the oxide material using a diffusion-driven process. A characteristic of oxides is that when dopant species are driven into an oxide with a relatively low thermal budget, they can be activated, for example, using rapid thermal annealing techniques. For example, diffusion-driven dopants can change the conductivity of Ga2O3 from low n-type doping used in drift layers to semi-insulating conductivity using doping species such as Mg, H, Fe, and Zn. In another example, Si or Ge can be used to increase the n-type doping of Ga2O3 by at least an order of magnitude, in some cases. In yet another example, spin-on-glass can be used to provide a surface reservoir of dopant impurities that can be driven into the relevant oxide region. Spin-on dopants can be patterned to provide selective area doping. The lateral and longitudinal range of the doping region can be controlled using diffusion time and temperature. Spin-on-glass materials may include SiO2, GeO2, Fe2O3, B2O3, MgO, P2O5, or hydrogen-containing materials.Accordingly, not only ion implantation or in-situ epitaxial layer doping, but also post-growth diffusion drive processes for doping the epitaxial oxide layer to be n-type or p-type can be used.

[0125] In one example, the intermediate layer 170 has a wider bandgap E than that of the semiconductor oxide material from which the drift layer 120 is formed G and is formed of a different semiconductor oxide. In one example, the oxide material of the intermediate layer 170 is selected to improve diode performance characteristics such as turn-on voltage and / or reverse breakdown voltage. In some cases, the intermediate layer 170 adjusts the Schottky potential barrier φ S , and this Schottky potential barrier changes diode performance characteristics such as turn-on voltage and / or reverse breakdown voltage. In some cases, the intermediate layer 170 has a correspondingly varying bandgap E G and can be formed with a graded semiconductor oxide composition. In another example, the intermediate layer has a multilayer, superlattice, or chirped layer configuration comprising two or more different semiconductor oxide materials selected to improve, for example, reverse breakdown voltage performance (e.g., by adjusting the Schottky potential barrier φ S ). In some cases, it may be advantageous for the bandgap of the intermediate layer 170 to be larger than the bandgap of the drift layer 120. For example, the drift layer 120 can comprise Ga₂O₃, and the intermediate layer 170 can comprise (Al x Ga 1-x )₂O₃, where 0<x≤1, or where 0<x≤0.3.

[0126] In another example, the intermediate layer 170 has a narrower or smaller bandgap E than that of the semiconductor oxide material from which the drift layer 120 is formed GIt is formed from different semiconductor oxides having the following properties. In one example, the intermediate layer 170 is selected to improve diode performance characteristics such as turn-on voltage and / or reverse breakdown voltage. For example, a material with a narrow bandgap can advantageously form an improved depletion region between the drift layer 120 and the intermediate layer 170 by exhibiting opposite conduction-type charge carriers. For example, nickel oxide (NiO), copper oxide (Cu2O), lithium oxide (Li2O), or composite oxides such as spinel crystal structures NiGa2O4, ZnGa2O4, MgGa2O4 are n-type (Al x Ga 1-x ) can be given p-type properties that can be advantageously used in the heterojunction formed with the 2O3UWBG drift layer 120. Furthermore, ternary or spinel oxides in the form of NiGa2O4, Cu2GaO4 and LiGaO2 may also be used in the intermediate layer 170. As a further example, an intermediate layer comprising multiple layers of p-type NiO / NiGaO formed on Ga2O3 may also be employed. For example, NiGaO can be formed explicitly or by intermixing NiO and Ga2O3 by high-temperature annealing. In some cases, the intermediate layer 170 has a smaller band gap than the drift layer 120, and by band alignment, there is a conduction band that is offset at the interface between the intermediate layer 170 and the drift layer 120. In such cases, even though the intermediate layer 170 has a smaller band gap than the drift layer 120, the intermediate layer 170 can form an electron tunnel barrier between the drift layer 120 and the Schottky metal layer 130.

[0127] The structures in Figures 8A and 8B may include an n-type or p-type 4H-SiC substrate 110, an n-type or p-type epitaxial oxide drift layer 120 (e.g., n-type Ga2O3 or p-type NiO), an optional n-type or p-type intermediate layer 170 (e.g., n-type Ga2O3 or p-type NiO), and a metal contact layer 130 that can form ohmic contact or a Schottky barrier with the intermediate layer 170. Furthermore, an optional n-type or p-type transition layer 160 (e.g., SiC or Ga2O3) may be included as shown in Figure 8B. The polar 4H-SiC substrate may be doped to n-type or p-type using endogenous and / or exogenous dopants, and / or may have n-type or p-type induced charges by polarity. The epitaxial oxide drift layer 120 and the intermediate layer 170 can also be polar in some cases (e.g., using Pna21Ga2O3), in which case they can be doped with endogenous and / or exogenous dopants and / or have n-type or p-type induced charges depending on their polarity. In other cases, the epitaxial oxide drift layer 120 and the intermediate layer 170 can be nonpolar and can be doped to n-type or p-type using endogenous and / or exogenous dopants.

[0128] Figures 8C to 8F show tables representing combinations of n-type and p-type layers having ohmic contacts ("metal S") to a SiC substrate and ohmic or Schottky contacts ("metal E") to an epitaxially grown semiconductor layer, according to several embodiments. The structures shown in Figures 1, 4, 8A, and 8B may include layers having the doping types shown in the respective tables in Figures 8C to 8F. In some cases, the n-type or p-type doping of the SiC (e.g., 4H-SiC) substrate 110 ("substrate" in Figures 8C to 8F) is 1e15cm -3 ~1e21cm -3 , or 1e17cm -3 ~1e20cm -3 , or 1e15cm -3 Less than, or 1e21cm -3It can be super. The n-type or p-type doping of the epitaxial oxide drift layer 120 ("Oxide" in Figures 8C to 8F) (e.g., n-type Ga2O3 or p-type NiO), the intermediate layer 170 ("IL" in Figures 8C to 8F) (e.g., n-type Ga2O3 or p-type NiO), and the transition layer 160 ("TL" in Figures 8C to 8F) are each 1e15cm². -3 ~1e21cm -3 , or 1e16cm -3 ~1e20cm -3 , or 1e15cm -3 ~1e18cm -3 , or 1e15cm -3 Less than 1e20cm -3 It can be super. The "i" (endogenous or not intentionally doped), "n--", or "p--" layer is approximately 1 e15 cm². -3 , or approximately 1 e 15 cm -3 It can have a doping density of less than 1 e 15 cm. The "n-" or "p-" layer is approximately 1 e 15 cm. -3 ~About 1e16cm -3 It can have a doping density of approximately 1 e 16 cm. The "n" or "p" layer is approximately 1 e 16 cm. -3 ~About 1e18cm -3 It can have a doping density of approximately 1 e 18 cm². The "n+" or "p+" layer is approximately 1 e 18 cm². -3 Over, or approximately 1e19cm -3 Over, or approximately 1 e 20 cm -3It is possible to have doping densities of over 100. It will be understood that these ranges can overlap by up to an order of magnitude. In general, increasing the band gap energy of the host material for the same impurity incorporation for doping may substantially lower the activated doping density. Thus, the substrate 110, the epitaxial oxide drift layer 120 (e.g., n-type Ga2O3 or p-type NiO), the intermediate layer 170 (e.g., n-type Ga2O3 or p-type NiO), and the transition layer 160 can each be n-type (e.g., n-, n, n+, etc.), p-type (p-, p, p+, etc.), or i-type (e.g., endogenous, or undoped, and can also be n-- or p--) layers in the structure and device.

[0129] Ohmic contacts to the SiC substrate ("metal S" in Figures 8C-8F) are optional and may be omitted in some cases. For example, the layers of the structure can be patterned and selectively etched so that two or more contacts are created on two or more epitaxial layers of the structure, instead of on the back side of the substrate.

[0130] For example, Figure 8E includes cases where the [polar 4H-SiC110 / epitaxial oxide 120 / interlayer 170 / metal 130] structure is an nnn Schottky metal structure or a ppp Schottky metal structure. In such cases, the Schottky metal contact 130 ("metal E" in Figures 8C-8F) forms a Schottky barrier with the n-type or p-type epitaxial oxide drift layer 120 and the interlayer 170. The resulting structure can be used to form diodes, transistors, or other devices. For example, metal oxide semiconductor field-effect transistors (MOSFETs) can be formed using ion implantation to form doping regions beneath the source and drain contacts, and the oxide layer of these structures can be used as a channel region, which is isolated from the gate contact by a gate oxide. The epitaxial interlayer 170 can form the gate oxide, or in other cases, a non-epitaxial (e.g., sputtered) gate oxide can be deposited. Furthermore, similar structures can be formed using the [polar 4H-SiC110 / transition layer 160 / epitaxial oxide 120 / metal 130] structure shown in Figure 8D, which includes nnn Schottky metal structures or ppp Schottky metal structures.

[0131] In another example, Figure 8E includes cases where the [polar 4H-SiC110 / epitaxial oxide 120 / interlayer 170 / metal 130] structure is an nnp ohmic contact structure, an nnp Schottky metal structure, a ppn ohmic contact structure, or a ppn Schottky metal structure. In such cases, a p / n junction is formed between the epitaxial oxide layer and the interlayer. Furthermore, if a Schottky metal is present, a Schottky barrier is formed with the n-type or p-type interlayer. This Schottky barrier can function to increase or decrease the built-in potential within the device and / or to form wells for 2D electron gas or 2D hole gas, as will be further described below. The resulting structure can be used to form diodes, transistors, or other devices. For example, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be formed using ion implantation to form doping regions beneath the source and drain contacts. In another example of a transistor, the intermediate layer can be patterned and selectively etched to form doping regions beneath the source and drain contacts, and the gate oxide can be formed between the epitaxial oxide drift layer 120 and the gate contact. In other cases, LEDs can be formed using such structures in which the epitaxial oxide and / or polar group III nitride layers emit light. Furthermore, similar structures can be formed using the [polar 4H-SiC110 / transition layer 160 / epitaxial oxide 120 / metal 130] structure shown in Figure 8D, including nnp ohmic contact structures, nnp Schottky metal structures, ppn ohmic contact structures, or ppn Schottky metal structures.

[0132] In another example, Figures 8E and 8F include cases where the [polar 4H-SiC 110 / epitaxial oxide 120 / intermediate layer 170 / metal 130] structure can be a pnn ohmic contact structure, a pnn Schottky metal structure, an npp ohmic contact structure, or an npp Schottky metal structure. In such cases, the p / n junction is formed between the polar 4H-SiC substrate and the epitaxial oxide layer. Furthermore, an optional n-type or p-type transition layer 160 (e.g., SiC, or Ga2O3) can be included between the polar 4H-SiC substrate and the epitaxial oxide layer, and the p / n junction interface can be moved to the interface between the polar 4H-SiC substrate and the transition layer, or to the interface between the transition layer and the epitaxial oxide layer. Furthermore, if a Schottky metal is included, a Schottky barrier can be formed with the n-type or p-type intermediate layer. This Schottky barrier can function as a second built-in potential within the device, and if the potentials are in opposite directions (e.g., forming a back-to-back potential), the structure can, in some cases (e.g., in metal-insulator-semiconductor (MIS) transistor architectures), be used as a transistor or switch. The resulting structure can be used to form diodes, transistors, or other devices. For example, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be formed using ion implantation to form doping regions beneath the source and drain contacts. In other cases, an LED can be formed using such a structure in which the epitaxial oxide and / or polar group III nitride layer emits light. Furthermore, similar structures can be formed using the [polar 4H-SiC110 / transition layer 160 / epitaxial oxide 120 / metal 130] structure shown in Figure 8D, including pnn ohmic contact structures, pnn Schottky metal structures, npp ohmic contact structures, or npp Schottky metal structures.

[0133] In another example, Figures 8E and 8F include cases where the [polar 4H-SiC110 / epitaxial oxide120 / interlayer170 / metal130] structure can be a pnp ohmic contact structure, a pnp Schottky metal structure, an npn ohmic contact structure, or an npn Schottky metal structure. In such cases, a p / n junction is formed between the polar 4H-SiC substrate and the epitaxial oxide layer, and a p / n junction is formed (in the opposite direction) between the epitaxial oxide layer and the interlayer. Furthermore, an optional n-type or p-type transition layer 160 (e.g., SiC, or Ga2O3) can be included between the polar 4H-SiC substrate and the epitaxial oxide layer, and the p / n junction interface can be moved to the interface between the polar 4H-SiC substrate and the transition layer, or to the interface between the transition layer and the epitaxial oxide layer. Furthermore, if a Schottky metal is included, a Schottky barrier is formed with the n-type or p-type interlayer. This Schottky barrier can function to increase or decrease the built-in potential within a device and / or to form wells for 2D electron gas or 2D hole gas, as further described below. The resulting structure can be used to form diodes, transistors, or other devices. For example, a bipolar junction transistor (BJT) can be formed by patterning and selectively etching a structure to form separate contacts in the p-type and n-type layers of an npn or pnp structure. In such a device, metal contacts adjacent to the oxide or intermediate layer can form either the source or drain contact of the BJT, and additional source or drain contacts can be formed. In other cases, a metal-oxide-semiconductor field-effect transistor (MOSFET) can be formed using patterning and selective etching and / or ion implantation of the intermediate layer to form doping regions beneath the source and drain contacts. In other cases, an LED can be formed using such a structure in which an epitaxial oxide and / or polar group III nitride layer emits light.Furthermore, similar structures can be formed using the [polar 4H-SiC110 / transition layer 160 / epitaxial oxide 120 / metal 130] structure shown in Figure 8D, which includes a pnp ohmic contact structure, a pnp Schottky metal structure, an npn ohmic contact structure, or an npn Schottky metal structure.

[0134] Another possible utility of the intermediate layer 170 is the favorable reaction of the Schottky metal 130 with selective alloying regions 141. The selective alloying regions 141 can be formed by rapid thermal annealing or a diffusion process.

[0135] Any of the drift layer 120, transition layer 160, and / or intermediate layer 170 (for example, those of devices 100, 400, 800, or 802 in Figures 1, 4, 8A, and 8B) may include a single epitaxial oxide layer or multiple layers of epitaxial oxide material (e.g., two-layer, three-layer, superlattice, and / or chirp layers). The two-layer, three-layer, and other multilayer structures of layers 120, 160, and / or 170 may include different compositions and / or different doping densities. In different examples, the total number of layers in any of the drift layer 120, transition layer 160, and / or intermediate layer 170 may be 1 to 100, or 1 to 20, or 1 to 10.

[0136] Any of the drift layer 120, transition layer 160, and / or intermediate layer 170 (for example, those of devices 100, 400, 800, or 802 in Figures 1, 4, 8A, and 8B respectively) may comprise a superlattice and / or chirp layer containing an epitaxial oxide semiconductor material. A superlattice, such as a short-period superlattice, includes alternating layers (i.e., barrier layers and well layers) that form a unit cell, and the unit cell is repeated to form the superlattice. A chirp layer is similar to a superlattice in that it also includes alternating layers, but the layer thickness and / or layer composition changes monotonically along the thickness (or growth direction) of the chirp layer. The thickness of each barrier layer, well layer, and / or unit cell within a superlattice or chirp layer can be less than 1 monolayer (ML) to 100ML, or less than 1ML to 20ML, or less than 1ML to 10ML, or less than 1ML to 5ML, or 1ML to 20ML, or 1ML to 10ML, or 1ML to 5ML. Layers with a thickness of less than 1ML may be discontinuous in the transverse direction (i.e., in the direction parallel to the surface of the substrate from which the layer grows).

[0137] By using superlattices to form digital alloys, the barrier layer and well layer of the superlattice have material properties that differ from the material properties of the barrier layer and the material properties of the well layer, resulting in an overall material property (i.e., composite material property) where the superlattice has these properties. Furthermore, by using superlattices, the effects of electrons and / or holes in a device can be modified, for example, by creating a barrier in the flow of electrons and / or holes across the superlattice.

[0138] Furthermore, chirp layers can be used to form digital alloys and to impact electrons and / or holes in devices as described herein. In addition, chirp layers introduce varying material parameters within the chirp layer, such as varying average lattice constants, varying average band gaps, and / or varying average doping densities. For example, chirp layers can be used to form electron blocking layers (EBLs). Chirp layers can also be used to change the lattice constant in a structure, for example, by forming a drift layer on a SiC substrate, where the drift layer has a different lattice constant than SiC.

[0139] Figure 9A shows the desired R ON and V br This document discloses design flow 9900 for achieving target performance of UWBG power devices based on specifications. In particular, a device simulator utilizing a Poisson solver and quantum mechanical model of a specific semiconductor is used to model this performance. This modeling is described in block 9910 (Schottky barrier "SB" diode target R ON and V br Select (), block 9912 (select drift layer bandgap), block 9914 (select drift layer conductivity / doping), and block 9916 (V br This may include selecting the drift layer thickness. Flow 9900 targets R before proceeding further. ON To check whether this is acceptable, a decision point 9920 may be included. ON If this is unacceptable, the flow returns to block 9914 to re-select the drift layer parameters. ONIf acceptable, flow 9900 proceeds to block 9930 (optionally, select substrate / drift transition layer), block 9932 (select Schottky barrier configuration), block 9934 (select substrate ohmic configuration), and block 9936 (simulate design). If the design is within specifications in block 9940, the device is manufactured in block 9950. If the design does not meet specifications, flow returns to block 9912 to re-select parameters for various layers of the device. 1D, 2D, and 3D simulation tools can be used in combination with finite element electrostatic solvers to detail the electric field distribution within the device structure.

[0140] Figure 9B is the energy band diagram 2000 of a detailed simulation of the conduction band and valence band edges of the vertical multilayer semiconductor device shown in Figure 4, and shows the region (from left to right) including the Schottky barrier metal 2010 (Ni in this example) and the substrate 2016 (Si polar 4H-SiC (0001) in this example) that forms a rectifying junction with the drift layer 2012 and the transition layer 2014 (β-Ga2O3(-201) in this example). The band diagram was constructed from detailed knowledge of the band structure and absolute electron affinity of each material, which enables the determination of accurate heterojunction offsets. The substrate is

[0141]

number

[0142] n-type doped 4H-SiC, transition layer n-type β-Ga2O3

[0143]

number

[0144] And, drift region

[0145]

number

[0146] And so it is.

[0147]

number

[0148] An ideal case of nickel Schottky metal with a barrier height of is shown, and the Fermi energy is chosen as the zero-energy reference. The diode is substantially a unipolar device, and the majority carriers are electrons. Holes in the valence band can be negligibly ignored. Furthermore, the detailed band structure of β-Ga2O3 reveals considerably heavier hole masses compared to 4H-SiC. The mobility of holes in the valence band is also limited by the flat valence band energy dispersion in crystal momentum space.

[0149] Referring to Band Diagram 2001 in Figure 9C, it can be seen that effective n-type doping of the drift layer has a strong influence on the depletion width of the Schottky potential penetrating the drift region. Band Diagram 2001 is an enlarged view of the energy band values ​​(y-axis) from 0eV to 1.4eV from Energy Band Diagram 2000. Depletion potential Z depl The width of φ affects the leakage behavior of the reverse bias, SB This determines the thermionic emission process under forward bias. As expected, the size or extent of the depletion region decreases as the doping concentration increases. The ohmic contact layer located directly beneath the substrate (e.g., the ohmic cathode contact region 152 in Figure 4) is not shown in Band Diagram 2001. The energy band diagram 2001 also shows the ideal Schottky barrier potential φ arising from the metal-semiconductor junction. SB This demonstrates that the Schottky barrier energy reduction effect due to image force, etc., has not been shown (this is important, but does not deviate from the main conclusions above).

[0150] In this example shown in Figures 9B and 9C, the doping concentration of the SiC substrate is approximately 10 19 ~about 10 20 cm -3 Because of the high concentration of n-type (i.e., n+) elements, electrical conductivity is high. When the epitaxial layer is deposited on a Si polar surface, the back side of the substrate is substantially C polar. Ohmic contacts to the C polar surface of the SiC substrate can be formed using Ti, Ti / Al, or nickel. Nickel silicide is formed when a portion of the Ni and Si deposited from the SiC surface region reacts with the Ni x Si 1-x This can be formed by high-temperature annealing. In some cases, high-temperature processing may cause carbonization of the SiC surface, which is unfavorable for creating ohmic contacts. In one example, a thin Si-based layer (approximately 1-3 nm) can be deposited on the SiC surface, after which Ni can be deposited. This prevents Si loss from the SiC surface, and Ni x Si 1-x It promotes formation. That is, the n+SiC / Si / Ni stack is n+SiC / Ni × Si 1-x The deposition can be heat-treated to form Ni. Alternatively, Ni and / or Si can be deposited in situ by heating. The Schottky barrier potential φ exceeds that possible with simple metal-semiconductor junctions. SB To increase this, it is further possible to insert an intermediate layer (e.g., intermediate layer 170 in Figure 8A or Figure 8B) as further described herein.

[0151] Figure 10 shows the breakdown voltage V of β-Ga2O3. br The selected thickness L ドリフト Plot 3000 shows the function of n-type doping concentrations at 0.3, 1, 3, 10, and 30 μm. For a given slab thickness, the yield voltage decreases as the doping density increases, and the inflection points 3005, 3010, 3015, 3020, and 3025 are (L ドリフト ,V br ,N d This shows the optimal selection of L. ドリフトWhen selecting the optimal configuration of =3μm, V br =1.2kV is possible N d = 5 × 10 16 cm -3 It will become.

[0152] Generally speaking, the on-resistance of a vertical multilayer semiconductor device under forward bias is mainly N d It is determined by the breakdown voltage V br is, N d This is determined by the thickness of the drift region under reverse bias.

[0153] Figure 11A is a plot of experimental work functions (shown on the x-axis) for various high work function metals preferred for forming Schottky barrier junctions into ultrawide bandgap semiconductor oxide materials, as determined in this disclosure. The energy selection of the work function of the metals is plotted on the left y-axis, with Cu having the lowest value and osmium having the highest. Vacuum energy E vac If we define E as zero, the work function energy WF of the metal is understood to have a value WF < 0. vac The electron affinity X of the conduction band edge of a given semiconductor with respect to A This can be used to compare metal-semiconductor absolute energy alignment. Figure 11A shows the ideal Schottky barrier height (φ) for various metals on a metal / β-Ga2O3(-2O1) oriented clean surface. SB ) are plotted on the right y-axis as white circular data points. Selenium (Se) and osmium (Os) are at their highest φ SB It provides approximately 1.4 eV. In practice, all the metals listed in this figure can be used to form Schottky barrier diodes, with Ni, Pt, and Pd being particularly stable.

[0154] The unique feature described in this disclosure is the β-Ga2O3(-201) oriented surface. As described below, this surface can be advantageously modified so that the surface depletion charge is engineered to produce an improved Schottky barrier diode. By depleting the n-type doped β-Ga2O3(-201) surface to a small depth, relative φ for all metals is achieved, as shown by the rhombic data points. SB A significant increase in can be achieved. By carefully examining Figure 11A, it can be seen that Cu metal / depleted β-Ga2O3(-201) has a similar φ as Ir metal / clean β-Ga2O3(-201). SB It can be seen that this can be achieved. Clean surfaces and depletion surfaces are described later in this disclosure. Using any of the metals in Figure 11A, an oxide layer can be formed between the Schottky metal contact layer and the drift layer, as described further herein. For example, the Schottky metal may include platinum, the drift layer may include Ga2O3 (or a different epitaxial oxide as described herein), and an intermediate layer containing PtO2 can be formed between the Schottky metal contact layer and the drift layer. The metal oxide of the intermediate layer (e.g., PtO2, or a metal oxide containing any of the metals in Figure 11A) can be deposited as an oxide (e.g., using MBE, ALD, MOCVD, or another epitaxial or non-epitaxial growth method) or as a metal that is subsequently oxidized to form a metal oxide.

[0155] Figures 11B and 11C show various doping concentrations N ドリフト The forward bias current-voltage (IV) behavior of a diode formed using Schottky barrier metal (SBM)=Ni deposited on the depletion surface of a β-Ga2O3(-201)n-type drift layer having a thickness of 2 μm, as shown in Figures 9B and 9C, is plotted. This structure is deposited on a Si polar 4H-SiC n-type substrate. Referring to Figure 11B at room temperature T=25C, the semi-logarithmic IV plot is approximately V F The forward bias voltage V is used until it turns on at =1V. F It shows an increasing subthreshold current along with φ.SB Thermionic emission (TE) transport of electrons across the voltage is performed under the applied forward bias voltage V F Forward conduction current density J TE Determine the value and follow the formula below.

[0156]

number

[0157] In the formula, the Richardson constant is

[0158]

number

[0159] It can be explicitly calculated as follows:

[0160]

number

[0161] is the effective electron mass, n is the ideal constant, q is the electron charge, k B is the Boltzmann constant. Therefore, in the case of conduction determined by TE, a strong temperature dependence is expected. In the example shown in Figures 11B to 11C, which includes Ni / clean β-Ga2O3, the effective electron mass of the drift layer is

[0162]

number

[0163] And as a result, A * = 36A / cm² 2 This is obtained. In practice, the ideal factor n can be extracted from a manufactured diode and fitted to the subthreshold slope 4005 in Figure 11B using Equation 1 above. The ideal factor ranges from 1 ≤ n ≤ 3, and in some cases, 1 ≤ n ≤ 2, etc., and N ドリフト It depends on.

[0164] Figure 11C shows a linear IV plot of the example in Figure 11B, where the on-resistance is 4010 (dI / dV) of the turn-on voltage. -1 As shown by the differential resistance after, n-type doping N ドリフト It decreases as increases.

[0165] Figure 12 is an energy band diagram 5000 of a simulation of the conduction band edge of a vertical multilayer semiconductor device having configuration 5050, which includes a substrate layer of SiC(0001) (i.e., SiC with (0001) orientation), a TL of n+β-Ga2O3(-201), a drift layer formed from β-Ga2O3(-201) (i.e., β-phase Ga2O3 with (-201) orientation), and a metal layer formed of Ni(111) (i.e., Ni with (111) orientation). In this example, the Schottky potential barrier has a value of approximately 1.15 eV, and the doping of the drift layer is 1 × 10⁻¹⁶ as shown by the five curves plotted in the energy band diagram 5000. 15 ≤N ドリフト ≤ 5 × 10 17 cm -3 It fluctuates within the range of N. The width of the depletion layer is as shown N ドリフト It is strongly controlled by, and as a result, N ドリフト = 5 × 10 17 cm -3 A quantum mechanically thin barrier (curve 5010) is obtained, and carrier transport is a combination of TE and quantum mechanical tunneling. That is, barrier J tot The total current density across the curve is the thermionic current J, which has two components: temperature and peak energy barrier dependence. TE And the quantum mechanical tunneling component J tun It has and as a result, J tot =J TE +J tun It becomes N ドリフト → 1 × 10 15 cm -3 If the value of is low, the width of the depletion barrier decreases, J tun →0. Conversely, quantum tunneling through potential barriers becomes particularly important for designing high-voltage reverse-biased operation.

[0166] Figure 13 is the energy band figure 6000 of a simulation of the conduction band edge of a vertical multilayer semiconductor device having configuration 6050, which is similar to that shown in Figure 12 except that it includes an additional intermediate layer (IL) with a thickness of 100 angstroms and formed of single-crystal MgO(111) (i.e., MgO in the (111) orientation). The simulation shows that in this example, the inclusion of the intermediate layer increases the Schottky potential barrier to a value of approximately 3.1 eV. Of particular interest is MgO, which exhibits a small electron affinity compared to Ga2O3 and SiC. As expected, drift layer doping is 1 × 10⁻⁶ 15 ≤N ドリフト ≤ 5 × 10 17 cm -3 While the width of the depletion layer is strongly controlled when it fluctuates between these two extremes, unlike the device in Figure 12, the IL presents a fixed quantum mechanical tunnel barrier for electron transport. The increased barrier potential of the device in Figure 13 can further be used to adjust the diode's turn-on voltage (or threshold voltage). For example, selecting an IL oxide with a large bandgap and low electron affinity results in a large SB potential, which, when used, allows for the engineering design of the diode's turn-on voltage. This is particularly advantageous for creating high-voltage diodes that are less susceptible to low-voltage noise. A large barrier potential is also advantageous for reducing reverse leakage current at high reverse electrical biases and high electric fields.

[0167] The intermediate layer 170 may include an epitaxial semiconductor oxide material formed on the epitaxial drift layer. In some cases, the intermediate layer 170 includes an epitaxial oxide material, and the structure further includes an epitaxial metal layer (e.g., metal layer 130 in Figure 8B) formed on the epitaxial intermediate layer 170. The intermediate layer 170 may include any of the oxide materials described herein, for example, any of the compositions of materials 1 to 7. The intermediate layer 170 may include a single semiconductor oxide composition, or more sublayers having different semiconductor oxide compositions, which can be selected from materials 1 to 7 (e.g., the sublayers may form a two-layer, multilayer, superlattice, or chirp layer). In some cases, the intermediate layer 170 may include a gradient composition (e.g., a linear, stepwise, or chirp composition gradient) containing one or more of materials 1 to 7. In some cases, the intermediate layer 170 contains one or more of materials 1 to 7 that are doped with a single dopant concentration or with dopant concentrations that vary with depth in the intermediate layer 170.

[0168] In some examples, the intermediate layer (for example, the intermediate layer 170 in Figure 8A or Figure 8B) may be formed from or include a material selected from one or more of the following materials: • Epitaxial single crystal, polycrystalline, or amorphous Al2O3 • Epitaxial single crystal, polycrystalline, or amorphous NiO · Epitaxial β-(Al x Ga 1-x )2O3(0≦x≦0.3) (See Figure 8) • Epitaxial α-(Al x Ga 1-x )2O3(0≦x≦1)(See Figure 7) • Epitaxial (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (0≦x,y,z≦1) • Epitaxial Zn x Ga y Oz (0≦x,y,z≦1) ·Epitaxial Zn x Al y O z (0≦x,y,z≦1) ·Epitaxial Mg x Ga y O z (0≦x,y,z≦1) ·Epitaxial Mg x Al y O z (0≦x,y,z≦1) ·Epitaxial Ni x Ga y O z (0≦x,y,z≦1) ·Epitaxial Ni x Al y O z (0≦x,y,z≦1) ·Epitaxial (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (0<x<1 and 0<y<1) ·Epitaxial (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (0≦x,y,z≦1).

[0169] In some examples, the drift layer may be made with the same composition as the intermediate layer, but may have a different doping concentration. In some examples, the drift layer may be made with a different composition from the intermediate layer, and may have a different doping concentration.

[0170] Other crystal plane orientations of SiC (e.g., 4H-SiC in particular) can also be favorably used for the epitaxial growth of other oxide compositions and polytopes for the devices, structures, and methods described herein. For example, A-plane, R-plane, and M-plane 4H-SiC substrates can be prepared from bulk-grown single-crystal materials by preferentially dicing along specific crystal planes, followed by chemical mechanical polishing (CMP) to form epitaxy-ready surfaces. Furthermore, some examples may involve epitaxially depositing alpha-phase Ga2O3 films on the aforementioned fine-graded SiC substrate surfaces. The ability to form α-Ga2O3 provides at least two improvements applicable to this disclosure. Firstly, at room temperature, α-Ga2O3 has a larger fundamental bandgap energy (E) than β-Ga2O3, which can improve the performance of diodes by favorably increasing the possible critical electric field. g (αGa2O3)=5.4eV>E g (βGa2O3) = 4.7 eV) is observed. Secondly, α-Ga2O3 grown on the A, R, and M planes exhibits E g All alloys in the range 0≦x≦1, including (αAl2O3)=8.6eV, are α(Al x Ga 1-x As is possible with 2O3, alloying with Al allows for the realization of a complete alloy range. Such a wide bandgap engineering range for creating heterojunctions dramatically improves the performance of possible diodes (and other devices such as p / n junction diodes, transistors, switches, varactors, or light-emitting devices) compared to conventional devices.

[0171] Figures 14 and 15 show examples of other vertical multilayer semiconductor device configurations including an intermediate layer according to the present disclosure. Figure 14 shows a SiC substrate oriented in the A-plane, R-plane, or M-plane, an α-Ga2O3 drift layer, and an α-(Al x Ga 1-x An example of structure 7000 is shown, which includes an α-(Al)2O3 intermediate layer (with 0≦x≦1) and a metal layer forming a Schottky barrier. The intermediate layer has an α-(Al)2O3 intermediate layer with a growth direction-dependent alloy content x(z). x Ga 1-x)2O3 gradient alloys are also possible. Figure 15 shows a SiC substrate oriented in the C plane, a β-Ga2O3 drift layer, and β-(Al x Ga 1-x An example of structure 8000 is shown, which includes a β-Ga2O3 intermediate layer (with 0 ≤ x ≤ 0.3) and a metal layer forming a Schottky barrier. In practice, the maximum Al content that can maintain the single-crystal beta phase is x ~ 0.3, or in some cases x = 0.4, which is a heterojunction to x = 0, i.e., β-Ga2O3 / β-(Al x Ga 1-x This represents the maximum band gap that can be implemented as 2O3.

[0172] Figures 16 and 17 are simulation energy band diagrams of two exemplary vertical multilayer semiconductor device configurations having intermediate layer (IL) thicknesses of approximately 50 angstroms and 150 angstroms, respectively. Both devices include a 4H-SiC substrate, a Ga2O3 drift layer, an MgO intermediate layer, and a Ni metal layer. Drift layer doping is shown by five curves plotted in energy band diagrams 9000 and 10000, resulting in a 1 × 10⁻¹⁶ energy band. 15 ≤N ドリフト ≤ 5 × 10 17 cm -3 It varies within the range. In some examples, the thickness of the interlayer may be configured to control the quantum mechanical tunneling current, for example, under a reverse bias near the reverse breakdown voltage. In some examples, the thickness of the interlayer may be configured to mitigate the decrease in Schottky barrier height resulting from metal-induced gap states at the metal-interlayer interface. In these examples in Figures 16 and 17, the IL is selected as UWBG MgO and shows the band curvature of the conduction band edge with various drift region dopings for two examples of MgO thickness (50 angstroms in Figure 16 and 150 angstroms in Figure 17). Figure 16 represents a thin quantum mechanical tunneling barrier, while the thicker barrier in Figure 17 reduces or blocks quantum mechanical tunneling. This design option is advantageous for managing reverse leakage at high voltages and electric fields.

[0173] Figure 18 shows a simplified example of a typical current-voltage characteristic curve 11000 for a vertical multilayer semiconductor device according to this disclosure. Under reverse bias, voltage breakdown (V br The previous leakage current region itself consists of the following three regions, namely, • A thermionic emission region ("thermionic emission region") that occurs in low to medium electric fields, where the current originates from charge carriers with sufficient energy to overcome the potential barrier, • A combined region of quantum tunneling and thermionic emission ("tunneling & thermionic emission combined region") that occurs in a medium electric field, wherein the current arises from a combination of charge carriers having sufficient energy to overcome the potential barrier (i.e., thermionic emission) and charge carriers passing through the potential barrier by tunneling effect, and the combined region of quantum tunneling and thermionic emission. This includes quantum tunneling regions ("QM tunneling regions") that occur in high electric fields, where the current originates from charge carriers that pass through a potential barrier via the tunneling effect.

[0174] In conventional devices, the actual reverse bias breakdown voltage (V br The yield strength in the drift region is determined not only by the device structure, the specific material properties used, and the possible AC leakage paths when exposed to extreme electric fields.

[0175] For example, a simple metal-semiconductor Schottky barrier presents only a potential with limited quantum mechanical barrier height and asymmetric width. In some cases, due to tunneling current, devices with Schottky barrier junctions in extremely high electric fields may exhibit a lower-than-expected reverse breakdown voltage due to barrier drop effects (BLE).

[0176] Furthermore, the breakdown voltage field value and the low, medium, and high field values ​​in Figure 18 can vary depending on the materials and device structure used. For example, the low field can be less than 100 V / cm or less than 1000 V / cm, the medium field can be between 100 V / cm and 1000 V / cm or between 1000 V / cm and 10,000 V / cm, and the high field can be greater than 1000 V / cm or greater than 10,000 V / cm.

[0177] The reverse bias current is generated by thermionic electrons J as follows: TE Current components and quantum mechanical tunneling J tun Includes superposition with current components:

[0178]

number

[0179] In the equation, T(E) is the quantum mechanical (QM) transmission probability as a function of the incident electron energy with respect to the potential barrier, and E f This is the Fermi energy reference of the conduction band energy. Upper and lower bounds of the integral.

[0180]

number

[0181] This ranges from the injection of incident quasi-ballistic electrons into the structure. Figures 19A and 19B show the Fermi level (E F Plots 12000 and 12100, respectively, of the QM tunneling current transmission coefficient / probability T(E) as a function of the injected electron energy for (=0). Insets 12001 and 12101 show the respective energy barriers within the conduction band edge and the electrons passing through each barrier by tunneling effect in these examples. The curves are calculated using the finite element method for piecewise approximations of the spatial potential coupled to the complex transfer matrix for each subdomain, considering the real and imaginary parts of the reflected and transmitted wave functions. Figure 19A shows N ドリフト = 5e16cm-3 In this case, the band structure shown in Figure 9C corresponds to T(E) 12010, showing significant SB penetration below the potential barrier maximum (indicated by arrow 12015), and approaching 1 above this barrier. Note that even for incident energies above the potential maximum, T(E) < 1. The triangular potential represents an asymmetric barrier that suppresses QM interference between the reflected electron wavefunction and the transmitted electron wavefunction. Arrow 12015 corresponds to the height of the Schottky barrier in this example.

[0182] Introducing a wider bandgap IL between the Schottky metal and the Ga2O3 drift layer can be used to effectively increase the potential barrier of the rectifying contact. In Figure 19B, the IL provides a maximum potential barrier of 3.0 eV. A MgO with an electron affinity of (MgO) = -1.0 eV (Eg = 7.8 eV) is selected. While doping of the drift layer has a slight effect on the T(E) characteristics, the thickness of the MgO layer has a dramatic effect on the vibrational behavior observed in Figure 19B. The "soft turn-on" T(E) curve 12110 is affected by the thin MgO layer L IL This is for the case where (MgO)=5nm, and the sharp "turn-on" and narrow resonance T(E) curve 12120 is for thicker L IL This is the case where (MgO) = 10 nm. Referring again to equation (2), we can use T(E) to calculate the reverse leakage current with respect to the surface electric field. The introduction of UWBG IL significantly reduces the reverse leakage current, which is advantageous for applications to high-voltage diodes, for example, by increasing the forward-reverse (on-off) ratio.

[0183] Furthermore, a further example of an IL containing a ZnGa2O4(111) oriented layer is: Ni metal / IL = ZnGa2O4NID10nm / Ge:β-Ga2O35e16cm -3 / TL=Ge:β-Ga2O31e17cm -3 / 1e19cm -3The IL is inserted into a device on a 4H-SiC Si polar substrate, as shown in Figures 19C and 19D. Figure 19C shows a band diagram along the growth direction z, and Figure 19D shows a magnified view of the conduction band near the Schottky barrier (at z=0nm). The IL effectively increases the Schottky barrier potential, which directly affects the performance of the diode, as shown in Figures 19E and 19F. The semi-logarithmic forward bias IV curve plot in Figure 19E shows the shift to a higher voltage in the subthreshold slope for the metal-intermediate-substrate structure (MIS) (IL=Zn2Ga2O4) compared to the Ni / β-Ga2O3 diode (MS curve) in the case of a clean and depleted β-Ga2O3(-201) surface. The plot in Figure 19F shows a linear IV forward bias comparison for the three cases from Figure 19E. The introduction of the IL also has the effect of increasing the impedance of the device in conduction mode.

[0184] Including an intermediate layer in various embodiments brings about many advantages, including the following: • When the band gap of the intermediate layer is larger than the band gap of the drift region, it has the advantage of improving the turn-on voltage to a higher value; • The advantage of reducing the Schottky potential barrier height from its theoretical expected value is the reduction in the occurrence rate of defects and / or metal-induced gap states (MIGS) between the metal layer and the drift layer. While MIGS may exist between the intermediate layer and the metal layer, their effect on the barrier height is reduced because this interface is separated from the semiconductor / metal Schottky junction interface. • The advantage of increasing the reverse breakdown voltage through both thermionic emission and quantum tunneling; and • A wider bandgap interlayer offers the advantage of spatially separating the metal-induced gap state (MIGS) from the active semiconductor oxide material on the surface of the drift region, which helps maintain the Schottky barrier potential and reduce reverse leakage current.

[0185] The devices and methods of this disclosure utilize the unique insight that by configuring the intermediate layer to present further limitations on the tunnel current, the performance in the high-field region can be improved under reverse bias, and as a result, the reverse breakdown voltage of the device can be further improved.

[0186] In any of the examples described herein, the intermediate layer may include repeating properties. These repeating properties may be repeating compositional variations (e.g., in a superlattice structure) or repeating doping concentration variations (e.g., in the concentration of exogenous dopant species or in the concentration of defects or vacancies within the crystal layer).

[0187] Figure 20 is a schematic cross-sectional view of a vertical multilayer semiconductor device 14000, where the repeatability of the intermediate layer (IL) 1450 or the transition layer (TL) 1460 is achieved by forming the IL and / or TL as a superlattice or multilayer epitaxial stack. The substrate 1400 is SiC, such as 4H polytope. The substrate may have specific micro-inclined surface orientations, i.e., C-plane, A-plane, R-plane, or M-plane, as known in the literature. The micro-inclined planes may be axial or intentionally mis-cut toward a specific crystal plane. For example, the mis-cut angle of the C-plane may range from 0 to 6 degrees. The transition layer 1460 may be a semiconducting oxide, a non-oxide, or a combination thereof. For example, the transition layer 1460 may be silicon germanium carbide (Si) which allows for in-plane lattice constant and strain adjustment to match the drift region composition. x Ge y C 1-x-y ) may include. Other optional TL and IL compositions may include polar or nonpolar semiconductors. For example, nitrogen-polar or metallic-polar aluminum nitride (AlN) may be formed.

[0188] In the example in Figure 20, the superlattice within at least a portion of the IL (or TL) is formed from two repeating sublayers 14010 and 14020 (or sublayers 14030 and 14040 of the TL) with varying thicknesses that cross the intermediate layer. In another example, the superlattice may form a digital alloy. In yet another example, the superlattice may be formed from three or more repeating sublayers of either constant or varying thickness. In various examples, the superlattice may be periodic or aperiodic.

[0189] By using A-face, R-face and M-face 4H-SiC, an alpha phase α-(Al) having space group R3c is obtained. x Ga 1-x This enables epitaxial and selective growth of α-(Al x Ga 1-x Epitaxial growth of )2O3 is possible over the entire alloy range 0 ≤ x ≤ 1. Therefore, TL or IL is α-(Al x Ga 1-x )2O3 / α-(Al y Ga 1-y ) may include a superlattice of 2O3 (0≦x≦1 and 0≦y≦1, x≠y). This allows the band gap to be adjusted from 4.7eV (x=0) to 8.6eV (x=1) while imposing a conduction band discontinuity of about 4eV on the electron confinement and transport design. (Al x Ga 1-x )2O3 / α-(Al y Ga 1-y Biaxial strain occurs at heterointerfaces due to lattice constant mismatches between 2O3 layers, but this can be controlled by selecting appropriate layer thicknesses.

[0190] Figure 21A is a simplified energy band diagram 15000 of a vertical multilayer semiconductor device having a structure similar to structure 14000 in Figure 20, and including an intermediate layer formed of a finite-periodic superlattice with sublayers of ZnGa2O4(111) and β-Ga2O3(-201). Other numbers of layers and / or other combinations of superlattice materials are also possible. The complete conduction and valence energy band diagram 15000 shows the step-like potential barrier (φ) arising from the superlattice structure of the intermediate layer and the Ga2O3 drift layer. S Figure 21B shows the effective φ. S = 2.25eV and N ドリフト = 5e16cm -3 An expanded energy band diagram 15020 near the metal / SL IL / drift layer is shown. In one example, the superlattice structure is configured such that the quantum mechanical tunneling transmission coefficient decreases as the equivalent potential barrier increases, and thermionic emission onset is tuned to a higher turn-on voltage. The high-temperature performance of the device can also be improved by increasing the effective barrier potential energy. Moreover, as mentioned above, the leakage current associated with quantum tunneling through the potential barrier under reverse bias can be reduced by using such a structure and increasing the effective barrier potential energy.

[0191] In practice, Schottky barriers and UWBG intermediate layers can be realized in the devices, structures, and methods described herein, but a phenomenological potential barrier reduction effect (BLE) exists under the influence of high electric fields. In particular, BLE correlates with both the bandgap energy and dielectric constant of the specific material used. Figure 21C shows the bandgap E g (The distance between the dashed lines) is included, and further sandwiched between the two metals 15031 and 15033, the zero-bias (V=0) potential barrier is heterojunction φ B Formed to a thickness L IL A schematic diagram of the energy diagram 15030 of a semiconductor slab (oxide 15032) having the structure is shown. The metal-oxide-metal (MOM) structure changes the band diagram when a bias is applied, as shown by the electric field ε. z=V / IL is generated, and the rectangular barrier (V=0) becomes a distorted parallelogram 15035 (for example, with some band curvature) (V<0).

[0192] Electrons injected from the metal electrode on the left into the oxide layer induce equal but opposite positive image charges within the metal. When electrons are injected into the oxide at a distance z>0, a Coulomb image force F arises between charges separated by a distance of 2z. im The following applies:

[0193]

number

[0194] Next, the electrostatic potential V is given by the following: im Generate (z).

[0195]

number

[0196] Clearly, the MOM oxide barrier space potential under bias is composed of (i) a rectangular barrier potential, (ii) a linear electric field, and (iii) an image potential, as follows:

[0197]

number

[0198] Figure 22 shows the ideal Ni / 1e16cm -3 Ga2O3 / n + Ga2O3 / n + The enantiomer band curvature of an example Schottky barrier, including a 4H-SiC device, is shown. Figure 23 shows a magnified view of the band curvature near the potential peak. For UWBG oxides, sensitivity analysis is performed using BLE, where φ is available. B This indicates that it is relatively smaller compared to [another value].

[0199] BLE is a quantity ΔE that can be quantitatively expressed in relation to the high frequency (optical) permittivity and the applied electric field. バリア Only the peak barrier potential φ B This is the cause of the reduction.

[0200] Condition dV 酸化物 / dz=0 yields the maximum value, away from the heterointerface.

[0201]

number

[0202] It is located as follows:

[0203]

number

[0204] Figure 22 shows that an example of a metal Schottky barrier device includes BLE. In this example, N ドリフト = 1e16cm -3 φ B This is the case for a Schottky barrier metal (SBM) with a voltage of 1.3 eV. n + β - Ga₂O₃(-2O₁) 1e₁ₙcm -3 The transition layer is nitrogen-doped n+1e18cm -3 The material is deposited on a 4H-SiC substrate. Band diagrams for zero bias (0V) and reverse bias (4V and 8V) are plotted showing the change in depletion width. Figure 23 shows a magnified view of the conduction band of Figure 22 near the Schottky barrier peak for a series of applied reverse bias voltages and the resulting surface electric field. Band drop effects and band bending are shown.

[0205] Figure 24 shows the surface electric field E Fz The effective barrier height reduction energy ΔE is a function of バリア (Curve 15110 and the y-axis on the right) and the effective barrier width W バリアPlot the extracted values ​​(curve 15120 and the left y-axis). E Fz When = 0 MV / cm, the built-in electric field is approximately 52 kV / cm due to the depletion field.

[0206] Referring again to Equation 2, the tunneling current also depends on temperature and the transmission coefficient of electrons passing through the barrier as a function of the surface electric field (see Figure 23).

[0207] Figures 25 and 26 show (i) Ni SBM / 5e16cm in Figure 25. -3 Ga2O3 / n+4H-SiC and (ii) Ni SBM / 5nm MgO IL / 5e16cm in Figure 26 -3 The quantum mechanical transmission coefficients of two device configurations, Ga2O3 / n+4H-SiC and the device shown in Figure 26, incorporate a 5nm UWBG MgO intermediate layer. The transmission coefficient T(E) is calculated. e ,E Fz ) is the incident electron energy E relative to the Fermi energy. e Depends on (E フェルミ (is considered to be zero), the potential profile is the surface electric field E Fz It depends on the tunnel current integral, which ranges from 0 to the maximum potential energy shown in Figure 23. e This is performed over a certain period, resulting in the curves shown in Figures 27 and 28.

[0208] Figures 27 and 28 show the total current (J) for each of the two device structures in Figures 25 and 26. tot Thermionic current (J) therm ) and tunnel current (J tun Plot the calculated contribution of ). Three exemplary operating temperatures, namely T s The values ​​of 300K, 400K, and 500K are shown, representing the operating temperatures discussed above for the thermal performance of oxide / SiC hybrid devices.

[0209] The detailed examination of the curve shown in Figure 27 is due to the low surface electric field E zFor ≤0.5 MV / cm, we show that the reverse leakage current of a Schottky barrier diode is mainly determined by the thermionic current component. This critical surface field E z Above >0.5 MV / cm, temperature-dependent tunneling current dominates, effectively overwhelming the contribution from thermionic emission. This demonstrates the importance of heterojunction Schottky barrier design in managing and limiting reverse leakage current in high surface field regimes.

[0210] Figure 28 shows an analogy plot of the calculated reverse leakage current for a diode structure in which a UWBG 5nm MgO interlayer is intentionally incorporated between the Schottky metal and the Ga2O3 drift region. Examination of the curve in Figure 28 shows a decrease in the critical surface electric field, Ez ≤ 0.25 MV / cm, dominated by thermionic emission and tunneling components. However, the absolute reverse leakage currents for both thermionic and tunneling components are dramatically reduced compared to the case in Figure 27 where the IL is absent. Thus, this disclosure shows that the UWBG interlayer may be advantageous in improving the reverse leakage performance of the Schottky barrier diodes disclosed herein.

[0211] First-principles calculations and experimental data show that the band gap E of non-oxide and oxide materials g Static dielectric constant (low frequency) for [the specified value]

[0212]

number

[0213] and (high frequency) photodielectric constant

[0214]

number

[0215] The following trend is obtained. Density functional theory was used to simulate the energy band structure and dielectric dispersion of various crystal structures. In Figure 29A, the selection of oxide materials is plotted, and the dielectric constant generally corresponds to the band gap energy Eg This shows that it decreases (reduces) as the static permittivity ε increases. 静的 and photoelectric dielectric constant ε 光 These exhibit similar trends but have different bowing characteristics, as shown.

[0216] Figure 29B shows the results for three cases where an electric field is applied across a 5 μm thick slab containing a selected oxide semiconductor. g ΔE for バリア This shows the expected variation. The barrier degradation is observed to be higher as the band gap increases, partly due to dynamic screening which decreases with increasing band gap. Furthermore, because the time associated with electrons passing through the barrier is very short, the high-frequency (optical) dielectric constant should be used for screening models related to barrier degradation. High surface electric fields can be adapted using an intermediate layer, as described for applications to high-voltage rectifiers.

[0217] Figure 29C discloses further trends available for the advantageous incorporation of intermediate oxide materials into diode structures. Given the interface quality S of the surface state int The figure of merit of the (interface state parameters) can also be estimated in relation to the trend of the dielectric constant. For clarity, it is defined as follows:

[0218]

number

[0219] In the formula, 0≦S int ≤ 1, and S int =1 represents an ideal surface with a surface density of states of 0, S int =0 represents an infinite surface density of states. Also, if an empirical fit for the induced gap state is estimated, the minimum surface density of states

[0220]

number

[0221] It can become this, and is also related to the dielectric constant by the following equation.

[0222]

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[0223] During the ceremony,

[0224]

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[0225] Therefore, a normal dipole exists across at least one unit cell δ of the material, and in the case of MgO, δ is approximately 0.43 nm.

[0226] Referring again to both Figures 19C and 21A, heterostructure designs incorporating an intermediate layer (e.g., MgO, or other material(s)) between the metal and Ga2O3 allow for a reduction in surface density of states while maintaining the high barrier potential required for forward bias rectification and low reverse leakage current.

[0227] In another example, the repeatability of an intermediate or drift layer is achieved by introducing repeated spatial modulation of the doping concentration as a function of the growth direction ("z"). For example, the intermediate or drift layer may have a single material composition, and the conduction band potential may be modulated using repeated spatial modulation of the doping concentration. In one example, the spatial extent of the doping region is very small, and it has a very high doping concentration. In another example, the doping region extends over more than one unit cell of the host composition, but is less than about 10 nm. In yet another example, the doping region is

[0228]

number

[0229] It has an extremely high doping concentration of orders of magnitude. In yet another example, the doped region is called a delta doping region, and the thickness of the doped area is about 10-20 nm or less. In some cases, the thickness of the doped region is about one monolayer or more of the host material composition. For very thin doped region thicknesses, an equivalent two-dimensional doping density

[0230]

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[0231] As shown in the following equation, bulk-like

[0232]

number

[0233] It can be stipulated in relation to this.

[0234]

number

[0235] In other words,

[0236]

number

[0237] area density

[0238]

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[0239] It is equivalent to this. In one example, repeated spatial modulation of doping concentration can result in a homoepitaxial superlattice-type structure similar to the superlattice described above, except that the sublayers have a constant composition but different doping concentrations, instead of having sublayers with different compositions.

[0240] In another example, the repeatability of the intermediate layer includes both repeated spatial modulation of the doping concentration and repeated changes in the composition of the intermediate layer.

[0241] Figure 30 shows an example of a homoepitaxial delta-doped superlattice (δ-SL) forming the drift region of Schottky barrier diode 16000. Nickel metal forms SB ("SB metal") in the delta-doped SL drift region ("δ-doped SL") formed by using a shallow dopant of either Sn, Ge, or Si in the host β-Ga2O3 composition (i.e., Ga2O3 is used throughout the drift region). Plot 16100 shows the overall structure, sheet density doping of two different periods of the periodic [δ-doped Ga2O3 / NID Ga2O3] superlattice (δ-SL) extending over 2 μm, forming a drift layer of Ni / δ-doped SL drift / n+TL / n+4H-SiC.

[0242]

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[0243] This is shown. The high work function Ni metal maximizes the SB potential by being in direct contact with the first NID Ga2O3 layer of the δ-SL. As an example, two δ-SL periods are selected and the conduction band diagram is plotted as a function of the growth direction. Plot 16100 is

[0244]

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[0245] The first δ-SL16110, which includes a 19x period,

[0246]

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[0247] The curves shown represent the second δ-SL16120, which includes a 4x period. The ratio of the SL doping region is defined as follows: γ=L(NID) / L(δ doping) As a result, the first and second δ-SLs have γ1=20 and γ2=80, respectively.

[0248] The band structure also behaves as a Schottky barrier diode, with δ-SL being the first and second δ-SL respectively.

[0249]

number

[0250] and 1.3e16cm -3 It has an effective bulk doping density. Compared to continuous co-doping growth of Ga2O3, the advantage of using a periodic delta-doping method in the drift region to achieve an effective bulk-like n-type doping level is that higher epitaxial material quality is possible. Generally, 1e17cm -3 Higher-level n-type impurity doping within the above range results in a relative decrease in crystallinity during co-doped epitaxial growth. Furthermore, reactive oxygen species may interact with Si, Ge, or Sn doping sources in the growth reactor, potentially forming undesirable byproducts. Periodic and short doping bursts during epitaxial growth allow for the confinement of dopants within small layers, and subsequent NID material growth also tends to repair any crystal strain by incorporating impurity atoms into the Ga2O3 crystal lattice. This method of periodic doping further improves the crystallinity of the doped drift region, which is effective for coating thick drift regions of 5 microns or more.

[0251] Figure 31 shows the target using δ-SL.

[0252]

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[0253] This shows the possible design space to achieve this, at three different 2D sheet doping densities, i.e.,

[0254]

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[0255] An exemplary configuration using individual delta-doping layers L(δ-doping) with lengths of 5 nm can be interpolated between the sheet doping densities and the curves.

[0256] Figures 32A and 32B are shown below.

[0257]

number

[0258] Figure 30 shows the forward bias IV curves of Schottky barrier diodes incorporating two examples of the δ-SL drift region, with Figure 32A using a semi-logarithmic scale and Figure 32B using a linear scale. The subthreshold slopes are equivalent, but the differential resistance is as expected.

[0259]

number

[0260] That one is more expensive. In another example, an intermediate layer is formed containing at least one quantum well (QW) sublayer sandwiched between wider bandgap layers, the QW being formed by electron confinement by a potential well thus formed. The QW has at least one quantized discrete energy level within the narrow bandgap QW layer. In one example, the quantum well sublayer is configured such that a resonant tunneling current can only be generated in a specific bias configuration, i.e., the quantum well sublayer is configured to have a bias-dependent tunneling current. In one example, this can be used in a voltage-dependent switch to create a pulsed current or a bistable switch. Such a device may be a resonant tunneling diode having two electrical terminals and exhibiting a nonlinear IV response. The nonlinear IV response may have negative differential resistance properties, which can be advantageously used in switching or oscillating circuit configurations of electrical circuits.

[0261] In another example, this two-terminal switch can be used as part of a power converter to control the pulse width and duration of the current.

[0262] An example of a vertical conduction resonant tunneling diode is described below. The double barrier interlayer incorporating a single QW is further deposited on an n-type β-Ga2O3 drift layer on a SiC conductive substrate, and further deposited on a β-(Al 0.2 Ga 0.8 )2O3 / β-Ga2O3 / β-(Al 0.2 Ga 0.8 It is formed using a heterostructure of )2O3. β-(Al 0.2 Ga 0.8 The thickness of the 2O3 barrier is thin enough to allow electron tunneling, for example, L バリア =1~10nm, or along the growth direction (Al 0.2 Ga 0.8) is equal to a unit multiple of the 2O3 crystal unit cell (e.g., 1, 2, 3, 5, or 1-10). The thickness of the β-Ga2O3 layer containing QW can be selectively n-type doped or NID, and can have a thickness of about 1 monolayer to about 10 monolayers, where 1 monolayer is defined as half the unit crystal dimension along the epitaxial growth direction. β-Ga2O3

[0263]

number

[0264] and 4H-SiC

[0265]

number

[0266] Because the effective electron mass is relatively large in both (basically isotropic with respect to crystal momentum), quantum confinement occurs even in shallow potential wells within physically thin QW layers. As an example, consider a double heterostructure containing a thin QW: α-(Al x Ga 1-x )2O3 / QW α-Ga2O3 / α-(Al x Ga 1-x )2O3 / drift α-Ga2O3 is shown in Figures 33A and 33B with two electric field strengths applied to the structure along z, i.e.,

[0267]

number

[0268] The case is shown below. The thickness of the QW is selected as 1 nm to achieve only two quantum confinement states in the potential well, and the barrier composition x=1 gives the highest barrier potential. The wider the QW thickness, the more quantum confinement states are supported. Lowest energy quantum confinement electron space wavefunction profile

[0269]

number

[0270] These are plotted with respect to their quantized energy levels within the QW. The barrier states described above are also plotted to represent the propagation states. To achieve significant barrier penetration of the electron wavefunction, the barrier thickness can be as small as 1 nm or less. Such resonant tunneling structures require precise epitaxial growth to precisely control the layer thickness and enable resonance.

[0271] The advantage of the devices and structures described herein lies in the fact that the thermal conductivity of SiC is approximately two orders of magnitude greater than that of Ga2O3, which favorably allows heat generated within the oxide drift layer to conduct rapidly through the SiC substrate until it is completely dissipated from the device. The self-heating effect in conventional all-Ga2O3 power devices utilizing thick β-Ga2O3 substrates presents one of the most challenging problems for practical application in high power density technology. In contrast to all-SiC devices using thick SiC substrates, the Ga2O3 substrates in conventional devices exhibit low thermal conductivity, requiring other forms of thermal management, such as substrate thinning and integration with diamond heat spreaders. This disclosure describes devices, structures, and methods that simultaneously improve the electrical performance of devices utilizing UWBG oxide materials by integrating with a SiC substrate with extremely high thermal conductance and low electrical resistance. In other words, a simultaneous solution for the electrical and thermal performance of the device becomes possible. This represents a significant improvement in the overall performance of the device compared to β-Ga2O3 substrates with thermal insulation and electrical conductivity.

[0272] Furthermore, a further advantage of the hybrid integration of semiconducting oxide-SiC materials when forming Schottky barrier diodes, as described in this disclosure, is the improved electrostatic field distribution within the device.

[0273] Figure 34 shows a plot of simulated field lines 915 (and associated potential lines 910) for a vertical multilayer semiconductor device, which is similar in configuration to device 100 shown in Figure 1, but includes a separation layer 180 surrounding a metal layer 130 that functions to reduce surface current and manage the electrostatic vector field. The field lines 915 and equipotential lines 910 shown in Figure 34 represent the expected potential differences between the conductive substrate 110 and the metal layer 130 in the range of approximately 100 V to approximately 10,000 V.

[0274] In this example, the Ni metal patterned contact (metal layer 130) is located on a β-Ga2O3 drift layer 120, which is placed on a conductive 4H-SiC substrate 110. The isolation layer 180 is selected from low dielectric constant compositions, for example, Al2O3. The device is surrounded by vacuum or air. The contact (metal layer 130) is forced to a positive potential (+V), and the conductive substrate 110 is forced to a negative potential (-V).

[0275] As can be seen from the inspection, the electric field line 915 is directed from the surface boundary of the rectangular contact toward the conductive substrate surface 110, forming an equipotential line between the metal layer 130 and the substrate 110. Plot 900 shows a high concentration of electric field within the region of the isolation layer 180 and drift layer 120 near the corner of the metal layer 130. As can be understood, in certain circumstances, the electric field strength |ε x,y,z The field can concentrate to such an extent that it exceeds the yield field of the host material (for example, as shown in Figure 2B). In practice, sharp angles in conductive features concentrate the electric field and can be rounded if possible. Manufacturing methods for metal patterning, such as the lift-off method or damascene method, typically cannot create features that are perfectly rounded in the longitudinal section. However, in-plane (outermost surface) patterning of contacts can be controlled by lithographic representation to form circular pads or rounded corners, etc., which can also help reduce the electric field density.

[0276] It should be noted that the isolation layer 180 contains a material with a substantially larger band gap than the oxide active drift layer. In its original state, the isolation layer 180 is not effectively insulating. Low electrical conductivity also indicates the selection of a suitable material for the isolation layer 180. Compatibility with the UWBG active drift region 120 is another factor for the isolation layer 180 material. In some cases, the isolation layer 180 also has a low dielectric constant so that the electric field strength within the host isolation layer 180 can be reduced. Again, referring to the exemplary selection of materials in Figure 29A, which shows the trend of dielectric constant by band gap energy, there is a range of suitable materials that are compatible with the Ga2O3 active drift layer and can be used for the material of the isolation layer 180.

[0277] In some examples, the separation layer 180 can include one or more materials with lower dielectric constants and higher band gaps than the drift layer semiconductor. If the drift layer contains Ga2O3, separation layer compositions of MgO and Al2O3 are possible. SiO2 has even better separation layer properties, but practical deposition methods (e.g., PECVD) produce hydrogenated H:SiO2 films that are amorphous and have substantially different properties from single-crystal quartz (α-SiO2). Atomic layer deposition of Al2O3 is one of the most preferred methods for producing high-quality amorphous and conformal coatings, exhibiting a larger effective band gap and lower dielectric constant than Ga2O3. ALD deposition of amorphous (Al) for x>0 x Ga 1-x )2O3, or other materials described herein, may also be used.

[0278] Referring again to the mesa-type metal contact device, Figure 34 shows that the electric field around contact 130 is relatively infinite (unbounded). Improved high-voltage contact arrangements can be implemented to manage the lateral range of the electric field while fixing and maintaining the contact area 130 in the drift region.

[0279] Figures 35A and 35B show a top view and a schematic cross-sectional view, respectively, of a vertical multilayer semiconductor diode device 1000, according to an exemplary embodiment that incorporates a lateral field-plate arrangement to modify the vector electric field of the device.

[0280] In this example, device 1000 includes a substrate 1010 (Figure 35B), an epitaxial drift layer 1020, and a metal layer 1030, as previously described (for example, in device 100 in Figure 1). In this example, a separation layer 1080 is formed on the epitaxial drift layer 1020 and surrounds the metal layer 1030. A field plate arrangement is formed on the outermost surface of the metal layer 1030 and the outermost surface of the separation layer 1080 in the form of a field plate layer 1090, which is made of metal and has a central aperture 1091 of a size and shape that exposes the metal layer 1030. In this example, both the metal layer 1030 and the field plate layer 1090 have a circular configuration, and the separation layer 1080 has a ring or annular configuration that surrounds (or wraps around) the metal layer 1030. The field plate layer has an outer diameter d FP And, an overhang above the separation layer 1080 lol FP It has the following characteristics.

[0281] In this example, the metal layer 1030, the separation layer 1080, and the field plate layer 1090 each have complementary circular or annular configurations, which typically helps minimize edges where stronger electric fields may be formed. In other examples, the Schottky barrier metal of the metal layer 1080 may have an n-gonal configuration (e.g., rectangle, elongated stripe with rounded corners, hexagon, etc.), and the other layers may have complementary configurations as needed. Figure 35B shows the diameter d of the Schottky barrier metal layer 1030. SBM , diameter of field plate layer 1090 and ring width d FP and w FP In addition, the respective thicknesses t of the drift layer 1020 and the separation layer 1070 D and t Iso This is shown.

[0282] In one example, the drift layer 1020 has a dielectric constant ε1 and a bandgap energy Eg1 The separation layer 1080 has a dielectric constant ε I And the band gap energy E g2 It has the following characteristics. In one example, when the materials of the drift layer 1020 and the separation layer 1080 are selected, ε2≪ε1 and E g2 ≫E g1 It will look like this.

[0283] Next, design principles that can be used to design the isolation layer and field plate described herein are explained. Consider a planar parallel metal plate capacitor separated by a thickness t, where a dielectric is located between metal plates in a finite lateral range of area A. Capacitance C p C p =ε r It is defined as ε0A / t. Field plate overhang w FP Effective parasitic capacity C p To minimize low-k (i.e., low ε), r ) Selecting the material and / or the thickness of the separation layer t ISO It is possible to increase this. Furthermore, low-k dielectric materials can be compared to Ga2O3 using the following relationship.

[0284]

number

[0285]

number

[0286] When the thickness is used, (C p / A) = 89 fF / μm 2 This will be the target value.

[0287]

number

[0288] To achieve a relative reduction in overhang capacity density, the device has a thickness t low-k Al2O3 with a wavelength of 640nm can be used.

[0289] In one example, the field plate layer 1090 and the SB metal contact 1030 may be formed from the same metal, e.g., a high work function metal or alloy of Cu, Te, Be, Rh, Co, C, Ni, Au, Ir, Pd, Pt, Se, Os and combinations thereof (see Figure 11A). In another example, the metal layer 1030 may be formed from a high work function metal, including but not limited to Cu, Te, Be, Rh, Co, C, Ni, Au, Ir, Pd, Pt, Se, Os and combinations thereof, while the metal of the field plate layer 1090 may be selected from metals with lower work functions, such as Al, Ti, Mo, and W. High melting point metals can be advantageous for use in high-temperature operations (e.g., above 300°C).

[0290] Ohmic contacts to the substrate may also include metals with high work function to enable co-processing of the front and back sides of the device structure. For example, Ni can be used as the SB metal on the surface of the drift layer, but Ni can also function as an ohmic contact to a highly doped SiC substrate. Furthermore, silicides can be used to form low-resistance ohmic contacts to the substrate. Silicon can be removed from the SiC substrate by thermal annealing of the contact metal to form a silicide. For example, Ni x Si 1-x It can form Ti x Si 1-x It can form a SiC / Ti x Si 1-x Materials such as Ti / Al can form ohmic contacts with the substrate.

[0291] Some examples of the field plate metal layer 1090 / separation layer 1080 / Schottky barrier metal 1030 / wide bandgap oxide drift layer 1020 / substrate 1010 / ohmic contact layer structure are as follows: Al / Al2O3 / Al / Ni / Ga2O3 / 4H-SiC / Ni / Al Cu / Al2O3 / Al / Ni / Ga2O3 / 4H-SiC / Ni / Cu Cu / Al2O3 / Al / Ni / NiO / Ga2O3 / 4H-SiC / Ni / Cu Cu / Al2O3 / Al / Ni / Ni x Cu y O / Ga2O3 / 4H-SiC / Ni / Cu Al / Al2O3 / Al / Ni / Pd / Ga2O3 / 4H-SiC / Ni / Cu.

[0292] In one embodiment, the separation layer 1080 is formed from a material with a wider band gap than the drift layer 1020. In one example, the separation layer 1080 is formed from Al2O3. In another example, the separation layer 1080 is formed from SiO2.

[0293] In other examples, the separation layer can be a wide-bandgap oxide having a p-type conductivity. For example, the oxide of the separation layer may include nickel oxide, nickel-copper oxide, copper oxide, tellurium oxide, or osmium oxide. The separation layer may also include a portion of a metal oxide formed from an SB metal.

[0294] In other examples, the IL may also have p-type characteristics, with or without having a bandgap larger than the drift layer.

[0295] Figure 36 shows a plot of the electric field distribution 1110 of a simulation of a vertical multilayer semiconductor device with a configuration similar to the device 1000 shown in Figures 35A and 35B, incorporating the field plate arrangement described above (for example, the one in Figures 35A and 35B).

[0296] As can be seen from the inspection, the field plate layer 1090 has an outer diameter (for example, d in Figure 35B). FP ) and the overhang above the separation layer 1080 (for example, w in Figure 35B) FP The low-k isolation layer 1080 also functions to reduce the concentration of electric field lines near the longitudinal boundaries or corners of the metal layer 1030 in contact with the drift layer surface. The equipotential lines 1110 between a portion of the interface of the contact metal 1030 and the drift layer 1020 are significantly flattened compared to the absence of the field plate layer 1090. The concentration of electric field lines 1115 is also significantly reduced near the contact region (metal layer 1030) in direct contact with the drift region 1020. The low-k isolation layer 1080 also functions to reduce the maximum electric field strength directly beneath the field plate layer 1090 by spreading the equipotential lines laterally. Furthermore, the conduction channel formed between the metal layer 1030 in contact with the drift region and the laterally oriented conductive substrate 1010 exhibits a substantially uniform electric field. Although not limited by theory, a decrease in electric field density in regions adjacent to the metal layer 1030 (particularly the angular regions near the interface between the drift layer 1020 and the metal layer 1030, such as the interface region 140 shown in Figure 1) can improve device performance by, for example, reducing the peak electric field within the device to a level far below the critical yield field of the host drift material.

[0297] In the case of a fixed vertical device configuration, the current-carrying capacity of the diode structure in Figure 1 can be increased by scaling the contact area 140 to a larger area or by multiplexing several parallel-connected diodes. By dividing the longitudinal current among several parallel interconnected diodes, trade-offs are possible between the consumed epitaxial area, maximum longitudinal current capacity, and thermal effects.

[0298] Figures 37A and 37B show transverse and longitudinal cross-sectional views, respectively, of a composite diode device 1200 having multiple unit cells 1250 similar to the vertical multilayer semiconductor diode device 1000 shown in Figures 35A and 35B. The top cross-section of Figure 37A is taken along section AA and represents a plane parallel to the substrate surface where the circular metal layer 1030 and the isolation layer 1080 intersect. The longitudinal cross-section of Figure 37B relates to the feature of an optional continuous top contact metal 1220 interconnecting multiple Schottky barrier metal contacts 1030, the top contact metal 1220 functioning as a top field plate 1090. The drift layer 1020 is located on the substrate 1010 as well as on the ohmic contacts 1240. The metal layer 1030 contains several circular metal regions. The isolation layer 1080 extends across the composite diode device 1200 and surrounds each of the circular metal regions of the metal layer 1030. A drift layer (e.g., drift layer 1020 in Figure 35B) can be located between the metal layer 1030 and the substrate (e.g., substrate 1010 in Figure 35B) and can extend across the composite diode device 1200. A field plate layer 1220 (e.g., 1090 in Figure 35B) can be formed above the metal layer 1030 and can also extend across the composite diode device 1200. Each unit cell 1250 has an outer periphery 1092, which can relate to the outer diameter and overhang dimensions of the field plate required for each unit cell to reduce electric field concentration in each of the circular regions of the metal layer 1030. Thus, in this example, the dimensions of the field plate layers 1090 / 1220 are limiting factors regarding the number of unit cells that can be arranged within a given surface area.

[0299] In various examples, each unit cell may have a width ranging from 1 micron to 100 microns, or from 100 microns to 1 cm. In one example, each unit cell shares a common substrate (1010) and a drift layer 1020. In these examples, high-resistance edge termination regions can be formed between each unit cell. In one example, the termination region is formed as a physical trench or channel, extending downward into the drift layer 120 and forming a boundary between each unit cell 1250. In another example, the termination region may be formed by ion implantation, where a resistive trench or channel region is formed within the oxide material of the drift layer 1020.

[0300] In various embodiments, a metal layer (e.g., metal layer 130 in Figure 1, or metal layer 1030 in Figures 35A and 35B) is deposited using a metal deposition process (such as sputtering, thermal deposition, electron beam deposition, or electrodeposition) within any further epitaxial layer formed above an epitaxial drift layer (e.g., drift layer 120 in Figure 1, or drift layer 1020 in Figures 35A and 35B), following the formation of an epitaxial drift layer. That is, the metal deposition process is carried out separately from the epitaxial oxide deposition. As understood, this requires a process change from the epitaxial oxide layer deposition process to the metal deposition process. The final deposited epitaxial oxide surface can be protected by limiting its exposure to a contaminating environment before metal deposition. This can be achieved by configuring a separate deposition chamber with a vacuum wafer transport mechanism. Alternatively, metal deposition can be performed within the same process chamber as oxide deposition, once undesirable species have been removed from the chamber. In some cases, as further described herein, metals can be deposited epitaxially within an epitaxial oxide deposition chamber.

[0301] Figures 38A to 38C show process flows for forming vertical multilayer semiconductor devices, including epitaxial drift layers of oxide material with metal layers forming Schottky barrier junctions, according to several embodiments. The metal layer 1330 can be an epitaxial metal layer (e.g., formed using MBE, ALD, or MOCVD) or a non-epitaxial metal layer (e.g., formed using sputtering, pulsed laser deposition, or thermal deposition of metal). The result of each process block (or unit operation) of the process is the intermediate product shown in Figures 38A to 38C.

[0302] In the process stage / block, the epitaxial drift layer 120 is formed on the substrate 110, as shown by the intermediate product 1310 in Figure 38A.

[0303] In another block of the process, the (epitaxial) metal layer 1330 is formed on the drift layer 120, as shown by the intermediate product 1340 in Figure 38B. The mismatch in lattice constants and / or crystal structure between the specific metal and the final surface reconstruction of the oxide surface plays a crucial role in the quality of the metal-oxide interface. Methods for forming a favorable metal-oxide interface are disclosed later in this disclosure. In other examples, the (epitaxial) metal layer 1330 may be formed on either an intervening or intermediate epitaxially deposited layer formed on the drift layer 120. In one example, the thickness of the (epitaxial) metal layer 1330 is between 1 angstrom and 100 angstroms. The epitaxial metal or the first deposited metal layer may be relatively thin, and then another metal layer may be deposited to increase the total layer thickness. The second metal deposition step may include a different metal composition from the first metal, or the same metal.

[0304] In another block of the process, the metal layer 1330 may be patterned as shown by the intermediate product 1370 in Figure 38C. The intermediate product 1370 may be manufactured by photolithographic patterning of a mask and selective material removal via a subsequent physical etching process. The etching process may be at least one of a dry reactive gas plasma process or a wet etching process. The device may also be further processed as needed to form a vertical multilayer semiconductor diode device according to the present disclosure. For example, in some cases, a patterned contact layer 1351 is included on top of the epitaxial metal layer. In some cases, a non-epitaxial metal layer may also be used to form a Schottky barrier junction with an epitaxially deposited drift layer 120. In some cases, a transition layer (e.g., shown in structure 400 in Figure 4 and described above) may be deposited between the substrate 110 and the drift layer 120. In some cases, an intermediate layer (e.g., shown in structure 800 of Figure 8 and described above) can be deposited between the drift layer 120 and the (epitaxial) metal layer 1330. In some cases, some of the layers are patterned (e.g., using wet etching, plasma etching, and / or photolithography) to form the structures described herein. Optionally, the oxide surface exposed by the metal patterning 1335 may be treated to reduce surface damage, reduce surface leakage, and passivate the surface.

[0305] Any of the device structures described herein (for example, structure 100 in Figure 1, 300 in Figures 3A and 3B, 400 in Figure 4, 600 in Figure 6, 800 in Figure 8, 1000 in Figures 35A and 35B, and 1200 in Figure 37A) can be fabricated using the above process.

[0306] Figures 39A–39G show a process flow for forming a vertical multilayer semiconductor diode device according to another exemplary embodiment, which includes an epitaxial drift layer of oxide material forming a Schottky barrier junction with a metal layer. In this process, the metal layer 1430 can also be an epitaxial metal layer (e.g., formed using MBE or MOCVD) or a non-epitaxial metal layer (e.g., formed using sputtering, pulsed laser deposition, or thermal deposition of metal). The result of each process block (or unit operation) of the process is the intermediate product shown in Figures 39A–39G.

[0307] In the process block, an epitaxial drift layer 1420 containing semiconductor oxide material is formed on a SiC substrate 1410, as depicted by the intermediate product 1401 shown in Figure 39A. In some cases, the SiC substrate 1410 is a composite substrate including a bulk substrate layer and a surface layer (e.g., the bulk substrate layer 112 and surface layer 114 of substrate 110 in Figure 1), the surface layer containing single-crystal SiC.

[0308] In another block of the process, the separation layer 1480 is formed on the drift layer 1420, as depicted by the intermediate product 1402 shown in Figure 39B. In one example, the separation layer 1480 is formed from a suitable oxide material such as Al2O3, NiGa2O4, AlCu2O4, GaCu2O4, MgO, ZnGa2O4, or SiO2. In one example, the separation layer 1480 is formed on the drift layer 1420 by a conformal deposition process such as atomic layer deposition (ALD). In another example, the separation layer 1480 is an epitaxial layer formed using an epitaxial deposition process (e.g., MBE or MOCVD). In one example, the separation layer 1480 is formed to have a layer thickness of 100 nm to 300 nm.

[0309] In another block of the process, the opposing in-device field termination region 1471 and the opposing inter-device isolation region 1475 are formed by the physical removal of portions of the isolation layer 1470 and drift layer 1420, respectively, as depicted by the intermediate product 1403 shown in Figure 39C. Alternatively, physical changes in selective area and depth can be achieved by an ion implantation process. Furthermore, the central contact area region 1477 is formed by removing the isolation layer 1480 to expose the drift layer 1420. The opposing in-device field termination region 1471 and the opposing inter-device isolation region 1475 can be formed by patterning and etching the isolation layer 1480 and drift layer 1420 (e.g., using wet etching, plasma etching, and / or photolithography). In one example, these portions are removed by etching following the application of a photoresist.

[0310] In another block of the process, a top metal layer is deposited, forming the metal layer 1430 and the field plate layer 1490, as depicted by the intermediate product 1404 shown in Figure 39D in this example. In some cases, the metal layer 1430 is thinner than the field plate layer 1490. For example, the metal layer 1430 can be deposited using epitaxial techniques and be thinner than the field plate layer 1490, which can be deposited using a fast growth rate method (e.g., sputtering or thermal deposition). In this example, a guard ring 1495 is formed on the isolation layer 1480 outside the field termination region 1471. The guard ring 1495 can provide a reference voltage and / or reduce parasitic currents and voltages. In various examples, the top metal layers (e.g., 1430, 1490 and / or 1495) may be formed from Ti / Al, Al, Ni, Mo, Pd, or combinations thereof. In some cases, the device may not include an intermediate layer (for example, as shown in structure 100 in Figure 1 or structure 400 in Figure 4), and the guard ring 1495 can be deposited on an epitaxial oxide layer. The portions of the top metal layer corresponding to the field termination region 1471 and isolation region 1475 (e.g., 1430, 1490 and / or 1495) are also removed, for example, using patterning and plasma etching processes. In another example, a patterning and metal lift-off (MLO) process is used.

[0311] In another block of the process, the top passivation layer 1476 is formed on top of the entire device, as depicted by the intermediate product 1405 shown in Figure 39E. In one example, the top passivation layer 1476 is formed from a suitable oxide material such as Al2O3 or SiO2.

[0312] In another block of the process, the bottom contact layer 1452 is formed on the back surface of the substrate 1410, as depicted by the intermediate product 1406 shown in Figure 39F. The bottom contact layer 1452 can create an ohmic contact with the substrate 1410 and can be deposited using any of the metal deposition techniques described herein.

[0313] In another block of the process, the metal layer 1430, which also forms the top contact in this example, is exposed by a further etching process that removes a portion of the passivation layer 1476, as depicted by the intermediate product 1407 shown in Figure 39G.

[0314] Figure 40 shows an example of a schematic cross-sectional view of a vertical multilayer semiconductor diode device configuration Y100 used to simulate the thermal heating effect. In this example's thermal model, the semiconductor diode device configuration Y100 is assumed to be continuous from left to right (i.e., semi-infinite) without lateral boundary conditions.

[0315] Moving generally upwards from the back surface (in the positive z direction) in Figure 40, the semiconductor device configuration Y100 includes a horizontally extending backside drain metal ohmic contact layer F1 (cathode), and its lower surface (i.e., S1) is at temperature T S1 It is held in place. The next layer contains substrate Y110(F5). In the various examples shown below, thermal modeling is performed to compare different substrate materials such as highly doped (n-type or p-type) SiC or Ga2O3. Firstly, the doping level and type do not significantly alter the thermal conductivity of the host material.

[0316] Above substrate Y110, an epitaxial drift layer Y120 (F6+F7+F8) containing semiconductor oxide material is formed, which in this example is modeled as three regions including a central region F8 and opposing boundary regions F6 and F7. By dividing the epitaxial drift layer Y120 into three regions in this way, the temperature performance characteristics of the central region F8 can be individually characterized (see, for example, Figure 44 below). The central region F8 is where the most ohmic heating occurs due to the large forward conduction channel. Regions F7 and F6 represent semiconductor regions with little or no longitudinal current flow.

[0317] Above the central region F8 of the epitaxial drift layer Y120, there is a Schottky barrier metal layer Y130 (within region F3) that forms a Schottky barrier junction between the metal layer Y130 and the central region F8 of the epitaxial drift layer Y120.

[0318] Above the boundary regions F6 and F7 of the epitaxial drift layer are the boundary regions F2 and F4 of the separation layer Y180, which is formed from a material with a wider band gap compared to the semiconductor oxide material forming the epitaxial drift layer Y120, respectively. Generally, the separation layer regions F2 and F4 may contain compositions with lower thermal conductivity than the drift layer Y120 (F7, F8, and F6). Extending above the Schottky barrier metal layer Y130 and partially above regions F2 and F4 of the separation layer Y180 is the field plate layer Y190 (within region F9), formed from a low, medium, or high work function metal. The centrally located metal interconnect F10 extends upward from the field plate layer Y190 to the top contact bus metal layer F11 (anode), which overlaps and extends horizontally. In one example, the field plate layer Y190, the metal interconnect F10, and the top contact metal layer F11 may be formed of Al. In another example, the electrical conduction type can be changed to the opposite conduction type, in which case the top bath metal layer F11 functions as a cathode. As understood, the thermal conductivity performance is equivalent.

[0319] In this example, the exposed back surface of the top contact bus metal layer F11, the exposed side surface of the interconnection part F10, the exposed side surface and outermost surface of the field plate layer Y190, as well as the exposed outermost surfaces of the boundary regions F2 and F4 of the separation layer Y180, are all (as shown in Figure 40) at ambient air temperature T a It is assumed that this is the case. In this way, these exposed surfaces are modeled to allow convective transfer of heat generated by the device configuration Y100 to the "air". This would be considered a worst-case scenario, as in other examples the "air" region is a thermally insulating dielectric material (e.g., a polymer planarization layer) and also minimizes heat transfer from the device configuration Y100 (e.g., the interconnect F10 implemented as a wire bond connected to the contact bus metal layer F11 in the form of a bond pad). Furthermore, the lower surface S1 of the metal contact region F1 is at temperature T S1 It is assumed that the upper surface of the metal contact bus region F11 is held at a temperature T S2 It is assumed that it will be held there.

[0320] Figure 41 shows a plot Y200 of the thermal conductivity of various semiconducting materials as a function of temperature, which can be used to model the temperature of the vertical multilayer semiconductor device configuration Y100 described later. The plot shows the thermal conductivity curves of semiconducting materials, including not only the thermal conductivity curves of the potential substrate material 4H-SiC Y210 and n+-doped (Sn)Ga2O3Y220, but also the thermal conductivity curve of intentionally undoped Ga2O3Y230, which can be used as an example to form the epitaxial drift layer Y120 of the device configuration Y100 shown in Figure 40.

[0321] As can be seen from the tests, the thermal conductivity of all the materials depicted decreases with increasing temperature. At an operating temperature of 200°C, the thermal conductivity of SiC is at least five times higher than that of the Ga2O3-based materials shown. This aspect represents one of the main advantages of the hybrid approach disclosed herein.

[0322] In one example, the thermal modeling involves simulating an initial voltage applied to a central region of approximately 1 μm in a top contact layer F11 with a drain contact layer F1 held at ground potential. In this example, the simulated applied voltage corresponds to an initial current of 65 Amp conducted by the model configuration Y100 between the top contact layer F11 and the drain contact layer F1. Furthermore, the temperature T of the surface S1 of the configuration model Y100 is also simulated. S1 The temperature is set to 25°C, and the temperature of the surface S2 is T S2 The temperature is set to 75°C. The model then becomes capable of reaching an equilibrium state in which a steady-state forward current is conducted by the semiconductor device configuration Y100.

[0323] The model is computed using the finite element method to construct the spatial distribution of material properties in a high-density tensor mesh. Heat transfer across the entire 2D model structure is applied and solved using parabolic partial differential equations.

[0324]

number

[0325] In the equation, Q is heat transfer, T is temperature, and C h ρ is the specific heat, κ is the thermal conductivity, and ρ is the material density. Each parameter is a function of the time and spatial position of each element (t,x,y).

[0326] The simulation workflow involves (i) creating a 2D physical model for steady-state or transient state simulation, (ii) applying a spatial mesh algorithm to discretize the model, and (iii) matrix element C hThis includes steps or blocks such as (iv) assigning (t=0,x,y), ρ(t=0,x,y), and κ(t=0,x,y); (v) specifying an internal heat source Q within the geometry; (v) specifying the temperature on the boundary or the heat flux T(t=0,x,y) through the boundary; (v) specifying the ambient temperature and convective heat transfer coefficient, and the radiative heat flux; and (vi) specifying the emissivity ε and Stefan-Boltzmann constant σ for each material of the structure. Once the model is fully specified, the simulation heat flow algorithm is initialized with the initial temperature or initial estimate.

[0327] Referring to Figure 42, a temperature contour shaded plot Y300 is shown, which in this example shows the steady-state temperature distribution resulting after thermal modeling of a semiconductor device configuration Y100 consisting of a highly doped Ga2O3 substrate Y110 (e.g., material Y220 in Figure 41) and a Ga2O3 epitaxial drift layer Y120 (e.g., material Y230 in Figure 41). The Schottky barrier metal layer Y130 is selected to be a metal with a high work function, such as Ni, and the Ga2O3-based epitaxial drift layer Y120 is n - It is doped. In other examples, the Schottky barrier metal layer Y130 can be selected from other metals with high work functions, such as Pt, Pd, Cu, or Os. In alternative configurations, the Ga2O3 epitaxial oxide layer is p - The doped Schottky barrier metal layer Y130 can be selected from metals with low work functions such as Al or Ti. The thermal conductivity of most selected metals does not significantly alter the conclusions herein. The internal heat source within structure Y300 is generated by the resistive heating effect due to a longitudinal current (e.g., constant current) flowing within region F8 of drift region Y120.

[0328] As can be seen from Figure 42, the maximum temperature region Y310 is located within the central region F8 of the drift layer Y120, at approximately 400°C, and the temperature gradient extends laterally into the contact and field plate Y190. The top contact and separation layer are bonded to an open surface for air convection. Nevertheless, the top contact Y190 rises to approximately 300°C, meaning that a refractory metal may be required for stability (or reliability, or durability). In general, metal bonding temperatures above 250°C are problematic for high-power and high-reliability applications. For this exemplary model, it can be concluded that the material, including the Schottky barrier metal layer Y130, separation layer Y180, and field plate layer Y190, must operate at temperatures in the 250°C–300°C range, where reliability is expected to be negatively affected.

[0329] Forward bias diode operation is performed with the central epitaxial drift layer Y130 region F8, and the heating power is IR 2 It is modeled as current "filament" conduction following a relationship, where I is the current flowing through the region and R is the effective resistance of the region governed by the doping concentration.

[0330] Referring again to Figure 42, it is shown that the steady-state temperature at the interface between the Ga2O3 drift region and the substrate junction is also approximately 350°C, with the gradient extending towards the rear contact, where it is maintained at 25°C. This self-heating effect of the drift region is caused by the low thermal conductivity of the Ga2O3 substrate.

[0331] In contrast to the structure in Figure 42, here it is replaced with a high thermal conductivity substrate as shown in Figure 43. Except that a SiC substrate (see, for example, material Y210 in Figure 41) is used instead of the Ga2O3 substrate in the structure adopted in Figure 42, a temperature contour shaded plot Y400 is shown, which represents the temperature distribution obtained as a result of thermal modeling of the semiconductor device configuration Y100 modeled in Figure 42.

[0332] In contrast to the modeling results shown in Figure 42, the results in Figure 43 show that the maximum temperature Y410 of the central region F8 has a maximum temperature in the range of 200°C to approximately 220°C, which is significantly lower than the maximum temperature of the structure with the Ga2O3 substrate modeled in Figure 42. The same thermal heat source is applied to both Figure 42 and Figure 43. Furthermore, the material including the Schottky barrier metal layer Y130, the isolation layer Y180, and the field plate layer Y190 operates at a temperature of approximately 175°C, which is more advantageous than conventional heat dissipation methods. The SiC substrate with high thermal conductivity provides an efficient heat sink in the drift region and offers lateral thermal management throughout the structure. The temperature reduction enabled by the improved thermal management described herein also relaxes the constraints on the type of metal that can be used, which has a favorable impact on the reliability of the device.

[0333] Many material parameters are temperature-dependent. Thermal conductivity, heat capacity, and bandgap energy generally decrease as the temperature rises. Also, thermal activation of carrier generation increases the number of free carriers, reducing the electrical resistance of semiconductors. Conversely, in metals, electrical resistance usually increases with increasing temperature. Therefore, the self-heating effect disclosed in Figure 42 can cause thermal "runaway," and if heat dissipation is limited, it can lead to premature yielding of the device.

[0334] The transient thermal response of the model reveals further advantages and disadvantages of the oxide drift region coupled to high and low thermal conductivity substrates.

[0335] Referring to Figure 44, the transient responses of device models Y300 and Y400 for two current pulse periods occurring within the current filament region F8 are shown. A plot of the integrated thermal intensity β(t) of region F8 of the drift layer Y120 as a function of time (in microseconds) Y500 is provided for two device configurations shown in Figure 42 (i.e., with a Ga2O3 substrate) and Figure 43 (i.e., with a SiC substrate), assuming a pulsed current input having a 5μs on-period and a 5μs off-period (at a 50% duty cycle) within region F8. Upon examination, the maximum thermal intensity Y510 of the SiC substrate-based device is approximately one-third lower than the maximum thermal intensity Y520 of the Ga2O3 substrate-based device, despite both devices having the same Ga2O3 drift layer and top contact structure. Furthermore, the thermal intensity of the SiC substrate-based device can recover to zero Y530 before the next 5μs pulse begins, in contrast to the recovery Y540 of the Ga2O3 substrate-based device.

[0336] As is understood, the time required for Ga2O3 substrate-based diode devices to dissipate heat increases, which in turn increases the minimum dwell time required for any switching application compared to SiC substrate-based diode devices. Alternatively, if such a minimum dwell time (or off-period duration) is not long enough, Ga2O3 substrate-based devices may suffer from thermal "runaway."

[0337] Figure 45 shows a schematic cross-sectional view of a vertical multilayer semiconductor diode device configuration Y600 used to simulate the thermal performance of a mesa-type semiconductor device. In this example, the epitaxial drift layer Y620 (F6+F7+F8) of the device model configuration Y600 is formed within a mesa-type structure with an angled wall extending upward from the substrate Y610 (F5), and the region outside the mesa-type is at an ambient air temperature T (as shown in Figure 45). a It is assumed that this is the case.

[0338] Moving generally upwards from the back surface of Figure 45, the device model configuration Y600 includes a horizontally extending backside drain metal ohmic contact layer F1 (cathode), and its lower surface (i.e., S1) is at temperature T S1 It is held in place. The next layer includes the substrate Y610(F5). Above the substrate F5, an epitaxial drift layer Y620 containing a semiconductor oxide material is formed, which is again modeled as three regions including the central region F8 and the boundary regions F6 and F7 facing the central region F8, in order to enable characterization of the central region F8. Above the central region F8 of the epitaxial drift layer Y620 lies a Schottky barrier metal layer Y630(F3) which forms a Schottky barrier junction between the metal layer Y630(F3) and the central region F8 of the epitaxial drift layer Y620. In this example, the metal layer Y630 also forms a top contact layer, and its upper surface is at a temperature T S2 It is assumed that it will be held at (for example, the upper surface at temperature T S2 (It is coupled to the thermal heatsink.)

[0339] In this example, the thermal modeling involves simulating the voltage initially applied to a central region of approximately 1 μm in a Schottky barrier metal layer Y630 with a drain contact layer F1 held at ground potential. In this example, the simulated applied voltage corresponds to an initial current of 65 Amp conducted by the model configuration Y600 between the Schottky barrier metal layer Y630 and the drain contact layer F1. Furthermore, the temperature T of the surface S1 of the configuration model Y600 is also simulated. S1 The temperature is set to 25°C, and the temperature of the surface S2 is T S2 The temperature is set to 75°C. The model then becomes capable of reaching an equilibrium state in which the steady-state forward current is conducted by the device configuration Y600.

[0340] Referring here to Figure 46, a steady-state temperature contour shaded plot Y700 is shown, which in this example shows the resulting temperature distribution after thermal modeling of configuration Y600, consisting of a highly doped Ga2O3 substrate (e.g., see material Y220 in Figure 41) and a Ga2O3 epitaxial drift layer (e.g., see material Y230 in Figure 41). The Schottky barrier metal layer Y630 is selected to be a metal with a high work function, such as Ni, and the Ga2O3 epitaxial oxide layer is n - It is doped. In other examples, the Schottky barrier metal layer Y630 can be selected from other metals with high work functions, such as Pt, Pd, or Os. In alternative configurations, the Ga2O3 epitaxial oxide layer is p - The doped Schottky barrier metal layer Y630 can be selected from metals with low work function, such as Al.

[0341] Similar to the modeling results in Figure 42, as can be seen from the modeling results shown in Figure 46, the maximum temperature Y710 of the central region F8 is approximately 350°C, again far exceeding the desired operating temperature of 200°C to 220°C for semiconductor diode devices. Furthermore, the extended region of the epitaxial drift layer Y620 needs to operate at temperatures in the range of 250°C to 300°C, which is expected to affect reliability.

[0342] Referring now to Figure 47, we see a steady-state temperature contour shaded plot Y800 showing the resulting temperature distribution after thermal modeling of the semiconductor device configuration Y600 modeled in Figure 46, except that a SiC substrate (see, for example, material Y210 in Figure 41) is used instead of a Ga2O3 substrate. In contrast to Figure 46, the maximum temperature Y810 in the central region F8 has a maximum temperature in the range of 200°C to 220°C, which is significantly lower than the maximum temperature of the Ga2O3 substrate-based device shown in Figure 46. Furthermore, the epitaxial drift layer Y620 considered in total has an overall operating temperature of about 150°C, which is sufficient within the conventional operating temperature range of these types of diode devices.

[0343] The thermal models described herein demonstrate the advantageous hybrid integration of oxide drift layers on high thermal conductivity SiC substrates to dramatically improve steady-state and transient device performance, which can be applied to high-power switching.

[0344] Next, further detailed embodiments and manufacturing methods of hybrid metal oxide semiconductor and SiC substrate device architectures will be described.

[0345] Figure 48 shows the crystal surface orientation electron affinity (χ) on the absolute energy scale with respect to vacuum between a slightly sloped surface of β-Ga2O3 labeled with Miller indices (hkl) and a (000±1) surface of 4H-SiC (i.e., Si polar and C polar surfaces). A The plot of Z1-1000 is shown. The band gap of each material is represented by a shaded box, the outermost surface level represents the conduction band edge, and the lower boundary of each box represents the valence band edge. Figure 48 shows the band gap and (χ A The results were calculated using density functional theory (DFT) on a specific material crystal slab.

[0346] In particular, the Si polar 4H-SiC(0001) surface is favorable for the epitaxial deposition of β-Ga2O3(-201) aligned films. Assuming the material is not intentionally doped, the electron affinity of β-Ga2O3(-201) is shown as Z1-1010, and that of 4H-SiC(0001) is Z1-1020.

[0347] The interface between the epitaxially grown β-Ga2O3(-201) layer and the 4H-SiC(0001) layer results in an energy band lineup as shown in Figure 49. The conduction band edge Z2-2020 is shown along the device growth direction in Figure 9C at the heterointerface junction. The drift region is n-type (5e16cm). -3 ) and the n-type 4H-SiC region is 1e19cm -3As shown, this results in a discontinuity in the conduction band, inducing a triangular potential well on the Ga2O3 side. Furthermore, the device configuration in Figure 9C shows that the first quantization energy level in the potential well falls below the Fermi energy, inducing a two-dimensional electron gas (2DEG) in the heterojunction. An example of a 2DEG localized in the heterojunction, the lowest energy quantization electron wavefunction, is shown as Z2-2010. The presence of the 2DEG is advantageously used in this disclosure to form an electrical contact between the two regions, effectively pinning the conduction band locally.

[0348] The devices, structures, and methods described herein may include crystallographic matching of two different crystalline space groups (SGs), including Ga2O3 (SG=C2m) and 4H-SiC (SG=P63mc).

[0349] Figures 50 and 51 show the detailed atomic arrangement of Si and C atoms in a single-crystal 4H-SiC polytope, oriented along the C direction Z3-3020 on the C plane, respectively. Figure 50 shows the single-crystal unit lattice Z3-3010 containing a wurtzite-like hexagonal atomic arrangement. The polarity orientation refers to Si-C bonds oriented along the

[0001] or [000-1] axis, as is evident from the Si and C planes shown. Figure 51 shows a C-plane (i.e., (0001) or (000-1)) oriented surface with in-plane Si-Si and CC lattice spacing α(Si-Si) = 3.095 angstroms. The stacking order along the Si polarity direction is (ABCB-ABCB-...) with an equal number of cubic and hexagonal bonds.

[0350] Epitaxial bonding of single-crystal Ga2O3 compositions is possible on different SiC surfaces, but Ga2O3 can be formed in various polytopes exhibiting distinct symmetry groups selected from monoclinic (C2m), rhombohedral (R3c or R3m), orthorhombic (Pna21), cubic (Fm3m), and even hexagonal (P63mc). Ideally, a single, uniform polytope is desirable for the epitaxial layer to achieve the best electronic performance in this application. Mixed polytope epitaxial layer compositions are possible, but may produce lower quality materials and devices. The stability of a given polytope epitaxially formed on a SiC surface is governed not only by several factors, namely (i) in-plane lattice mismatch between different crystal symmetry space groups of the epitaxial layer and the substrate relative to a given crystal orientation plane and epitaxial layer, (ii) surface energy of the SiC surface, (iii) first bonding species of the SiC surface to a first complementary species of Ga2O3 (i.e., Ga or O), and (v) the relative ratio of incident flux Ga and active O atoms chemiadsorbed and physiadsorbed at a given surface deposition temperature, but also by other factors.

[0351] The devices, structures, and methods described herein may include a beta-phase monoclinic form of Ga2O3 that can be stabilized to a wide growth window by selective deposition on a prepared C-plane surface of 4H-SiC. Furthermore, the β-Ga2O3 film is formed epitaxially in a layer-by-layer growth mode oriented in the [-201] crystal direction Z4-4020, as shown in Figure 52. In monoclinic Ga2O3, 50% of the Ga-O bonds are tetrahedral and the remaining 50% are octahedral. The coordination of the O-terminated SiC surface, along with its influence on the stacking order of the Ga2O3 epitaxy, will be discussed later. Of interest is the stacking order of Ga atoms and O atoms along the epitaxial growth direction Z4-4020. The atomic plane consists of a buckled Ga-Ga layer followed by a substantially planar two-dimensional O lattice, a substantially planar two-dimensional Ga lattice, and again a substantially planar two-dimensional O lattice, and this order is repeated along the growth direction. During the simultaneous deposition of Ga and O species, self-assembly of the crystal structure occurs. An optional final surface on the (-201) plane is shown as the oxygen-terminated surface Z4-4030. This can be achieved after epitaxial deposition by exposing its surface to active O species (or only active O species). In Figure 53, the surface reconstruction of the O-terminated surface is shown, indicating a hexagonal arrangement of O atoms Z4-4010.

[0352] Figure 54 shows a further simplified lattice model for the axial C-plane oriented 4H-SiC in Figure 54, which has planar hexagonal interatomic distances α(Si-Si)=α(CC)=3.095 angstroms, in order to evaluate the lattice mismatch at the first Si-terminated or C-terminated surface.

[0353] Figure 55 shows the oxygen hexagonal lattice on the oxygen-terminated (-201) oriented β-Ga2O3 surface. The O lattice is a hexagon deformed by 2.985 ≤ α(OO) ≤ 3.083 angstroms. This allows us to estimate the range of the in-plane lattice constant mismatch (LM) as follows:

[0354]

number

[0355] In practice, LM < 5% is desirable for epitaxial layers with low defect density, indicating that the O lattice can respond elastically to in-plane compressive strain.

[0356] Figure 56 schematically shows possible epitaxial orientations for manufacturing oxide-SiC articles. A C-plane cut 4H-SiC substrate Z9-9030 can be oriented to present either a Si plane or a C plane for epitaxial deposition. The intrinsic polarity Z9-9040 of 4H-SiC affects the surface electron affinity (shown in Figure 48) and, consequently, the heterojunction band alignment with the epitaxial oxide. If the 4H-SiC is oriented with a surface normal Z9-9010, this defines the epitaxial growth direction Z9-9010. The epitaxial layer may also be grown / organized at an angle such that the surface normal does not perfectly coincide with the epitaxial layer crystal plane. For example, the semiconducting oxide Z9-9020 can be β-Ga2O3. The first surface of the epitaxial layer Z9-9050 can be predetermined by the growth sequence in which the epitaxy process is initiated. Furthermore, the final epitaxial layer surface Z9-9060 may also be predetermined by the growth process.

[0357] Further analysis of the C-plane oriented surface structure of 4H-SiC is shown in Figures 57A, 57B, 57C, and 57D.

[0358] Figure 57A shows a cross-sectional view of the atomic arrangement of a prepared C-plane 4H-SiC crystal with Si polarity Z10-10010, presenting the final surface having the top surface of Si atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing up to approximately 1000°C. Optionally, exposure to low-flux Si atoms colliding with the surface can also secure the final Si surface state after the desorption of spontaneously generated silicon oxycarbide. Exposure of the Si-terminated surface by the active species of oxygen can self-limit the surface to have an O-terminated surface. In that case, the stacking order from the surface downwards is -O-Si-C-Si-C-.

[0359] Figure 57B shows a cross-sectional view of the atomic arrangement of a prepared C-plane 4H-SiC crystal with C polarity Z10-10020, presenting the final surface with top Si atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing up to approximately 1000°C. Optionally, exposure to low-flux Si atoms colliding with the surface can also secure the final Si surface state after the desorption of spontaneously generated silicon oxycarbide. Exposure of the Si-terminated surface by the active species of oxygen can self-limit the surface to have an O-terminated surface. In that case, the stacking order from the surface downwards is -O-Si-C-Si-C-.

[0360] A comparison of Figure 57A and Figure 57B reveals oxygen bonds between surface O-Si atoms with distinct bond symmetries that indicate the preferred next adsorbed atomic layer in the Ga configuration (see Ga and O configurations in Figure 52).

[0361] Oxygen can bond to either Si or C with the following bond strengths: E 結合 (Si-O) = 452 kJ / mol, E 結合 (Si=O)=590kJ / mol E 結合 (CO) = 360 kJ / mol, and E 結合 (C=O)=715kJ / mol Figures 57C and 57D show alternative first oxygen bond configurations to the carbon outermost surface constructed on Si-polar or C-polar 4H-SiC surfaces, respectively.

[0362] Figure 57C shows a cross-sectional view of the atomic arrangement of a prepared C-plane 4H-SiC crystal with Si polarity Z10-10030, presenting the final surface with top-faced C atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing above approximately 1000°C. Optionally, exposure to low-flux C atoms colliding with the surface can also secure the final C surface state after the desorption of spontaneously generated silicon oxycarbide. Exposure of the C-terminated surface by the active species of oxygen can self-limit the surface with an O-terminated surface. In this case, the stacking order is -OC-Si-C- from the surface downwards. Further crystal growth is shown with an additional Ga adsorption layer, where the tetragonal bonding arrangement is shown to form the order -Ga-OC-Si-C-.

[0363] Figure 57D shows a cross-sectional view of the atomic arrangement of a prepared C-plane 4H-SiC crystal with C polarity Z10-10040, presenting the final surface with top-faced C atoms preferentially bonded to oxygen (O) atoms. This can be achieved by ultra-high vacuum annealing above approximately 1000°C. Optionally, exposure to low-flux C atoms colliding with the surface can also secure the final C surface state after the desorption of spontaneously generated silicon oxycarbide. Exposure of the C-terminated surface by the active species of oxygen can self-limit the surface with an O-terminated surface. In this case, the stacking order is -OC-Si-C- from the surface downwards. Further crystal growth is shown with an additional Ga adsorption layer, where the tetragonal or octagonal bonding arrangement is shown to form the order -Ga-OC-Si-C-.

[0364] SiC surface preparation is a crucial step in realizing a high-quality single-crystal β-Ga2O3(-201) oriented epitaxial layer using the methods and structures disclosed herein.

[0365] Figures 57E and 57F show the effect of a misoriented C-plane 4H-SiC surface (i.e., miscut at an angle > 0 from the axial surface) on the epitaxial layer growth of Ga2O3.

[0366] Figure 57E shows a cross-sectional view of a Si polar 4H-SiC crystal along the direction Z10-10010, where the miscut surface Z10-10070 is tilted at an angle θ from the axial c-plane surface Z10-10050. Z10-10065 is the miscut direction perpendicular to the substrate surface, and direction Z10-10060 is the c-axis of SiC. The angle θ (or miscut angle) in Figure 57E is not drawn to scale. In some cases, θ is 2 to 6 degrees, or about 4 degrees. Below the plane of the miscut surface Z10-10070, the SiC crystal is included, and above it, epitaxial Ga2O3 growth is included. The epitaxial layer can grow either along the Z10-10060 direction with stacking faults, or tilted at a substantially directed inclination at the epitaxial layer crystal plane Z10-10055. Figure 57F schematically shows the growth of an epitaxial layer crystal plane having a step-terrace surface Z10-10080 on a 4H-SiC crystal Z10-10080, with an inclined plane Z10-10055.

[0367] Figure 57G further discloses an exemplary process flow Z10G-1000 for manufacturing the structural template surface disclosed in Figures 57A, 57B, 57C, and 57D, which can be further incorporated into the structures and devices disclosed herein.

[0368] The integration of two different crystal symmetry groups (SGs) is initiated by epitaxial deposition of an oxide having symmetry group SG-2 (e.g., monoclinic Ga2O3) on a substrate having symmetry group SG-1 (e.g., hexagonal 4H-SiC). Favorable alignment of SG-2 and SG-1 can be achieved by careful selection of the substrate crystal plane to match the possible epitaxial layers of the oxide SG-2. For example, the Si polar plane of the C-plane 4H-SiC can be terminated at the Si sublattice surface. The Si sublattice can be terminated at the oxygen adsorption layer to form a connecting layer with the Ga adsorption atomic layer.

[0369] The final surface of the oxide epitaxial layer (e.g., β-Ga2O3) can also be terminated with a surface type and a seed that promotes the subsequent formation of a high-quality first metal layer. The first metal layer can be about 1-10 nm or thicker and may be followed by another second metal layer.

[0370] Figure 57H shows another example of a manufacturing process flow for epitaxial deposition of a thick oxide film deposited on a SiC substrate. The growth conditions required for Ga and O to self-assemble into the specific polytope of Ga2O3 (e.g., monoclinic) can be achieved by providing the growth temperature, a predetermined incident flux, and the ratio of co-deposited Ga species and reactive oxygen species. Stacking faults and other crystal misalignments and coordinations are possible and can accumulate depending on the film thickness. An exemplary method for achieving a thick epitaxial film beyond a certain limit of co-deposited thickness is to perform a growth interruption, pausing film growth and restoring surface quality. For example, epitaxial growth of β-Ga2O3(-201) can be interrupted after reaching approximately 100 nm and annealed in an oxygen environment by pausing the Ga flux. Surface improvement can be demonstrated by in-situ diagnostics. Epitaxial growth can then be resumed for a predetermined time or over a figure of merit indicating film quality. This cycle can be repeated multiple times until the desired thickness is achieved. In some cases, growth interruption involves introducing non-growing species, such as nitrogen, atomic nitrogen, surfactants (e.g., bismuth, zinc, magnesium, or germanium), hydrogen, or atomic hydrogen.

[0371] Figure 58 shows experimental data from epitaxial β-Ga2O3(-201) films directly deposited on the surface of a prepared axial n-type 4H-SiC(0001) oriented substrate. Atomic beam epitaxy was performed in an ultra-high vacuum deposition chamber using pure Ga metal and an activated oxygen source from a high-power quartz valve inductively coupled RF plasma source. In some exemplary growths, O2, N2, and N2O were co-supplied to one or more RF plasma sources. Epitaxy systems and methods are described, for example, in U.S. Patents 10,964,537, 11,282,704, 11,342,484, and 11,670,508, which are incorporated herein by reference.

[0372] The 4H-SiC substrate in the example shown in Figure 58 was directly heated with a high-temperature or mid-infrared emissivity SiC heater. The wafer was rotated and positioned relative to the source during growth to allow for the deposition of a very uniform film on a 4” diameter wafer. The substrate growth temperature was between 500 and 1000°C, depending on the resistivity of the SiC substrate. N-type 4H-SiC(0001) substrates were grown at approximately 500–700°C without backside coating due to the matching of direct emissivity between the heater and the substrate. Semi-insulating 4H-SiC substrates were grown at approximately 700–950°C without backside coating due to the matching of direct emissivity between the heater and the substrate. In several exemplary epitaxial growths, it was found that the highest quality single-crystal films were obtained from higher substrate deposition temperatures.

[0373] Reflected high-energy electron diffraction (RHEED) is an essential in-situ diagnostic for direct and real-time evaluation of the quality and crystal structure of epitaxial layers. Figure 58 shows a RHEED image at high symmetry points as a function of azimuth rotation of the substrate around the surface normal of a β-Ga2O3(-201) epitaxial layer approximately 2 microns thick grown on the n-type 4H-SiC(0001)Si polar axis. Excellent single-crystal quality is evidenced by long, sharp RHEED diffraction streaks indicating an atomically flat film. RHEED streaks were monitored and maintained throughout the film growth process. The (-201) oriented film exhibits a 60-degree periodicity as expected and shows no polycrystalline arc or pyramidal surface features as spots.

[0374] Figure 59 shows a RHEED image of a thick β-Ga2O3(-201) epitaxial layer grown on an n-type 4H-SiC(0001)Si polar substrate that has been intentionally miscut 4 degrees from the on-axial surface toward plane A. Sharp and strong streaks are also shown, which are curved due to the miscut of the substrate. Spots overlap the streaks, indicating that the incident RHEED electron beam is partially transmitted through the terrace step. In this disclosure, it is determined that growth on a miscut SiC surface can give excellent Ga2O3 film quality with respect to rotational domains that are capable of (-201) reconstruction.

[0375] Figures 60A and 60B provide further evidence of the high crystallinity and optical quality of the epitaxial layer Ga2O3 grown on a SiC substrate, in the form of in-situ oblique laser reflectance at a wavelength of λ=405 nm (instrument setup shown in Figure 60A). The high initial reflectance from the bare SiC surface (plot in Figure 60B) decreases during Ga2O3 film deposition, with optical film thickness oscillations appearing every λ / 2n, where n(Ga2O3)=1.9. Growth rates (GR) between 0.1 and 4 angstroms per second are possible. Higher growth rates are also possible with scaled elemental sources and chamber characterization.

[0376] Figure 61A shows a wide-angle double-crystal diffraction Ω-2θ symmetric scan of a Ga2O3 epitaxial layer on a SiC substrate. Clear and strong Bragg peaks for β-Ga2O3n(-2O1), n=1, 2, 3, 4, and 5 are shown, and there is no evidence of parasitic polytopes.

[0377] Figures 61B and 61C disclose asymmetric X-ray diffraction reciprocal lattice maps near two Bragg peaks centered on 4H-SiC(107) and βGa2O3(-403) for a heteroepitaxial structure formed when a 2 μm thick βGa2O3(-201) / / 4H-SiC(0001) film is miscut at 0 degrees. The RSM maps indicate that the oxide film is a single crystal of high quality and that different crystal symmetry space groups can be fitted to it.

[0378] In another example, Ga2O3 epitaxial layers can have other pure polytopes when deposited on alternating SiC surface orientations. For example, Figure 62 shows the crystal structure of alpha-phase Ga2O3 (SG=R3c), which is similar to sapphire and can form on AR- or M-plane SiC (2H-, 4H-, or 6H-). Figure 63 also shows a possible wurtzite-type crystalline polytope of Ga2O3 having SG=P63mc, which can form on several SiC substrate orientations. Other polytopes, e.g., SG=Pna21 or cubic (defective SG=Fm3m), are also possible. Of particular interest are the Pna21 and P63ms space groups, due to their intrinsic property of being polar crystals. This disclosure determines that new electronic devices can potentially be constructed using spontaneous and piezoelectric polarization-induced carrier doping by forming Ga-polar or O-polar Ga2O3 films (e.g., including Pna21 and P63ms space groups) on Si-polar or C-polar SiC.

[0379] Figure 64 schematically illustrates a novel embodiment of this disclosure aimed at pre-determining the electronic properties of the final surface of an oxide epitaxial film. It has been found that the β-Ga2O3(-201) surface has electron affinity sensitive to deposition conditions, post-deposition conditions, thermal annealing, annealing in oxygen, and other environmental exposures. Furthermore, it has been found that hydrogen can play a significant role in controlling the final state of surface electron affinity. The bulk region of the β-Ga2O3 film or substrate is shown as Z17-17010, and pre-integrated hydrogen-like (or hydrogen-containing) impurities Z17-17020 can be distributed throughout the bulk or within a thickness of Z17-17030. For example, a bulk-grown Ga2O3 substrate exhibits high-level hydrogen-like impurities. These hydrogen-like impurities may be released from the surface region Z17-17040 by heat or chemical treatment Z17-17050, and the hydrogen-like (or hydrogen-containing) particles Z17-17045 may diffuse or migrate onto the surface Z17-17055 and be removed from the structure Z17-17060. Therefore, the outermost surface portion with a thickness of Z17-17035 may be different from the bulk region Z17-17030.

[0380] Conversely, the surface region Z17-17040 can be chemically or thermally treated in process Z17-17050, which introduces hydrogen-like species to a depth of Z17-17035 within the surface region Z17-17040. In one example, high-temperature epitaxial growth of an oxide layer is completed, and despite the growth temperature ramping down to ambient temperature over time (t), it is subjected to a large oxygen partial pressure. Oxygen annealing during the substrate temperature ramp-down after the growth of the epitaxial layer may induce an effect that selectively depletes the surface region Z17-17040 of impurities or depletes the surface of charge carriers. Such techniques can be useful, for example, if the epitaxial layer is co-doped with Si, Ge or Sn during epitaxy, the final surface region Z17-17040 may have significantly lower doping than the bulk region Z17-17010. Such depleted surfaces, if left unmodified, directly affect Schottky barrier formation, as discussed herein.

[0381] Figure 65 shows the effect on the surface of a β-Ga2O3(-201) oriented epitaxial layer deposited as an n-type drift layer on a highly doped n+ layer or substrate. The band gap Eg is the conduction band edge E. C (z) and valence band edge E V (z) is shown separated. In this example, Si-doped Ga2O3 by impurity donor doping is formed in the epitaxial layer ("epi") N ドリフト = 5e16cm -3 It is used.

[0382] If the surface after epitaxial growth is intentionally exposed to hydrogen and atomic hydrogen, a neutral surface can be created. However, as the substrate temperature rises, hydrogen exposure causes a layer to form within the epitaxial layer at a depth of Z. 蓄積 (Z 空乏、蓄積 A surface electron storage layer can be created that penetrates to the ) layer. Conversely, when the surface of the grown epitaxial layer is exposed to oxygen by increasing the temperature, a depletion surface is created. Possible scenarios of surface band curvature are shown in Figure 65 as “depletion surface” or “charge storage surface”.

[0383] Figures 65, 66A, and 66B show the effect of surface modification on the β-Ga2O3(-201) drift layer of a device similar to the one shown in Figure 9B using Ni metal contacts. Since the surface of the drift layer is neutral, φ SB The SB potential becomes 1.05 eV, and the depletion surface has a high barrier φ at the heterointerface. SB It has a voltage of 1.3eV, but the surface charge is φ when accumulated. SB This becomes 0.85eV. The results for the forward bias IV are shown in Figure 66A (semi-logarithmic) and Figure 66B (linear) plots.

[0384] The plot shows that the surface state of the drift layer after growth directly affects the diode's turn-on voltage and subthreshold slope.

[0385] Figure 67 shows a comparison of the "clean" and "depleted" surfaces of a β-Ga2O3(-201) drift layer with a range of high work function metals for a device structure similar to that shown in Figure 9B (but with a different contact metal). The clean surface is treated with hydrogen at a rising temperature, while the depleted surface is annealed in oxygen.

[0386] Figure 67 shows the large variation in the possible forward IV curves when metals with various high work functions are deposited on two types of surfaces (depleted or clean). This helps to explain the variation in experimental results for various devices and processing methods.

[0387] Figures 68A and 68B show an exemplary process flow for manipulating the surface charge state of the final surface of an epitaxial oxide layer. The epitaxial oxide layer is intentionally grown in a highly oxidizing environment to form a metal oxide composition at a high growth temperature T_growth. After epitaxial layer growth, the metal source is abruptly removed from the growth region, a step referred to as “growth cessation.” Oxygen and reactive oxygen species in the growth chamber can be in the range of 1e-6 to 1e-4 torr, and a finite amount of time is required to evacuate the epitaxial layer surface from the chamber so that it does not substantially interact with it. The substrate can be cooled with a ramp plate, which can result in lower or higher temperatures. In one example, the growth temperature is reduced to a low idle value, while the ambient gas environment is substantially oxygen.

[0388] In this example, the epitaxial layer surface may be modified to exhibit a depletion surface charge density. In another example, once epitaxial layer growth stops, the oxidizing gas is removed and replaced with an alternative gas species, or there is no gas species at all. The alternative gas species may be nitrogen or argon, such that the surface does not substantially interact with the gas during the ramp to idle. In yet another example, the grown epitaxial layer is kept at a high or low temperature while the chamber gas is replaced with a non-oxidizing hydrogen-like species, such as hydrogen, a forming gas or hydrogen plasma, or methane. In yet another example, the surface may be exposed to hydrogen and oxygen or hydrogen peroxide or hydrocarbons. During the ramp to idle, the hydrogen-like species may be maintained or pumped out.

[0389] After the surface charge state is achieved, the epitaxial layer article may be transferred to another chamber under vacuum or remain in the growth chamber for subsequent in-situ direct metal deposition. The metal deposition may be a high work function metal deposited directly onto the surface where the epitaxial layer charge state has been modified. In one example, a nickel fusion source is used to deposit pure Ni directly onto a β-Ga2O3(-201) surface in a UHV environment. In one example, the Ni may form an epitaxial, Ni(111)-oriented first metal layer directly onto a hexagonal β-Ga2O3(-201) surface. The surface electronic charge of β-Ga2O3(-201) can be maintained by the in-situ Ni(111) cap. Subsequent off-situ processing may involve depositing additional metal(s) to thicken the contact layer to increase mechanical strength and / or conductivity.

[0390] In some cases, a Ni-oxide layer can be formed directly on the oxygen-terminated β-Ga2O3(-201) surface, followed by the formation of a Ni metal cap.

[0391] Figure 69 illustrates the direct deposition of an epitaxial Ni metal contact layer (SB) onto a semiconducting β-Ga2O3(-201) surface ("Semi"). A monolayer of oxygen (OI) can be used on the O-terminal surface to form a linkage bond to the nickel (M) metal contact (SB). In some cases, a thick, intentional deposition of NiO can be formed before the Ni metal cap is formed. Structures similar to those shown in Figure 69 are also possible. In some cases, any of the metallic materials used in the Schottky metals described herein can form an oxide at the interface between the drift layer and the Schottky metal layer. For example, any of the metallic materials in Figure 11A can form an oxide containing the metal species and oxygen (e.g., PtO2) at the interface between the drift layer (e.g., including Ga2O3 or other epitaxial oxide materials) and the metal layer (Schottky contact). In some cases, the oxide of the metal forming the Schottky barrier can form an intermediate layer, as described herein. In some cases, the metal oxide forming the Schottky barrier may be thicker than the example shown in Figure 69. For example, it may have a thickness within the range of intermediate layers described herein.

[0392] The devices, structures, and methods described herein may include in-situ single-crystal Ni(111) oriented films deposited directly onto a β-Ga2O3(-201) surface at low temperatures and high vacuum <1e-8 torr.

[0393] Furthermore, many other possible configurations exist for implementing an intermediate layer (IL) or drift layer containing a UWBG oxide composition.

[0394] Figures 70A to 70G show experimental examples of epitaxial structures comprising an epitaxial β-Ga2O3(-201) layer and an epitaxial Ni(111) layer formed on a SiC(0001) substrate. The Ni(111) layer in this example was 20 nm thick. The epitaxial structure in this example was formed using MBE employing the techniques described herein, for example, method Z10G-10000 in Figure 57G, or methods Z21-21010 and Z21-21020 in Figures 68A to 68B.

[0395] Figure 70A schematically shows a multilayer epitaxial structure 70100, which includes a SiC substrate 70105, an epitaxial semiconducting oxide layer 70110, an epitaxial metal layer 70115, an optional further contact layer 70120 to the metal layer 70115, and an optional contact layer 70125 to the substrate 70105.

[0396] Figure 70B shows the highly symmetrical surface inplane azimuth (φ=203) of structure 70205, which includes a single-crystal epitaxial β-Ga2O3(-201) oriented layer on the outermost surface, formed on an n-type Si polar 4H polytope SiC(0001) substrate that has been miscut at 4 degrees. o The RHEED image 70200 of the diffractogram is shown. The single-crystal high-quality oxide film is indicated by elongated, thin RHEED streaks in Figure 70B.

[0397] Figure 70C shows the same high-symmetry surface inplane azimuth (φ=203) of structure 70215, which includes a single-crystal epitaxial metallic Ni(111) oriented layer directly deposited on the single-crystal epitaxial β-Ga2O3(-201) oriented surface of structure 70205. о ) The RHEED image 70210 of the diffractogram is shown. The single-crystal high-quality metal film is indicated by elongated, thin RHEED streaks in Figure 70C.

[0398] Figure 70D shows a highly symmetrical surface in-plane azimuth (φ=233) of the same structure 70205 as in Figure 70B, including a single-crystal epitaxial β-Ga2O3(-201) oriented surface directly deposited on a 4-degree miscut n-type Si polar 4H polytope SiC(0001) substrate. о The RHEED image of the diffractogram 70300 is shown. The single-crystal high-quality oxide film is again indicated by elongated, thin RHEED streaks as shown.

[0399] Figure 70E shows the same high-symmetry surface in-plane azimuth (φ=233) of structure 70215, including a single-crystal epitaxial metallic Ni(111) oriented surface directly deposited on the single-crystal epitaxial β-Ga2O3(-201) oriented surface of structure 70205. o The RHEED image 70310 of the diffractogram is shown. The single-crystal high-quality metal film is again shown by elongated, thin RHEED streaks as indicated.

[0400] The RHEED results are shown in Figures 70C and 70E, and the periodicity of the surface azimuth RHEED diffractogram is Δφ=60, indicating a Ni(111) orientation film containing face-centered cubic crystals. o Confirm that it occurs each time.

[0401] Figures 70F and 70G show wide-angle X-ray diffraction plots 70400 and high-resolution X-ray diffraction plots 70500, respectively, of the completed multilayer structure 70215, which includes an epitaxial Ni(111) layer formed on an epitaxial β-Ga2O3(-201) layer formed on a Si polar 4H polytope SiC(0001) substrate. Inset 70505 shows the atomic structure of the Ni(111) oriented surface. The high-resolution X-ray diffraction plot 70500 in Figure 70G includes thickness fringes of the Ni(111) peak, indicating a high-quality interface and a low-surface-roughness structure 70215.

[0402] Figures 70B to 70G clearly show Bragg diffraction patterns of phase-pure (or single-phase) semiconducting oxides and Ni metals, which exhibit consistent epitaxial relationships between the deposited layers, as observed in the RHEED and X-ray diffraction results.

[0403] Figures 71A, 71B, 72, and 73 disclose a range of suitable UWBG semiconducting oxide compositions that are possible and advantageous for improving the performance of semiconductor devices, such as high-power devices and diodes.

[0404] Generally, any of the materials described herein (for example, any of the compositions of materials 1 to 7, (Mg x Zn 1-x )(Al y Ga 1-y )2O4 (wherein the formula, 0≦(x,y)≦1) or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein the formula 0≦(x,y,z)≦1), or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4(wherein 0≦(x,y,z)≦1), or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein the formula 0≦(p,x,y,z)≦1)) can be used for drift layers, intermediate layers, and other layers of the devices, structures, and methods described herein.

[0405] For example, Figure 71A discloses possible bandgap ranges for compositions in the form of zinc-gallium oxide and zinc-aluminum oxide. The spinel structures ZnGa2O4 and ZnAl2O4 exhibit SG=Fd3m and are deposited as (111) oriented films on β-Ga2O3(-201) or C-plane 4H-SiC.

[0406] In another example, Figure 71B discloses possible bandgap ranges for compositions in the form of magnesium-gallium oxide and magnesium-aluminum oxide. The spinel structures MgGa2O4 and MgAl2O4 exhibit SG=Fd3m and are deposited as (111) oriented films on β-Ga2O3(-201) or C-plane 4H-SiC.

[0407] In other examples, Figures 72 and 73 show quaternary composition oxide materials that can be used for drift layers, intermediate layers, and other layers in the devices, structures, and methods described herein.

[0408] Figure 73 shows the possible band gap variations for magnesium-zinc-gallium oxide and magnesium-zinc-aluminum oxide.

[0409] Figure 74 shows the possible band gap variations for magnesium-aluminum-gallium oxide and zinc-aluminum-gallium oxide.

[0410] In some cases, the drift layer, intermediate layer, and other layers of the devices, structures, and methods described herein may contain (Mg x Zn 1-x )(Al y Ga 1-y This can include spinel forms (SG=Fd3m) of 2O4 (wherein the formula 0≦(x,y)≦1), and when a composite oxide is formed, it can be realized as an intrinsically p-type or n-type conductive form (without impurity doping), thereby reducing the need for impurity doping. In another form, spinel can be deposited as a (111) oriented film on β-Ga2O3(-2O1) or C-plane 4H-SiC.

[0411] In one example, (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4(wherein 0≦(x,y,z)≦1), or (Mg x Ni 1-x ) z (Aly Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦(x,y,z)≦1) forms a composite oxide (for example, having a spinel structure (SG=Fd3m)), and in the structures and devices described herein, by being used as an intrinsic, p-type, or n-type conductivity type (without impurity doping), the need for impurity doping can be reduced. In another form, the spinel can be deposited as a (111)-oriented film on β-Ga2O3(-201) or C-plane 4H-SiC in the structures and devices described herein.

[0412] Other SG forms, that is, Ga2O3 (for example, α-phase or β-phase); (Al x Ga 1-x )2O3 (for example, α-phase or β-phase) (wherein 0≦x≦1); Mg x Ga 2(1-x) O 3-2x (wherein 0≦x≦1); Mg x Al 2(1-x) O 3-2x (wherein 0≦x≦1); (Mg x Zn 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Zn x Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Zn x Al y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Mg x Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Mg x Al y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Ni x Ga y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); Ni xAl y O z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1); (Ni x Mg 1-x ) y Ga 2(1-y) O 3-2y (wherein 0<x<1 and 0<y<1); or (Mg x Ni 1-x ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦x≦1, 0≦y≦1, and 0≦z≦1), or (Ni z Mg x Zn 1-x-z )(Al y Ga 1-y )2O4 (wherein 0≦(x,y,z)≦1), or (Zn p Mg x Ni 1-x-p ) z (Al y Ga 1-y ) 2(1-z) O 3-2z (wherein 0≦(p,x,y,z)≦1) can also be used in the materials, structures and devices described in the present specification.

[0413] Yet another aspect of the heterojunction β-Ga2O3(-201) / 4H-SiC(0001) relating to the doping density of SiC is disclosed.

[0414] In FIGS. 74 and 75, consider a diode formed as shown as a β-Ga2O3(-201) epilayer deposited on a 4H-SiC(0001) layer or substrate on the Si-polar axis with structure 75-28010 showing the anode contact (A) and the cathode contact (K). Further, the oxide is n-type and doped to a concentration of 1e17cm-3, while the n-type doping concentration of the 4H-SiC layer varies

[0415] [Equation]

[0416] That's what I think. Figure 74 shows the complete conduction and valence band structure as a function of the growth direction. The conduction band heterointerface is magnified in Figure 75, showing the depletion effect in the junction extending into the SiC region. In this case, low

[0417]

number

[0418] For example, in the diode structure shown in Figure 9C, a large potential barrier is generated, which can significantly affect device performance.

[0419] Therefore, it can be advantageous to control the doping density of the SiC (substrate or layer) by controlling the epitaxy process used to fabricate the structure. For example, a highly conductive 4H-SiC substrate can be prepared for epitaxial oxide growth. While the SiC substrate is heated in a vacuum to the required growth temperature, the surface of the SiC substrate may change its surface charge density and desorb potential impurity dopants. This can significantly reduce the 4H-SiC surface donor density, potentially creating a remarkably large depletion region extending into the SiC material. As a result, the on-resistance of the diode may become higher, and electrical losses may increase.

[0420] In some cases, the SiC substrate is heated to the required growth temperature in an environment that avoids changes in surface charge density. For example, the SiC substrate may be heated in an inert environment or under a Si flux to prevent Si desorption.

[0421] Those skilled in the art may not fully understand that heterojunctions formed at the interface between two different oxide materials can also form complex interactions. Metal-[oxide-semiconductor] junctions, as described above, can form Schottky barrier contacts or ohmic contacts. Heterojunctions between two oxides with different bandgap energies, compositions, electron affinities, and even different dielectric constants directly affect the properties near the heterojunction.

[0422] Figure 76 shows a simplified cross-sectional physical structure of a drift oxide semiconductor with a portion of the drift oxide surface where metal is deposited along the A-A' direction parallel to the growth direction z. Similarly, the above-mentioned isolation layer (see Figures 79-86), which functions as a dielectric insulator between the field plate and the oxide drift layer, is also formed along a portion of the oxide drift surface in the B-B' direction, as shown. Thickness t of the isolation layer (ISO) isо And the thickness of the drift layer t ドリフト This is shown. E g1 <E g2 Assuming that the separation layer further contains an oxide material composition having a wider band gap energy than the drift layer oxide composition, the equivalent energy band diagram along the B-B' direction is shown in Figure 77.

[0423] Figure 77 is a plot of the spatial energy band diagram of a heterojunction formed between oxide semiconductor drift and a heterogeneous oxide or material region that forms a separation region. Spatial conduction band diagram E C The left side of (z) corresponds to the drift layer, and the right side corresponds to the separation layer, with the Fermi energy E in equilibrium state. F It lies between two possible first electron quantization states within an inverted potential well located at the heterointerface.

[0424] E F If is located above the first quantized electronic state, the heterointerface two-dimensional electron gas is surface charge N s intis present at >0, which may form a negative charge sheet at the interface. This charge sheet, which may be continuous or discontinuous depending on the surface roughness at the interface, represents a surface leakage path that is detrimental to the operation of vertical conductive devices. This can be utilized in lateral transport devices.

[0425] Conversely, E F is located below the first quantized electronic state, the heterointerface does not accumulate surface charges N S =0, and thus can function as a suitable blocking barrier.

[0426] Furthermore, a further aspect specific to the interaction between abrupt interfaces between dissimilar oxide material compositions is the possible large variation in dielectric constant and the resulting large dielectric constant discontinuity at the heterointerface (Δε=ε ドリフト -ε iso ). The dielectric confinement (anti-confinement) effect can increase (decrease) the Coulomb interaction between charge carriers located at or near the discontinuity.

[0427] For example, when the drift layer comprises Ga2O3 and the separation layer is a low-k dielectric constant material, Δε=ε ドリフト -ε iso >0. Alternatively, in another example, when the drift layer comprises Ga2O3 and the separation layer is a high-k dielectric constant material, Δε=ε ドリフト -ε iso <0.

[0428] Figure 78A tabulates the calculated static and optical dielectric constants for several exemplary UWBG oxide materials suitable for incorporation into the present disclosure. Some materials have properties that depend on the crystallographic orientation.

[0429] The concepts of dielectric confinement and screening are treated herein with specific reference to the boundary between two slabs of oxide materials with dissimilar dielectric constants.

[0430] Figures 78B and 78C plot electrostatic equipotential lines between two equal-quantity, opposite-sign charge regions placed in slabs of different dielectric constants of the host material, separated by a distance of 0.5 units in the x-direction. Figure 78B provides the case where the dielectric constants are equal between both the left (ε1) and right (ε2) slabs. Symmetrical equipotential lines are shown. However, in Figure 78C, where the ratio ε2 / ε1 = 10 is shown, the equipotential lines are highly asymmetric across the heterodielectric interface with respect to the potential screened in the higher dielectric constant slab.

[0431] From Figures 78B and 78C, the electric field strengths shown in the contour plots of Figures 78D and 78E, respectively, are calculated. The electric field screening effect in the high-dielectric region is shown. The quantitative value of the electric field vector is calculated near the heterodielectric interface and is shown in Figures 78F and 78G.

[0432] Figure 78F shows the electric field E X (E Y This shows the spatial variation of the x and y components of ). When both halves of the structure have equal dielectric constants and ε2 / ε1=1, E along the interface X Ingredients and E Y The symmetry of the components is shown in three cases: at the interface x=0, and on both sides with small amounts (x=+ / -0.005 units). As expected, the symmetry of the curve reflects equiquantity of oppositely charged charges.

[0433] Figure 78G shows a simulation for the case ε2 / ε1=10, in which the electric field within the high dielectric region is substantially screened as shown. This phenomenon can be utilized in this disclosure to engineer the maximum electric field generated within the device structure due to manufacturing-induced geometric shape effects. For example, sharp edges typically formed around metal contacts by photolithography, lift-off, or etching can generate unfavorable fringing electric fields. Therefore, it is desirable to control these fringing electric fields with sharp metallic features, as the electric field may exceed the yield strength of the oxide electric field.

[0434] Figures 79 and 80 show two-dimensional electrostatic models of two types of vertical multilayer semiconductor devices used to form Schottky barrier diodes.

[0435] Two similar structures are shown, distinguished by the thickness between the field plate (FP) overhang region and the final surface (F4) of the drift region. The SiC substrate F3 is electrically conductive, while the isolated region F2 is given the property of having a dielectric constant that can be selected differently from the drift layer, although it has a bandgap energy beyond the drift region. Region F1 is taken as air, and the drift region F4 is Ga2O3 with a low charge density. The gap between the FP and the drift region is 0.4 units in the longitudinal direction of the model in Figure 79 and 0.05 units in the longitudinal direction of the model in Figure 80. Furthermore, the Schottky metal contact is depicted as a split field plate, with the left side having no field plate overhang. This allows for comparison of designs with and without a field plate in the same simulation. The contribution of the FP to the overall device capacitance is greater in small gap configurations, which is important for high-speed switching applications.

[0436] Figures 81 and 82 show the magnitude of the spatial electric field calculated as contour lines between a thin FP biased at +1000V and the rear contact at -1000V. Dielectric constants in all regions were considered, and Figure 81 is ε ISO / ε ドリフト It has =0.2, and Figure 82 is ε ISO / ε ドリフト It has =3.

[0437] Figures 83 and 84 show enlarged views of the “thick” FP (Functional Product) of the electrostatic field contour lines for low-k and high-k, respectively.

[0438] Figures 85 and 86 show magnified views of the "thin" FP (Functional Product) of the electrostatic field contour lines for low-k and high-k, respectively.

[0439] The quantitative potential energy near the horizontal interface of the drift layer in contact with the metal contact and the separation layer was calculated. Figures 87 and 88 plot the cases of thin FPs with low-k and high-k separation materials, respectively. The potential is maximum at the metal interface, slightly lower near the contact, but located slightly below the interface. The lateral magnitude of the FP indicates that the potential is maintained for high-k separation materials, but decreases rapidly for low-k separation materials.

[0440] The spatial magnitude of the electric field near the interface is plotted in Figures 89 and 90 for thin fission products (FPs) with low-k and high-k separating materials, respectively. The large peak in the electric field located at the metal contact corner and the effect of lateral FPs are clearly evident. The results indicate that the high-k separating layer is effective in reducing the peak electric field at the metal contact critical point.

[0441] Further analysis of the split FP structure allows for a direct comparison of the maximum electric field generated at the interface between the drift layer and the metal contact.

[0442] Figures 91 and 92 are plots of the spatial variation of the magnitude of the electric field generated at the heterointerface within the structure of three horizontal planes slightly above and below the heterointerface between the drift layer and the separation layer. The device structure is the spacing between the thin field plate / separation layer / drift layer.

[0443] Figure 91 plots the maximum electric field within the structure at the drift layer and metal contact interface region as a function of the dielectric constant used in the separation material, for the cases of "without field plate" and "with field plate". It is shown that FP reduces the maximum electric field for all cases of separation layer dielectric constant, either lower or higher than that of the drift layer material. ISO / ε ドリフトWhen the value exceeds >4, the return decreases, and as an alternative, a simple metal-mesa type contact can provide superior performance by being accompanied by a conformal high-k dielectric. Alternatively, a high-k isolation layer can be deposited, and then the region for defining the Schottky metal contact can be etched. Figure 92 further investigates the ratio γ of the maximum electric field with and without FP by defining it as follows:

[0444]

number

[0445] The greatest advantage of FP is supported in Figure 92 by the minimum value of ratio γ when the ratio of dielectric constants between the isolation layer and the drift layer is in the range of approximately 0.5 ≤ κ ≤ 2.0. In this range, a reduction of approximately 45% in the maximum electric field is possible. For high-k isolation materials, i.e., κ > 3.0, dielectric confinement and screening prevail, reducing the usefulness of FP, and simple metal mesa-type contacts become more efficient.

[0446] In various embodiments, the results of the above investigations of the isolation layer material and the effects of FP may be taken into consideration when optimizing the diode design according to this disclosure.

[0447] Figure 93 shows a two-dimensional electrostatic model used to investigate simple metallic mesa-type Schottky contacts embedded in isolation materials of various dielectric constants.

[0448] Figure 94 plots the results of calculations for drift and the maximum surface electric field strength at the metal / separation layer interface. By utilizing a separation layer material selected for its high dielectric constant, the peak surface electric field can be reduced by an order of magnitude. High dielectric materials with a band gap larger than the drift region and a dielectric constant far exceeding that of Ga2O3 can be found in rare earth oxides, titanium oxide, and the like. Of interest are rare earth oxides, which can be alloyed with aluminum to increase the effective band gap while maintaining a high dielectric constant.

[0449] Of particular note is nickel oxide, which exhibits a high dielectric constant at low bandgap energies.

[0450] Figure 95 shows a photograph of a partially completed Schottky barrier diode formed on a Ga2O3 epitaxial layer deposited on a 4H-SiC substrate. The Schottky barrier metal is Ni, and the contacts were thickened using a second metal, Al. The rear ohmic contacts are untreated, demonstrating the transparency of the substrate.

[0451] In some embodiments, the structures and devices described herein include a “T-channel” design, which can further improve the operating characteristics of the epitaxial oxide / Schottky metal devices described herein.

[0452] As mentioned above, the dielectric constant of the materials incorporated into the device structure determines the electrostatic behavior of the device under high (or strong) electric fields. Furthermore, as described herein, the surface electric field can be engineered at the oxide drift layer and metal interface using a separator layer surrounding the Schottky metal contacts. For example, the surface electric field can be minimized at the critical point of the Schottky metal contacts by using a separator layer material with a high dielectric constant.

[0453] Figure 96A shows an alternative device design, referred to herein as the “T-channel” design. The rear contact 96132 (F4) is fabricated on the SiC substrate 96110 (F2), and the oxide semiconductor drift layer 96125 (F6) is shown. In the “T-channel” design, the oxide semiconductor channel region 96120 (F3), with a Schottky metal layer 96130 (F5), is formed within a mesa-type structure (e.g., by etching of a selective area). In some cases, the oxide semiconductor drift layer 96125 has a higher doping density than the oxide semiconductor channel region 96120. The high doping density of the oxide semiconductor drift layer 96125 may be advantageous, for example, in reducing the on-resistance of the device. The doping density of the oxide semiconductor channel region 96120 can be adjusted to create a Schottky junction with tunable properties (e.g., having a desired depletion width). Therefore, the doping density of the oxide semiconductor channel region 96120 can be either higher or lower than the doping density of the drift layer 96125, depending on the desired Schottky junction characteristics. Sidewall layers 96180 (F7 and F8) are formed around the mesa-type structure. Sidewall layers 96180 (F7 and F8) can surround the mesa-type structure. Sidewall layers 96180 (F7 and F8) can be in physical contact with one or more walls 96122 and 96124 of the mesa-type structure. The walls 96122 and 96124 of the mesa-type structure include the interface between the oxide semiconductor channel region 96120 and the Schottky metal layer 96130. The field plate layer 96190 (F9) may be on the outermost surface of the Schottky metal layer 96130 and may extend laterally (i.e., in the x-direction) beyond the Schottky metal layer 96130 (and also extend laterally beyond the mesa structure), as may be on the outermost surface of the sidewall layer 96180 (as shown in Figure 96A). The Schottky metal layer 96130 may contain any of the suitable metals described herein, e.g., Figure 11A (i.e., Cu, Te, Be, Rh, Co, C, N, Ni, Au, Ir, Pd, Pt, Se, or Os), or any alloy of the metals in Figure 11A.Furthermore, in some cases, the substrate 96110 is a composite substrate including a surface layer and a bulk substrate layer (for example, the bulk substrate layer 112 and surface layer 114 of the substrate 110 in Figure 1), and the surface layer includes single-crystal SiC.

[0454] For example, the mesa-type structure in Figure 96A includes an oxide semiconductor channel region 96120 and a Schottky metal layer 96130, and may have a circular cross-section, with the sidewall layer 96180 surrounding (or encircling) an annular mesa-type structure. In such an example, the walls 96122 and 96124 (or sidewalls) are the ...

Claims

1. A multilayer semiconductor diode device, A substrate containing silicon carbide (SiC), An epitaxial drift layer comprising a first semiconductor oxide material, wherein the epitaxial drift layer is located above the substrate with respect to the growth direction, A polar nitride layer comprising a polar semiconductor nitride material, wherein the polar nitride layer is located above the epitaxial drift layer with respect to the growth direction, A metal layer located above the polar nitride layer with respect to the aforementioned growth direction, The multilayer semiconductor diode device comprising the above-mentioned features.

2. The multilayer semiconductor diode device according to claim 1, wherein the metal layer includes a high work function metal such that a Schottky barrier is formed between the metal layer and the polar nitride layer.

3. The multilayer semiconductor diode device according to claim 2, wherein the metal layer comprises a metal selected from the metals shown in Figure 11A, or an alloy thereof.

4. The multilayer semiconductor diode device according to claim 2, wherein the metal layer is an epitaxial metal layer.

5. The multilayer semiconductor diode device according to claim 1, wherein the substrate and the first semiconductor oxide material are configured such that there is substantially no barrier to the flow of electrons from the substrate to the first semiconductor oxide material.

6. The multilayer semiconductor diode device according to claim 1, further comprising an epitaxial transition layer containing a third semiconductor oxide material or SiC, wherein the epitaxial transition layer is located between the substrate and the epitaxial drift layer.

7. The multilayer semiconductor diode device according to claim 6, wherein the epitaxial transition layer further includes a lattice constant different from that of the substrate.

8. The multilayer semiconductor diode device according to claim 6, wherein the epitaxial transition layer further includes a band gap different from the band gap of the substrate.

9. The multilayer semiconductor diode device according to claim 6, wherein the substrate comprises a first doping density, the epitaxial transition layer comprises a second doping density, and the epitaxial drift layer comprises a third doping density, wherein the first doping density is greater than the second doping density, and the second doping density is greater than the third doping density.

10. The multilayer semiconductor diode device according to claim 6, wherein the epitaxial transition layer further includes a variable doping density that varies in the longitudinal direction perpendicular to the outermost surface of the substrate.

11. The multilayer semiconductor diode device according to claim 1, wherein the epitaxial drift layer is doped in the n-type, the polarization axis of the polar semiconductor nitride material is aligned with the growth direction such that the polar nitride layer contains p-type charges, and the polar nitride layer and the epitaxial drift layer form a p / n junction.

12. The first semiconductor oxide material is Ga ２ O ３ The polar semiconductor nitride material is Al ０．３ Ga ０．７ A multilayer semiconductor diode device according to claim 1, comprising N.

13. On the polar nitride layer, a separation layer surrounding the metal layer, comprising a material having a dielectric constant higher than the dielectric constant of the first semiconductor oxide material, A field plate located on the outermost surface of the metal layer, comprising metal, extending laterally beyond the metal layer onto the outermost surface of the separation layer, A multilayer semiconductor diode device according to claim 1, further comprising the features described in claim 1.

14. A first mesa-type structure comprising the polar nitride layer and the metal layer, A sidewall layer comprising a dielectric material, wherein the sidewall layer is located on the epitaxial drift layer, contacts the wall portion of the first mesa-type structure, and the dielectric constant of the dielectric material is higher than the dielectric constant of the first semiconductor oxide material, and the sidewall portion A multilayer semiconductor diode device according to claim 1, further comprising the features described in claim 1.

15. Further comprising a second mesa-type structure and interconnection section, The first mesa-type structure includes a first portion of the polar nitride layer and a first portion of the metal layer. The second mesa-type structure includes a second portion of the polar nitride layer and a second portion of the metal layer, The aforementioned side wall layer further contacts the wall portion of the second mesa-type structure, The multilayer semiconductor diode device according to claim 14, wherein the first portion of the metal layer and the second portion of the metal layer are coupled to the interconnection portion.

16. A method for forming a multilayer semiconductor diode device, A substrate containing silicon carbide (SiC) is provided, Forming an epitaxial drift layer containing a first semiconductor oxide material on the substrate, Forming an epitaxial polar nitride layer containing a polar semiconductor nitride material on the epitaxial drift layer, Forming a metal layer on the epitaxial polar nitride layer, wherein the metal layer and the epitaxial polar nitride layer form a Schottky barrier junction, The method, including the method described above.

17. The method according to claim 16, further comprising forming a template layer containing a second nitride material on the surface of the epitaxial drift layer before forming the epitaxial polar nitride layer on the epitaxial drift layer.

18. The method according to claim 17, wherein the second nitride material of the template layer is formed by exposing the surface of the epitaxial drift layer to an active nitrogen species by increasing the temperature.

19. A multilayer semiconductor diode device, A substrate containing silicon carbide (SiC), An epitaxial drift layer comprising a first semiconductor oxide material, wherein the epitaxial drift layer is located above the substrate with respect to the growth direction and is doped in an n-type manner, A template layer comprising a nitride template material, wherein the template layer is in contact with the epitaxial drift layer, A polar nitride layer comprising a polar semiconductor nitride material, wherein the polar nitride layer is in contact with the template layer, the polarization axis of the polar semiconductor nitride material is aligned with the growth direction such that the polar nitride layer contains p-type charges, and the polar nitride layer and the epitaxial drift layer form a p / n junction, A metal layer is placed above the aforementioned polar nitride layer, The multilayer semiconductor diode device comprising the above-mentioned features.

20. The multilayer semiconductor diode device according to claim 19, wherein the template layer has a thickness of 1 nm to 100 nm, and the polar nitride layer has a thickness of 100 nm to 5 microns.

21. The multilayer semiconductor diode device according to claim 19, wherein the metal layer includes a high work function metal such that a Schottky barrier is formed between the metal layer and the polar nitride layer.

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