Gate trench power semiconductor device with deep support shield and method for fabricating such device

Abstract

The semiconductor device comprises a silicon carbide-based semiconductor layer structure including a drift layer having a first conductivity type; a gate trench extending to a first depth into the upper surface of the semiconductor layer structure; a gate electrode located within the gate trench; a support-shield trench extending to a second depth shallower than the first depth into the upper surface of the semiconductor layer structure; and a source metallization layer located on the upper surface of the semiconductor layer structure and extending into the support-shield trench.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 18 / 482,097, filed on 6 October 2023, the entirety of which is incorporated herein by reference.

[0002] The present invention relates to power semiconductor devices, and more particularly to power semiconductor devices having gate trenches, and to methods for manufacturing such devices. [Background technology]

[0003] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a well-known type of semiconductor transistor that can be used as a switch. A MOSFET is a three-terminal device having a gate terminal, a drain terminal, a source terminal, and a semiconductor body. In this specification, the semiconductor body is referred to as a “semiconductor layer structure” and may contain one or more semiconductor layers / regions. Within the semiconductor layer structure, a source region and a drain region are formed, separated by a channel region. The gate electrode (which can function as a gate terminal or be electrically connected to a gate terminal) is positioned adjacent to the channel region and separated from it by a thin oxide layer. A MOSFET can be turned on or off by setting the bias voltage applied to the gate electrode to be above or below a threshold. When a MOSFET is on (i.e., in the “on state”), current flows through the channel region between the source and drain regions. When the bias voltage is reduced below the threshold level, current stops flowing through the channel region.

[0004] An n-type MOSFET has a source and drain region having n-type (electron) conductivity, and a channel region having p-type (hole) conductivity (i.e., an "npn" design). When a gate bias voltage sufficient to generate a conductive n-type inversion layer in the p-type channel region is applied to the gate electrode, the n-type MOSFET turns on, thereby electrically connecting the n-type source and drain regions and enabling majority carrier conduction between them. A p-type MOSFET has a "pnp" design (i.e., a p-type source and drain region, and an n-type channel region) and turns on when a gate bias voltage sufficient to generate a conductive p-type inversion layer in the n-type channel region to electrically connect the p-type source and drain regions is applied to the gate electrode. In this specification, the terms "first conductivity type" and "second conductivity type" are used to indicate either n-type or p-type, and are distinct from the first and second conductivity types. Therefore, if a first region of the device has a first conductivity type and a second region of the device has a second conductivity type, this means either the first region has n-type conductivity and the second region has p-type conductivity, or alternatively, the first region has p-type conductivity and the second region has n-type conductivity.

[0005] As described above, the gate electrode of a MOSFET is isolated from the channel region by a thin oxide layer called the gate oxide layer. In certain applications, other non-oxide gate dielectric layers may be used instead of the gate oxide layer. It will be understood that the techniques according to the embodiments of the present invention described herein are equally applicable to devices having gate dielectric layers formed from non-oxide materials.

[0006] Because the gate electrode of a MOSFET is isolated from the channel region by the gate oxide layer, a minimal gate current is sufficient to maintain the MOSFET in the ON state or to switch it between the OFF and ON states. Since the gate forms a capacitor with the channel region, the gate current during switching is kept low. Therefore, only minimal charge / discharge current is required during switching, allowing for a simpler gate drive circuit and faster switching speeds. MOSFETs may be standalone devices or combined with other circuit devices. For example, an insulated gate bipolar transistor ("IGBT") is a semiconductor device that includes both a MOSFET and a bipolar junction transistor ("BJT"), combining the high-impedance gate electrode of the MOSFET with the low on-state conduction loss that can be achieved by the BJT. An IGBT may be implemented, for example, as a Darlington pair with a high-voltage n-channel MOSFET at the input and a BJT at the output. The basic current of the BJT is supplied through the MOSFET channel, which allows for a simplified external drive circuit (since the drive circuit only charges and discharges the gate electrode of the MOSFET).

[0007] In some applications, MOSFETs may need to carry large currents and / or block high voltages. Such MOSFETs are often called “power” MOSFETs. Power MOSFETs are often fabricated from wide-bandgap semiconductor materials (in this specification, the term “wide-bandgap semiconductor” encompasses any semiconductor having a bandgap of at least 1.4 eV). Power semiconductor devices are often formed from silicon carbide ("SiC": silicon carbide), which has several advantageous properties, including, for example, high field dielectric strength, high thermal conductivity, high electron mobility, high melting point, and high saturation electron drift rate.

[0008] Power semiconductor devices such as power MOSFETs may have a lateral or vertical structure. In devices with a lateral structure, the device terminals (e.g., drain terminal, gate terminal, and source terminal for a power MOSFET) are located on the same main surface (i.e., top or bottom) of the semiconductor layer structure. In contrast, in devices with a vertical structure, at least one terminal is provided on each main surface of the semiconductor layer structure (for example, in a vertical MOSFET, the source and gate may be on the top surface of the semiconductor layer structure, and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include a substrate such as a growth substrate.

[0009] The semiconductor layer structure of a power semiconductor device typically includes an "active region" on which one or more functional semiconductor devices are formed. The active region acts as a primary junction for blocking voltage during reverse bias (off-state) operation and allowing current to flow during forward bias (on-state) operation. Power semiconductor devices may also have edge termination structures, such as guard rings or junction termination extensions, in the termination regions of the semiconductor layer structure adjacent to (usually surrounding) the active region. Edge termination structures can, among other things, reduce electric field concentration effects that may occur at the outer edges of the power semiconductor device. Typically, multiple power semiconductor devices are formed in / on a common wafer, and each power semiconductor device will usually have its own edge termination structure. After the wafer is fully processed, the resulting structure can be diced to isolate individual edge-terminated power semiconductor devices. Each power semiconductor device may have a unit cell structure, in which the active regions of each power semiconductor device include multiple individual "unit cell" devices that are electrically connected in parallel and function together as a single power semiconductor device.

[0010] Vertical power semiconductor devices, including MOSFETs, can have a planar gate electrode design in which the transistor's gate electrode is formed on top of the semiconductor layer structure, or alternatively, the gate electrode may be embedded in a gate trench within the semiconductor layer structure. MOSFETs with embedded gate electrodes are commonly called gate trench MOSFETs. In a planar gate electrode design, the channel region of each unit cell transistor is located horizontally beneath the gate electrode. In contrast, in a gate trench MOSFET design, the channel is typically located vertically adjacent to the sidewall of the gate electrode. Gate trench MOSFETs can offer performance enhancements but typically require more complex manufacturing processes.

[0011] One failure mechanism of a power MOSFET is the so-called "breakdown" of the gate oxide layer. The gate oxide layer is subjected to high electric fields during normal device operation. The stress on the gate oxide layer caused by these electric fields creates defects in the oxide material, and these defects accumulate over time. When the concentration of defects reaches a critical value, a so-called "percolation path" may be formed through the gate oxide layer, which electrically connects the gate electrode to the source region or the drain region, thereby causing a short circuit that can destroy the device. The "lifetime" of the gate oxide layer (i.e., how long the device can be operated before dielectric breakdown occurs) depends inter alia on the magnitude of the electric field to which the gate oxide layer is subjected and the length of time the electric field is applied. FIG. 1 is a schematic graph showing the relationship between the operating time until dielectric breakdown occurs ("gate oxide lifetime") and the level of the electric field applied to the gate oxide layer. This graph assumes that the same electric field is always applied (which is not necessarily the case). As shown in FIG. 1, when the gate oxide lifetime is plotted on a logarithmic scale, the relationship can in some cases be substantially linear. An important point that can be seen from FIG. 1 is that as the electric field level increases, the lifetime of the gate oxide layer decreases exponentially. Although the lifetime of the gate oxide layer can be extended by increasing the thickness of the gate oxide layer, increasing the thickness of the gate oxide layer is generally not acceptable as a way to extend the lifetime of the gate oxide layer, since various performance parameters of the MOSFET may depend on the thickness of the gate oxide layer.

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0013] According to some embodiments of the present invention, a semiconductor device is provided comprising: a silicon carbide-based semiconductor layer structure including a drift layer having a first conductivity type; a gate trench extending into the upper surface of the semiconductor layer structure to a first depth; a gate electrode located in the gate trench; a support-shield trench extending into the upper surface of the semiconductor layer structure to a second depth shallower than the first depth; and a source metallization layer located on the upper surface of the semiconductor layer structure and extending into the support-shield trench.

[0014] In some embodiments, the semiconductor layer structure further comprises a well contact region having a second conductivity type located beneath the support-shield trench.

[0015] In some embodiments, the semiconductor layer structure further comprises a support shield having a second conductivity type located beneath the well contact region. In some embodiments, the source metallization layer is in direct contact with the well contact region, and the well contact region is in direct contact with the support shield.

[0016] In some embodiments, the semiconductor layer structure further comprises a trench shielding region having a second conductivity type located beneath the gate trench.

[0017] In some embodiments, the semiconductor layer structure further comprises a well region having a second conductivity type located on the upper surface of the drift layer, and a source region having a first conductivity type located on the upper surface of the well region.

[0018] In some embodiments, the source metallization layer within the support shield trench is in direct contact with the side surface of the source region and the upper surface of the well contact region.

[0019] In some embodiments, the well contact region has a first doping concentration of the second conductive dopant that is at least 10 times higher than the second doping concentration of the second conductive dopant in the well region. In some embodiments, the first doping concentration of the second conductive dopant is at least 10 times higher than the third doping concentration of the second conductive dopant in the support shield.

[0020] In some embodiments, the semiconductor layer structure further comprises a source region, and the source metallization layer is in direct contact with both the top and side surfaces of the source region.

[0021] In some embodiments, the support shield extends further down within the semiconductor layer structure than the trench shielding region extends.

[0022] In some embodiments, the well contact region electrically connects the well region to the source metallization layer.

[0023] A semiconductor device is provided comprising a silicon carbide-based semiconductor layer structure, the silicon carbide-based semiconductor layer structure comprising: a drift layer having a first conductivity type; a well region having a second conductivity type located on the upper surface of the drift layer; a source region having the first conductivity type located on the well region; a well contact region having a second conductivity type located within the well region, wherein the upper surface of the well contact region is recessed lower than the upper surface of the source region; and a support shield having a second conductivity type located below the well contact region. The support shield extends into the drift layer. The semiconductor device further comprises a gate trench on the upper surface of the semiconductor layer structure; a gate electrode located within the gate trench; a support shield trench on the upper surface of the semiconductor layer structure; and a metal layer extending into the support shield trench.

[0024] In some embodiments, the semiconductor layer structure further comprises a trench shielding region having a second conductivity type located beneath the gate trench.

[0025] In some embodiments, the well contact region has a first doping concentration of the second conductivity type dopant that is at least 10 times higher than the second doping concentration of the second conductivity type dopant in the well region.

[0026] In some embodiments, the metal layer within the support shield trench is in direct contact with the side surface of the source region and the upper surface of the well contact region.

[0027] In some embodiments, the gate trench extends further down within the semiconductor layer structure than the support shield trench extends.

[0028] In some embodiments, the well contact region has a first doping concentration of the second conductive dopant that is at least 10 times higher than the third doping concentration of the second conductive dopant in the support shield.

[0029] In some embodiments, the metal layer is in direct contact with both the top and side surfaces of the source region.

[0030] In some embodiments, the support shield extends further down within the semiconductor layer structure than the trench shielding region extends.

[0031] In some embodiments, the well contact region electrically connects the well region to the metal layer.

[0032] According to an additional embodiment of the present invention, a semiconductor device is provided comprising a silicon carbide-based semiconductor layer structure, the silicon carbide-based semiconductor layer structure comprising: a drift layer having a first conductivity type; a well region having a second conductivity type located on the upper surface of the drift layer; a source region having the first conductivity type located on the upper surface of the well region; and a well contact region having the second conductivity type located within the well region, which is a portion of the well region having a higher dopant concentration. The upper surface of the well contact region is recessed lower than the upper surface of the source region. The semiconductor device further comprises a gate trench extending to a first depth into the upper surface of the semiconductor layer structure, and source metallization extending between adjacent source regions of unit cell transistors so as to be in direct contact with the well contact region.

[0033] In some embodiments, the semiconductor layer structure further comprises a support shield having a second conductivity type located beneath the well contact region. In some embodiments, the source metallization is in direct contact with the well contact region, and the well contact region is in direct contact with the support shield.

[0034] In some embodiments, the source metallization layer is in direct contact with the sides of the source region.

[0035] In some embodiments, the well contact region has a first doping concentration of the second conductive dopant that exceeds the second doping concentration of the second conductive dopant in the well region and also exceeds the third doping concentration of the second conductive dopant in the support shield.

[0036] In some embodiments, the semiconductor layer structure further comprises a trench shielding region having a second conductivity type below the gate trench, and the support shield extends further down within the semiconductor layer structure than the trench shielding region extends.

[0037] According to additional embodiments of the present invention, a semiconductor device is provided comprising a silicon carbide-based semiconductor layer structure, the silicon carbide-based semiconductor layer structure comprising: a drift layer having a first conductivity type; a well region having a second conductivity type located on the upper surface of the drift layer; a source region having the first conductivity type located on the upper surface of the well region; and a well contact region having the second conductivity type located within the well region, which is a portion of the well region having a higher dopant concentration. These devices further include a source metallization layer in contact with the upper and side surfaces of the source region and in contact with the upper surface of the well contact region.

[0038] In some embodiments, the semiconductor layer structure further comprises a support shield having a second conductivity type located beneath the well contact region. In some embodiments, the source metallization layer is in direct contact with the well contact region, and the well contact region is in direct contact with the support shield.

[0039] In some embodiments, the well contact region has a first doping concentration of the second conductive dopant that exceeds the second doping concentration of the second conductive dopant in the well region and also exceeds the third doping concentration of the second conductive dopant in the support shield.

[0040] In some embodiments, the semiconductor layer structure further comprises a trench shielding region having a second conductivity type below the gate trench, and the support shield extends further down within the semiconductor layer structure than the trench shielding region extends.

[0041] A semiconductor device is provided, comprising: a silicon carbide-based semiconductor layer structure comprising: a drift layer having a first conductivity type; a well region having a second conductivity type located on the upper surface of the drift layer; a well contact region having a second conductivity type extending downward through the well region into the drift layer; a gate trench on the upper surface of the semiconductor layer structure; a gate electrode located within the gate trench; a support-shield trench extending through the well contact region and further downward within the semiconductor layer structure than the well contact region; and a support shield located within the support-shield trench.

[0042] In some embodiments, the support shield is in direct contact with the well contact area.

[0043] In some embodiments, the support shield trenches extend further down within the semiconductor layer structure than the gate trenches.

[0044] In some embodiments, the semiconductor layer structure further comprises a trench shielding region having a second conductivity type below the gate trench, and the support shield trench extends further down within the semiconductor layer structure than the trench shielding region.

[0045] In some embodiments, the well contact region has a first doping concentration of the second conductivity type dopant that is at least 10 times higher than the second doping concentration of the second conductivity type dopant in the well region.

[0046] In some embodiments, the support shield comprises a metal in Schottky contact with doped polysilicon, nickel oxide, or silicon carbide.

[0047] In some embodiments, the semiconductor layer structure further comprises a source region having a first conductivity type located on a well region, and well contact regions are located between the support shield and the well region, and between the support shield and the source region.

[0048] In some embodiments, the well contact region extends through the well region into the drift layer.

[0049] In some embodiments, the well contact region extends into the semiconductor layer structure to at least the same depth as the gate trench.

[0050] According to another embodiment of the present invention, a semiconductor device is provided, comprising a semiconductor layer structure comprising: a drift layer having a first conductivity type; a well region having a second conductivity type located on the upper surface of the drift layer; a well contact region having a second conductivity type extending downward through the well region into the drift layer; and a source region having a first conductivity type located on the upper surface of the well region. These semiconductor devices further comprise a gate trench on the upper surface of the semiconductor layer structure; a gate electrode located within the gate trench; a trench extending into the well contact region; and a conductive material other than silicon carbide located within the trench.

[0051] In some embodiments, the semiconductor layer structure further comprises a trench shielding region having a second conductivity type below the gate trench, and the support shield extends further down within the semiconductor layer structure than the trench shielding region.

[0052] In some embodiments, the conductive material includes a metal in Schottky contact with doped polysilicon, nickel oxide, or silicon carbide.

[0053] In some embodiments, the support shield extends to the top surface of the semiconductor layer structure.

[0054] In some embodiments, the trenches extend further into the semiconductor layer structure than the gate trenches.

[0055] In some embodiments, the trench does not penetrate the bottom surface of the well contact area.

[0056] In some embodiments, the well contact region extends into the semiconductor layer structure to at least the same depth as the gate trench.

[0057] Further embodiments of the present invention provide a method for forming a semiconductor device. These methods provide a silicon carbide-based semiconductor layer structure comprising a drift layer having a first conductivity type. A gate trench is formed extending into the upper surface of the semiconductor layer structure to a first depth. A gate electrode is formed within the gate trench. A support-shield trench is formed extending into the upper surface of the semiconductor layer structure to a second depth shallower than the first depth. A source metallization layer is formed on the upper surface of the semiconductor layer structure and extending into the support-shield trench.

[0058] In some embodiments, the support shield trench is formed before the gate trench is formed.

[0059] In some embodiments, the method further includes forming a well contact region having a second conductivity type below a support shield trench.

[0060] In some embodiments, the method further includes forming a support shield having a second conductivity type below the well contact area.

[0061] In some embodiments, the source metallization layer is in direct contact with the well contact region, and the well contact region is in direct contact with the support shield.

[0062] In some embodiments, the method further includes forming a well region having a second conductivity type on the upper surface of the drift layer, forming a source region having a first conductivity type on the upper surface of the well region, and forming a trench shielding region having a second conductivity type below the gate trench.

[0063] In some embodiments, the source metallization layer within the support shield trench is in direct contact with the sides of the source region and the upper surface of the well contact region.

[0064] In some embodiments, the support shield extends further down within the semiconductor layer structure than the trench shielding region extends.

[0065] In some embodiments, the well contact region has a first doping concentration of the second conductive dopant that is at least 10 times higher than the second doping concentration of the second conductive dopant in the well region and at least 10 times higher than the third doping concentration of the second conductive dopant in the support shield. [Brief explanation of the drawing]

[0066] [Figure 1] This figure shows the relationship between the lifetime of the gate oxide layer and the applied electric field strength, plotted on a semi-logarithmic graph. In some embodiments, the upper surface of the well contact region is lower and recessed compared to the upper surface of the well region. [Figure 2A] This is a schematic top view of a gate-trench silicon carbide power MOSFET according to a specific embodiment of the present invention. [Figure 2B] Figure 2A is a schematic top view of the gate-trench silicon carbide power MOSFET with various upper metal and dielectric layers removed. [Figure 2C] Figures 2A and 2B show schematic cross-sectional views of a gate-trench silicon carbide power MOSFET taken along line 2C-2C in Figure 2A. [Figure 3A] Figures 2A to 2C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 3B] Figures 2A to 2C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 3C] Figures 2A to 2C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 3D] Figures 2A to 2C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 3E] Figures 2A to 2C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 3F] Figures 2A to 2C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 4A] Figures 2A and 2B show schematic cross-sectional views of five modified versions of the gate-trench silicon carbide power MOSFET, with the cross-section taken along line 2C--2C in Figure 2A. [Figure 4B] Figures 2A and 2B show schematic cross-sectional views of five modified versions of the gate-trench silicon carbide power MOSFET, with the cross-section taken along line 2C--2C in Figure 2A. [Figure 4C] Figures 2A and 2B show schematic cross-sectional views of five modified versions of the gate-trench silicon carbide power MOSFET, with the cross-section taken along line 2C--2C in Figure 2A. [Figure 4D] Figures 2A and 2B show schematic cross-sectional views of five modified versions of the gate-trench silicon carbide power MOSFET, with the cross-section taken along line 2C--2C in Figure 2A. [Figure 4E] Figures 2A and 2B show schematic cross-sectional views of five modified versions of the gate-trench silicon carbide power MOSFET, with the cross-section taken along line 2C--2C in Figure 2A. [Figure 5] Figures 2A to 2C are flowcharts illustrating the method for fabricating the gate-trench silicon carbide power MOSFETs shown. [Figure 6]This is a schematic cross-sectional view of a gate-trench silicon carbide power MOSFET according to a further embodiment of the present invention. [Figure 7A] Figure 6 is a schematic cross-sectional view showing the method for fabricating the gate-trench silicon carbide power MOSFET. [Figure 7B] Figure 6 is a schematic cross-sectional view showing the method for fabricating the gate-trench silicon carbide power MOSFET. [Figure 7C] Figure 6 is a schematic cross-sectional view showing the method for fabricating the gate-trench silicon carbide power MOSFET. [Figure 7D] Figure 6 is a schematic cross-sectional view showing the method for fabricating the gate-trench silicon carbide power MOSFET. [Figure 7E] Figure 6 is a schematic cross-sectional view showing the method for fabricating the gate-trench silicon carbide power MOSFET. [Figure 7F] Figure 6 is a schematic cross-sectional view showing the method for fabricating the gate-trench silicon carbide power MOSFET. [Figure 8] Figure 6 is a schematic cross-sectional view showing a modified gate-trench silicon carbide power MOSFET. [Figure 9] This is a schematic cross-sectional view of a trench gate type silicon carbide power MOSFET according to yet another embodiment of the present invention. [Figure 10A] Figure 9 is a schematic cross-sectional view showing a modified gate-trench silicon carbide power MOSFET. [Figure 10B] Figure 9 is a schematic cross-sectional view showing a modified gate-trench silicon carbide power MOSFET. [Figure 11] Figures 2A and 2B show schematic cross-sectional views of another modified version of the gate-trench silicon carbide power MOSFET, with the cross-section taken along line 2C--2C in Figure 2A. [Modes for carrying out the invention]

[0067] Silicon carbide-based vertical power semiconductor devices with gate trenches, such as vertical power MOSFETs and IGBTs, are attractive for many applications because their inherent on-resistivity is relatively low, which can result in more efficient power switching operation. Gate trench vertical power devices exhibit relatively low resistivity during on-state operation because the channel is formed in the sidewall of the gate trench. Furthermore, carrier mobility in the sidewall channel can be approximately 2 to 4 times higher than the corresponding carrier mobility in the horizontal channel of a standard (i.e., non-gate trench) vertical power device, resulting in higher current density during on-state operation and enabling higher switching speeds. The gate trench design also reduces the overall pitch of the device, allowing for increased integration density. The reduced conduction losses (due to lower on-state resistance) and improved switching speeds make gate trench power devices particularly suitable for high-frequency power applications with low to medium cutoff voltage requirements (e.g., 600 to 1200 volts). These devices have relaxed requirements for associated passive components, and relatively simple cooling methods may suffice. Since MOSFETs are the most widely used silicon carbide-based gate trench power semiconductor devices, the following discussion will focus on MOSFET embodiments. However, it will be understood that each of the described embodiments can be implemented using alternative non-oxide gate dielectric layers (e.g., nitrides, high dielectric constant materials, etc.), and that other gate trench power semiconductor devices such as IGBTs and gate-controlled thyristors can be formed using the same techniques.

[0068] As discussed above, gate trench power MOSFETs are prone to oxide reliability issues due to the presence of a high electric field in the gate oxide layer lining the bottom and side walls of the gate trench. This high electric field causes the gate oxide layer to degrade over time, potentially leading to device failure. When a gate trench MOSFET operates in reverse-cut operation (i.e., the MOSFET is in its off state), the MOSFET's source terminal is typically grounded, the gate terminal is typically grounded or placed under a negative bias voltage, and the drain terminal is typically placed under a high positive voltage. During such reverse-cut operation, a high electric field extends upward from the drain terminal (located on the bottom surface of the semiconductor layer structure) towards the top surface of the semiconductor layer structure. Therefore, under reverse-cut operation, the bottom portion of the gate dielectric layer experiences the highest electric field level. Due to the concentration effect of the electric field, the electric field level can be particularly high at the lower "corner" of the gate oxide layer at the bottom edge of the gate trench (i.e., the portion of the gate oxide layer that covers the area where the sidewalls of the gate trench meet the bottom of the gate trench). Furthermore, due to the difference in dielectric constant between silicon carbide and silicon oxide, the electric field within the silicon oxide gate oxide layer can be approximately 2.6 times higher than the electric field within the adjacent silicon carbide semiconductor layer structure. When the electric field reaches a critical level, dielectric breakdown of the silicon oxide occurs. To avoid such dielectric breakdown, the power MOSFET may be operated at a lower drain voltage level during reverse cutoff operation to ensure that the electric field does not reach a level that causes breakdown. In other words, the rated voltage of the power MOSFET may be set to ensure that premature dielectric breakdown of the gate oxide does not occur.

[0069] To reduce the electric field level in the gate oxide layer during reverse blocking operation, a so-called "trench shielding region" (also called a "trench shield" or "bottom shield") is often provided beneath the gate trench of a gate trench power MOSFET. These trench shielding regions are formed by doping a portion of the semiconductor layer structure beneath the gate trench with a dopant having the same conductivity type as the dopant contained in the device's channel region. The trench shielding region is usually formed by one or more ion implantation processes in which p-type dopant ions (in the case of an n-type MOSFET) are implanted through the bottom of the gate trench. The trench shielding region may extend downward from the bottom of the gate trench into the semiconductor layer structure of the device by 0.5 to 1.0 microns or more, and is a region doped to a medium to high concentration. The trench shielding region is electrically connected to the source terminal of the MOSFET by p-type trench shielding region connection patterns. These trench shielding connection patterns may be located within and / or outside the active region of the device.

[0070] Recently, gate trench power MOSFETs have been proposed that include an additional shielding region called a "support shield." The support shield is formed between adjacent gate trenches within the semiconductor layer structure and, like the trench shielding region, may comprise a highly doped semiconductor region having the same conductivity type as the MOSFET's channel region. The support shield may extend, for example, to the same depth as the trench shielding region within the semiconductor layer structure and can be formed by a high-energy ion implantation process. The support shield may be directly connected to the source metallization within the device's active region.

[0071] Adding support shields to gate trench power semiconductor device designs can enhance protection against the gate oxide layer. However, this may reduce the device's "pitch" because it may be necessary to widen the spacing between adjacent gate trenches to accommodate the support shields. Furthermore, adding support shields typically involves several additional processing steps (e.g., mask formation, ion implantation, and / or mask removal), which increases fabrication costs. Therefore, adding support shields to gate trench power semiconductor devices involves trade-offs.

[0072] According to embodiments of the present invention, gate trench silicon carbide power semiconductor devices with improved support shield design are provided. For example, in some embodiments, gate trench silicon carbide power semiconductor devices are provided that include relatively shallow support shield trenches formed on the upper surface of the semiconductor layer structure. The well contact regions of the MOSFET (typically the highly doped portion of the p-well) are formed such that at least a portion of each well contact region is located below the corresponding support shield trench. In this configuration, at least a portion of each well contact region can be recessed below the top surface of the semiconductor layer structure. The support shield is located below the corresponding well contact region. The ion implantation process used to form the support shield can be carried out through the support shield trench, thereby enabling the use of a low-energy ion implantation process. This reduces the amount of damage and struggling to the semiconductor layer structure. Furthermore, since at least a portion of the well contact regions is recessed below the top surface of the semiconductor layer structure, source metallization of the MOSFET can directly contact both the top and side surfaces of the source region of the MOSFET. This configuration works to increase the contact area between the source metallization and the source region. Since the width of the source region is typically defined to ensure a sufficiently low-resistance connection between the source metallization and the source region, directly contacting the source metallization with both the top and sides of the source region allows for a reduced width of the source region while establishing a sufficiently low-resistance connection. Therefore, the above design makes it possible to reduce the device pitch without any performance degradation.

[0073] Further embodiments of the present invention provide gate trench power semiconductor devices having deep support-shield trenches formed within a semiconductor layer structure. The support-shield trenches may extend deeper into the semiconductor layer structure than the gate trenches, and in some embodiments, the support-shield trenches may even extend deeper into the semiconductor layer structure than the trench shielding region formed beneath the gate trenches. The support-shield trenches may be filled with conductive materials other than silicon carbide, such as doped polysilicon, nickel oxide, or metals that form Schottky contacts with silicon carbide. The conductive material within the support-shield trenches forms a support shield. These gate trench power semiconductor devices may further include well-contact regions that may have highly doped regions within the semiconductor layer structure having the same conductivity type as the channel region. These well-contact regions can directly contact the support shield to provide low-resistance contact between the source metallization and the support shield. The well contact region may extend deeper into the semiconductor layer than the well region, and in some embodiments, it may even extend to the same depth as the gate trench or even deeper than the gate trench, so that the well contact region may also act to shield the gate oxide layer from high electric field values ​​during reverse blocking operation.

[0074] According to yet another embodiment of the present invention, a gate trench power semiconductor device is provided having deep support shields formed within a semiconductor layer structure, with trenches formed within each deep support shield. The trenches can be filled by source metallization or with another conductive material, such as p-type polysilicon. The deep support shields can contact the conductive material filling the corresponding trenches with low resistance. In some embodiments, the trenches can extend into the semiconductor layer structure to the same depth as the gate trenches, or to a depth greater than the gate trenches. In some embodiments, the trenches can be formed after the gate trenches.

[0075] According to some specific embodiments of the present invention, a semiconductor device such as a MOSFET or IGBT is provided, comprising: a silicon carbide-based semiconductor layer structure including a drift layer having a first conductivity type; a gate trench extending into the upper surface of the semiconductor layer structure to a first depth; a gate electrode located in the gate trench; a support-shield trench extending into the upper surface of the semiconductor layer structure to a second depth shallower than the first depth; and a source metallization layer located on the upper surface of the semiconductor layer structure and extending into the support-shield trench.

[0076] The semiconductor layer structure may further comprise a well contact region having a second conductivity type beneath the support-shield trench, and may also comprise a support shield having a second conductivity type beneath the well junction region. The source metallization layer may be in direct contact with the well contact region, and the well contact region may be in direct contact with the support shield. The semiconductor layer structure may also comprise a trench shield having a second conductivity type beneath the gate trench. The support shield may extend further down within the semiconductor layer structure than the trench shield extends.

[0077] In some embodiments, the semiconductor layer structure may further comprise a well region having a second conductivity type on the upper surface of the drift layer, and a source region having a first conductivity type on the upper surface of the well region. In such embodiments, the source metallization layer in the support-shield trench may be in direct contact with the side surface of the source region and the upper surface of the well contact region. The well contact region may have a first doping concentration of the second conductivity type dopant that is at least 10 times higher than the second doping concentration of the second conductivity type dopant in the well region, and / or at least 10 times higher than the third doping concentration of the second conductivity type dopant in the support-shield.

[0078] A further embodiment of the present invention provides a semiconductor device such as a MOSFET or IGBT comprising a silicon carbide-based semiconductor layer structure, the silicon carbide-based semiconductor layer structure comprising: a drift layer having a first conductivity type; a well region having a second conductivity type located on the upper surface of the drift layer; a source region having the first conductivity type located on the upper surface of the well region; a well contact region having the second conductivity type located within the well region; and a support shield having the second conductivity type located below the well contact region. The upper surface of the well contact region is recessed and lower than the upper surface of the source region. The support shield extends into the drift layer. A gate trench is formed on the upper surface of the semiconductor layer structure, and a gate electrode is provided within the gate trench. A support-shield trench is also provided on the upper surface of the semiconductor layer structure, and a source metallization layer extends into the support-shield trench.

[0079] According to additional embodiments of the present invention, a semiconductor device is provided which includes a plurality of unit cell transistors, each unit cell transistor. These semiconductor devices include a silicon carbide-based semiconductor layer structure comprising: a drift layer having a first conductivity type; a well region having a second conductivity type located on the upper surface of the drift layer; a source region having the first conductivity type located on the upper surface of the well region; and a well contact region having the second conductivity type located within the well region, which is a portion of the well region having a higher dopant concentration. The upper surface of the well contact region is recessed lower than the upper surface of the source region. A gate trench extends into the upper surface of the semiconductor layer structure to a first depth, and a source metallization layer extends between the source regions of adjacent unit cell transistors so as to be in direct contact with the well contact region.

[0080] According to another additional embodiment of the present invention, a semiconductor device is provided comprising a silicon carbide-based semiconductor layer structure. The semiconductor layer structure comprises a drift layer having a first conductivity type, a well region having a second conductivity type located on the upper surface of the drift layer, a source region having the first conductivity type located on the upper surface of the well region, and a well contact region having the second conductivity type located within the well region, which is a portion of the well region having a higher dopant concentration. These devices further comprise a source metallization layer in contact with the upper and side surfaces of the source region and in contact with the upper surface of the well contact region.

[0081] A semiconductor device is provided comprising a silicon carbide-based semiconductor layer structure, the silicon carbide-based semiconductor layer structure comprising: a drift layer having a first conductivity type; a well region having a second conductivity type located on the upper surface of the drift layer; and a well contact region having a second conductivity type extending downward through the well region into the drift layer. A gate trench is provided on the upper surface of the semiconductor layer structure, and a gate electrode is provided within the gate trench. A support-shield trench extends through the well contact region, and this support-shield trench extends further downward within the semiconductor layer structure than the well contact region. A support shield is provided within the support-shield trench.

[0082] According to another embodiment of the present invention, a semiconductor device is provided comprising a silicon carbide-based semiconductor layer structure, the silicon carbide-based semiconductor layer structure comprising: a drift layer having a first conductivity type; a well region having a second conductivity type located on the upper surface of the drift layer; a well contact region having a second conductivity type extending downward through the well region into the drift layer; a source region having a first conductivity type located on the upper surface of the well region; and a support shield having a second conductivity type extending downward into the drift layer. A gate trench is provided on the upper surface of the semiconductor layer structure, and a gate electrode is provided within the gate trench. These devices may further comprise a trench extending into the support shield and a conductive material other than silicon carbide located within the trench.

[0083] Embodiments of the present invention will be described in further detail here with reference to Figures 2A to 11. It will be understood that many additional embodiments can be realized by combining the features of the different embodiments disclosed herein in any way. Therefore, it will be understood that although various features of the present invention are described below with respect to specific embodiments, many additional embodiments can be realized by adding these features to other embodiments and / or using them in place of the exemplary features of other embodiments. Thus, the present invention should be understood to encompass these different combinations. In addition, although the exemplary embodiments focus on the implementation of MOSFETs, it will be understood that the same techniques can be used for other gate trench power semiconductor devices such as insulated gate bipolar transistors (IGBTs) and gate-controlled thyristors.

[0084] Figure 2A is a schematic top view of a gate-trench silicon carbide power MOSFET 100 according to a particular embodiment of the present invention. Figure 2B is a schematic plan view of the power MOSFET 100 with various top-side metal and dielectric layers omitted to show the gate electrode and gate bus. Figure 2C is a schematic cross-sectional view of a unit cell of the gate-trench silicon carbide power MOSFET 100 taken along line 2C-2C in Figure 2A. It should be understood that the thicknesses of the various layers and regions in Figures 2A to 2C are not necessarily depicted to the correct scale. The same applies to other figures included in this application.

[0085] The power MOSFET 100 includes a semiconductor layer structure 160 (see Figure 2C) comprising one or more semiconductor substrates and / or layers. At least one of the semiconductor layers of the semiconductor layer structure 160 may be a silicon carbide layer. Various metal layers and / or dielectric layers are formed on both sides of the semiconductor layer structure 160 and embedded in the semiconductor layer structure 160.

[0086] As shown in Figure 2A, the upper metal layer is formed on the upper side of the semiconductor layer structure 160 and includes a gate bond pad 102 and one or more source bond pads 104-1, 104-2. A metal drain pad 106 (not visible in Figure 2A, and therefore shown as a dotted line in Figure 2A) is provided on the bottom side of the power MOSFET 100. The gate bond pad 102, source bond pad 104, and drain pad 106 form the gate terminal, source terminal, and drain terminal, respectively, of the power MOSFET 100. The gate pad 102 and source pad 104 may each be formed of a metal such as aluminum, to which bond wires can be easily attached via conventional techniques such as thermal compression or soldering. The drain pad 106 may also be a metal pad. A protective layer 109, such as a polyimide layer, may cover the entire upper surface of the power MOSFET 100 other than the gate pad 102 and source pad 104.

[0087] Continuing to refer to Figure 2A, the power MOSFET 100 includes a source metallization 190 (shown as a dotted box in Figure 2A) that electrically connects a specific region of the semiconductor layer structure 160 to the source bond pads 104-1, 104-2. The source bond pads 104-1, 104-2 may be part of the source metallization 190 exposed through an opening in the protective layer 109, or they may be a separate metal layer. The source metallization 190 may cover or coincide with the entire “active region” 107 of the power MOSFET 100 where the unit cell transistor is located. The inactive region 108 of the power MOSFET 100 surrounds the active region 107. The inert region 108 may include a termination region extending along the periphery of the MOSFET 100, which includes a guard ring, a junction termination element, or other termination structure (not shown), a gate pad region located below the gate pad 102, and a gate bus region (described later).

[0088] A bond wire 103 is shown in Figure 2A and may be used to connect the gate bond pad 102 and the source bond pad 104 to an external circuit. The drain pad 106 on the bottom side of the power MOSFET 100 may be connected to an external circuit, for example, through a submount (not shown) placed underneath.

[0089] Figure 2B is another plan view of the power MOSFET 100 with the gate bond pad 102 and source bond pad 104, polyimide layer 109, source metallization 190, and various other metal and dielectric layers removed to show the gate electrode 184 formed within the gate trench 180 of the semiconductor layer structure 160. Within the inactive region 108 of the MOSFET 100, a patterned field oxide layer (not shown) is formed on the semiconductor layer structure 160. The field oxide layer may be a relatively thick oxide layer (for example, 10 to 20 times thicker than the gate oxide layer described later). A polysilicon layer 101 can be formed on the field oxide layer and can be formed within the region where the gate bond pad 102 is formed, such that the gate bond pad 102 overlaps perpendicularly with the field oxide layer and the polysilicon layer 101. As used herein, two elements of a semiconductor device are considered to "overlap perpendicularly" if the axis perpendicular to the main plane of the semiconductor layer structure of the semiconductor device intersects both elements. One or more gate buses 186 are provided extending around the periphery of the active region 107. The field oxide layer typically passes beneath each gate bus 186 and is located beneath the gate bond pad 102. The gate buses 186 are often electrically connected to the gate bond pad 102 through gate resistors (not shown). Multiple gate trenches 180 (see Figure 2C) are formed throughout the active region 107. A gate electrode 184 is formed within each gate trench 180. In the MOSFET 100 depicted, the gate electrode 184 extends horizontally across the semiconductor layer structure 160. In other cases, the gate electrode 184 may extend vertically across the semiconductor layer structure 160, and both horizontally extending and vertically extending gate electrode 184 may be provided to form a lattice gate electrode structure, or an annular hexagonal gate electrode 184 or a gate electrode 184 of other shapes may be used. The gate electrode 184 may be connected to the gate pad 102 through the gate bus 186. The gate electrode 184 may include, for example, a doped polysilicon pattern.In the exemplary embodiment, the gate bus 186 may have a polysilicon structure and / or a metallic structure, and is typically located within the inert region 108 of the power MOSFET 100.

[0090] Figure 2C is a schematic cross-sectional view taken along line 2C--2C in Figure 2A, showing a unit cell of approximately 1.5 power MOSFETs 100. As shown in Figure 2C, the power MOSFET 100 includes an n-type silicon carbide semiconductor substrate 110. The substrate 110 may include, for example, a single-crystal 4H silicon carbide semiconductor substrate (i.e., an n+ silicon carbide substrate) highly doped with n-type impurities. The impurities may include, for example, nitrogen or phosphorus. In an exemplary embodiment, the n-type substrate 110 is, for example, 1 × 10 18 atoms / cm 3 ~1 × 10 21 atoms / cm 3 The doping concentration may be such that, but other doping concentrations may be used. In some embodiments, the substrate 110 may be relatively thick (e.g., 20-100 microns or more). It should be noted that the substrate 110 is depicted as a relatively thin layer, but this is done to allow for scaling of the thickness of other layers and regions in Figure 2C, and it will be understood that the substrate 110 is usually much thicker than shown. Similarly, the thicknesses of various other layers of the power MOSFET 100 may not be shown at the correct scale in the figure to allow for scaling of other parts of the device.

[0091] A low-concentration doped n-type (n-) silicon carbide drift layer 120 (also referred to herein as the drift region 120) is provided on the upper surface of the substrate 110. Typically, the drift layer 120 is formed via an epitaxial growth process and doped during growth. The n-type drift region 120 is, for example, 5 × 10 15 ~5×10 17 Dopant / CM 3may have a doping concentration. The n-type drift region 120 may, for example, be a thick region having a vertical height of 3 to 50 microns above the substrate 110, and may be doped during growth. The upper portion of the n-type drift region 120 may optionally include an n-type current spreading layer 122 doped to a higher concentration than the lower portion of the n-type drift region 120. The n-type current spreading layer 122, when provided, is for example 5×10 16 ~1×10 18 may have an n-type dopant concentration. As used herein, the n-type current spreading layer 122, when provided, is considered part of the drift region 120 and is generally not referred to separately. The n-type current spreading layer 122, when provided, may be doped during epitaxial growth or by a subsequent ion implantation step.

[0092] The drift layer 120 and the substrate 110 together act as a common drain region for the power MOSFET 100. A drain pad 106 is formed on the substrate 110 on the opposite side of the drift region 120.

[0093] With continued reference to FIG. 2C, a moderately doped (p) p-type silicon carbide well region 130 is formed on the top surface of the n-type drift region 120 or on the upper portion of the n-type drift region 120 (i.e., the upper portion of the n-type drift region 120 is converted to the well region 130). The moderately doped (p) p-type silicon carbide well region 130 may be formed either by epitaxial growth, or by implanting p-type dopant ions into the upper portion of the n-type drift region 120 to convert the upper portion of the n-type drift layer into the p-type silicon carbide well region 130. In an illustrative embodiment, the moderately doped p-type well region 130 has, for example, 5×10 16 ~1×10 18 may have a p-type dopant concentration.

[0094] A selected portion of the p-type well region 130 can be doped to a higher concentration than the rest of the well region 130 to form a p-type well contact region 132 within the well region 130. The p-type well contact region 132 can be, for example, 1 × 10⁻⁶. 18 ~1 × 10 22 It may have a p-type dopant concentration. In some embodiments, the p-type well contact region 132 may have a p-type dopant concentration at least 10 times higher than the p-type dopant concentration of the well region 130. In some embodiments, the p-type well contact region 132 may have, for example, 1 × 10⁻⁶ dopant concentrations. 19 ~1 × 10 21 or 1 × 10 19 ~5×10 20 It may have a p-type dopant concentration.

[0095] A highly doped (n+), n-type silicon carbide source region 140 can be formed on or above the p-type silicon carbide well region 130 (depending on whether the p-type silicon carbide well region 130 extends to the surface of the semiconductor layer structure 160). The highly doped n-type silicon carbide source region 140 can be formed by ion implantation. Each highly doped n-type silicon carbide source region 140 can be, for example, 1 × 10⁻⁶. 19 atoms / cm 3 ~5×10 21 atoms / cm 3 It may have a doping concentration of [value missing].

[0096] As further shown in Figure 2C, within the silicon carbide drift region 120, a p-type support shield 152 and a p-type trench shielding region 154 are formed. The p-type support shield 152 is formed below the p-type well contact region 132, so that the upper surface of each support shield 152 is in direct contact with the lower surface of the corresponding well contact region 132. The p-type support shield 152 is doped to a medium or high concentration (p + ) The silicon carbide region may also be. For example, each p-type support shield 152 is approximately 5 × 10 16 ~1 × 10 22It may have a doping concentration of about 1 × 10⁻⁶. In other embodiments, each p-type support shield 152 has about 1 × 10⁻⁶ doping concentration. 18 ~1 × 10 20 , about 1×10 19 ~1 × 10 20 , about 1×10 17 ~1 × 10 19 , about 1×10 17 ~1 × 10 20 , or approximately 1 x 10 18 ~1 × 10 21 The doping concentration may be as follows. In exemplary embodiments, each p-type support shield 152 may extend to a depth of 0.1 to 4.0 microns from the top surface of the semiconductor layer structure 160. In other embodiments, the depth of each p-type support shield 152 may be 1.0 to 3.0 microns, 1.0 to 2.5 microns, 1.5 to 3.0 microns, 1.5 to 2.5 microns, or 0.5 to 2.5 microns. Any of the above dopant concentration ranges for the p-type support shield 152 can be combined with any of the depths listed above for the p-type support shield 152. The p-type support shield 152 may work to reduce the electric field level formed in the gate oxide layer (described later) during the reverse blocking operation of the device, as will be discussed in more detail later.

[0097] The p-type trench shielding region 154 is formed beneath the corresponding gate trench 180 and may extend beneath the corresponding gate trench 180 for the entire length of the gate trench 180 or substantially the entire length of the gate trench 180. The p-type trench shielding region 154 is doped to a medium concentration or a high concentration (p + ) It may also be a silicon carbide region. For example, each p-type trench shielding region 154 is approximately 1 × 10⁻⁶ 17 ~1 × 10 21 It may have a doping concentration of about 1 × 10⁻¹⁶. In other embodiments, each p-type trench shielding region 154 is about 1 × 10⁻¹⁶. 18 ~1 × 10 20 , about 1×10 19 ~1 × 10 20 , about 1×10 17 ~1 × 10 20 , or approximately 1 x 10 18~1 × 10 21 The doping concentration may be as follows. In the exemplary embodiment, each p-type trench shielding region 154 may extend to a depth of 0.5 to 3.0 microns from the top surface of the semiconductor layer structure 160. In other embodiments, the depth of each p-type trench shielding region 154 may be 1.0 to 3.0 microns, 1.0 to 2.5 microns, 1.5 to 3.0 microns, 1.5 to 2.5 microns, or 0.5 to 2.5 microns. Any of the above dopant concentrations can be combined with any of the depths listed above for the p-type trench shielding region 154. The p-type trench shielding region 154 may work to reduce the electric field level formed on the gate oxide layer (described later) during device operation, as will be discussed in more detail later. The p-type trench shielding region 154 may be doped to have a higher p-type dopant concentration, a lower p-type dopant concentration, or approximately the same p-type dopant concentration as the p-type support shield 152.

[0098] Although not shown in Figure 2C, electrical connections are provided within and / or outside the active region 107 to electrically connect the p-type trench shielding region 154 to the p-type silicon carbide well region 130. Patent documents 1 and 2 each describe designs of p-type silicon carbide trench-shield connection patterns that can be used to electrically connect the p-type trench shielding region to the p-type silicon carbide well region. The p-type trench shielding region 154 can be electrically connected to the p-type silicon carbide well region 130 using any of the p-type silicon carbide trench-shield connection patterns disclosed in these patents (each of which is incorporated herein by reference). In addition or alternatively, the p-type trench shielding region 154 may be directly connected to the source metallization 190 through a p-type silicon carbide trench-shield connection pattern formed within the gate trench 180, for example, as shown in Patent document 3, whose entire contents are also incorporated herein by reference.

[0099] The n-type silicon carbide substrate 110, the n-type silicon carbide drift layer 120 (including an optional current diffusion layer 122), the p-type silicon carbide well region 130 (including a p-type well contact region 132), the n-type silicon carbide source region 140, the p-type silicon carbide support / shield 152, and the p-type silicon carbide trench shielding region 145 together can constitute the semiconductor layer structure 160 of the power MOSFET 100.

[0100] As described above, multiple gate trenches 180 are formed on the upper part of the semiconductor layer structure 160. Although the cross-sectional view in Figure 2C shows only one complete gate trench 180 and a portion of a second gate trench 180, it will be understood from Figure 2B that the MOSFET 100 may contain a number of gate trenches 180. Each gate trench 180 may extend along a longitudinal axis through the semiconductor layer structure 160, and the gate trenches 180 may extend parallel to each other, as best shown in Figure 2B. It will be understood that the longitudinal axes of the gate trenches 180 extend into the plane of paper in Figure 2C. The gate trenches 180 may be formed by an etching process.

[0101] Within each gate trench 180, a gate oxide layer 182 is provided so as to cover the side walls and bottom surface of the gate trench 180. In some embodiments, each gate oxide layer 182 may extend onto the upper surface of the semiconductor layer structure 160. Each gate oxide layer 182 may include, for example, a silicon oxide (SiO2) pattern. The gate oxide layers 182 may or may not be connected to each other outside the field of view in Figure 2C. The gate oxide layers 182 may be formed conformally as a whole within each gate trench 180.

[0102] A gate electrode 184 is formed on the gate oxide layer 182 within each gate trench 180. The gate electrode 184 may comprise a conductive material such as silicide (e.g., NiSi, TiSi, WSi, CoSi), doped polycrystalline silicon (poly-Si), and / or a stable conductor. Other suitable materials for the gate electrode include various metals such as Ti, Ta, or W, or metal nitrides such as TiN, TaN, or WN. The gate oxide layer 182 insulates the gate electrode 184 from the semiconductor layer structure 160, thereby preventing the gate electrode 184 from short-circuiting to the semiconductor layer structure 160. Each gate electrode 184 can be connected to one of the gate buses 186 (see Figure 2B). In the embodiment depicted, the gate electrode 184 extends above and onto the upper surface of the semiconductor layer structure 160, with the gate oxide layer 182 insulating the gate electrode 184 from the semiconductor layer structure 160. In other embodiments, the gate electrodes 184 may be recessed such that the upper surface of each gate electrode 184 is lower than the upper surface of the semiconductor layer structure 160. It will be understood that each embodiment disclosed herein may have any of these gate electrode designs. Figure 10B shows a power MOSFET having a gate electrode 184' in which the upper surface of each gate electrode 184 is recessed such that the upper surface of each gate electrode 184 is lower than the upper surface of the semiconductor layer structure 160.

[0103] An intermetallic dielectric layer 188 is formed covering each gate electrode 184. The intermetallic dielectric layer 188 insulates the source metallization 190 from the gate electrode 184.

[0104] Support shield trenches 150 are formed on the upper surface of the semiconductor layer structure 160. In the embodiment depicted, each support shield trench 150 is formed between a pair of corresponding source regions 140 located between adjacent gate electrodes 184. Each support shield trench 150 may expose the sidewalls of one or two source regions 140. In the embodiment depicted, the support shield trench 150 extends into the semiconductor layer structure 160 to the same depth as the bottom surface of the source region 140 (which is the same depth as the top surface of the p-type well region 130). In other embodiments, as will be discussed in more detail below, the support shield trenches 150 may extend deeper or shallower into the semiconductor layer structure 160.

[0105] In Figure 2C, the p-type well contact area 132 is shown aligned with the support shield 152, but it should be understood that embodiments of the present invention are not limited thereto. In other embodiments, the p-type well contact area 132 may be shifted to the left or right from the position shown in Figure 2C, and may partially overlap the support shield 152 vertically, or not overlap the support shield 152 vertically at all. As shown in Figure 4E (described later), in yet another embodiment, the p-type well contact area 132 may be wider than the support shield 152, and in yet another embodiment, they may be narrower than the support shield 152.

[0106] The source metallization 190 is formed on the upper surface of the semiconductor layer structure 160 and on the intermetallic dielectric layer 188. In this specification, the source metallization 190 may also be referred to as the “source contact”. The source metallization 190 may comprise a single metal layer or multiple metal layers. Typically, multiple metal layers are provided because the source metallization 190 may include a single or multilayer adhesive layer, one or more barrier layers, and bulk metal layers (e.g., an aluminum layer) that contact the semiconductor layer structure 160. The source metallization 190 may also be filled with a support shield trench 150 such that the source metallization 190 directly contacts both the upper surface of the well contact region 132 and the upper and side surfaces of the source region 140. Because the source metallization 190 directly contacts both the upper and side surfaces of the source region 140, the interface resistance between the source metallization 190 and the source region 140 is reduced compared to conventional power MOSFETs. Typically, the width of the portion of each source region 140 that directly contacts the source metallization 190 is set to achieve a sufficiently low-resistance connection between the source metallization 190 and the source region 140. Since the source metallization 190 in the power MOSFET 100 contacts the side of the source region 140, it is possible to achieve a sufficiently low-resistance connection between the source metallization 190 and the source region 140 while reducing the width of the source region 140.

[0107] As described above, the source metallization 190 often includes one or more adhesive layers to ensure that the source metallization 190 adheres properly to the semiconductor layer structure 160 and is not easily delaminated. Since the source metallization 190 extends into the recesses of the semiconductor layer structure 160, improved adhesion between the source metallization 190 and the semiconductor layer structure 160 can be achieved. This eliminates the need for adhesive layers in the source metallization 190, or makes it possible to obtain a more robust device that is less prone to failure.

[0108] As will be discussed in more detail below, the p-type support shield 152 can be formed by ion implantation. In some embodiments, the p-type support shield 152 may be formed after the support shield trench 150 has been formed, which allows the ion implantation process used to form the p-type support shield 152 to be carried out so that the ions are implanted at the bottom of the support shield trench 150. This reduces the distance that the ions must travel within the semiconductor layer structure 160 to achieve implantation at the desired depth, thereby enabling the use of lower energy implantation. As discussed above, lower energy implantation can reduce damage to the silicon carbide lattice structure and consequently reduce struggling, both of which can improve the performance of the power MOSFET 100 compared to conventional power MOSFETs.

[0109] The power MOSFET 100 may be turned on by applying a gate bias voltage higher than a threshold level to the gate pad 102. The gate bias voltage is transmitted to the gate electrode 184 via the gate bus 186, creating a conductive n-type inversion layer in the portion of the p-type silicon carbide well region 130 adjacent to the gate trench 180. These regions of the p-type silicon carbide well region 130 are referred to herein as channel regions 134 because, during on-state operation, current flows through these channel regions 134 from the source region 140 to the drift region 120. The channel regions 134 are oriented vertically (i.e., extending in the z direction) because current flows downward from the source region 140 through the channel regions 134 to the drift layer 120, the substrate 110, and the drain contact 106.

[0110] As discussed above, one common failure mechanism in power semiconductor devices such as power MOSFETs is device failure due to dielectric breakdown of the gate oxide layer. Since the lifetime of the gate oxide layer (i.e., the time until dielectric breakdown) depends on the strength of the electric field within the gate oxide layer during device operation, one way to reduce the occurrence of device failure is to design the MOSFET to have a reduced peak electric field value in the gate oxide layer.

[0111] During reverse blocking operation, the electric field extends upward from the bottom of the MOSFET 100. Therefore, a strong electric field may extend upward toward the bottom of the gate oxide layer 182. The p-type silicon carbide trench shielding region 154 acts as a shield to reduce the electric field value directly beneath the gate trench 180. However, the electric field tends to extend upward on both sides of each trench shielding region 154. Therefore, the electric field tends to be highest in parts of the gate oxide layer 182 that are not directly protected by the trench shielding region 154, such as the lower side walls and lower corners of each gate oxide layer 182. Furthermore, an electric field concentration effect occurs at the lower corners of each gate oxide layer 182, and the electric field strength in this part of each gate oxide layer 182 becomes even greater. Therefore, although the trench shielding region 154 helps to reduce the electric field level in the gate oxide layer 182, the lower corners of the gate oxide layer 182 are usually only partially protected, and these lower corners are the parts of the gate oxide layer 182 that are most susceptible to dielectric breakdown due to electric field concentration effects.

[0112] The support shield 152 is provided to help further protect the lower corner of the gate oxide layer 182. The support shield 152, like the trench shielding region 154, suppresses the range over which the electric field extends upward from the drain pad 106. Because the support shield 152 can be formed deeper within the semiconductor layer structure 160 (by being formed by ion implantation into the support shield trench 150), the support shield 152 can be very effective in reducing the electric field value at the lower corner of the gate oxide layer 182. Therefore, the power MOSFET 100 may also see improved reliability, as its gate oxide layer 182 becomes less susceptible to dielectric breakdown.

[0113] Figures 3A to 3F are schematic cross-sectional diagrams illustrating the method for fabricating the gate-trench silicon carbide power MOSFET 100 shown in Figures 2A to 2C.

[0114] Referring to Figure 3A, an n-type silicon carbide substrate 110 is provided. Then, usually by epitaxial growth, a low concentration of (n) doped onto the upper surface of the substrate 110 is applied. - A silicon carbide drift layer 120 is formed. By increasing the n-type dopant concentration during growth of the top of the drift layer 120, a current diffusion layer 122 can be formed on top of the drift layer 120. Subsequently, the epitaxial growth process can be continued (with the n-type dopant source turned on or off) to grow the regions that will become the p-type well region 130, the well contact region 132, and the source region 140 of the semiconductor layer structure 160.

[0115] Continuing to refer to Figure 3A, a first ion implantation process is performed to implant p-type ions into the upper part of the semiconductor layer structure 160. This ion implantation process may be an embedding process that primarily implants p-type ions into the region above the current diffusion layer 122 to form p-type well regions 130. Next, a second ion implantation process is performed to implant n-type ions into the upper part of the semiconductor layer structure 160 to form an n-type source layer 142 above the p-well regions 130. It will be understood that the first and second ion implantation steps may be performed in reverse order, and that the p-type well regions 130 and / or the n-type source layer 142 can alternatively be formed by appropriately doping these regions during the epitaxial growth process. Subsequently, a first mask 192, such as an oxide mask, is formed on the upper surface of the semiconductor layer structure 160, and this is then patterned (for example, using standard photolithography patterning techniques) to form openings 194 in the first mask 192 that expose selected portions of the semiconductor layer structure 160. The openings 194 may be located above the locations in the semiconductor layer structure 160 where support shield trenches 150 will be formed in subsequent processing steps.

[0116] Next, referring to Figure 3B, an etching process is performed to etch the exposed portion of the semiconductor layer structure 160 to form a support-shield trench 150. In the embodiment shown as an example, the semiconductor layer structure 160 is etched to completely remove a portion of the n-type source layer 142, thereby converting the n-type source layer 142 into multiple spaced n-type source regions 140 and forming the support-shield trench 150. This etching process also works to expose a selected portion of the p-type well region 130.

[0117] Referring to Figure 3C, an ion implantation process is performed to implant p-type dopant ions into the portion of the semiconductor layer structure 160 exposed through the opening 194. In some embodiments, a multi-stage ion implantation process may be used. As shown in Figure 3C, this ion implantation process may be used to convert a selected portion of a moderately doped p-type well region 130 into a highly doped p-type well contact region 132, and to form a p-type support shield 152 within the current diffusion layer 122 and the drift layer 120. The p-type support shield 152 may be a deep p-type support shield 152 that extends considerably into the semiconductor layer structure 160. In exemplary embodiments, the bottom of the p-type support shield 152 may be 0.1 to 4.0 microns below the top surface of the semiconductor layer structure 160. In some embodiments, the p-type support shield 152 may extend deeper into the semiconductor layer structure 160 than the trench shielding region 154 formed in a subsequent processing step. For example, in some embodiments, the p-type support shield 152 may extend 0.1 to 2.0 microns deeper into the semiconductor layer structure 160 than the trench shielding region 154.

[0118] Referring to Figure 3D, the first mask 192 can be removed, and a second mask 196 (for example, another oxide mask) can be formed to cover the semiconductor layer structure 160. The second mask 196 can then be patterned (for example, using standard photolithography patterning techniques) to form openings 198 therein, which expose selected portions of the semiconductor layer structure 160. The openings 198 may be located above the location in the semiconductor layer structure 160 where gate trenches 180 will be formed in subsequent processing steps.

[0119] Referring to Figure 3E, an etching process is performed to etch the exposed portion of the semiconductor layer structure 160 to form a gate trench 180. As shown, in some embodiments, the gate trench 180 may extend deeper into the semiconductor layer structure 160 than the well contact region 132, but not as deep as the bottom of the support shield 152. Next, an ion implantation process is performed to implant p-type dopant ions into the portion of the semiconductor layer structure 160 below the gate trench 180 to form a trench shielding pattern 154. As discussed above, the trench shielding pattern 154 may not extend as deep into the semiconductor layer structure 160 as the support shield 152.

[0120] As shown in Figure 3F, a gate oxide layer 182 and a gate electrode 184 can then be formed within the gate trench 180, and an intermetallic dielectric layer 188 is formed to cover the gate oxide layer 182 and the gate electrode 184. Next, a source metallization layer 190 is formed on the source region 140, the intermetallic dielectric layer 188, and the well contact region 132. As shown, the source metallization 190 extends into the support shield trench 150 and is in direct contact with the sidewall of the source region 140 and the upper surface of the well contact region 132.

[0121] Figures 4A to 4E are schematic cross-sectional views of gate-trench silicon carbide power MOSFETs 100A to 100E, which are modified versions of gate-trench silicon carbide power MOSFET 100. Since gate-trench silicon carbide power MOSFETs 100A to 100E are almost identical to MOSFET 100, the following discussion will focus only on the differences between each of MOSFETs 100A to 100E and MOSFET 100.

[0122] As can be seen by comparing Figure 2C and Figure 4A, the only difference between MOSFET 100 and MOSFET 100A is that MOSFET 100A includes a p-type support shield 152' formed using channel ion implantation technology, whereas the p-type support shield 152 on MOSFET 100 is formed using conventional (and higher-energy) ion implantation technology. For example, as discussed in Patent Document 4, the entirety of which is incorporated herein by reference, channel ion implantation refers to ion implantation in which dopant ions are implanted along a specific crystal axis that forms a channel in silicon carbide, thereby enabling dopants to be implanted to greater depths while using lower implantation energies (which favorably reduces damage to silicon carbide by implantation and also reduces scattering of dopant ions to unintended locations within the crystal lattice). As shown in Figure 4A, because channel-type ion implantation is used, the shape of the p-type support shield 152' in MOSFET 100A differs from the shape of the p-type support shield 152 in MOSFET 100. The width of the p-type support shield 152 increases as it approaches the substrate 110, while the width of the p-type support shield 152' may remain relatively constant with respect to depth (not shown), or it may become even narrower as it approaches the substrate 110, as shown in Figure 4A. The narrower p-type support shield 152' may help to lower the on-state resistance of MOSFET 100A compared to MOSFET 100.

[0123] As can be seen by comparing Figure 2C and Figure 4B, the only difference between MOSFET 100 and MOSFET 100B is that MOSFET 100B includes a deeper support-shield trench 150' that penetrates the entire source layer 142 and extends into the p-type well region 130. As a result, the thickness of the p-type well contact region 132' can be reduced.

[0124] Alternatively, as shown in Figure 4C, the thickness of the p-type well contact region 132' can be kept the same as in the case of MOSFET 100 in Figure 2C, and the p-type well contact region 132' can be extended into the current diffusion layer 122. In fact, as shown in Figure 4C, extending the p-type well contact region 132' into (or even through) the current diffusion layer 122 can advantageously contribute to the deactivation of parasitic npn bipolar junction transistors formed within the semiconductor layer structure 160.

[0125] As can be seen by comparing Figure 2C and Figure 4D, the only difference between MOSFET 100 and MOSFET 100D is that MOSFET 100D includes a shallower support shield trench 150" that does not penetrate the entire source layer 142. As a result, the thickness of the p-type well contact region 132" can be increased.

[0126] As can be seen by comparing Figure 2C and Figure 4E, the only difference between MOSFET100 and MOSFET100E is that MOSFET100D includes a wider p-type well contact region 132'' than the support shield trench 150.

[0127] Figure 5 is a flowchart showing a method for forming the gate trench silicon carbide power MOSFET shown in Figures 2A to 2C. As shown in Figure 5, first, a silicon carbide-based semiconductor layer structure 160 is provided (block 200). The semiconductor layer structure 160 includes a drift layer 120 having a first conductivity type, and may further include a well region 130 having a second conductivity type on the upper surface of the drift layer 120, and a source layer 142 having the first conductivity type on the upper surface of the well region 130.

[0128] Next, a support-shield trench 150 is formed within the semiconductor layer structure 160. The support-shield trench 150 may extend into the upper surface of the semiconductor layer structure 160 to a second depth, the second depth being shallower than the first depth (block 210). Next, a plurality of gate trenches 180 are formed on the upper surface of the semiconductor layer structure 160 (block 220). Each gate trench 180 can extend into the upper surface of the semiconductor layer structure 160 to a first depth. A gate electrode 184 is formed within each gate trench 180. A gate oxide layer 182 may be formed in the gate trench 180 before the gate electrode 184, such that the gate oxide layer 182 exists between the gate electrode 184 and the semiconductor layer structure, and the gate oxide layer 182 is capacitively coupled to the semiconductor layer structure 160. Finally, a source metallization 190 is formed on the upper surface of the semiconductor layer structure 160, and the source metallization 190 extends into the support shield trench 150 (block 230).

[0129] Referring to Figures 3A to 3F and Figure 5, it will be understood that the processing steps discussed above may be carried out in a different order in further embodiments. For example, in other embodiments, the gate trench 180 may be formed before the support shield trench 150. It will also be understood that in other embodiments, some of the processing steps may be omitted, and / or other processing steps may be added to this method.

[0130] Figure 6 is a schematic cross-sectional view of a gate-trench silicon carbide power MOSFET 300 according to a further embodiment of the present invention. The gate-trench silicon carbide power MOSFET 300 may be identical to the gate-trench silicon carbide power MOSFET 100 when viewed from above, and therefore Figure 2A also accurately represents the power MOSFET 300. The cross-section in Figure 6 is also taken along line 2C-2C in Figure 2A, showing how the power MOSFET 300 differs from the power MOSFET 100. Since many of the elements of the power MOSFET 300 are the same as the corresponding elements of the power MOSFET 100, the same reference numerals are used for those elements in Figures 2A-2C and Figure 6. In the following description, we will focus on the elements of the power MOSFET 300 that differ from those of the power MOSFET 100.

[0131] As can be seen by comparing Figure 2C and Figure 6, the power MOSFET 300 includes a drain contact 106, a substrate 110, a drift layer 120, a current diffusion layer 122, a well region 130, a source region 140, a gate shielding region 154, a gate trench 180, a gate oxide layer 182, a gate electrode 184, and an intermetallic dielectric layer 188, which may be identical (or substantially identical in the case of the well region 130 and the source region 140) to the corresponding layers / regions in the power MOSFET 100. Therefore, an additional explanation of these elements of MOSFET 100 is omitted here.

[0132] The power MOSFET 300 further includes a well contact region 332, a support shield trench 350, and a support shield 352 formed within the support shield trench 350. The support shield 352 may perform the same function as the support shield 152 of the power MOSFET 100; that is, they work to reduce the strength of the electric field extending upward from the drain contact 106 into the semiconductor layer structure 360 ​​during the reverse blocking operation of the MOSFET 300.

[0133] The p-type well contact region 332, similar to the well contact region 132 of the MOSFET 100, provides low-resistance contact between the well region 130 and the source metallization 190. The well contact region 332 also contributes to protecting the gate oxide layer 182 from high electric field values ​​during reverse blocking operation because the well contact region 332 extends deep into the semiconductor layer structure 360. The well contact region 332 extends, for example, 5 × 10⁻⁶ 16 ~1 × 10 22 or 1 × 10 18 ~1 × 10 21 It has a p-type dopant concentration. In some embodiments, the well contact region 332 may have a p-type dopant concentration at least 10 times higher than the p-type dopant concentration of the well region 130. The well contact region 332 may extend deeper into the semiconductor layer structure 360 ​​than the p-type well region 130, and may extend deeper into the semiconductor layer structure 360 ​​than the well contact region 132 of the power MOSFET 100. In some embodiments, the well contact region 332 may extend deeper into the semiconductor layer structure 360 ​​than the gate trench 180. In exemplary embodiments, the well contact region 332 may extend 0.1 to 3.0 microns into the semiconductor layer structure 360.

[0134] The support shield trench 350 may be formed through the well contact region 332 such that the well contact region 332 forms part of the side wall of the support shield trench 350. The support shield trench 350 may be a deep trench formed on the upper surface of the semiconductor layer structure 360. In exemplary embodiments, the support shield trench 350 may extend 0.1 to 4.0 microns or 1.0 to 3.5 microns into the semiconductor layer structure 360. The support shield trench 350 may extend deeper into the semiconductor layer structure 360 ​​than the gate trench 180, and in some embodiments, the support shield trench 350 may extend deeper into the semiconductor layer structure 360 ​​than the trench shielding region 154 formed below the gate trench 180. The support shield trench 350 may be filled with a conductive material 352 other than silicon carbide, such as p-type polysilicon, nickel oxide, or a metal that forms a Schottky contact with silicon carbide. The conductive material 352 filling each support shield trench 350 forms multiple support shields 352. The well contact region 332 may have a highly doped p-type region that directly contacts the corresponding support shield 352, forming a low-resistance contact to the support shield 352.

[0135] Having a support shield 352 formed from a conductive material other than silicon carbide can be advantageous in certain applications. For example, p-type silicon carbide may still have relatively high resistance even when doped to high concentrations. Therefore, performance improvements may be obtained by using other conductive materials with lower resistance levels. In addition, the non-silicon carbide conductive material used to form the support shield 352 can form a heterojunction diode with the drift layer 320 that can turn on at a lower voltage, thereby reducing conduction losses. The MOSFET 300 also has a faster switching speed than comparable conventional devices, and during avalanche breakdown, the conductive material can provide a current path that does not pass through the normal channel region of the MOSFET.

[0136] Figures 7A to 7F are schematic cross-sectional views illustrating the method for fabricating the gate-trench silicon carbide power MOSFET 300 shown in Figure 6.

[0137] Referring to Figure 7A, an n-type silicon carbide substrate 110 is provided. Next, a low concentration of (n) doped onto the upper surface of the substrate 110 is provided. - A silicon carbide drift layer 120 is formed, and p-type well regions 130 and n-type source layers 142 are formed in the same manner as described above, for example with reference to Figure 3A. A first mask 392, such as an oxide mask, is formed on the upper surface of the semiconductor layer structure 360, and this is then patterned (for example, using standard photolithography patterning techniques) to form openings 394 in the first mask 392 that expose selected portions of the semiconductor layer structure 360. The openings 394 are located above the location in the semiconductor layer structure 360 ​​where deep well contact regions 332 will be formed in subsequent processing steps.

[0138] Next, referring to Figure 7B, a high-energy ion implantation process is carried out to form a deep well contact region 332. The deep well contact region 332 can extend through the entire well region 130 into (or even through) the current diffusion layer 122. The formation of the deep well contact region 332 transforms the n-type source layer 142 into multiple spaced-apart n-type source regions 140. The mask 392 can then be removed.

[0139] Referring to Figure 7C, a second mask 396 (for example, another oxide mask) can be formed to cover the semiconductor layer structure 360. The second mask 396 can then be patterned (for example, using standard photolithography patterning techniques) to form openings 398 therein that expose selected portions of the semiconductor layer structure 360. The second mask 396 is then used as an etch mask to carry out an etching process to form a number of trenches 350 within the semiconductor layer structure 360. The trenches 350 are formed to extend into the drift layer 120 through the well contact regions 332. Each trench 350 can, for example, divide one well contact region into two well contact regions 332.

[0140] Referring to Figure 7D, a conductive material 352 other than silicon carbide can be deposited or formed in each trench 350. The conductive material 352 may be, for example, polysilicon, nickel oxide, or a metal that forms a Schottky contact with silicon carbide. The two masks 396 can then be removed.

[0141] Referring to Figure 7E, a third mask 399 (for example, another oxide mask) can be formed to cover the semiconductor layer structure 360 ​​and patterned to include openings where the gate trench 180 will be formed. An etching process is performed to etch the exposed portion of the semiconductor layer structure 360 ​​to form the gate trench 180. As shown, in some embodiments, the well contact region 332 may extend into the semiconductor layer structure 360 ​​to approximately the same depth as the gate trench 180. In other embodiments, the well contact region 332 may extend deeper into the semiconductor layer structure 360 ​​than the gate trench 180. Alternatively, the gate trench 180 may extend deeper into the semiconductor layer structure 360 ​​than the well contact region 332. Next, an ion implantation process is performed to implant p-type dopant ions into the portion of the semiconductor layer structure 360 ​​below the gate trench 180 to form a trench shielding pattern 154.

[0142] As shown in Figure 7F, a gate oxide layer 182 and a gate electrode 184 can then be formed in the gate trench 180, and an intermetallic dielectric layer 188 is formed to cover the gate oxide layer 182 and the gate electrode 184. Next, a source metallization layer 190 is formed on the source region 140, the intermetallic dielectric layer 188, the conductive material 352, and the well contact region 332.

[0143] Figure 8 is a schematic cross-sectional view of the gate-trench silicon carbide power MOSFET 300A, which is a modified version of the gate-trench silicon carbide power MOSFET 300. The gate-trench silicon carbide power MOSFET 300A is almost identical to the power MOSFET 300. As can be seen by comparing Figure 7 and Figure 8, the only difference between the power MOSFET 300 and the power MOSFET 300A is that the power MOSFET 300A includes a shallower support shield 352' that extends only to the same depth as the p-type well contact region 332, so that the bottom of the support shield 352' and the bottom of the p-type well contact region 332 are on the same plane or approximately on the same plane.

[0144] Figure 9 is a schematic cross-sectional view of a trench-gate silicon carbide power MOSFET 400 according to yet another embodiment of the present invention. The gate-trench silicon carbide power MOSFET 400 may be identical to the gate-trench silicon carbide power MOSFET 100 when viewed from above, and therefore Figure 2A also accurately represents the power MOSFET 400. The cross-section in Figure 9 is also taken along line 2C-2C in Figure 2A, showing how the power MOSFET 400 differs from the power MOSFET 300. Since many of the elements of the power MOSFET 400 are the same as the corresponding elements of the power MOSFET 300, the same reference numerals are used for those elements in Figures 6 and 9. In the following description, we will focus on the elements of the power MOSFET 400 that differ from those of the power MOSFET 300.

[0145] As can be seen by comparing Figures 6 and 9, the power MOSFETs 300 and 400 have different designs for the well contact regions 332 and 432, the support-shield trenches 350 and 450, and the support shields 352 and 452. In particular, in power MOSFET 300 (Figure 6), the well contact region 332 does not extend as deeply into the semiconductor layer structure 360 ​​as the support-shield trench 350, while in power MOSFET 400 (Figure 9), the well contact region 432 extends deeper into the semiconductor layer structure 460 than the trench 450. Therefore, in power MOSFET 400, the conductive material 452 filling each trench 450 is surrounded by the well contact region 452, and the main purpose of the conductive material 452 may be to provide a low-resistance electrical connection between the source metallization 190 and the well contact region 432. The electric field blocking function during reverse blocking operation (to protect the gate oxide layer 182) is performed by a deep well contact region 432 in the power MOSFET 400. The conductive material 452 may be a conductive material other than silicon carbide, such as polysilicon, nickel oxide, or a metal that forms a Schottky contact with silicon carbide. Although not shown in Figure 9, in yet another embodiment, the conductive material 452 may be a source metallization layer 190 (i.e., the source metallization layer 190 fills the trench 450). This same modification can also be made for MOSFET 300 in Figure 6, MOSFET 300A in Figure 8, and / or MOSFETs 400A, 400B (described later) in Figures 10A-10B.

[0146] In power MOSFET 400, the well contact area 432 is, for example, 5 × 10 16 ~1 × 10 22The well contact region 432 may have a p-type dopant concentration. In some embodiments, the well contact region 432 may have a p-type dopant concentration at least 10 times higher than that of the well region 130. The well contact region 432 may extend 0.1 to 4.0 microns into the semiconductor layer structure 460. In some embodiments, the well contact region 432 may extend deeper into the semiconductor layer than the gate trench 180. In some embodiments, the well contact region 432 may extend deeper into the semiconductor layer than the trench shielding region 154.

[0147] The trench 450 can be formed to any desired depth. In some embodiments, the trench 450 may penetrate the well region 130 completely but not extend as deeply into the semiconductor layer structure 460 as the gate trench 180. In other embodiments, the trench 450 may extend deeper into the semiconductor layer structure 460 than the gate trench 180.

[0148] Figures 10A and 10B are schematic cross-sectional views of the gate-trench silicon carbide power MOSFETs 400A and 400B, respectively, which are modified versions of the gate-trench silicon carbide power MOSFET 400 shown in Figure 9. Since the gate-trench silicon carbide power MOSFETs 400A and 400B are almost identical to the MOSFET 400, the following discussion will focus only on the differences between the MOSFETs 400A and 400B and the MOSFET 400.

[0149] As can be seen by comparing Figure 9 and Figure 10A, the only difference between MOSFET 400 and MOSFET 400A is that MOSFET 400A includes a pair of p-type well contact regions 432' between each pair of adjacent gate electrodes 184. Each support shield 452 is positioned between the two well contact regions 432' of each pair of well contact regions 432'. As a result, the bottom of each support shield can directly contact the drift layer 120.

[0150] As can be seen by comparing Figure 9 and Figure 10B, the only difference between MOSFET 400 and MOSFET 400B is that MOSFET 400B includes a recessed gate electrode 184' having a top surface lower than the top surface of the semiconductor layer structure 460. This arrangement configuration advantageously reduces the peak electric field at the upper corner of the gate oxide layer 182 during on-state operation. It will be understood that any of the semiconductor devices according to the embodiments of the present invention discussed above can be modified to have the gate electrode design shown in Figure 10B to provide additional embodiments of the present invention.

[0151] Figure 11 is a schematic cross-sectional view of the gate-trench silicon carbide power MOSFET 500, which is another modified version of the gate-trench silicon carbide power MOSFET 100 shown in Figures 2A-2C. Since the gate-trench silicon carbide power MOSFET 500 is almost identical to MOSFET 100, the following discussion will focus only on the differences between each of the MOSFET 500s and MOSFET 100.

[0152] As shown in Figure 11, MOSFET 500 differs from MOSFET 100 in that MOSFET 500 includes a highly doped p-type (p+) auxiliary well contact region 132A adjacent to the source region 140 above the p-well region 130. By providing the auxiliary well contact region 132A, the contact area between the source metallization layer 190 and the p-type material in the semiconductor layer structure 160 is increased, resulting in a lower resistance connection between them. The auxiliary well contact region 132A can be highly doped (p+) or moderately doped (p) with a p-type dopant and can be formed, for example, in the same ion implantation step used to form the well contact region 132. By providing the auxiliary well contact region 132A, the amount of contact between the source metallization layer 190 and the source region 140 can be reduced. Consequently, in MOSFET 500, the width of the source region 140 may be wider in some cases compared to MOSFET 100.

[0153] Embodiments of the present invention are described above, primarily with reference to cross-sectional views. In each of the embodiments of the present invention depicted, it will be understood that the well contact regions (e.g., 132, 332, 432) and support shields (e.g., 152, 352, 452) may be elongated structures that extend seamlessly into the plane of the figure across the active region of the semiconductor device. However, it will also be understood that in other embodiments, the well contact regions (e.g., 132, 332, 432) and support shields (e.g., 152, 352, 452) may instead be segmented structures with portions removed, in which case these structures will not extend seamlessly into the plane of the figure, but rather have multiple segments that are collinear and extend into the plane of the figure.

[0154] In the above description, each example embodiment has a specific conductivity type. In each of the above embodiments, it will be understood that a device with the opposite conductivity type can be formed simply by reversing the conductivity of the n-type and p-type layers. Therefore, it will be understood that the present invention encompasses both n-channel and p-channel devices for each different device structure (e.g., MOSFET, IGBT, etc.).

[0155] The present invention has been discussed primarily in relation to silicon carbide-based power semiconductor devices. However, it should be understood that silicon carbide is used as an example in this specification, and that the devices discussed herein can be formed from any suitable broadband gap semiconductor material system. For example, in any of the above embodiments, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used instead of silicon carbide.

[0156] Embodiments of the present invention have been described above with reference to the accompanying drawings illustrating embodiments of the present invention. However, it will be understood that the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments are provided to give thoroughness and completeness to this disclosure and to fully convey the scope of the invention to those skilled in the art. Similar reference numerals refer to similar elements throughout.

[0157] In this specification, the term "multiple" means two or more. In this specification, "substantially" means within ±10%.

[0158] Throughout this specification, terms such as "first," "second," etc., are used to describe various elements, but it will be understood that these elements are not limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The terms "and / or" include any combination of one or more of the related enumerated items.

[0159] The technical terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless explicitly indicated otherwise in the context. It will be further understood that, where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” indicate the presence of the mentioned feature, part, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, parts, steps, operations, elements, components, and / or groups thereof.

[0160] When an element, such as a layer, region, or substrate, is described as being "on top of" or "extending upward" to another element, it will be understood that the element may directly exist on top of or extend directly onto the other element, or there may be an intervening element. In contrast, when an element is described as being "directly on top of" another element or extending "directly upward" to another element, there is no intervening element. Similarly, when an element is described as being "connected to" or "bonded" to another element, it will be understood that the element may directly connect to or bond to the other element, or there may be an intervening element. In contrast, when an element is described as being "directly connected to" or "directly bonded" to another element, there is no intervening element.

[0161] In this specification, relative terms such as “below” or “above” or “upper side” or “lower side” or “top” or “bottom” may be used to describe the relationship between one element, layer, or region and another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass various arrangements of the device in addition to the arrangement depicted in the figures.

[0162] This specification describes embodiments of the present invention with reference to schematic cross-sectional views of idealized embodiments (and intermediate structures) of the present invention. Thicknesses of layers and regions in the drawings may be exaggerated for clarity. In addition, differences from the shapes shown in the drawings are naturally expected as a result of manufacturing techniques and / or tolerances. Embodiments of the present invention are further described with reference to a flowchart. It will be understood that the steps shown in the flowchart do not have to be performed in the order shown.

[0163] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions having a conductivity type such as n-type or p-type, where conductivity type refers to the majority carrier concentration within the layer and / or region. Thus, n-type materials have a majority equilibrium concentration of negatively charged electrons, while p-type materials have a majority equilibrium concentration of positively charged holes. Depending on the material, "+" or "-" may be used to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers compared to another layer or region (as in n+, n-, p+, p-, n++, n--, p++, or p--). However, such notation does not imply that a particular concentration of majority or minority carriers exists within the layer or region.

[0164] Typical embodiments of the present invention are disclosed in the drawings and specification, and although certain terms are used, they are used only in a general and descriptive sense and are not intended to be limiting, and the scope of the present invention is defined in the following claims.

Claims

1. A silicon carbide-based semiconductor layer structure including a drift layer having a first conductivity type, A gate trench extending to a first depth into the semiconductor layer structure, The gate electrode located in the gate trench, A support shield trench extending into the semiconductor layer structure to a second depth shallower than the first depth, A source metallization layer located on the aforementioned semiconductor layer structure and extending into the aforementioned support shield trench, A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the semiconductor layer structure further comprises a well contact region having a second conductivity type located beneath the support shield trench.

3. The semiconductor device according to claim 2, wherein the semiconductor layer structure further comprises a support shield having the second conductivity type located below the well contact region.

4. The semiconductor device according to claim 3, wherein the source metallization layer is in direct contact with the well contact region, and the well contact region is in direct contact with the support shield.

5. The semiconductor device according to claim 3, wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type located below the gate trench.

6. The aforementioned semiconductor layer structure is A well region having the second conductivity type located on the upper surface of the drift layer, A source region having the first conductivity type located on the upper surface of the well region The semiconductor device according to claim 3, further comprising the above.

7. The semiconductor device according to claim 6, wherein the source metallization layer in the support shield trench is in direct contact with the side surface of the source region and the upper surface of the well contact region.

8. The semiconductor device according to claim 3, wherein the well contact region has a first doping concentration of the second conductivity type dopant that is at least 10 times higher than the second doping concentration of the second conductivity type dopant in the well region.

9. The semiconductor device according to claim 8, wherein the first doping concentration of the second conductivity type dopant is at least 10 times higher than the third doping concentration of the second conductivity type dopant of the support shield.

10. The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor layer structure further comprises a source region, and the source metallization layer is in direct contact with both the upper and side surfaces of the source region.

11. The semiconductor device according to claim 5, wherein the support shield extends further downward within the semiconductor layer structure than the trench shielding region extends.

12. The semiconductor device according to claim 6, wherein the well contact region electrically connects the well region to the source metallization layer.

13. A silicon carbide-based semiconductor layer structure, The support shield trench within the semiconductor layer structure, The metal layer extending into the aforementioned support shield trench, The gate trench within the aforementioned semiconductor layer structure, The gate electrode located in the gate trench and Equipped with, The silicon carbide-based semiconductor layer structure is A drift layer having a first conductivity type, A well region having a second conductivity type on the drift layer, A source region having the first conductivity type located on the well region, A support shield having a second conductive type, located below the support shield trench and extending into the drift layer. A semiconductor device equipped with the following features.

14. The semiconductor device according to claim 13, wherein the semiconductor layer structure further comprises a well contact region having the second conductivity type located within the well region and a trench shielding region having the second conductivity type located below the gate trench, wherein the upper surface of the well contact region is recessed and lower than the upper surface of the source region.

15. The semiconductor device according to claim 14, wherein the well contact region has a first doping concentration of the second conductivity type dopant that is at least 10 times higher than the second doping concentration of the second conductivity type dopant in the well region.

16. The semiconductor device according to claim 14, wherein the metal layer in the support shield trench is in direct contact with the side surface of the source region and the upper surface of the well contact region.

17. The semiconductor device according to any one of claims 13 to 16, wherein the gate trench extends further downward within the semiconductor layer structure than the support shield trench extends.

18. The semiconductor device according to any one of claims 14 to 16, wherein the well contact region has a first doping concentration of the second conductivity type dopant that is at least 10 times higher than the third doping concentration of the second conductivity type dopant of the support shield.

19. The semiconductor device according to any one of claims 13 to 16, wherein the metal layer is in direct contact with both the upper and side surfaces of the source region.

20. The semiconductor device according to any one of claims 14 to 16, wherein the support shield extends further downward within the semiconductor layer structure than the trench shielding region extends.

21. The semiconductor device according to any one of claims 14 to 16, wherein the upper surface of the well contact region is recessed and lower than the upper surface of the well region.

22. The semiconductor device according to any one of claims 14 to 16, wherein the well contact region electrically connects the well region to the metal layer.

23. A semiconductor device comprising multiple unit cell transistors, A silicon carbide-based semiconductor layer structure, A drift layer having a first conductivity type, A well region having a second conductivity type on the drift layer, A source region having the first conductivity type located on the well region, and A well contact region having the second conductivity type located within the well region, wherein the well contact region is a portion of the well region having a higher dopant concentration, and the upper surface of the well contact region is recessed and lower than the upper surface of the source region. A silicon carbide-based semiconductor layer structure comprising, A gate trench extending to a first depth into the upper surface of the semiconductor layer structure, A source metallization layer extends between the source regions of adjacent unit cell transistors so as to be in direct contact with the well contact region. A semiconductor device equipped with the following features.

24. The semiconductor device according to claim 23, wherein the semiconductor layer structure further comprises a support shield having the second conductivity type located below the well contact region.

25. The semiconductor device according to claim 24, wherein the source metallization layer is in direct contact with the well contact region, and the well contact region is in direct contact with the support shield.

26. The semiconductor device according to claim 24, wherein the source metallization layer is in direct contact with the side surface of the source region.

27. The semiconductor device according to claim 24, wherein the well contact region has a first doping concentration of the second conductivity type dopant that exceeds the second doping concentration of the second conductivity type dopant in the well region and also exceeds the third doping concentration of the second conductivity type dopant in the support shield.

28. The semiconductor device according to claim 24, wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type located below the gate trench, and the support shield extends further downward within the semiconductor layer structure than the trench shielding region extends.

29. A silicon carbide-based semiconductor layer structure, A drift layer having a first conductivity type, A well region having a second conductivity type on the drift layer, A source region having the first conductivity type located on the well region, and A well contact region having the second conductivity type within the well region, which is a portion of the well region having a higher dopant concentration. A silicon carbide-based semiconductor layer structure comprising, The source metallization layer is in contact with the upper and side surfaces of the source region and the upper surface of the well contact region. A semiconductor device comprising multiple unit cell transistors.

30. The semiconductor device according to claim 29, wherein the semiconductor layer structure further comprises a support shield having the second conductivity type located below the well contact region.

31. The semiconductor device according to claim 30, wherein the source metallization layer is in direct contact with the well contact region, and the well contact region is in direct contact with the support shield.

32. The semiconductor device according to claim 31, wherein the well contact region has a first doping concentration of the second conductivity type dopant that exceeds the second doping concentration of the second conductivity type dopant in the well region and also exceeds the third doping concentration of the second conductivity type dopant in the support shield.

33. The semiconductor device according to claim 30, wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type located below the gate trench, and the support shield extends further downward within the semiconductor layer structure than the trench shielding region extends.

34. A silicon carbide-based semiconductor layer structure, A drift layer having a first conductivity type, A well region having a second conductivity type on the drift layer, A well contact region having the second conductivity type extending below the well region, and A silicon carbide-based semiconductor layer structure comprising, The gate trench within the aforementioned semiconductor layer structure, The gate electrode located in the gate trench, A support shield trench extending through the well contact region, and a support shield trench extending below the well contact region, The support shield located within the aforementioned support shield trench and A semiconductor device equipped with the following features.

35. The semiconductor device according to claim 34, wherein the support shield is in direct contact with the well contact area.

36. The semiconductor device according to claim 34, wherein the support shield trench extends further downward within the semiconductor layer structure than the gate trench.

37. The semiconductor device according to any one of claims 34 to 36, wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type below the gate trench, and the support shield trench extends further downward within the semiconductor layer structure than the trench shielding region.

38. The semiconductor device according to any one of claims 34 to 36, wherein the well contact region has a first doping concentration of the second conductivity type dopant that is at least 10 times higher than the second doping concentration of the second conductivity type dopant in the well region.

39. The semiconductor device according to any one of claims 34 to 36, wherein the support shield comprises doped polysilicon.

40. The semiconductor device according to any one of claims 34 to 36, wherein the support shield comprises nickel oxide.

41. The semiconductor device according to any one of claims 34 to 36, wherein the support shield includes a metal that is in Schottky contact with silicon carbide.

42. The semiconductor device according to any one of claims 34 to 36, wherein the semiconductor layer structure further comprises a source region having the first conductivity type located on the well region, and the well contact region is located between the support shield and the well region, and between the support shield and the source region.

43. The semiconductor device according to any one of claims 34 to 36, wherein the well contact region extends through the well region into the drift layer.

44. The semiconductor device according to any one of claims 34 to 36, wherein the well contact region extends into the semiconductor layer structure to at least the same depth as the gate trench.

45. A silicon carbide-based semiconductor layer structure, A drift layer having a first conductivity type, A well region having a second conductivity type on the drift layer, A well contact region having the second conductivity type extending below the well region, and Source region having the first conductivity type located on the well region A silicon carbide-based semiconductor layer structure comprising, A gate trench on the upper surface of the semiconductor layer structure, The gate electrode located in the gate trench, A trench extending into the well contact region, The conductive material other than silicon carbide located in the trench A semiconductor device equipped with the following features.

46. The semiconductor device according to claim 45, wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type located below the gate trench, and the support shield extends further downward within the semiconductor layer structure than the trench shielding region.

47. The semiconductor device according to claim 46, wherein the conductive material includes doped polysilicon.

48. The semiconductor device according to claim 46, wherein the conductive material includes nickel oxide.

49. The semiconductor device according to claim 46, wherein the conductive material includes a metal that is in Schottky contact with silicon carbide.

50. The semiconductor device according to any one of claims 45 to 49, wherein the support shield extends to the upper surface of the semiconductor layer structure.

51. The semiconductor device according to any one of claims 45 to 49, wherein the trench extends further into the semiconductor layer structure than the gate trench.

52. The semiconductor device according to claim 45, wherein the trench does not penetrate the bottom surface of the well junction region.

53. The semiconductor device according to any one of claims 45 to 49, wherein the well contact region extends into the semiconductor layer structure to at least the same depth as the gate trench.

54. The steps include providing a silicon carbide-based semiconductor layer structure including a drift layer having a first conductivity type, The steps include forming a gate trench extending to a first depth into the upper surface of the semiconductor layer structure, The steps include forming a gate electrode in the gate trench, The steps include forming a support shield trench extending into the upper surface of the semiconductor layer structure to a second depth shallower than the first depth, The steps include forming a source metallization layer on the upper surface of the semiconductor layer structure and extending into the support shield trench, and A method for forming a semiconductor device, including [a specific component].

55. The method according to claim 54, wherein the support shield trench is formed before the gate trench is formed.

56. The method according to claim 54, further comprising the step of forming a well contact region having a second conductivity type below the support shield trench.

57. The method according to claim 56, further comprising the step of forming a support shield having the second conductivity type below the well contact region.

58. The method according to claim 57, wherein the source metallization layer is in direct contact with the well contact region, and the well contact region is in direct contact with the support shield.

59. The steps include forming a well region having the second conductivity type on the upper surface of the drift layer, The steps include forming a source region having the first conductivity type on the upper surface of the well region, The steps include forming a trench shielding region having the second conductivity type below the gate trench, The method according to claim 58, further comprising:

60. The method according to claim 59, wherein the source metallization layer in the support shield trench is in direct contact with the side surface of the source region and the upper surface of the well contact region.

61. The method according to claim 59, wherein the support shield extends further downward within the semiconductor layer structure than the trench shielding region extends.

62. The method according to claim 59, wherein the well contact region has a first doping concentration of the second conductive dopant that is at least 10 times higher than the second doping concentration of the second conductive dopant in the well region and at least 10 times higher than the third doping concentration of the second conductive dopant in the support shield.

63. A silicon carbide-based semiconductor layer structure including a drift layer having a first conductivity type, A gate trench extending into the aforementioned semiconductor layer structure, The gate electrode located in the gate trench, Support shield trenches extending into the aforementioned semiconductor layer structure, The non-silicon carbide conductive material located within the aforementioned support shield trench and A semiconductor device equipped with the following features.

64. The semiconductor device according to claim 63, further comprising a support shield having a second conductivity type, wherein the support shield trench extends into the support shield.

65. The semiconductor device according to claim 64, wherein the support shield extends through both the upper and lower surfaces of the support shield.

66. The semiconductor device according to claim 64, wherein the non-silicon carbide conductive material includes doped polysilicon, nickel oxide, or a metal that forms a Schottky contact with silicon carbide.

67. The semiconductor device according to claim 64, wherein the support shield trench extends further into the semiconductor layer structure than the gate trench.

68. The semiconductor device according to claim 64, wherein the gate trench extends further into the semiconductor layer structure than the support shield trench.

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