Gate trench power semiconductor devices with deep support shields that reduce cell pitch and on-state resistance.

Abstract

A semiconductor device, typically a trench-gate vertical MOSFET, includes a silicon carbide-based semiconductor layer structure and first gate trenches 180, 182, 184 extending into the upper part of the semiconductor layer structure. The semiconductor layer structure comprises a drift region 120 having a first conductivity type, a well layer 130 having a second conductivity type, and a support shield 150 having a second conductivity type. The width of the first segment of the support shield, which is deeper in the semiconductor layer structure than the well layer and shallower in the semiconductor layer structure than the bottom of the first gate trench, narrows as the distance from the well region increases. Furthermore, the support shield 150 may have an embedded lateral extension 158A, and the gate trench 180 may be provided with a trench shielding region 152.

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 18 / 482,105, filed on 6 October 2023, the entirety of which is incorporated herein by reference.

[0002] The present invention relates to power semiconductor devices, and more particularly to power semiconductor devices having gate trenches, and to methods for manufacturing such devices. [Background technology]

[0003] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a well-known type of semiconductor transistor that can be used as a switch. A MOSFET is a three-terminal device having a gate terminal, a drain terminal, a source terminal, and a semiconductor body. In this specification, the semiconductor body is referred to as a “semiconductor layer structure” and may contain one or more semiconductor layers / regions. Within the semiconductor layer structure, a source region and a drain region are formed, separated by a channel region. The gate electrode (which can function as a gate terminal or be electrically connected to a gate terminal) is positioned adjacent to the channel region and separated from it by a thin oxide layer. A MOSFET can be turned on or off by setting the bias voltage applied to the gate electrode to be above or below a threshold. When a MOSFET is on (i.e., in the “on state”), current flows through the channel region between the source and drain regions. When the bias voltage is reduced below the threshold level, current stops flowing through the channel region.

[0004] An n-type MOSFET has a source and drain region having n-type (electron) conductivity, and a channel region having p-type (hole) conductivity (i.e., an "npn" design). When a gate bias voltage sufficient to generate a conductive n-type inversion layer in the p-type channel region is applied to the gate electrode, the n-type MOSFET turns on, thereby electrically connecting the n-type source and drain regions and enabling majority carrier conduction between them. A p-type MOSFET has a "pnp" design (i.e., a p-type source and drain region, and an n-type channel region) and turns on when a gate bias voltage sufficient to generate a conductive p-type inversion layer in the n-type channel region to electrically connect the p-type source and drain regions is applied to the gate electrode. In this specification, the terms "first conductivity type" and "second conductivity type" are used to indicate either n-type or p-type, and are distinct from the first and second conductivity types. Therefore, if a first region of the device has a first conductivity type and a second region of the device has a second conductivity type, this means either the first region has n-type conductivity and the second region has p-type conductivity, or alternatively, the first region has p-type conductivity and the second region has n-type conductivity.

[0005] As described above, the gate electrode of a MOSFET is isolated from the channel region by a thin oxide layer called the gate oxide layer. In certain applications, other non-oxide gate dielectric layers may be used instead of the gate oxide layer. It will be understood that the techniques according to the embodiments of the present invention described herein are equally applicable to devices having gate dielectric layers formed from non-oxide materials.

[0006] Because the gate electrode of a MOSFET is isolated from the channel region by the gate oxide layer, a minimal gate current is sufficient to maintain the MOSFET in the ON state or to switch it between the OFF and ON states. Since the gate forms a capacitor with the channel region, the gate current during switching is kept low. Therefore, only minimal charge / discharge current is required during switching, allowing for a simpler gate drive circuit and faster switching speeds. MOSFETs may be standalone devices or combined with other circuit devices. For example, an insulated gate bipolar transistor ("IGBT") is a semiconductor device that includes both a MOSFET and a bipolar junction transistor ("BJT"), combining the high-impedance gate electrode of the MOSFET with the low on-state conduction loss that can be achieved by the BJT. An IGBT may be implemented, for example, as a Darlington pair with a high-voltage n-channel MOSFET at the input and a BJT at the output. The basic current of the BJT is supplied through the MOSFET channel, which allows for a simplified external drive circuit (since the drive circuit only charges and discharges the gate electrode of the MOSFET).

[0007] In some applications, MOSFETs may need to carry large currents and / or block high voltages. Such MOSFETs are often called “power” MOSFETs. Power MOSFETs are often fabricated from wide-bandgap semiconductor materials (in this specification, the term “wide-bandgap semiconductor” encompasses any semiconductor having a bandgap of at least 1.4 eV). Power semiconductor devices are often formed from silicon carbide ("SiC": silicon carbide), which has several advantageous properties, including, for example, high field dielectric strength, high thermal conductivity, high electron mobility, high melting point, and high saturation electron drift rate.

[0008] Power semiconductor devices such as power MOSFETs may have a lateral or vertical structure. In devices with a lateral structure, the device terminals (e.g., drain terminal, gate terminal, and source terminal for a power MOSFET) are located on the same main surface (i.e., top or bottom) of the semiconductor layer structure. In contrast, in devices with a vertical structure, at least one terminal is provided on each main surface of the semiconductor layer structure (for example, in a vertical MOSFET, the source and gate may be on the top surface of the semiconductor layer structure, and the drain may be on the bottom surface of the semiconductor layer structure). The semiconductor layer structure may or may not include a substrate such as a growth substrate.

[0009] The semiconductor layer structure of a power semiconductor device typically includes an "active region" on which one or more functional semiconductor devices are formed. The active region acts as a primary junction for blocking voltage during reverse bias (off-state) operation and for allowing current flow during forward bias (on-state) operation. Power semiconductor devices may also have edge termination structures, such as guard rings or junction termination extensions, in the termination regions of the semiconductor layer structure adjacent to (usually surrounding) the active region. Edge termination structures can, among other things, reduce the electric field concentration effects that may occur at the outer edges of the power semiconductor device. Typically, multiple power semiconductor devices are formed on / within a common wafer, and each power semiconductor device will usually have its own edge termination structure. After the wafer is fully processed, the resulting structure can be diced to isolate the individual edge-terminated power semiconductor devices. Each power semiconductor device may have a unit cell structure, in which the active regions of each power semiconductor device include multiple individual "unit cell" devices that are electrically connected in parallel and function together as a single power semiconductor device.

[0010] Vertical power semiconductor devices, including MOSFETs, can have a planar gate electrode design in which the transistor's gate electrode is formed on top of the semiconductor layer structure, or alternatively, the gate electrode may be embedded in a gate trench within the semiconductor layer structure, the latter of which is commonly called a gate trench MOSFET. In a planar gate electrode design, the channel region of each unit cell transistor is located horizontally beneath the gate electrode. In contrast, in a gate trench MOSFET design, the channel is typically located vertically adjacent to the sidewall of the gate electrode. Gate trench MOSFETs can achieve performance enhancements, but typically require more complex manufacturing processes.

[0011] One failure mechanism of power MOSFETs is the so-called "breakdown" of the gate oxide layer. The gate oxide layer is subjected to high electric fields during normal device operation. The stress on the gate oxide layer caused by these electric fields creates defects in the oxide material, and these defects accumulate over time. When the concentration of defects reaches a critical value, a so-called "percolation path" may form through the gate oxide layer, which electrically connects the gate electrode to the source region or the drain region, causing a short circuit that can destroy the device. The "lifetime" of the gate oxide layer (i.e., how long the device can be operated before dielectric breakdown occurs) depends inter alia on the magnitude of the electric field to which the gate oxide layer is subjected and the length of time the electric field is applied. Figure 1 is a schematic graph showing the relationship between the operating time until dielectric breakdown occurs ("gate oxide lifetime") and the level of the electric field applied to the gate oxide layer. This graph assumes that the same electric field is always applied (which is not necessarily the case). As shown in Figure 1, when the gate oxide lifetime is plotted on a logarithmic scale, the relationship can in some cases be substantially linear. An important point that can be seen from Figure 1 is that as the electric field level increases, the lifetime of the gate oxide layer decreases exponentially. Although the lifetime of the gate oxide layer can be extended by increasing the thickness of the gate oxide layer, various performance parameters of the MOSFET may depend on the thickness of the gate oxide layer, so increasing the thickness of the gate oxide layer is generally not an acceptable way to extend the lifetime of the gate oxide layer.

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

[0013] According to some embodiments of the present invention, there is provided a semiconductor device comprising: a silicon carbide-based semiconductor layer structure including a drift region having a first conductivity type, a well layer having a second conductivity type, and a support shield having the second conductivity type; and a first gate trench extending into an upper portion of the semiconductor layer structure. The width of the first portion of the support shield narrows as the distance from the well region increases.

[0014] In some embodiments, the first portion of the support shield includes a portion that is deeper than the well layer in the semiconductor layer structure and shallower than the bottom of the first gate trench in the semiconductor layer structure.

[0015] In some embodiments, the entire support shield located deeper than the well layer in the semiconductor layer structure has a width that narrows as the distance from the well region increases.

[0016] In some embodiments, the bottom of the first gate trench has a first depth from the top of the semiconductor layer structure, the bottom of the support shield has a second depth from the top of the semiconductor layer structure, and the second depth is greater than the first depth. In some embodiments, the semiconductor layer structure further includes a trench shield region of the second conductivity type located below the first gate trench, the bottom of the trench shield region has a third depth from the top of the semiconductor layer structure, and the second depth is greater than the third depth.

[0017] In some embodiments, the semiconductor layer structure further includes an embedded support shield extension extending laterally from the support shield.

[0018] In some embodiments, the semiconductor device comprises a MOSFET, the semiconductor layer structure further comprising a source layer having a first conductivity type on a well layer, and a gate oxide layer and a gate electrode within a first gate trench, the gate oxide layer being between the gate electrode and the semiconductor layer structure.

[0019] In some embodiments, the maximum width of the support shield portion that horizontally overlaps the source region is at least 10% wider than the width of the support shield portion that horizontally overlaps the bottom of the first gate trench.

[0020] In some embodiments, the semiconductor device further comprises a second gate trench extending into the upper part of the semiconductor layer structure, and a support shield is located between the first gate trench and the second gate trench.

[0021] In some embodiments, the semiconductor layer structure includes a support-shield trench that extends at least partway through the support-shield, and a conductive material other than silicon carbide is present within the support-shield trench. In some embodiments, the conductive material may be doped polysilicon, nickel oxide, or a metal in Schottky contact with silicon carbide.

[0022] In some embodiments, the support shield trench does not penetrate the bottom surface of the support shield.

[0023] A semiconductor device is provided comprising a silicon carbide-based semiconductor layer structure, the silicon carbide-based semiconductor layer structure comprising: a drift region having a first conductivity type; a JFET region having a first conductivity type above the drift region and having a doping concentration of the first conductivity type higher than that of the drift region; a well layer having a second conductivity type above the JFET region; and a support shield having a second conductivity type. A first gate trench extends into the upper part of the semiconductor layer structure. The first portion of the JFET region between the first gate trench and the support shield has a width that increases with increasing distance from the well layer.

[0024] In some embodiments, at least a portion of the support shield has a width that narrows as the distance from the top of the semiconductor layer structure increases.

[0025] In some embodiments, the bottom of the first gate trench has a first depth from the top of the semiconductor layer structure, and the bottom of the support shield has a second depth from the top of the semiconductor layer structure, the second depth being greater than the first depth.

[0026] In some embodiments, the semiconductor layer structure further comprises a trench shielding region having a second conductivity type located below the first gate trench, the bottom of which has a third depth from the top of the semiconductor layer structure, and the second depth is greater than the third depth.

[0027] In some embodiments, the semiconductor layer structure further comprises an embedded support-shield extension extending laterally from the support-shield. In some embodiments, the support-shield extension extends laterally over a distance of 0.1 to 5.0 microns. In some embodiments, the support-shield extension has a thickness of 0.1 to 20 microns.

[0028] In some embodiments, the semiconductor device comprises a MOSFET, the semiconductor layer structure further comprising a source layer having a first conductivity type on a well layer, and a gate oxide layer and a gate electrode within a first gate trench, the gate oxide layer being between the gate electrode and the semiconductor layer structure.

[0029] In some embodiments, the semiconductor device comprises a MOSFET, and the semiconductor layer structure further comprises a source layer having a first conductivity type on a well layer, wherein the maximum width of the support shield portion that horizontally overlaps the source layer is at least 10% wider than the width of the support shield portion that horizontally overlaps the bottom of the first gate trench.

[0030] In some embodiments, the semiconductor device further comprises a second gate trench extending into the upper part of the semiconductor layer structure, and a support shield is located between the first gate trench and the second gate trench.

[0031] In some embodiments, the semiconductor layer structure includes a support-shield trench extending at least partway through the support-shield, and a conductive material other than silicon carbide is present within the support-shield trench. In some embodiments, the conductive material includes one of doped polysilicon, nickel oxide, or a metal that is in Schottky contact with silicon carbide.

[0032] In some embodiments, the support shield trench does not penetrate the bottom portion of the support shield.

[0033] According to an additional embodiment of the present invention, a semiconductor device is provided comprising a silicon carbide-based semiconductor layer structure, the silicon carbide-based semiconductor layer structure comprising: a drift region having a first conductivity type; a support shield having a second conductivity type; and an embedded lateral support shield extension having a second conductivity type, extending laterally from the support shield. A first gate trench extends into the upper part of the semiconductor layer structure. The sidewalls of the support shield extend along the crystal axis of the semiconductor layer structure.

[0034] In some embodiments, the sidewalls of the embedded lateral support shield extensions do not extend along the crystal axes of the silicon carbide semiconductor layer structure. In some embodiments, the crystal axis is one of the <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113> crystal axes. In other embodiments, the crystal axis is <0001> This is the crystal axis.

[0035] In some embodiments, at least portions of the first and second sidewalls of the support shield are inclined inward as the depth into the semiconductor layer structure increases.

[0036] In some embodiments, the semiconductor layer structure further comprises a JFET region having a first conductivity type between the drift region and the well region and between the support shield and the first gate trench, wherein the minimum distance between the embedded lateral support shield extension and the trench shield is at least the same as the minimum width of the JFET region.

[0037] In some embodiments, the semiconductor layer structure further comprises a trench shielding region having a second conductivity type located below the first gate trench, and the upper part of the support shield extension is located deeper within the semiconductor layer structure than the depth of the bottom surface of the trench shielding region.

[0038] In some embodiments, the embedded support shield extension extends laterally from the support shield over a distance of 0.1 to 20 microns.

[0039] In some embodiments, the semiconductor device further comprises a second gate trench extending into the upper part of the semiconductor layer structure, and a support shield is located between the first gate trench and the second gate trench.

[0040] A further embodiment of the present invention provides a method for fabricating a semiconductor device. According to these methods, a semiconductor layer structure is provided, comprising a drift region having a first conductivity type. First and second gate trenches are formed within the semiconductor layer structure. A mask including an opening is formed on top of the semiconductor layer structure, and at least one of the sidewalls of the mask defining the opening is an inclined sidewall that forms an obtuse angle with respect to the upper part of the semiconductor layer structure exposed through the opening. Using the mask as an ion implantation shield, a dopant of the second conductivity type is implanted into the semiconductor layer structure to form a support shield having the second conductivity type between the first gate trench and the second gate trench.

[0041] In some embodiments, the obtuse angle is between 100° and 160°.

[0042] In some embodiments, the width of the support shield decreases as the distance from the top of the semiconductor layer structure increases.

[0043] In some embodiments, the bottom of the first gate trench has a first depth from the top of the semiconductor layer structure, and the bottom of the support shield has a second depth from the top of the semiconductor layer structure, the second depth being greater than the first depth.

[0044] In some embodiments, the semiconductor layer structure further comprises a trench shielding region having a second conductivity type located below the first gate trench, the bottom of which has a third depth from the top of the semiconductor layer structure, and the second depth is greater than the third depth.

[0045] In some embodiments, the method further includes injecting a dopant of a second conductivity type into a semiconductor layer structure to form an embedded support shield extension that extends laterally from the support shield.

[0046] In some embodiments, a second conductivity type dopant, which is implanted into the semiconductor layer structure to form an embedded support shield extension, is implanted using a random ion implantation process.

[0047] In some embodiments, a second conductivity type dopant, which is implanted into the semiconductor layer structure to form a support shield, is implanted using a channel-type ion implantation process.

[0048] In some embodiments, a second conductivity type dopant, which is implanted into the semiconductor layer structure to form a support shield, is implanted using a channel-type ion implantation process.

[0049] In some embodiments, the semiconductor layer structure further comprises a well layer having a second conductivity type on a drift region and a source layer having a first conductivity type on the well layer, wherein the maximum width of the support shield portion horizontally overlapping the source region is at least 10% wider than the width of the support shield portion horizontally overlapping the bottom of the first gate trench.

[0050] According to another additional embodiment of the present invention, a method for fabricating a semiconductor device is provided, wherein a semiconductor layer structure is provided which has a drift region having a first conductivity type. First and second gate trenches are formed within the semiconductor layer structure. A support-shield structure is formed within the semiconductor layer structure by implanting a dopant of the second conductivity type into the semiconductor layer structure using both a non-channel ion implantation process and a channel ion implantation process.

[0051] In some embodiments, the same ion implantation mask is used for both non-channel ion implantation processes and channel ion implantation processes.

[0052] In some embodiments, the support-shield structure comprises a support shield formed by a channel-type ion implantation process and an embedded lateral support-shield extension formed by a non-channel-type ion implantation process.

[0053] In some embodiments, the channel-type ion implantation process is carried out along one of the following crystal axes: <0001, <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113>.

[0054] According to yet another embodiment of the present invention, a method for fabricating a semiconductor device is provided. According to these methods, a semiconductor layer structure is provided, comprising a drift region having a first conductivity type. A dopant of a second conductivity type is injected into the semiconductor layer structure to form a preliminary support shield. A dopant of the first conductivity type is injected into the semiconductor layer structure to convert the outer portion of the preliminary support shield to a material of the first conductivity type, thereby forming a support shield having a first sidewall, wherein at least a portion of the first sidewall is inclined inward as the depth into the semiconductor layer structure increases.

[0055] In some embodiments, a second conductive dopant is implanted into the semiconductor layer structure using a channel-type ion implantation process.

[0056] In some embodiments, a first-conductivity dopant is implanted into a semiconductor layer structure using a random ion implantation process.

[0057] In some embodiments, a second conductivity type dopant is implanted into the semiconductor layer structure using a random ion implantation process, and a first conductivity type dopant is implanted into the semiconductor layer structure using a random ion implantation process. [Brief explanation of the drawing]

[0058] [Figure 1] This graph shows the relationship between the lifetime of the gate oxide layer and the applied electric field strength as a function, plotted on a semi-logarithmic graph. [Figure 2] This is a schematic cross-sectional view of a unit cell of a gate trench power MOSFET with a support shield. [Figure 3A] This is a schematic top view of a gate-trench silicon carbide power MOSFET according to a specific embodiment of the present invention. [Figure 3B] Figure 3A is a schematic top view of a gate-trench silicon carbide power MOSFET with various upper metal and dielectric layers removed. [Figure 3C] Figures 3A and 3B show schematic cross-sectional views of a gate-trench silicon carbide power MOSFET taken along line 3C-3C in Figure 3A. [Figure 4A] Figures 3A to 3C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 4B] Figures 3A to 3C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 4C] Figures 3A to 3C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 4D] Figures 3A to 3C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 4E] Figures 3A to 3C are schematic cross-sectional views illustrating the method for fabricating gate-trench silicon carbide power MOSFETs. [Figure 5] Figures 3A to 3C are flowcharts showing the method for fabricating the gate-trench silicon carbide power MOSFETs. [Figure 6A] Figures 3A and 3C show schematic cross-sectional views of a modified gate-trench silicon carbide power MOSFET, with the cross-section taken along line 3C-3C in Figure 3A. [Figure 6B]Figures 3A and 3C show schematic cross-sectional views of a modified gate-trench silicon carbide power MOSFET, with the cross-section taken along line 3C-3C in Figure 3A. [Figure 6C] Figures 3A and 3C show schematic cross-sectional views of a modified gate-trench silicon carbide power MOSFET, with the cross-section taken along line 3C-3C in Figure 3A. [Figure 6D] Figures 3A and 3C show schematic cross-sectional views of a modified gate-trench silicon carbide power MOSFET, with the cross-section taken along line 3C-3C in Figure 3A. [Figure 6E] Figures 3A and 3C show schematic cross-sectional views of a modified gate-trench silicon carbide power MOSFET, with the cross-section taken along line 3C-3C in Figure 3A. [Figure 7] This is a schematic cross-sectional view of a gate-trench silicon carbide power MOSFET according to a further embodiment of the present invention. [Figure 8A] Figure 7 shows schematic cross-sectional views of three modified versions of the gate-trench silicon carbide power MOSFET. [Figure 8B] Figure 7 shows schematic cross-sectional views of three modified versions of the gate-trench silicon carbide power MOSFET. [Figure 8C] Figure 7 shows schematic cross-sectional views of three modified versions of the gate-trench silicon carbide power MOSFET. [Figure 9A] Figures 4A to 4B, along with Figure 7, are schematic cross-sectional views illustrating the method for fabricating the gate-trench silicon carbide power MOSFET shown in Figure 7. [Figure 9B] Figures 4A to 4B, along with Figure 7, are schematic cross-sectional views illustrating the method for fabricating the gate-trench silicon carbide power MOSFET shown in Figure 7. [Figure 10A] This figure shows another process according to an embodiment of the present invention, which can be used to form a support shield having side walls that slope inward as the depth increases. [Figure 10B] This figure shows another process according to an embodiment of the present invention, which can be used to form a support shield having side walls that slope inward as the depth increases. [Figure 10C] This figure shows another process according to an embodiment of the present invention, which can be used to form a support shield having side walls that slope inward as the depth increases. [Modes for carrying out the invention]

[0059] Silicon carbide-based vertical power semiconductor devices with gate trenches, such as vertical power MOSFETs and IGBTs, are attractive for many applications because their inherent relative on-resistance is relatively low, which can result in more efficient power switching operation. The channels in gate-trench vertical power devices are formed in the sidewalls of the gate trench, thus creating vertical channels. Carrier mobility in these vertically oriented sidewall channels can be approximately 2 to 4 times higher than the corresponding carrier mobility in the horizontal channels of standard planar-gate (i.e., non-gate-trench) vertical power devices, resulting in higher current density during on-state operation and enabling higher switching speeds. The gate-trench design also reduces the overall pitch of the device, thereby improving device integration. The reduced conduction losses (due to lower on-state resistance) and improved switching speeds make gate-trench power devices particularly suitable for high-frequency power applications with low to medium cutoff voltage requirements (e.g., 600 to 1200 volts). These devices have relaxed requirements for associated passive components, and relatively simple cooling methods may suffice. Since MOSFETs are the most widely used silicon carbide-based gate trench power semiconductor devices, the following discussion will focus on MOSFET embodiments. However, it will be understood that each of the described embodiments can be implemented using alternative non-oxide gate dielectric layers (e.g., nitrides, high dielectric constant materials, etc.), and that other gate trench power semiconductor devices such as IGBTs and gate-controlled thyristors can be formed using the same techniques.

[0060] As discussed above, gate trench power MOSFETs are prone to oxide reliability issues due to the presence of a high electric field in the gate oxide layer lining the bottom and side walls of the gate trench. This high electric field causes the gate oxide layer to degrade over time, potentially leading to device failure. When a gate trench MOSFET operates in reverse-cut operation (i.e., the MOSFET is in its off state), the MOSFET's source terminal is typically grounded, the gate terminal is typically grounded or placed under a negative bias voltage, and the drain terminal is typically placed under a high positive voltage. During such reverse-cut operation, a high electric field extends upward from the drain terminal (located on the bottom surface of the semiconductor layer structure) towards the top surface of the semiconductor layer structure. Therefore, under reverse-cut operation, the bottom portion of the gate dielectric layer experiences the highest electric field level. Due to the concentration effect of the electric field, the electric field level can be particularly high at the lower "corner" of the gate oxide layer at the bottom edge of the gate trench (i.e., the portion of the gate oxide layer that covers the area where the sidewalls of the gate trench meet the bottom of the gate trench). Furthermore, due to the difference in dielectric constant between silicon carbide and silicon oxide, the electric field within the silicon oxide gate oxide layer can be approximately 2.6 times higher than the electric field within the adjacent silicon carbide semiconductor layer structure. When the electric field reaches a critical level, dielectric breakdown of the silicon oxide occurs. To avoid such dielectric breakdown, the power MOSFET may be operated at a lower drain voltage level during reverse cutoff operation to ensure that the electric field does not reach a level that causes breakdown. In other words, the rated voltage of the power MOSFET may be set to ensure that premature dielectric breakdown of the gate oxide does not occur.

[0061] To reduce the electric field level in the gate oxide layer during reverse blocking operation, a so-called "trench shielding region" (also called a "trench shield" or "bottom shield") is often provided beneath the gate trench of a gate trench power MOSFET. These trench shielding regions are formed by doping a portion of the semiconductor layer structure beneath the gate trench with a dopant having the same conductivity type as the dopant contained in the device's channel region. The trench shielding region is usually formed by one or more ion implantation processes in which p-type dopant ions (in the case of n-type MOSFETs) are implanted through the bottom of the gate trench. The trench shielding region is, for example, a medium to high-density doped region extending downward from the bottom of the gate trench into the semiconductor layer structure of the device by 0.5 to 1.0 microns or more. The trench shielding region is electrically connected to the source terminal of the MOSFET by p-type trench shielding region connection patterns. These trench shielding connection patterns may be located within and / or outside the active region of the device.

[0062] Recently, gate trench power MOSFETs have been proposed that include an additional shielding region called a "support shield." The support shield is formed between adjacent gate trenches within the semiconductor layer structure and, like the trench shielding region, may comprise a highly doped semiconductor region having the same conductivity type as the MOSFET's channel region. The support shield may extend, for example, to the same depth as the trench shielding region within the semiconductor layer structure and can be formed by a high-energy ion implantation process. The support shield may be directly connected to the source metallization within the device's active region.

[0063] Figure 2 is a schematic cross-sectional view of a small portion of the silicon carbide power MOSFET 1, including the support shield. The cross-section in Figure 2 shows one complete unit cell of MOSFET 1 and portions of two adjacent unit cells. As shown in Figure 2, MOSFET 1 includes a highly doped n-type (n+) silicon carbide semiconductor substrate 10. The upper surface of the substrate 10 is doped with a less densely doped n-type (n+) silicon carbide semiconductor. - A silicon carbide drift region 20 is provided. An n-type silicon carbide JFET region 22 is formed above the drift region 20. The JFET region 22 may be doped to a higher concentration than the rest of the drift region 20. A medium-concentration doped (p) silicon carbide p-type well 30 (also called a "p-well") is provided above the p-well 30. A highly doped (n + An n-type silicon carbide source region 40 is formed. The substrate 10, the drift region 20, the p-well 30, and the source region 40 are part of the semiconductor layer structure 60 of the MOSFET 1.

[0064] The semiconductor layer structure 60 further includes a p-type support shield 50 extending downward from the top (e.g., top surface) of the semiconductor layer structure 60. The p-type support shield 50 is moderately doped (p) or highly doped (p) + )This may also be a silicon carbide region. As further shown in Figure 2, a plurality of gate trenches 80 are formed on the upper part of the semiconductor layer structure 60. The semiconductor layer structure 60 also includes p-type trench shielding regions 52 below each gate trench 80, which are formed usually by injecting a p-type dopant through the bottom of the gate trench 80. The p-type trench shielding regions 52 extend below the corresponding gate trench 80 for the entire length of the gate trench 80 or substantially the entire length of the gate trench 80 and are doped with a medium concentration (p) or a high concentration (p) + ) This may be a silicon carbide region. The p-type support shield 50 and the p-type trench shielding region 52 work to reduce the electric field level formed within the gate oxide layer (described later) during reverse blocking operation.

[0065] A gate oxide layer 82 is conformally formed within each gate trench 80, and a gate electrode 84 is formed on the gate oxide layer 82 within the gate trench 80. The gate electrode 84 is covered by an intermetallic insulator pattern 88. A source metallization layer 90 is formed on the intermetallic insulator pattern 88, as well as on the highly doped n-type source region 40 and support shield 50. A drain contact 6 is formed on the lower surface of the substrate 10.

[0066] As shown, the p-type support shield 50 may extend downward through or through part of the JFET region 22. Similarly, the gate trench 80 and the p-type trench shielding region 52 beneath it may also extend downward through or through part of the JFET region 22. As a result, the JFET region 22 may horizontally overlap with the p-type support shield 50, as well as one or both of the gate trench 80 and the p-type trench shielding region 52. As used herein, two elements of a semiconductor device are considered to "horizontally overlap" if the axes parallel to the main planes of the semiconductor layer structure of the semiconductor device intersect with both elements.

[0067] As shown in Figure 2, the minimum width of the JFET region 22 between the p-type support shield 50 and the adjacent gate trench 80 (or p-type trench shielding region 52) is called the JFET gap 24. During on-state operation, the current from source to drain flows through these JFET gaps 24, so the width of the JFET gaps 24 directly affects the on-state resistance of MOSFET 1.

[0068] Adding a support shield 50 within a gate trench power MOSFET 1 enhances protection against the gate oxide layer 82, but the support shield 50 may increase the "pitch" of the MOSFET 1. In particular, the pitch of a power MOSFET refers to the distance between adjacent unit cells. When adding a support shield to a gate trench power MOSFET, the spacing between adjacent gate trenches 80 must be increased to make space for the support shield 50, which can increase the pitch and thus reduce the integration level of the MOSFET. In addition, adding a support shield 50 to the MOSFET 1 usually adds several additional processing steps (e.g., mask formation, ion implantation, and / or mask removal), which increases the manufacturing cost. Therefore, adding a support shield 50 to a gate trench power MOSFET or other power semiconductor devices involves trade-offs.

[0069] According to embodiments of the present invention, gate trench silicon carbide power MOSFETs (and other power semiconductor devices) with improved support shield design are provided. For example, in some embodiments, the support shield can be fabricated using special ion implantation techniques to enable a reduction in the MOSFET's cell pitch and / or on-state resistance. Thus, power MOSFETs according to embodiments of the present invention can be seen as having reduced manufacturing costs and / or improved performance.

[0070] Providing a deep support shield has been shown to offer additional advantages beyond protecting the gate oxide layer within the gate trench during reverse bias operation. In particular, if the support shield extends further (i.e., deeper) into the semiconductor layer structure than the trench shielding region located beneath the gate trench, the support shield can act as a current path for avalanche breakdown current, displacement current, and body diode current in place of the trench shielding region located beneath the gate trench. This is advantageous as it allows these currents to flow away from the device's channel region. However, when forming a support shield using a standard ion implantation process, the width of the support shield tends to increase with increasing depth into the semiconductor layer structure due to the increased opportunity for implanted dopant ions to collide with atoms in the crystal lattice and be reoriented laterally as the implantation depth increases. This phenomenon is sometimes called "blooming." The blooming phenomenon can be seen in Figure 2 above, which shows that the deep support shield 50 has sidewalls that slope outward as the depth increases. Lateral extension of the support shield 50 works to narrow the width of the JFET gap 24, thereby causing current to flow through the narrowed region, which works to increase the on-state resistance. Thus, the distance between each gate trench 80 and its associated support shield 50 can be set to satisfy the desired on-state resistance value. However, in this case, in order to obtain a sufficiently large JFET gap 24, it may be necessary to widen the distance between the support shield 50 and the gate trench 80, which is disadvantageous because it increases the cell pitch of the power MOSFET 1.

[0071] In some embodiments of the present invention, silicon carbide-based gate trench power MOSFETs (and other gate trench power semiconductor devices) are provided, having a support shield with substantially vertical sidewalls or sidewalls that slope inward as the depth increases. In these cases, the JFET gap in these devices remains constant or actually widens as the depth increases. As a result, the unit cells of the power MOSFETs according to embodiments of the present invention can be packed more densely while achieving the same or possibly improved on-resistance performance.

[0072] In some embodiments, an ion implantation mask with inclined sidewalls is used in combination with a channel-type ion implantation process to form a support shield. Channel-type ion implantation tends to produce significantly less blooming than random (standard) ion implantation, which is not performed along channels in the semiconductor crystal lattice. Furthermore, because dopant ions implanted into the inclined sidewalls of the ion implantation mask only pass through a portion of the mask's thickness as they move, some of these dopant ions will pass through the mask to the end and enter the semiconductor layer structure. In this case, dopant ions implanted into the thinner outer portion of the inclined sidewalls of the mask are more likely to pass through the mask and enter the semiconductor layer structure than dopant ions implanted into the thicker inner portion of the inclined sidewalls. In addition, dopant ions implanted into the semiconductor layer structure through the mask tend to be shallower because collisions with atoms in the mask act to reduce the energy of the dopant ions. As a result of all these factors, this technique can be used to form a support shield within the semiconductor layer structure that has a width that narrows with increasing depth. In that case, the distance between the top surface of the support shield and the adjacent gate trench can be shortened, thereby reducing the device pitch.

[0073] In other embodiments, channel-type ion implantation techniques can be used in conjunction with conventional ion implantation masks having substantially vertical sidewalls. By carefully controlling the channel-type ion implantation conditions, it is possible to form support shields with generally vertical sidewalls (i.e., little to no blooming). This also makes it possible to reduce the device pitch.

[0074] In yet another embodiment of the present invention, a silicon carbide-based gate trench power MOSFET (and other gate trench power semiconductor devices) is provided, having a support shield having lateral support shield extensions extending from (or near) the bottom of the support shield. In some embodiments, these lateral support shield extensions can be formed at a depth below the bottom of the gate shield such that they do not narrow the width of the current path between the JFET region and the drift region, and at the same time the support shield can be extended to approach the bottom corner of the gate trench, in which case the lateral support shield extensions can provide stronger protection to the gate oxide layer extending around the bottom corner of the gate trench. This technique can further improve the reliability of the device without adversely affecting the on-state resistance. Furthermore, the support shield can be formed by the processes discussed above such that the support shield has a constant width, or a width that narrows as the depth in the semiconductor layer structure or vertical sidewall increases.

[0075] Embodiments of the present invention will be described in further detail here with reference to Figures 3A to 10C. It will be understood that many additional embodiments can be realized by combining the features of the different embodiments disclosed herein in any way. Therefore, it will be understood that although various features of the present invention are described below with respect to specific embodiments, many additional embodiments can be realized by adding these features to other embodiments and / or using them in place of the exemplary features of other embodiments. Thus, the present invention should be understood to encompass these different combinations. In addition, although the exemplary embodiments focus on the implementation of MOSFETs, it will be understood that the same techniques can be used for other gate trench power semiconductor devices such as insulated gate bipolar transistors (IGBTs) and gate-controlled thyristors.

[0076] Figure 3A is a schematic top view of a gate-trench silicon carbide power MOSFET 100 according to a particular embodiment of the present invention. Figure 3B is a schematic plan view of the power MOSFET 100 with various top-side metal and dielectric layers omitted to show the gate electrode and gate bus. Figure 3C is a schematic cross-sectional view of a unit cell of the gate-trench silicon carbide power MOSFET 100 taken along line 3C-3C in Figure 3A. It should be understood that the thicknesses of the various layers and regions in Figures 3A to 3C are not necessarily depicted to the correct scale. The same applies to other figures included in this application.

[0077] The power MOSFET 100 includes a semiconductor layer structure 160 (see Figure 3C) comprising one or more semiconductor substrates and / or layers. At least one of the semiconductor layers of the semiconductor layer structure 160 may be a silicon carbide layer. Various metal layers and / or dielectric layers are formed on both sides of the semiconductor layer structure 160 and embedded in the semiconductor layer structure 160.

[0078] As shown in Figure 3A, the upper metal layer is formed on the upper side of the semiconductor layer structure 160 and includes a gate bond pad 102 and one or more source bond pads 104-1, 104-2. A metal drain pad 106 (shown as a dotted box in Figure 3A) is provided on the bottom side of the semiconductor layer structure 160. The gate bond pad 102, source bond pad 104, and drain pad 106 form the gate terminal, source terminal, and drain terminal, respectively, of the power MOSFET 100. The gate pad 102 and source pad 104 may each be formed of a metal such as aluminum, to which bond wires can be easily attached via conventional techniques such as thermal compression or soldering. The drain pad 106 may also be a metal pad. A protective layer 109, such as a polyimide layer, may cover the entire upper surface of the power MOSFET 100 other than the gate pad 102 and source pad 104.

[0079] Continuing to refer to Figure 3A, the power MOSFET 100 includes a source metallization layer 190 (shown as a dotted box in Figure 3A) that electrically connects a specific region of the semiconductor layer structure 160 to source bond pads 104-1, 104-2. The source bond pads 104-1, 104-2 may be part of the source metallization layer 190 exposed through an opening in the protective layer 109, or they may be separate metal layers. The source metallization layer 190 may cover or coincide with the entire “active region” 107 of the power MOSFET 100 where the unit cell transistor is located. The inactive region 108 of the power MOSFET 100 surrounds the active region 107. The inert region 108 may include a termination region extending along the periphery of the MOSFET 100, which includes a guard ring, a junction termination element, or other termination structure (not shown), a gate pad region located below the gate pad 102, and a gate bus region (described later).

[0080] A bond wire 103 is shown in Figure 3A and may be used to connect the gate bond pad 102 and the source bond pad 104 to an external circuit. The drain pad 106 on the bottom side of the power MOSFET 100 may be connected to an external circuit, for example, through a submount (not shown) placed underneath.

[0081] Figure 3B is another plan view of the power MOSFET 100 with the gate bond pad 102 and source bond pad 104, polyimide layer 109, source metallization layer 190, intermetallic dielectric layer 188, and various other metal and dielectric layers removed to show the gate electrode 184 formed within the gate trench 180 of the semiconductor layer structure 160. A patterned field oxide layer (not shown) is formed on the semiconductor layer structure 160 within the inactive region 108 of the MOSFET 100. The field oxide layer may be a relatively thick oxide layer (for example, 10 to 20 times thicker than the gate oxide layer described later). A polysilicon layer 101 can be formed on the field oxide layer and can be formed within the region where the gate bond pad 102 is formed, such that the gate bond pad 102 overlaps perpendicularly with the field oxide layer and the polysilicon layer 101. As used herein, two elements of a semiconductor device are considered to "overlap perpendicularly" if the axis perpendicular to the main plane of the semiconductor layer structure of the semiconductor device intersects both elements.

[0082] One or more gate buses 186 are provided extending around the periphery of the active region 107. The field oxide layer typically passes beneath each gate bus 186 and is located beneath the gate bond pad 102. The gate buses 186 are often electrically connected to the gate bond pad 102 through gate resistors (not shown). Multiple gate trenches 180 (see Figure 3C) are formed throughout the active region 107. A gate electrode 184 is formed within each gate trench 180. In the MOSFET 100 depicted, the gate electrode 184 extends horizontally across the semiconductor layer structure 160. In other cases, the gate electrode 184 may extend vertically across the semiconductor layer structure 160, and both horizontally extending and vertically extending gate electrode 184 may be provided to form a lattice gate electrode structure. The gate electrode 184 may be connected to the gate pad 102 through the gate buses 186. The gate electrode 184 may include, for example, a doped polysilicon pattern. The gate bus 186 may, in the exemplary embodiment, comprise a polysilicon structure and / or a metallic structure, and is typically located within the inert region 108 of the power MOSFET 100.

[0083] Figure 3C is a schematic cross-sectional view taken along line 3C-3C in Figure 3A, showing a unit cell of approximately 1.5 power MOSFETs 100. As shown in Figure 3C, the power MOSFET 100 includes an n-type silicon carbide semiconductor substrate 110. The substrate 110 may include, for example, a single-crystal 4H silicon carbide semiconductor substrate (i.e., an n+ silicon carbide substrate) highly doped with n-type impurities. The impurities may include, for example, nitrogen or phosphorus. In an exemplary embodiment, the n-type substrate 110 is, for example, 1 × 10⁻¹⁶ 18 atoms / cm 3 ~1 × 10 21 atoms / cm 3may have a doping concentration of, but other doping concentrations may also be used. In some embodiments, the substrate 110 may be relatively thick (e.g., 20 to 100 microns or more). Although the substrate 110 is depicted as a relatively thin layer, it should be noted that this is done to allow enlargement of the thickness of other layers and regions in FIG. 3C, and it will be appreciated that the substrate 110 is typically much thicker than shown. Similarly, the thicknesses of various other layers of the power MOSFET 100 may not be shown to scale in the figures to allow enlargement of other portions of the device.

[0084] On the upper surface of the substrate 110, a lightly doped n-type (n-) silicon carbide drift layer 120 (also referred to herein as drift region 120) is provided. Typically, the drift layer 120 is formed via an epitaxial growth process and is doped during growth. The n-type drift region 120 may, for example, be 5×10 15 ~5×10 17 dopants / cm 3 may have a doping concentration of. The n-type drift region 120 may be, for example, a thick region having a vertical height of 3 to 50 microns above the substrate 110, and may be doped during growth. The upper portion of the n-type drift region 120 may comprise an n-type JFET region 122 that is more heavily doped than the lower portion of the n-type drift region 120. The n-type JFET region 122 may, for example, be 5×10 16 ~1×10 18 may have an n-type dopant concentration of. The n-type JFET region 122 is considered part of the drift region 120.

[0085] The drift layer 120 and the substrate 110 collectively act as a common drain region for the power MOSFET 100. The drain pad 106 is formed on the substrate 110 on the opposite side of the drift region 120.

[0086] Continuing to refer to Figure 3C, a moderately doped (p), p-type silicon carbide well layer 130 is formed on the upper surface of the n-type JFET region 122, or on the upper part of the n-type drift region 120 (i.e., the upper part of the n-type drift region 120 is converted into a well layer 130). The moderately doped (p), p-type silicon carbide well layer 130 can be formed either by epitaxial growth or by implanting p-type dopant ions into the upper part of the n-type drift region 120 to convert the upper part of the n-type drift layer 120 into a p-type silicon carbide well layer 130. In an exemplary embodiment, the moderately doped p-type well layer 130 is, for example, 5 × 10 16 ~1 × 10 18 It may have a p-type dopant concentration.

[0087] A highly doped (n+), n-type silicon carbide source layer 140 is formed on the p-type silicon carbide well layer 130. The highly doped n-type silicon carbide source layer 140 can be formed by ion implantation. The highly doped n-type silicon carbide source region 140 is, for example, 1 × 10⁻¹⁶ 19 atoms / cm 3 ~5×10 21 atoms / cm 3 It may have a doping concentration of [value missing].

[0088] As further shown in Figure 3C, a p-type support shield 150 is provided, extending downward from the top (e.g., top surface) of the semiconductor layer structure 160 into the silicon carbide drift region 120. The p-type support shield 150 is doped to a medium or high concentration (p + ) The silicon carbide region may also be present. For example, each p-type support shield 150 is approximately 5 × 10 16 ~1 × 10 22 It may have a doping concentration of about 1 × 10. In other embodiments, each p-type support shield 150 has about 1 × 10 18 ~1 × 10 20 , about 1×10 19 ~1 × 10 20 , about 1×10 17 ~1 × 10 19, about 1×10 17 ~1 × 10 20 , or approximately 1 x 10 18 ~1 × 10 21 The p-type support shield 150 may have a doping concentration that varies with depth. In exemplary embodiments, each p-type support shield 150 may extend to a depth of 0.1 to 4.0 microns from the top surface of the semiconductor layer structure 160. In other embodiments, the depth of each p-type support shield 150 may be 1.0 to 3.0 microns, 1.0 to 2.5 microns, 1.5 to 3.0 microns, 1.5 to 2.5 microns, or 0.5 to 2.5 microns. Any of the above dopant concentration ranges for the p-type support shield 150 can be combined with any of the depths listed above for the p-type support shield 150. The p-type support shield 150 may work to reduce the electric field level formed in the gate oxide layer (described later) during the reverse blocking operation of the device, as will be discussed in more detail later.

[0089] As discussed above, a plurality of gate trenches 180 are formed on the upper surface of the semiconductor layer structure 160. The p-type trench shielding region 152 is formed beneath the corresponding gate trench 180 and may extend beneath the corresponding gate trench 180 for the entire length or substantially the entire length of the gate trench 180. The p-type trench shielding region 152 is moderately doped or heavily doped (p + )It may also be a silicon carbide region. For example, each p-type trench shielding region 152 is approximately 1 × 10⁻⁶ 17 ~1 × 10 21 It may have a doping concentration of about 1 × 10. In other embodiments, each p-type trench shielding region 152 is about 1 × 10 18 ~1 × 10 20 , about 1×10 19 ~1 × 10 20 , about 1×10 17 ~1 × 10 20 , or approximately 1 x 10 18 ~1 × 10 21The doping concentration may be as follows. In an exemplary embodiment, each p-type trench shielding region 152 may extend to a depth of 0.5 to 3.0 microns from the top surface of the semiconductor layer structure 160. In other embodiments, the depth of each p-type trench shielding region 152 may be 1.0 to 3.0 microns, 1.0 to 2.5 microns, 1.5 to 3.0 microns, 1.5 to 2.5 microns, or 0.5 to 2.5 microns. Any of the above dopant concentrations can be combined with any of the depths listed above for the p-type trench shielding region 152. The p-type trench shielding region 152 may work to reduce the electric field level formed on the gate oxide layer (described later) during device operation, as will be discussed in more detail later. The p-type trench shielding region 152 may be doped to have a higher p-type dopant concentration, a lower p-type dopant concentration, or approximately the same p-type dopant concentration as the p-type support shield 150.

[0090] Although not shown in Figure 3C, electrical connections are provided within and / or outside the active region 107 to electrically connect the p-type trench shielding region 152 to the p-type silicon carbide well layer 130. U.S. Patents 9,887,287 and 11,610,991 describe designs of metal or p-type silicon carbide trench shield connection patterns that can be used to electrically connect the p-type trench shielding region to the p-type silicon carbide well layer. The p-type trench shield connection pattern can be electrically connected to the p-type silicon carbide well layer 130 using any of the p-type silicon carbide trench shield connection patterns disclosed in these patents (each of which is incorporated by reference herein). In addition or alternatively, the p-type trench shielding region 152 may be directly connected to the source metallization layer 190 through a p-type silicon carbide trench shield connection pattern formed within the gate trench 180, for example, as shown in U.S. Patent Publication 2022 / 0130998, the entirety of which is also incorporated herein by reference.

[0091] The n-type silicon carbide substrate 110, the n-type silicon carbide drift layer 120 (including the JFET region 122), the p-type silicon carbide well layer 130, the n-type silicon carbide source region 140, the p-type silicon carbide support / shield 150, and the p-type silicon carbide trench shielding region 152 together can constitute the semiconductor layer structure 160 of the power MOSFET 100.

[0092] As described above, multiple gate trenches 180 are formed on the upper part of the semiconductor layer structure 160. Although the cross-sectional view in Figure 3C shows only one complete gate trench 180 and a portion of a second gate trench 180, it will be understood from Figure 3B that the MOSFET 100 may contain a number of gate trenches 180. Each gate trench 180 may extend along a longitudinal axis through the semiconductor layer structure 160, and the gate trenches 180 may extend parallel to each other, as best shown in Figure 3B. It will be understood that the longitudinal axes of the gate trenches 180 extend into the plane of paper in Figure 3C. The gate trenches 180 may be formed by an etching process.

[0093] Within each gate trench 180, a gate oxide layer 182 is provided so as to cover the side walls and bottom surface of the gate trench 180. In some embodiments, each gate oxide layer 182 may extend to the upper surface of the semiconductor layer structure 160. Each gate oxide layer 182 may include, for example, a silicon oxide (SiO2) pattern. The gate oxide layers 182 may or may not be connected to each other outside the field of view in Figure 3C. The gate oxide layers 182 may be formed conformally as a whole within each gate trench 180.

[0094] A gate electrode 184 is formed on the gate oxide layer 182 within each gate trench 180. The gate electrode 184 may comprise a conductive material such as silicide (e.g., NiSi, TiSi, WSi, CoSi), doped polycrystalline silicon (poly-Si), and / or a stable conductor. Other suitable materials for the gate electrode include various metals such as Ti, Ta, or W, or metal nitrides such as TiN, TaN, or WN. The gate oxide layer 182 insulates the gate electrode 184 from the semiconductor layer structure 160, thereby preventing the gate electrode 184 from short-circuiting to the semiconductor layer structure 160. Each gate electrode 184 can be connected to one of the gate buses 186 (see Figure 3B). In the depicted embodiment, the gate electrode 184 is recessed such that its upper surface is lower than the upper surface of the semiconductor layer structure 160. In other embodiments, the gate electrode 184 may extend above and into the upper surface of the semiconductor layer structure 160, and it will be understood that the gate oxide layer 182 insulates the gate electrode 184 from the upper surface of the semiconductor layer structure 160.

[0095] An intermetallic dielectric layer 188 is formed covering each gate electrode 184. The intermetallic dielectric layer 188 insulates the source metallization layer 190 from the gate electrode 184.

[0096] The source metallization layer 190 is formed on the upper surface of the semiconductor layer structure 160 and on the intermetallic dielectric layer 188. In this specification, the source metallization layer 190 may also be referred to as the "source contact". The source metallization layer 190 may comprise a single metal layer or multiple metal layers. Typically, multiple metal layers are provided because the source metallization layer 190 may include a single or multilayer adhesive layer in contact with the semiconductor layer structure 160, one or more barrier layers, and bulk metal layers (e.g., aluminum layers).

[0097] The p-type support shield 150 can be formed by ion implantation. When using standard (random) ion implantation techniques, dopant ions are implanted at high energy into the top surface of the semiconductor body. As the dopant ions penetrate into the semiconductor material, they collide with atoms in the crystal lattice, causing them to lose energy and potentially changing their orientation. Most commonly, dopant ions are implanted at a 90° angle (i.e., perpendicular) to the top surface of the semiconductor body. When dopant ions collide with atoms in the crystal lattice, their orientation is changed so that they can move both laterally and vertically within the crystal lattice. As a result of this lateral movement, the implanted region expands laterally (the "blooming" phenomenon discussed above), and the amount of lateral expansion tends to increase with increasing depth into the semiconductor body. This can be seen in the cross-section of Figure 2, where the sidewalls of the support shield 50 are inclined outward as the depth increases within the semiconductor layer structure 60. As discussed above, this phenomenon works to narrow the JFET gap 24, which can potentially increase the on-state resistance of MOSFET 1.

[0098] In contrast, the support shield 150 of the MOSFET 100 has sidewalls that slope inward as the depth into the semiconductor layer structure 160 increases, and therefore the cross-sectional area of ​​each support shield 150 (taken along the horizontal cross-section of the support shield 150) decreases as the support shield extends further into the semiconductor layer structure 160 (from the top surface). As a result, the JFET gap 124 is narrowest at the top surface of the JFET region 122. This can work to lower the on-state resistance. As will be discussed later, one technique that can be used to form the support shield 150 having the shape shown in Figure 3C is to perform channel-type ion implantation, which uses an ion implantation mask with sloped sidewalls during the channel-type ion implantation process.

[0099] The power MOSFET 100 may be turned on by applying a gate bias voltage higher than a threshold level to the gate pad 102. The gate bias voltage is transmitted to the gate electrode 184 via the gate bus 186, creating a conductive n-type inversion layer in the portion of the p-type silicon carbide well layer 130 adjacent to the gate trench 180. These regions of the p-type silicon carbide well layer 130 are referred to herein as channel regions because, during on-state operation, current flows through these channel regions from the source layer 140 to the drift region 120. The channel regions are oriented vertically (i.e., extending in the z direction) because current flows downward from the source layer 140 through the channel regions to the drift region 120, the substrate 110, and the drain contact 106.

[0100] As discussed above, one common failure mechanism in power semiconductor devices such as power MOSFETs is device failure due to dielectric breakdown of the gate oxide layer. Since the lifetime of the gate oxide layer (i.e., the time until dielectric breakdown) depends on the strength of the electric field in the gate oxide layer during device operation, one way to reduce the occurrence of device failure is to design the MOSFET to have a reduced peak electric field value in the gate oxide layer during reverse cutoff operation.

[0101] During reverse blocking operation, the electric field extends upward from the bottom of the MOSFET 100. Therefore, a strong electric field may extend upward toward the bottom of the gate oxide layer 182. The p-type silicon carbide trench shielding region 152 acts as a shield to reduce the electric field value directly beneath the gate trench 180. However, the electric field tends to extend upward on both sides of each trench shielding region 152. Therefore, the electric field tends to be highest in parts of the gate oxide layer 182 that are not directly protected by the trench shielding region 152, such as the lower side walls and lower corners of each gate oxide layer 182. Furthermore, an electric field concentration effect occurs at the lower corners of each gate oxide layer 182, and the electric field strength in these parts of the gate oxide layer 182 becomes even greater. Therefore, although the trench shielding region 152 helps to reduce the electric field level in the gate oxide layer 182, the lower corners of the gate oxide layer 182 are usually only partially protected, and these lower corners are the parts of the gate oxide layer 182 that are most susceptible to dielectric breakdown due to electric field concentration effects.

[0102] The support shield 150, like the trench shielding region 152, suppresses the range over which the electric field extends upward from the drain pad 106. The minimum JFET gap 124 can be set by the on-state resistance requirement of the MOSFET 100. This parameter directly affects the level of integration of the MOSFET 100 because a larger minimum JFET gap 124 results in a larger size for each unit cell of the MOSFET 100. Since the support shield 150 decreases in size as its depth increases, these allow for increased integration, thereby reducing manufacturing costs and the size of the MOSFET 100.

[0103] Continuing to refer to Figure 3C, it can be seen that the MOSFET 100 includes, in particular, a silicon carbide-based semiconductor layer structure 160 comprising a drift region 120 having a first (n) conductivity type, a well layer 130 having a second (p) conductivity type located on the upper surface of the drift region 120, and a support shield 150 having a second (p) conductivity type. A first gate trench 180 extends into the upper part of the semiconductor layer structure 160 (i.e., is formed). A second gate trench 180 also extends into the upper part of the semiconductor layer structure 160, and the support shield 150 may be located between the first gate trench 180 and the second gate trench 180. As shown in Figure 3C, the support shield 150 includes a first segment S1 located deeper than the well layer 130 within the semiconductor layer structure 160 (i.e., below the well layer 130 in the view of Figure 3C) and less than the depth of the bottom of the first gate trench 180 within the semiconductor layer structure 160. The width of the first segment S1 of the support shield 150 narrows as the distance from the well region 130 increases. As a result, as shown in Figure 3C, the sidewalls of the first segment S1 of the support shield 150 incline inward as the depth into the semiconductor layer structure 160 increases. As used herein, references to the “depth” of a structure or element within a semiconductor layer structure refer to the distance that structure or element takes from the top surface of the semiconductor layer structure, the top surface of the semiconductor layer structure being the surface opposite the substrate and the surface on which the gate trench is formed.

[0104] As shown in Figure 3C, in some embodiments, the entire portion of the support shield 150 extending below the well layer 130 may have a width that narrows as the distance from the well layer 130 increases (i.e., as the depth into the semiconductor layer structure 160 increases). As shown, in some embodiments, the entire support shield 150 may have a width that narrows as the distance from the top surface of the semiconductor layer structure 160 increases.

[0105] As also shown in Figure 3C, the bottom of the first gate trench 180 is at a first depth D1 from the top surface of the semiconductor layer structure 160, and the bottom of the support shield 150 is at a second depth D2 from the top surface of the semiconductor layer structure 160, where the second depth D2 is greater than the first depth D1. A trench shielding region 152 having a second (p) conductivity type is provided below the first gate trench 180. The bottom of the trench shielding region 152 has a third depth D3 from the top surface of the semiconductor layer structure 160. The second depth D2 may further be greater than the third depth D3.

[0106] As described above, the MOSFET 100 may further include a source layer 140 having a first (n) conductivity type located on a well layer 130 within the semiconductor layer structure 160, and a gate oxide layer 182 and a gate electrode 184 located within a first gate trench 180. Because the sidewalls of the support shield 150 are inclined inward as the depth into the semiconductor layer structure 160 increases, the maximum width of the second segment S2 of the support shield 150 that horizontally overlaps the source layer 140 is greater than the width of the support shield 150 at the point where the support shield 150 horizontally overlaps with the bottom of the first gate trench 180 (i.e., the portion of the support shield 150 that has the same depth as the first gate trench 180, and is the bottom of the first segment S1 of the support shield 150). In some embodiments, the maximum width of the second segment S2 of the support shield 150 can be at least 1 to 50% greater than the width of the support shield at the point where the support shield 150 horizontally overlaps with the bottom of the first gate trench 180. In other embodiments, the maximum width of the second segment S2 of the support shield 150 can be at least 2 to 40%, 2 to 20%, 5 to 40%, or 5 to 25% greater than the width of the support shield at the point where the support shield 150 horizontally overlaps with the bottom of the first gate trench 180.

[0107] The MOSFET 100 may further include a JFET region 122 which may include at least a portion of the upper region of the drift region 120. The JFET region 122 may have a higher doping concentration of the first conductivity type than the drift region 120. The well layer 130 may be on the upper surface of the JFET region 122. As shown in Figure 3C, the first portion P1 of the JFET region 122 between the first gate trench 180 and the support shield 150 has a width that increases with increasing distance from the well layer 130 because the sidewall of the first segment S1 of the support shield 150 (which overlaps horizontally with the first portion P1 of the JFET region 122) has a sidewall that slopes inward.

[0108] Figures 4A to 4e are schematic cross-sectional views illustrating the method for fabricating the gate-trench silicon carbide power MOSFET 100 shown in Figures 3A to 3C.

[0109] Referring to Figure 4A, an n-type silicon carbide substrate 110 is provided. Then, usually by epitaxial growth, a low concentration of (n) doped onto the upper surface of the substrate 110 is applied. - A silicon carbide drift layer 120 is formed. By increasing the n-type dopant concentration during growth on the top of the drift layer 120, a JFET region 122 can be formed on top of the drift layer 120. Subsequently, the epitaxial growth process can be continued (with the n-type dopant source turned on or off) to grow a region 124 on the surface of the JFET region 122. Region 124 will be converted into a p-type well layer 130 and an n-type source layer 140 in a later processing step.

[0110] Referring to Figure 4B, a first mask layer, such as an oxide mask layer, is formed on the upper surface of the semiconductor layer structure 160. Next, the first mask layer is patterned to form openings 192 therein, thereby providing a first patterned mask 191 that exposes a selected portion of the semiconductor layer structure 160. The openings 192 may be centered above the location where support shields 150 will be formed in the semiconductor layer structure 160, but the openings 192 may be narrower than the intended width of the top portion of each support shield 150. Notably, the sidewalls of the mask areas on either side of the openings 192 are inclined outward such that the width of these mask areas increases as they approach the semiconductor layer structure 160. In this case, the sidewalls of the mask 191 defining each opening 192 are inclined sidewalls that form an obtuse angle α with respect to the upper surface of the semiconductor layer structure 160 exposed through each opening 192, as shown in Figure 4B. In some embodiments, the obtuse angle α is an angle between 100° and 160°. The thickness of the first patterned mask 191 is sufficient to ensure that only a small amount or none of the dopant ions can pass through the entire thickness of the first patterned mask 191 and be injected into the semiconductor layer structure 160. The inclined sidewalls defining the opening 192 can be formed using various known etching techniques.

[0111] Continuing with Figure 4B, a channel-type ion implantation process is performed to implant p-type dopant ions into the semiconductor layer structure 160 to form a p-type support shield 150. A channel-type ion implantation process is an ion implantation process in which dopant ions are implanted along a specific crystal axis within silicon carbide that forms an atom-free channel, as discussed in its entirety in U.S. Patent No. 11,075,264 (Publication '264), which is incorporated herein by reference. Channel-type ion implantation can be performed by tilting the ion source relative to the semiconductor layer structure so that dopant ions are implanted along a desired crystal axis, as described in further detail in Publication '264. When dopant ions are implanted along a channel in the crystal axis, the dopant ions travel, on average, much further within the crystal lattice before colliding with atoms in the crystal lattice than would be possible in a standard (random) ion implantation process. As a result, ions implanted in channel-type ion implantation processes can be implanted to greater depths while using, on average, lower implantation energies (which favorably reduces damage to silicon carbide caused by implantation and also reduces scattering of dopant ions to unintended locations within the crystal lattice). In addition, in channel-type ion implantation, the number of atoms that dopant ions collide with is ultimately smaller, and / or the dopant ions are more constrained within the channel, so blooming of the implanted region with increasing depth is usually little to no.

[0112] As described above, the thickness of the first patterned mask 191 is selected so that dopant ions cannot pass through the entire thickness of the mask 191 in general. However, since the sidewalls defining the opening 192 of the first patterned mask 191 are inclined sidewalls, dopant ions that collide with the sidewalls do not need to travel through the entire thickness of the mask 191 to reach the semiconductor layer structure 160. In that case, some of the dopant ions injected into the inclined sidewalls of the first patterned mask 191 will pass through the mask 191 and be injected into the semiconductor layer structure 160. However, the energy of these dopant ions decreases by passing through the mask 191 (because they collide with atoms in the mask 191), and therefore, on average, the dopant ions that pass through the mask 191 before being injected into the semiconductor layer structure 160 do not reach as deep into the semiconductor layer structure 160 as dopant ions that are injected directly into the semiconductor layer structure 160 through the opening 192. Furthermore, the higher up the dopant ions are injected (i.e., further away from the bottom surface of the opening 192), the shallower, on average, the depth to which the dopant ions are injected into the semiconductor layer structure 160. As a result, as shown in Figure 4B, the width of the support shield 150 may be widest at the top and then narrower as it extends into the semiconductor layer structure 160. In other words, the width of each support shield 150 narrows as it increases in distance from the top surface of the semiconductor layer structure 160.

[0113] The support shield 150 having the shape shown in Figure 4B may be advantageous for at least two reasons. First, because the support shield 150 is widest at the top, it has a larger contact area with the source metallization layer 190. This allows for a lower resistance connection between the source metallization layer 190 and the support shield 150 and p-well layer 130, thereby improving the performance of the device. Second, as discussed above, the narrowing of the bottom portion of each support shield 150 works to widen the JFET gap 124, which reduces the on-state resistance of the MOSFET 100 or allows the unit cells to be closer together by reducing the distance between adjacent gate trenches 180.

[0114] The above description in Figure 4B shows that channel-type ion implantation is used to form the support shield 150, but it will be understood that embodiments of the present invention are not limited thereto. For example, in other embodiments, a standard (random) ion implantation process may be used instead. However, due to blooming that occurs in such implantation processes, it may be difficult to obtain a support shield with inwardly sloping sidewalls, even if the ion implantation mask has an opening with sloping sidewalls.

[0115] Referring to Figure 4C, a second mask layer is formed on the upper surface of the semiconductor layer structure 160, which is patterned to form a second ion implantation mask 193. A second ion implantation process is performed to implant p-type ions into the upper part of the semiconductor layer structure 160. The second ion implantation process may be an embedding process that primarily implants p-type ions into the portion of region 124 directly above the JFET region 122 to form a p-type well layer 130. A shallower third ion implantation process is then performed to implant n-type ions into the upper part of region 124 to form an n-type source layer 140 above the p-well layer 130. The second ion implantation mask 193 covers the support shield 150 during the second and third ion implantation processes. It will be understood that the second and third ion implantation steps may be performed in reverse order. Furthermore, it will be understood that the p-type well layer 130 and / or the n-type source layer 140 can also be formed by appropriately doping these regions during the epitaxial growth process discussed with respect to Figure 4A above.

[0116] Referring to Figure 4D, the second patterned mask 193 can be removed, and a third mask layer (e.g., another oxide mask layer) can be formed to cover the semiconductor layer structure 160. The third mask layer can then be patterned (e.g., using standard photolithography patterning techniques) to form openings 196 therein that expose selected portions of the semiconductor layer structure 160, thereby providing a third patterned mask 195. The openings 196 may be located above the location in the semiconductor layer structure 160 where gate trenches 180 will be formed in subsequent processing steps.

[0117] Referring to Figure 4E, an etching process is performed to etch the exposed portion of the semiconductor layer structure 160 to form a gate trench 180. As shown, in some embodiments, the gate trench 180 may not extend as deep into the semiconductor layer structure 160 as the bottom of the support shield 150. Next, an ion implantation process is performed to implant p-type dopant ions into the portion of the semiconductor layer structure 160 below the gate trench 180 to form a trench shielding pattern 152. As discussed above, in some embodiments, the trench shielding pattern 152 may not extend as deep into the semiconductor layer structure 160 as the support shield 150.

[0118] Referring again to Figure 3C, the gate oxide layer 182 and gate electrode 184 can then be formed within the gate trench 180, and an intermetallic dielectric layer 188 is formed to cover the gate oxide layer 182 and gate electrode 184. Next, a source metallization layer 190 is formed on the source region 140, the intermetallic dielectric layer 188, and the support shield 150. Then, a drain pad 106 is formed on the bottom of the substrate 110.

[0119] Figure 5 is a flowchart showing a method for forming the gate trench silicon carbide power MOSFETs shown in Figures 3A to 3C. As shown in Figure 5, first, a silicon carbide-based semiconductor layer structure 160 is provided (block 200). The semiconductor layer structure 160 includes a drift layer 120 having a first conductivity type.

[0120] Next, for example, an etching mask is formed on the upper surface of the semiconductor layer structure 160, the etching mask is patterned to expose selected areas of the semiconductor layer structure 160 where gate trenches 180 will be formed, and then the exposed portions of the semiconductor layer structure 160 are etched to form the first and second gate trenches 180 within the semiconductor layer structure 160, thereby forming the first and second gate trenches 180 within the semiconductor layer structure 160 (block 210). Each gate trench 180 can extend into the upper surface of the semiconductor layer structure 160 to a first depth D1.

[0121] Next, an ion implantation mask is formed on the upper surface of the semiconductor layer structure 160 (block 220). Then, the ion implantation mask is patterned so that there is an opening there. The ion implantation mask is patterned such that at least one of the patterned mask sidewalls defining the opening has an inclined sidewall (block 230). As shown in Figure 4B, the inclined sidewall forms an obtuse angle α with respect to the upper surface of the semiconductor layer structure 160 exposed through the opening. In some embodiments, the obtuse angle α is an angle of 100° to 160°.

[0122] Next, a dopant of the second conductivity type is injected into the upper surface of the semiconductor layer structure 160 to form a support shield 150 having the second conductivity type between the first gate trench 180 and the second gate trench 180 within the semiconductor layer structure 160 (block 240). The support shield trench 150 may extend into the upper surface of the semiconductor layer structure 160 to a second depth D2, where the second depth D2 is shallower than the first depth D1.

[0123] Referring to Figures 4A-4E and Figure 5, it will be understood that the processing steps discussed above may be performed in a different order in further embodiments. For example, in the flowchart of Figure 5, the first and second gate trenches 180 are formed before the support shield 150 is formed. However, in the description of Figures 4A-4E above, the support shield 150 is formed before the gate trenches 180 are formed. Therefore, it will be understood that various processing steps may be performed in a different order than those shown in Figure 5 (or Figures 4A-4E). It will also be understood that some of the processing steps may be omitted in other embodiments, and / or other processing steps may be added to this method.

[0124] Figures 6A to 6E are schematic cross-sectional views of gate-trench silicon carbide power MOSFETs 100A to 100E, which are modified versions of gate-trench silicon carbide power MOSFET 100. Since gate-trench silicon carbide power MOSFETs 100A to 100E are almost identical to MOSFET 100, the following discussion will focus only on the differences between each of MOSFETs 100A to 100E and MOSFET 100.

[0125] As can be seen by comparing Figure 3C and Figure 6A, the only difference between MOSFET 100 and MOSFET 100A is that MOSFET 100A includes an embedded p-type support shield 150A that extends downward from the p-well layer 130, rather than from the top surface of the semiconductor layer structure 160. In the embodiment of Figure 6A, a p-type semiconductor connection between the source metallization layer 190 and the p-well layer 130 may be made outside the cross-sectional view. Otherwise, MOSFET 100A can be identical to MOSFET 100, so further explanation will be omitted.

[0126] Referring to Figure 6B, a MOSFET 100B is depicted similarly to MOSFET 100 in Figures 3A-3C, but the support shield 150B0 included in MOSFET 100B is formed using a patterned ion implantation mask and channel-type ion implantation process with non-sloping (straight) sidewalls. As shown in Figure 6B, since blooming occurs little to no in channel-type ion implantation, the p-type support shield 150B in MOSFET 100B may have substantially vertical (non-sloping) sidewalls. Otherwise, MOSFET 100B may be identical to MOSFET 100, so further explanation will be omitted.

[0127] As can be seen by comparing Figure 3C and Figure 6C, the only difference between MOSFET100 and MOSFET100C is that MOSFET100C includes a support shield trench 154 formed within the support shield 150. The support shield trench 154 does not penetrate the bottom surface of the corresponding support shield 150. In other words, the support shield trench 154 extends partway through the corresponding support shield 150 but does not penetrate completely. The support shield trench 154 is filled with a conductive material 156 other than silicon carbide, such as p-type polysilicon, nickel oxide, or a metal that forms a Schottky contact with silicon carbide. The conductive material 156 filling each support shield trench 154 forms a low-resistance contact with the support shield 150. Otherwise, MOSFET100C can be identical to MOSFET100, so further explanation is omitted.

[0128] As can be seen by comparing Figure 3C and Figure 6D, the only difference between MOSFET 100 and MOSFET 100D is that the p-type support shield 150D in MOSFET 100D is formed using a combination of relatively low-energy random implantation, designed to implant p-type dopants to a depth less than, for example, the gate trench 180, and channel-type ion implantation, designed to implant dopants to a greater depth within the semiconductor layer structure 160. The random implantation forms an implantation region 155 that exhibits blooming. The channel-type implantation forms an implantation region 157. The channel-type implantation can be formed using a mask with inclined sidewalls such that the width of the implantation region 157 narrows as the depth into the semiconductor layer structure 160 increases, as shown in Figure 6D. The channel-type implantation may be an embedded implantation that primarily implants dopants into region 157, or it may be an unembedded implantation that also implants dopants into the central portion of region 155. One of the advantages of the MOSFET100D is its high p-type dopant concentration (e.g., 1 × 10⁻⁶). 20 It is easy to inject into the injection region 155 such that it has ), and low-resistance contact can be provided between the p-type semiconductor material and the source metallization layer 190. Otherwise, since MOSFET 100D can be identical to MOSFET 100, further explanation will be omitted.

[0129] As can be seen by comparing Figure 3C and Figure 6E, the only difference between MOSFET100 and MOSFET100E is that in MOSFET100E, the support shield 150 extends to a depth D2, which is less than the depth D3 of the trench shielding region 152. Otherwise, MOSFET100E may be identical to MOSFET100, so further explanation will be omitted.

[0130] Figure 7 is a schematic cross-sectional view of a gate-trench silicon carbide power MOSFET 300 according to a further embodiment of the present invention. The gate-trench silicon carbide power MOSFET 300 may be identical to the gate-trench silicon carbide power MOSFET 100 when viewed from above, and therefore Figure 3A also accurately represents the power MOSFET 300. The cross-section in Figure 7 is also taken along line 3C-3C in Figure 3A, showing how the power MOSFET 300 differs from the power MOSFET 100. Since most of the elements of the power MOSFET 300 are the same as the corresponding elements of the power MOSFET 100, the same reference numerals are used for those elements in Figures 3A-3C and Figure 7. In the following description, we will focus on the elements of the power MOSFET 300 that differ from those of the power MOSFET 100.

[0131] As can be seen by comparing Figure 3C and Figure 7, the power MOSFET 300 differs from the power MOSFET 100 in that it includes a plurality of embedded lateral support / shield extensions 158 within the semiconductor layer structure 160. Each of the embedded lateral support / shield extensions 158 extends laterally from both sides of the bottom portion of the corresponding support shield 150. Each of the embedded lateral support / shield extensions 158 has a second conductivity type and may have a doping concentration that is the same as or different from that of the support shield 150.

[0132] The embedded lateral support shield extension 158 may be formed using a high-energy random ion implantation process, for example, performed before or after the ion implantation process used to form the support shield 150. By using a high-energy channel-type ion implantation process, almost all of the dopant ions will pass through the source layer 140, the p-well layer 130, and the JFET region 122 to form the embedded implanted region. Because random (i.e., non-channel-type) ion implantation is used, blooming occurs, which creates the lateral extension 158.

[0133] As shown in Figure 7, the embedded lateral support shield extension 158 can be formed relatively deep within the semiconductor layer structure 160. As a result, even though the embedded lateral support shield extension 158 extends laterally toward the trench shielding region 152, the minimum gap (labeled 124' in Figure 7) between the support shield 150 / embedded lateral support shield extension 158 and the trench shielding region 152 can be kept relatively large, as shown in Figure 7. Therefore, the embedded lateral support shield extension 158 can provide enhanced protection to the portion of the gate oxide layer 182 at the bottom corner of the gate trench 180 without adversely affecting the on-state resistance.

[0134] As shown in Figure 7, each section of the JFET region 122 is interposed between the drift region 120 and the well region 130 in the vertical direction (z direction) and between the support shield 150 and the gate trench 180 in the lateral direction (y direction). The minimum distance between the embedded lateral support shield extension 158 and the nearest trench shield 152 can be at least the same as the minimum width of the JFET region 122. As a result, the gap 124' does not become a bottleneck for current flow during on-state operation.

[0135] In the exemplary embodiment, the upper part of each embedded lateral support / shield extension 158 may be 0.1 to 10 microns below the lower surface of the adjacent trench shielding region 152 (i.e., deeper within the semiconductor layer structure 160). In other embodiments, the upper part of each embedded lateral support / shield extension 158 may be 0.1 to 3 microns, 0.2 to 2 microns, or 0.2 to 1 micron below the lower surface of the adjacent trench shielding region 152. This is shown in Figure 7 by distance D4, which is the vertical distance between the upper part of each embedded lateral support / shield extension 158 and the lower surface of the adjacent trench shielding region 152. In the exemplary embodiment, distance 124' (i.e., the minimum distance between each embedded lateral support / shield extension 158 and its nearest trench shielding region 152) may be 0.1 to 10 microns. In other embodiments, the distance 124' may be 0.1 to 3 microns, 0.1 to 2 microns, 0.1 to 1 micron, or 0.3 to 3 microns. In exemplary embodiments, each of the embedded lateral support shield extensions 158 may extend laterally over a distance of 0.1 to 20 microns from the sidewall of its associated support shield 150. In other embodiments, each of the embedded lateral support shield extensions 158 may extend laterally over a distance of 0.1 to 5 microns, 0.1 to 3 microns, or 0.1 to 1 micron from the sidewall of its associated support shield 150. In exemplary embodiments, each of the embedded lateral support shield extensions 158 may have a thickness of 0.1 to 20 microns (i.e., in the z direction). In other embodiments, each of the embedded lateral support shield extensions 158 may have a thickness of 0.1 to 5 microns, 0.1 to 3 microns, or 0.1 to 1 micron.

[0136] Accordingly, as shown in Figure 7, according to some embodiments of the present invention, a MOSFET 300 is provided, comprising a silicon carbide semiconductor layer structure 360 ​​having a drift region 120 having a first (n) conductivity type, a support shield 150 having a second (p) conductivity type, and an embedded lateral support shield extension 158 having a second (p) conductivity type. The embedded lateral support shield extension 158 extends laterally from the support shield 150. In this specification, the term “vertically” refers to a direction perpendicular to the main surfaces (top and bottom surfaces) of a semiconductor layer structure such as the semiconductor layer structure 160 (i.e., the z-direction in Figure 7), and the term “lateral” refers to a direction perpendicular to both the longitudinal and vertical directions of the gate trench (i.e., the “lateral” direction is the y-direction in Figure 7). The MOSFET 300 further includes a first gate trench 180 extending into the upper surface of the semiconductor layer structure 160.

[0137] As shown in Figure 7, in some embodiments, the semiconductor layer structure 160 may include a trench shielding region 152 having a second (p) conductivity type. The trench shielding region 152 may be located below the first gate trench 180, and the upper surface of the embedded lateral support shield extension 158 may be located deeper within the semiconductor layer structure 160 than the depth of the bottom surface of the trench shielding region 152. The semiconductor layer structure 160 may further or alternatively include a JFET region 122 having a first (n) conductivity type. The JFET region 122 (or, more generally, a part thereof) may be located vertically between the drift region 120 and the well region 130, and laterally between the support shield 150 and the first gate trench 180. The minimum distance between the embedded lateral support shield extension 158 and the trench shielding region 152 is at least the same as the minimum width of the JFET region 122 in the region between the support shield 150 and the first gate trench 180.

[0138] As further shown in Figure 7, at least portions of the first and second sidewalls of the support shield 150 may be inclined inward as the depth into the semiconductor layer structure 160 increases. The walls of the channel-type injected embedded lateral support shield extensions 158 may extend along the crystal axes of the silicon carbide semiconductor layer structure 160. In some embodiments, the crystal axis along the sidewall extension is one of the <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113> crystal axes. In other embodiments, the crystal axis along the sidewall extension is <0001> These are crystal axes. Sidewalls extending along the crystal axes of the silicon carbide semiconductor layer structure 160 may be sidewalls located at the ends of embedded lateral support shield extensions 158. In some embodiments, the sidewalls of the support shield 150 do not extend along the crystal axes of the silicon carbide semiconductor layer structure. For example, the support shield 150 may be formed using standard (random) ion implantation, while the embedded lateral support shield extensions 158 may be formed using a channel-type ion implantation process. As shown in Figure 7, at least portions of the first and second sidewalls of each support shield 150 may be inclined inward as the depth into the semiconductor layer structure 160 increases. As discussed above, support shields 150 having such a shape can be formed by using an ion implantation mask with inclined sidewalls during the ion implantation step used to form the support shield 150.

[0139] To form the device shown in Figure 7, a channel-type ion implantation process can be used to form the support shield 150. As discussed above, during this implantation process, a mask can be used that has inclined sidewalls defining an opening in the mask, such that the long sidewalls of each support shield 150 inclin inward as the support shield extends deeper into the semiconductor layer structure 160.

[0140] Figures 8A to 8C are schematic cross-sectional views of gate-trench silicon carbide power MOSFETs 300A to 300C, which are modified versions of the gate-trench silicon carbide power MOSFET 300, respectively.

[0141] The gate trench silicon carbide power MOSFETs 300A to 300C are nearly identical to the power MOSFET 300, but include embedded lateral support shield extensions 158A to 158C with different designs. As shown in Figure 8A, in the MOSFET 300A, the embedded lateral support shield extension 158A each comprises a roughly rectangular area extending at an angle of approximately ±45° from the bottom corner of the support shield 150. The length of the embedded lateral support shield extension 158A can be changed from the length shown in Figure 8A, and similarly, the angle at which the embedded lateral support shield extension 158A extends from the bottom corner of the support shield 150 can also be changed. This design may allow for an even larger minimum gap of 124”. Figure 8B shows a MOSFET 300B with an embedded lateral support shield extension 158B having yet another shape to demonstrate that the size, shape, orientation, etc., of the embedded lateral support shield extension can be changed to improve electric field shielding and / or on-state resistance during reverse bias operation. As shown in Figure 8C, the MOSFET 300C has an embedded lateral support shield extension 158C that extends considerably far laterally so as to overlap vertically with the gate trench 180 and / or trench shielding area 152. This design can improve electric field shielding and / or on-state resistance during reverse bias operation.

[0142] Figures 9A and 9B, along with Figures 4A to 4C, are schematic cross-sectional views illustrating the method for fabricating the gate-trench silicon carbide power MOSFET shown in Figure 7.

[0143] First, referring to Figures 4A to 4C, the device shown in Figure 4C can be formed by the method described above. Next, referring to Figure 9A, a mask layer, such as an oxide mask, is formed on the upper surface of the semiconductor layer structure 160, and this is then patterned (for example, using standard photolithography patterning techniques) to form a patterned mask 397 having openings 398 that expose a selected portion of the semiconductor layer structure 160. The openings 398 are located above the location in the semiconductor layer structure 160 where an embedded lateral support / shield extension 158 will be formed in a subsequent processing step. Next, referring to Figure 9B, a high-energy random ion implantation process is performed to form the embedded lateral support / shield extension 158. Then, referring to Figure 4E, the processing steps discussed above can be performed to complete the MOSFET 300 in Figure 7.

[0144] As described above, one technique for forming a support shield having opposing first and second sidewalls that slope inward as the depth into the semiconductor layer structure increases is to use a channel-type ion implantation process to form the support shield and to use an ion implantation mask having an opening with sloped sidewalls. However, it will be understood that embodiments of the present invention are not limited thereto. For example, in other embodiments, a p-type support shield may be formed having opposing first and second sidewalls that slope outward as the depth into the semiconductor layer structure increases, and an n-type dopant is implanted into the semiconductor layer structure either before or after this ion implantation process using an embedded random ion implantation process. Due to depth-dependent blooming that occurs as the depth increases in the random ion implantation process, a dopant that counteracts the p-type dopant is implanted into the outer edge of the support shield, thereby converting the outer edge of the support shield into an n-type semiconductor material. The extent to which this occurs increases with depth because blooming increases with depth.

[0145] Figures 10A to 10C illustrate this technique. As shown in Figure 10A, a channel-type ion implantation process is used to implant a p-type dopant into a semiconductor layer structure 460, forming a support shield 400 with opposing first and second sidewalls that slope outward as the depth increases. As discussed above, this results in the formation of an implantation region 400 with relatively vertical sidewalls. Referring to Figure 10B, a patterned ion implantation mask 410 is formed, and then an n-type dopant is implanted into the semiconductor layer structure within region 420 using a high-energy random ion implantation process. Because a random ion implantation process is used, region 420 exhibits blooming, and as a result, its sidewalls slope outward as the depth into the semiconductor layer structure 460 increases. As shown in Figure 10C, if the dopant concentration of the n-type dopant implanted in the second ion implantation step exceeds the dopant concentration of the p-type dopant implanted in the first ion implantation step, region 420 will have n-type conductivity. In this way, a support shield can be formed in which at least a portion of the first and second side walls of the support shield are inclined inward as the depth increases.

[0146] Embodiments of the present invention are described above, primarily with reference to cross-sectional views. In each of the embodiments of the present invention depicted, it will be understood that support shields (e.g., 150), trench shielding regions 152, gate trenches 180, etc., may be elongated structures that extend seamlessly into the plane of the figure across the active region of the semiconductor device. However, it will also be understood that in other embodiments, the support shields (e.g., 150) and / or trench shielding regions 152 may instead be segmented structures with parts removed, in which case these structures will not extend seamlessly into the plane of the figure, but instead will have multiple segments that are collinear and extend into the plane of the figure.

[0147] In the above description, each example embodiment has a specific conductivity type. In each of the above embodiments, it will be understood that a device with the opposite conductivity type can be formed simply by reversing the conductivity of the n-type and p-type layers. Therefore, it will be understood that the present invention encompasses both n-channel and p-channel devices for each different device structure (e.g., MOSFET, IGBT, etc.).

[0148] The present invention has been discussed primarily in relation to silicon carbide-based power semiconductor devices. However, it should be understood that silicon carbide is used as an example in this specification, and that the devices discussed herein can be formed from any suitable broadband gap semiconductor material system. For example, in any of the above embodiments, a gallium nitride-based semiconductor material (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used instead of silicon carbide.

[0149] Embodiments of the present invention have been described above with reference to the accompanying drawings illustrating embodiments of the present invention. However, it will be understood that the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments are provided to give thoroughness and completeness to this disclosure and to fully convey the scope of the invention to those skilled in the art. Similar reference numerals refer to similar elements throughout.

[0150] In this specification, the term "multiple" means two or more. In this specification, "substantially" means within ±10%.

[0151] Throughout this specification, terms such as "first," "second," etc., are used to describe various elements, but it will be understood that these elements are not limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. The terms "and / or" include any combination of one or more of the related enumerated items.

[0152] The technical terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the invention. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless explicitly indicated otherwise in the context. It will be further understood that, where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” indicate the presence of the mentioned feature, part, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, parts, steps, operations, elements, components, and / or groups thereof.

[0153] When an element, such as a layer, region, or substrate, is described as being "on top of" or "extending upward" to another element, it will be understood that the element may directly exist on top of or extend directly onto the other element, or there may be an intervening element. In contrast, when an element is described as being "directly on top of" another element or extending "directly upward" to another element, there is no intervening element. Similarly, when an element is described as being "connected to" or "bonded" to another element, it will be understood that the element may directly connect to or bond to the other element, or there may be an intervening element. In contrast, when an element is described as being "directly connected to" or "directly bonded" to another element, there is no intervening element.

[0154] In this specification, relative terms such as “below” or “above” or “upper side” or “lower side” or “top” or “bottom” may be used to describe the relationship between one element, layer, or region and another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass various arrangements of the device in addition to the arrangement depicted in the figures.

[0155] This specification describes embodiments of the present invention with reference to schematic cross-sectional views of idealized embodiments (and intermediate structures) of the present invention. Thicknesses of layers and regions in the drawings may be exaggerated for clarity. In addition, differences from the shapes shown in the drawings are naturally expected as a result of manufacturing techniques and / or tolerances. Embodiments of the present invention are further described with reference to a flowchart. It will be understood that the steps shown in the flowchart do not have to be performed in the order shown.

[0156] Some embodiments of the present invention are described with reference to semiconductor layers and / or regions having a conductivity type such as n-type or p-type, where conductivity type refers to the majority carrier concentration within the layer and / or region. Thus, n-type materials have a majority equilibrium concentration of negatively charged electrons, while p-type materials have a majority equilibrium concentration of positively charged holes. Depending on the material, "+" or "-" may be used to indicate a relatively larger ("+") or smaller ("-") concentration of majority carriers compared to another layer or region (as in n+, n-, p+, p-, n++, n--, p++, or p--). However, such notation does not imply that a particular concentration of majority or minority carriers exists within the layer or region.

[0157] Typical embodiments of the present invention are disclosed in the drawings and specification, and although certain terms are used, they are used only in a general and descriptive sense and are not intended to be limiting, and the scope of the present invention is defined in the following claims.

Claims

1. A semiconductor layer structure comprising a drift region having a first conductivity type, a well layer having a second conductivity type, and a support / shield having the second conductivity type, The semiconductor layer structure comprises a first gate trench extending into the upper part of the semiconductor layer structure, The width of the first portion of the support shield narrows as the distance from the well region increases. Semiconductor devices.

2. The semiconductor device according to claim 1, wherein the first portion of the support shield is located deeper than the well layer in the semiconductor layer structure and shallower than the bottom of the first gate trench in the semiconductor layer structure.

3. The semiconductor device according to claim 1, wherein the entire support shield located deeper than the well layer within the semiconductor layer structure has a width that narrows as the distance from the well region increases.

4. The semiconductor device according to any one of claims 1 to 3, wherein the bottom of the first gate trench has a first depth from the top of the semiconductor layer structure, and the bottom of the support shield has a second depth from the top of the semiconductor layer structure, the second depth being greater than the first depth.

5. The semiconductor device according to claim 4, wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type located below the first gate trench, the bottom of the trench shielding region having a third depth from the top of the semiconductor layer structure, and the second depth is greater than the third depth.

6. The semiconductor device according to claim 5, wherein the semiconductor layer structure further comprises an embedded support shield extension extending laterally from the support shield.

7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device comprises a MOSFET, the semiconductor layer structure further comprises a source layer having the first conductivity type on the well layer, a gate oxide layer and a gate electrode are located in the first gate trench, and the gate oxide layer is located between the gate electrode and the semiconductor layer structure.

8. The semiconductor device according to claim 7, wherein the maximum width of the portion of the support shield that horizontally overlaps the source region is at least 10% wider than the width of the portion of the support shield that horizontally overlaps the bottom of the first gate trench.

9. The semiconductor device according to any one of claims 1 to 8, further comprising a second gate trench extending into the upper part of the semiconductor layer structure, wherein the support shield is located between the first gate trench and the second gate trench.

10. The semiconductor device according to any one of claims 1 to 3, wherein a support-shield trench is provided within the semiconductor layer structure, extending at least partway through the support-shield, and a conductive material other than silicon carbide is present within the support-shield trench.

11. The semiconductor device according to claim 10, wherein the conductive material includes doped polysilicon.

12. The semiconductor device according to claim 10, wherein the conductive material includes nickel oxide.

13. The semiconductor device according to claim 10, wherein the conductive material includes a metal that is in Schottky contact with silicon carbide.

14. The semiconductor device according to claim 10, wherein the support shield trench does not penetrate the bottom surface of the support shield.

15. A semiconductor layer structure comprising: a drift region having a first conductivity type; a JFET region having the first conductivity type located above the drift region and having a doping concentration of the first conductivity type higher than that of the drift region; a well layer having a second conductivity type located above the JFET region; and a support shield having the second conductivity type. The semiconductor layer structure comprises a first gate trench extending into the upper part of the semiconductor layer structure, The first portion of the JFET region between the first gate trench and the support shield has a width that increases as the distance from the well layer increases. Semiconductor devices.

16. The semiconductor device according to claim 15, wherein at least a portion of the support shield has a width that narrows as the distance from the top of the semiconductor layer structure increases.

17. The semiconductor device according to claim 15, wherein the bottom of the first gate trench has a first depth from the top of the semiconductor layer structure, and the bottom of the support shield has a second depth from the top of the semiconductor layer structure, the second depth being greater than the first depth.

18. The semiconductor device according to claim 17, wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type located below the first gate trench, the bottom of the trench shielding region having a third depth from the top of the semiconductor layer structure, and the second depth is greater than the third depth.

19. The semiconductor device according to claim 18, wherein the semiconductor layer structure further comprises an embedded support shield extension extending laterally from the support shield.

20. The semiconductor device according to claim 19, wherein the support shield extension extends laterally over a distance of 0.1 to 5.0 microns.

21. The semiconductor device according to claim 20, wherein the support shield extension has a thickness of 0.1 to 20 microns.

22. The semiconductor device according to any one of claims 15 to 21, wherein the semiconductor device comprises a MOSFET, the semiconductor layer structure further comprises a source layer having the first conductivity type on the well layer, and a gate oxide layer and a gate electrode are located in the first gate trench, the gate oxide layer is located between the gate electrode and the semiconductor layer structure.

23. The semiconductor device according to claim 22, wherein the semiconductor device comprises a MOSFET, the semiconductor layer structure further comprises a source layer having the first conductivity type on the well layer, and the maximum width of the portion of the support shield that horizontally overlaps the source layer is at least 10% wider than the width of the portion of the support shield that horizontally overlaps the bottom of the first gate trench.

24. The semiconductor device according to any one of claims 15 to 21, further comprising a second gate trench extending into the upper part of the semiconductor layer structure, wherein the support shield is located between the first gate trench and the second gate trench.

25. The semiconductor device according to any one of claims 15 to 21, wherein a support-shield trench is provided within the semiconductor layer structure, extending at least partway through the support-shield, and a conductive material other than silicon carbide is present within the support-shield trench.

26. The semiconductor device according to claim 25, wherein the conductive material comprises one of doped polysilicon, nickel oxide, or a metal in Schottky contact with silicon carbide.

27. The semiconductor device according to claim 26, wherein the support shield trench does not penetrate the bottom portion of the support shield.

28. A semiconductor layer structure comprising a drift region having a first conductivity type, a support shield having a second conductivity type, and an embedded lateral support shield extension having the second conductivity type extending laterally from the support shield, The semiconductor layer structure comprises a first gate trench extending into the upper part of the semiconductor layer structure, The sidewalls of the support shield extend along the crystal axis of the semiconductor layer structure. Semiconductor devices.

29. The semiconductor device according to claim 28, wherein the sidewalls of the embedded lateral support shield extensions do not extend along the crystal axis of the silicon carbide semiconductor layer structure.

30. The semiconductor device according to claim 29, wherein the crystal axis is one of the following crystal axes: <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113>.

31. The semiconductor device according to claim 29, wherein the crystal axis is a <0001> crystal axis.

32. The semiconductor device according to any one of claims 28 to 31, wherein at least portions of the first and second side walls of the support shield are inclined inward as the depth into the semiconductor layer structure increases.

33. The semiconductor device according to any one of claims 28 to 31, wherein the semiconductor layer structure further comprises a JFET region having the first conductivity type between the drift region and the well region and between the support shield and the first gate trench, and the minimum distance between the embedded lateral support shield extension and the trench shield is at least the same as the minimum width of the JFET region.

34. The semiconductor device according to any one of claims 28 to 31, wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type located below the first gate trench, and the upper part of the support shield extension is located deeper within the semiconductor layer structure than the depth of the bottom surface of the trench shielding region.

35. The semiconductor device according to any one of claims 28 to 31, wherein the embedded support shield extension extends laterally from the support shield over a distance of 0.1 to 20 microns.

36. The semiconductor device according to any one of claims 28 to 31, further comprising a second gate trench extending into the upper part of the semiconductor layer structure, wherein the support shield is located between the first gate trench and the second gate trench.

37. To provide a semiconductor layer structure having a drift region having a first conductivity type, Forming first and second gate trenches within the semiconductor layer structure, The method involves forming a mask including an opening on the upper part of the semiconductor layer structure, wherein at least one of the side walls of the mask defining the opening is an inclined side wall that forms an obtuse angle with respect to the upper part of the semiconductor layer structure exposed through the opening. To form a support shield having a second conductivity type between the first gate trench and the second gate trench, the mask is used as an ion implantation shield to implant a dopant of the second conductivity type into the semiconductor layer structure. A method for fabricating semiconductor devices, including [a specific component].

38. The method according to claim 37, wherein the obtuse angle is an angle between 100° and 160°.

39. The method according to claim 37, wherein the width of the support shield narrows as the distance from the top of the semiconductor layer structure increases.

40. The method according to claim 37, wherein the bottom of the first gate trench has a first depth from the top of the semiconductor layer structure, and the bottom of the support shield has a second depth from the top of the semiconductor layer structure, the second depth being greater than the first depth.

41. The method according to claim 40, wherein the semiconductor layer structure further comprises a trench shielding region having the second conductivity type located below the first gate trench, the bottom of the trench shielding region having a third depth from the top of the semiconductor layer structure, and the second depth is greater than the third depth.

42. The method according to any one of claims 37 to 41, further comprising injecting a dopant of a second conductivity type into the semiconductor layer structure to form an embedded support shield extension that extends laterally from the support shield.

43. The method according to claim 42, wherein the second conductivity type dopant, which is implanted into the semiconductor layer structure to form the embedded support shield extension, is implanted using a random ion implantation process.

44. The method according to claim 43, wherein the second conductivity type dopant implanted into the semiconductor layer structure to form the support shield is implanted using a channel-type ion implantation process.

45. The method according to claim 43, wherein the second conductivity type dopant implanted into the semiconductor layer structure to form the support shield is implanted using a channel-type ion implantation process.

46. The semiconductor layer structure further comprises a well layer having the second conductivity type on the drift region and a source layer having the first conductivity type on the well layer, wherein the maximum width of the portion of the support shield that horizontally overlaps the source region is at least 10% wider than the width of the portion of the support shield that horizontally overlaps the bottom of the first gate trench, according to any one of claims 37 to 41.

47. To provide a semiconductor layer structure having a drift region having a first conductivity type, Forming first and second gate trenches within the semiconductor layer structure, By implanting a second conductivity type dopant into the semiconductor layer structure using both a non-channel type ion implantation process and a channel type ion implantation process, a support-shield structure is formed within the semiconductor layer structure. A method for fabricating semiconductor devices, including [a specific component].

48. The method according to claim 47, wherein the same ion implantation mask is used for both the non-channel type ion implantation process and the channel type ion implantation process.

49. The method according to claim 47 or 48, wherein the support-shield structure comprises a support shield formed by the channel-type ion implantation process and an embedded lateral support-shield extension formed by the non-channel-type ion implantation process.

50. The method according to claim 47, wherein the channel-type ion implantation process is carried out along one of the crystal axes <0001, > <11-23>, <-1-123>, <1-213>, <-12-13>, <2-1-13>, or <-2113>.

51. To provide a semiconductor layer structure having a drift region having a first conductivity type, To form a preliminary support shield, a second conductivity type dopant is injected into the semiconductor layer structure, The method involves injecting a dopant of the first conductive type into the semiconductor layer structure to convert the outer portion of the preliminary support shield into a first conductive type material and form a support shield having a first sidewall, wherein at least a portion of the first sidewall is inclined inward as the depth into the semiconductor layer structure increases. A method for fabricating semiconductor devices, including [a specific component].

52. The method according to claim 51, wherein the second conductive dopant is implanted into the semiconductor layer structure using a channel-type ion implantation process.

53. The method according to claim 52, wherein the first conductive dopant is implanted into the semiconductor layer structure using a random ion implantation process.

54. The method according to any one of claims 51 to 53, wherein the second conductivity type dopant is implanted into the semiconductor layer structure using a random ion implantation process, and the first conductivity type dopant is implanted into the semiconductor layer structure using a random ion implantation process.

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