Devices, systems, and methods for dynamically changing the frequency of a data link layer clock without downtime.

Abstract

An exemplary method for dynamically changing the frequency of the data link layer clock without downtime involves switching a first queue at the first end of the data link and a second queue at the second end of the data link from pacing mode to asynchronous mode. The exemplary method involves changing the frequency of the clock associated with the data link. The exemplary method further involves switching the first and second queues back from asynchronous mode to pacing mode after changing the clock frequency. Various other devices, systems, and methods are also disclosed.

Description

Technical Field

[0001] (Cross-Reference to Related Applications) This application claims the priority benefit of U.S. Patent Application No. 18 / 476,082, filed on September 27, 2023, entitled "DEVICES, SYSTEMS, AND METHODS FOR DYNAMICALLY CHANGING FREQUENCIES OF CLOCKS FOR THE DATA LINK LAYER WITHOUT DOWNTIME", the entire contents of which are incorporated herein by reference.

Background Art

[0002] Computing devices often include clocks, and clock signals are used to synchronize processes performed by digital circuits. In some examples, a computing device implements specific functions and / or modes that require changes to the frequency of a particular clock. For example, a pair of computing devices are communicatively coupled to each other via a data link. In this example, any of those computing devices needs to take down, pause, and / or deactivate the data link in order to change the frequency of the clock for the data link in response to performing a specific function or mode. Accordingly, the present disclosure identifies and addresses the need for additional improved devices, systems, and methods that support dynamically changing the frequency of a clock of a data link layer without downtime.

[0003] The accompanying drawings illustrate several exemplary embodiments and form part of the present specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

Brief Description of the Drawings

[0004] [Figure 1]This is a block diagram of an exemplary system for dynamically changing the frequency of a data link layer clock without downtime, according to one or more embodiments of the present disclosure. [Figure 2] This is a block diagram of an exemplary system for dynamically changing the frequency of a data link layer clock without downtime, according to one or more embodiments of the present disclosure. [Figure 3] A set of exemplary timing diagrams representing a sequence of events involved in dynamically changing the frequency of a clock for a data link without downtime, according to one or more embodiments of the present disclosure. [Figure 4] This is a block diagram of an exemplary embodiment of one or more embodiments of the present disclosure, which is involved in dynamically changing the frequency of the data link layer clock without downtime. [Figure 5] This is a flowchart illustrating an exemplary method for dynamically changing the frequency of a data link layer clock without downtime, according to one or more embodiments of the present disclosure. [Modes for carrying out the invention]

[0005] Throughout the drawings, the same reference numerals and designations indicate elements that are similar but not necessarily identical. The exemplary embodiments described herein are open to various modifications and alternative forms, but specific embodiments are shown in the drawings as examples and are described in detail herein. However, the exemplary embodiments described herein are not intended to limit to any particular form disclosed. Rather, this disclosure covers all modifications, equivalents and alternative forms that fall within the appended claims.

[0006] This disclosure describes various devices, systems, and methods for dynamically changing the frequency of the data link layer clock without downtime. In some examples, a computing device may implement power management functions and / or modes that require changing the frequency of the clocks responsible for the data link layer and / or media access control (MAC) layer. In one example, a computing device may be communicatively coupled to a remote device via the data link layer and / or MAC layer. In this example, the computing device may take down, pause, and / or deactivate the data link in response to the implementation of power management functions and / or modes to change the frequency of the clocks of the data link layer and / or MAC layer. By doing so, the computing device can avoid and / or prevent situations and / or events that would cause overflow and / or underflow in the queues implemented for the data link layer and / or MAC layer. Unfortunately, this takedown, pause, and / or deactivation of the data link can result in significant delays in the system, thereby adversely impacting system performance.

[0007] As will be described in more detail below, various devices, systems and / or methods described herein can eliminate, eliminate and / or overcome the need to take down, pause and / or deactivate a data link before changing the frequency of the data link layer and / or MAC layer clocks. For example, a system may include and / or represent a pair of computing devices coupled together to communicate with each other via a data link. In one example, a processor incorporated in these computing devices can switch first-in-first-out (FIFO) queues implemented at both ends of the data link from pacing mode (sometimes referred to as predictive mode) to asynchronous mode (sometimes referred to as credit mode). In this example, the processor can then reduce the frequency of their respective MAC clocks associated with the data link. After changing the frequency of their respective MAC clocks, the processor can switch the FIFO queues back from asynchronous mode to pacing mode. These steps, functions and / or actions can be achieved or performed in a variety of different ways.

[0008] The following provides a detailed description of exemplary devices, systems, and / or corresponding embodiments for dynamically changing the frequency of the data link layer clock without downtime, with reference to Figures 1 to 4. A detailed description of exemplary methods for dynamically changing the frequency of the data link layer clock without downtime is provided in reference to Figure 5.

[0009] Figure 1 shows an exemplary system 100 that facilitates and / or supports dynamically changing the frequency of the data link layer clock without downtime. As shown in Figure 1, the exemplary system 100 may include and / or represent computing devices 102(1) and 102(2) that are coupled to communicate with each other via a data link 110. In some examples, computing device 102(1) may include and / or represent a communication interface 104(1), a processor 106(1), a queue 108(1), and / or a clock 112(1). Additionally or alternatively, computing device 102(2) may include and / or represent a communication interface 104(2), a processor 106(2), a queue 108(2), and / or a clock 112(2). In certain embodiments, computing devices 102(1) and 102(2) may represent and / or constitute both ends of the data link 110.

[0010] In some examples, each of the communication interfaces 104(1) and 104(2) can facilitate, support, establish, and / or provide a data link 110 for and / or on behalf of computing devices 102(1) and 102(2). In one example, the communication interfaces 104(1) and 104(2) can facilitate, support, and / or provide a direct connection between computing devices 102(1) and 102(2) without any intermediate nodes. In another example, the communication interfaces 104(1) and 104(2) can facilitate, support, and / or provide an indirect connection between computing devices 102(1) and 102(2) with one or more intermediate nodes. For example, the communication interfaces 104(1) and 104(2) can facilitate, support, and / or provide connections through local area networks (such as Ethernet® networks), personal area networks, wide area networks, private networks (e.g., virtual private networks), telephone or cable networks, mobile phone connections, satellite data connections, wireless or wired connections, the Internet, a combination or variation of one or more of these, and / or any other suitable communication mechanisms and / or channels.

[0011] Examples of communication interfaces 104(1) and 104(2) include, but are not limited to, link adapters, wired network interfaces, network interface cards, wireless network interfaces, wireless network interface cards, serializer / deserializer (SerDes) interfaces, universal chiplet interconnect express (UCIe) interfaces, host adapters (small computer system interface (SCSI) host adapters, universal serial bus (USB) host adapters, IEEE 1394 host adapters, and / or external SATA (eSATA) host adapters), advanced technology attachments (ATA), parallel ATA (PATA), serial ATA (SATA), Fibre Channel interface adapters, Ethernet® adapters, one or more combinations or variations thereof, and / or any other suitable communication interface. Although shown as a single unit in the computing devices 102(1) and 102(2) in Figure 1, each of the communication interfaces 104(1) and 104(2) can include and / or represent a set of multiple communication interfaces implemented on the computing devices 102(1) and 102(2).

[0012] In some examples, data link 110 can carry, exchange, and / or provide traffic through the data link layer of the Open Systems Interconnection (OSI) model. In one example, the data link layer may include and / or represent several sublayers, such as the logic link control (LLC) layer and the MAC layer. In this example, data link 110 can carry, exchange, and / or provide traffic through the MAC layer within the data link layer. This allows clocks 112(1) and 112(2) to provide and / or associate services with the data link layer and / or the MAC layer.

[0013] In some examples, data link 110 may include and / or represent any type or form of physical cable, line, signal and / or code that can establish communication between computing devices 102(1) and 102(2). Examples of data link 110 include, but are not limited to, Quad Small Form-factor Pluggable (QSFP) cable, Ethernet® cable, fiber optic cable, Fibre Channel cable, optical cable, InfiniBand cable, CXP cable, Multiple-Fiber Push-On / Pull-Off (MPO) cable, XAUI cable, XFP cable, XFI cable, C Form-factor Pluggable (CFP) cable, one or more variations or combinations thereof, and / or any other suitable data link.

[0014] In some examples, each of processors 106(1) and 106(2) may include and / or represent a hardware implementation device and / or circuit capable of running firmware, an operating system and / or a user application. For example, each of processors 106(1) and 106(2) may include and / or represent a central processing unit (CPU), a CPU core, a graphics processing unit (GPU), and / or a GPU core. In one example, each of processors 106(1) and 106(2) may include and / or represent any of several processors (e.g., several x86 processors) implemented and / or deployed on a system-on-a-chip SoC. Additional examples of processors 106(1) and 106(2) include, but are not limited to, parallel accelerating processors, tensor cores, microprocessors, microcontrollers, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), chiplets, one or more parts thereof, one or more variations or combinations thereof, and / or any other suitable processors. Although shown as a single unit in computing devices 102(1) and 102(2) in Figure 1, each of processors 106(1) and 106(2) may include and / or represent a collection of multiple processors implemented on computing devices 102(1) and 102(2).

[0015] In some examples, each of the processors 106(1) and 106(2) may implement and / or be configured using a variety of different architectures and / or microarchitectures. For example, each of the processors 106(1) and 106(2) may be implemented and / or configured as a reduced instruction set computer (RISC) architecture. In another example, each of the processors 106(1) and 106(2) may be implemented and / or configured as a complex instruction set computer (CISC) architecture. Additional examples of such architectures and / or microarchitectures include, but are not limited to, 16-bit computer architectures, 32-bit computer architectures, 64-bit computer architectures, x86 computer architectures, advanced RISC machine (ARM) architectures, microprocessor without interlocked pipelined stage (MIPS) architectures, scalable processor architectures (SPARC), load-store architectures, one or more of these, one or more combinations or variations thereof, and / or any other suitable architectures or microarchitectures.

[0016] In some examples, each of the queues 108(1) and 108(2) may include and / or represent communication interfaces 104(1) and 104(2), data link 110, and / or any type or form of data structure and / or buffer associated with the MAC layer. In one example, each of the queues 108(1) and 108(2) may include and / or represent a FIFO queue that facilitates and / or supports data link 110. For example, each of the queues 108(1) and 108(2) may organize, manage, and / or store data intended for transmission and / or transfer over data link 110. In this example, each of the queues 108(1) and 108(2) may be positioned and / or incorporated within the data paths of computing devices 102(1) and 102(2). Although shown as a single unit in the computing devices 102(1) and 102(2) in Figure 1, each of the queues 108(1) and 108(2) can include and / or represent a set of multiple queues implemented on the computing devices 102(1) and 102(2).

[0017] In some examples, each of clocks 112(1) and 112(2) may include and / or represent any type or form of digital clock and / or system clock implemented on computing devices 102(1) and 102(2). In one example, each of clocks 112(1) and 112(2) may include and / or represent a fabric clock and / or MAC clock associated with the data link layer and / or MAC layer. Although shown as a single unit in computing devices 102(1) and 102(2) in Figure 1, each of clocks 112(1) and 112(2) may include and / or represent a collection of multiple clocks implemented on computing devices 102(1) and 102(2).

[0018] In some examples, processors 106(1) and 106(2) can switch and / or change each of queues 108(1) and 108(2) from pacing mode to asynchronous mode. In one example, pacing mode may involve the transmitter determining the bandwidth of each segment in data link 110 and then controlling and / or regulating the flow of traffic on data link 110 based at least in part on the bandwidth of those segments. For example, computing device 102(1) may represent and / or configure a transmitter, and computing device 102(2) may represent and / or configure a receiver. In this example, the processor 106(1) of computing device 102(1) may know and / or determine the available bandwidth of data link 110, communication interface 104(1), and / or communication interface 104(2). The processor 106(1) may then supply and / or provide a certain amount of traffic to the communication interface 104(2) for transmission via the data link 110, according to their available bandwidth.

[0019] In one example, the asynchronous mode may involve the transmitter receiving traffic credits and / or allocations from the receiver, and then controlling and / or regulating the flow of traffic on the data link 110, at least in part, based on those credits and / or allocations. For example, computing device 102(1) may represent and / or configure the transmitter, and computing device 102(2) may represent and / or configure the receiver. In this example, the processor 106(2) of computing device 102(2) may generate and / or create credits and / or allocations representing the amount of traffic that computing device 102(1) transmits over the data link 110. Upon receiving this generation and / or allocation from computing device 102(2), the processor 106(1) of computing device 102(1) may supply and / or provide a certain amount of traffic to the communication interface 104(2) for transmission over the data link 110 to the communication interface 104(2), in accordance with the credits and / or allocations. The processor 106(1) of computing device 102(1) may wait until it receives subsequent credits and / or allocations from computing device 102(2) before transmitting more traffic over data link 110.

[0020] In some examples, computing devices 102(1) and 102(2) can change the frequencies of clocks 112(1) and 112(2) to correspond to and / or comply with power management functions or modes affecting data link 110. For example, when queue 108(1) is switched from pacing mode to asynchronous mode, processor 106(1) can reduce and / or decrease the frequency of clock 112(1) without taking down, pausing and / or deactivating data link 110. Similarly, when queue 108(2) is switched from pacing mode to asynchronous mode, processor 106(2) can reduce and / or decrease the frequency of clock 112(2) without taking down, pausing and / or deactivating data link 110. By reducing and / or decreasing the frequencies of the clocks 112(1) and 112(2) in this manner, processors 106(1) and 106(2) can prevent overflow and / or underflow events or conditions in queues 108(1) and 108(2) as a result of a power management function or mode. In certain embodiments, each of processors 106(1) and 106(2) can verify and / or ensure that queues 108(1) and 108(2) have completed switching to asynchronous mode, respectively, before changing the frequencies of the clocks 112(1) and 112(2).

[0021] For example, computing devices 102(1) and 102(2) can exchange traffic over data link 110 during and / or at any given moment when the frequencies of clocks 112(1) and 112(2) are changed. In other words, even when the clock frequencies are reduced and / or decreased to accommodate and / or comply with power management functions, computing devices 102(1) and 102(2) can continue to send and / or receive traffic over data link 110 because queues 108(1) and 108(2) are currently operating in asynchronous mode rather than pacing mode. This allows computing devices 102(1) and 102(2) to maintain and / or keep data link 110 in active or mission mode when the frequencies of clocks 112(1) and 112(2) are reduced at any given moment. After a change in the frequency of clocks 112(1) and 112(2), computing devices 102(1) and 102(2) can return queues 108(1) and 108(2) from asynchronous mode to pacing mode and / or restore them.

[0022] Figure 2 shows an exemplary system 200 that facilitates and / or supports dynamically changing the frequency of the data link layer clock without downtime. In some examples, system 200 may include and / or represent certain components and / or features that perform and / or provide functionality similar to and / or identical to that described above in relation to Figure 1. As shown in Figure 2, in addition to those components and / or functions described above in relation to Figure 1, each of the computing devices 102(1) and 102(2) may include and / or represent power management functions 210(1) and 210(2), MAC layers 214(1) and 214(2), and / or clocks 212(1) and 212(2).

[0023] In some examples, the computing devices 102(1) and 102(2) can switch the queues 108(1) and 108(2) to an asynchronous mode in response to activation of the power management functions 210(1) or 210(2), and then initiate a process of changing the frequencies of the clocks 112(1) and 112(2). For example, the processor 106(1) can implement and / or detect the power management function 210(1). In this example, the power management function 210(1) can request and / or cause the processor 106(1) and / or other components of the computing device 102(1) to operate at a reduced power level. Similarly, the processor 106(2) can implement and / or detect the power management function 210(2). In this example, the power management function 210(2) can request and / or cause the processor 106(2) and / or other components of the computing device 102(2) to operate at a reduced power level.

[0024] In some examples, as part of and / or in response to the power management function 210(1), the computing device 102(1) reduces and / or decreases the amount of power dedicated to and / or consumed by the clock 112(1), the communication interface 104(1), and / or the data link 110. Similarly, as part of and / or in response to the power management function 210(1), the computing device 102(1) reduces and / or decreases the amount of power dedicated to and / or consumed by the clock 112(1), the communication interface 104(1), and / or the data link 110. Thereby, the processors 106(1) and 106(2) can instruct and / or cause each of the clocks 112(1) and 112(2) to reduce and / or decrease their respective frequencies to correspond to and / or comply with the power management functions 210(1) or 210(2).

[0025] As a specific example, the processor 106(1) can detect activation of the power management function 210(1) on the computing device 102(1). In response to the activation of the power management function 210(1), the processor 106(1) can switch the queue 108(1) from a pacing mode to an asynchronous mode, and instruct the computing device 102(1) to send a command to the computing device 102(2) via the data link 110. In addition, after switching the queue 108(1) to the asynchronous mode and sending the command, the processor 106(1) can reduce the frequency of the clock 112(1) as part of the power management function 210(1).

[0026] Continuing this example, the computing device 102(2) can receive the command from the computing device 102(1). In one example, the command can prompt, instruct and / or direct the computing device 102(2) to reduce the frequency of the clock 112(2) to correspond to the activation of the power management function 210(1) on the computing device 102(1). To do so, the processor 106(2) can first switch the queue 108(2) from the pacing mode to the asynchronous mode in response to the command. The processor 106(2) can then reduce the frequency of the clock 112(2) to correspond to the power management function 210(1), and instruct the computing device 102(2) to send an acknowledgment to the computing device 102(1) via the data link 110.

[0027] Continuing this example, computing device 102(1) can receive this acknowledgment from computing device 102(2). In one example, processor 106(1) can determine and / or confirm, at least in part, that computing device 102(2) has switched queue 108(2) to asynchronous mode and / or reduced the frequency of clock 112(2) to accommodate the activation of power management function 210(1). In response to this determination and / or confirmation, processor 106(1) can return queue 108(1) from asynchronous mode to pacing mode and / or restore it, and / or instruct computing device 102(1) to send additional commands to computing device 102(2) via data link 110.

[0028] Continuing this example, computing device 102(2) can receive additional commands from computing device 102(1). For example, the additional commands may prompt, instruct, and / or instruct computing device 102(2) to return the switch queue 108(2) from pacing mode to asynchronous mode and / or restore it, depending on the command. The data link 110 can then operate and / or carry traffic at a reduced and / or decreased rate or speed to accommodate the power management function 210(1).

[0029] Subsequently, if the power management function 210(1) is deactivated on the computing device 102(1), the computing device 102(1) may switch queues 108(1) and 108(2) to asynchronous mode and then initiate a process to increase the frequencies of clocks 112(1) and 112(2) in response to the deactivation of the power management function 210(1). For example, the computing devices 102(1) and 102(2) may perform any of the steps, functions, and / or actions described above in response to the deactivation of the power management function 210(1) and / or to increase the frequencies of clocks 112(1) and 112(2) back to their original states.

[0030] The various steps, functions, and / or actions described above can be performed and / or carried out by any of the various different components found on computing devices 102(1) and 102(2). For example, one or more of the processors 106(1) and 106(2) can implement and / or run firmware that performs and / or carries out one or more of the steps, functions, and / or actions described above in order to dynamically change the frequencies of the clocks 112(1) and 112(2). In another example, each of the hardware on computing devices 102(1) and 102(2) (e.g., the data link layer and / or MAC interface) can perform and / or carry out one or more of the steps, functions, and / or actions described above in order to dynamically change the frequencies of the clocks 112(1) and 112(2).

[0031] As a specific example, firmware implemented on one or more of processors 106(1) and 106(2) can send commands to the data link layer for high-speed protocols on both sides of data link 110. In this example, the commands can instruct and / or cause the data link layer to change all FIFO queues in the data path from pacing mode to asynchronous mode. In one example, the firmware can poll and / or check the status of the FIFO queues to confirm and / or guarantee that they have changed to asynchronous mode. Once the change is confirmed and / or guaranteed, the data link layer can start operating at a lower frequency.

[0032] For example, the data link layer may set each of the clocks 112(1) and 112(2) to a lower frequency than the clocks 212(1) and 212(2) implemented and / or incorporated by the computing devices 102(1) and 102(2). In this example, each of the clocks 212(1) and 212(2) may include and / or represent separate reference clocks of the computing devices 102(1) and 102(2). Additionally or alternatively, the firmware may notify and / or inform the data link layer of a new target frequency for the clocks 102(1) and 102(2) on both sides of the data link 110. When the frequencies of clocks 112(1) and 112(2) change, the firmware may send additional commands to the data link layers on both sides of the data link 110. These additional commands may instruct and / or cause the data link layer to return all FIFO queues in the data path from asynchronous mode to pacing mode.

[0033] As an additional example, firmware implemented in one or more of processors 106(1) and 106(2) can program the data link layer to a new target frequency and / or MAC clock speed. In this example, the MAC can initiate and / or start a MAC clock change and / or notify the data link layer of the MAC clock change by deasserting a clock stabilization signal (e.g., "clkStable") on the MAC interface. In response to the deasserted clock stabilization signal, the data link layer can change all FIFO queues in the data path from pacing mode to asynchronous mode and deassert a clock request signal (e.g., "clkRequest"). The MAC clocks on both sides of data link 110 can then be set to a lower frequency and / or speed.

[0034] For example, the MAC clocks on both sides of data link 110 can start operating at the frequency and / or speed of a slower reference clock (e.g., "Refclk"). In this example, after the MAC clock changes to the frequency and / or speed of the slower reference clock, the MAC can reassert the clock stabilization signal. In response to the reasserted clock stabilization signal, the data link layer can assert the clock request signal. The data link layer can then change all FIFO queues in the data paths on both sides of data link 110 back from asynchronous mode to pacing mode.

[0035] As a further example, firmware implemented on processor 106(1) can send commands to the data link layer on computing device 102(1). In this example, the commands can instruct and / or change all FIFO queues in the data path of computing device 102(1) from pacing mode to asynchronous mode. In one example, the firmware can poll and / or check the status of the FIFO queues to confirm and / or guarantee that they have changed to asynchronous mode. Once the change is confirmed and / or guaranteed, the firmware can program the data link layer to a new target frequency and / or MAC clock speed.

[0036] Continuing this example, the firmware may program the clock stabilization override (e.g., "REGS_clkStableOverride") to "1" and the clock stabilization register or signal (e.g., "REGS_clkStable") to "0" in order to issue a clock change request to the computing device 102(2) via the data link 110. In one example, the firmware may poll and / or check the status of the status register (e.g., "REGS_remoteFclkRequest") until it indicates that the computing device 102(2) has acknowledged the clock change request. In this example, the firmware may program the clock stabilization register or signal to "0" and then program the clock stabilization override to "0". The firmware may then program the computing device 102(1) to change all FIFO queues in its data path from asynchronous mode back to pacing mode.

[0037] Figure 3 shows an exemplary timing diagram 300 corresponding to an embodiment of a system in which the clock frequency dynamically changes relative to the data link without downtime. In some examples, the system to which the timing diagram 300 corresponds may include and / or represent certain components and / or functions that perform and / or provide functionality similar to and / or identical to that described above in relation to either Figure 1 or Figure 2. In one example, the timing diagram 300 may include and / or represent a diagram corresponding to the local side 302 and another diagram corresponding to the remote side 304. In this example, the local side 302 may correspond to computing device 102(1), and the remote side 304 may correspond to computing device 102(2).

[0038] In some examples, firmware implemented on the local side 302 can program the data link layer to a new target frequency and / or MAC clock speed. In this example, the MAC can initiate and / or start a MAC clock change and / or notify the data link layer of the MAC clock change by deasserting the clkStable signal on the MAC interface of the local side 302. In response to the deasserted clkStable signal, the data link layer can issue command 320 to the remote side 304 via data link 110, changing all FIFO queues in the data path of the local side 302 from pacing mode 310 to asynchronous mode 312, and then reduce the MAC clock frequency of the local side 302. In response to receiving command 320, the remote side 304 can change all FIFO queues in its data path from pacing mode 310 to asynchronous mode 312, reduce the MAC clock frequency, and then issue acknowledgment 322 to the local side 302 via data link 110.

[0039] Continuing this example, when the local side 302 receives an acknowledgment 322 from the remote side 304, the data link layer can deassert the clkRequest signal. The MAC can then reassert the clkStable signal. In response to the reasserted clkStable signal, the data link layer can increase the frequency of the MAC clock to its original speed, change all FIFO queues in the data path of the local side 302 from asynchronous mode 312 to pacing mode 310, and issue a command 324 to the remote side 304 via the data link 110. The data link layer can then reassert the clkRequest signal. In response to receiving the command 324, the remote side 304 can increase the frequency of its MAC clock to its original speed and change all FIFO queues in its data path from asynchronous mode 312 to pacing mode 310. The remote side 304 can then issue an acknowledgment 326 to the local side 302 via the data link 110.

[0040] Figure 4 shows an exemplary embodiment 400 of components and / or functions involved in dynamically changing the frequencies of clocks 112(1) and 112(2) without downtime. In some examples, embodiment 400 may include and / or represent specific components and / or functions that perform and / or provide functionality similar to and / or identical to that described above in relation to any of Figures 1 to 3. In one example, embodiment 400 may include and / or represent an OSI layer 402 that facilitates, supports and / or provides different network channels and / or protocols for communication. In this example, the OSI layer 402 may include and / or represent a physical layer 404(1), a data link layer 404(2), a network layer 404(3), a transport layer 404(4), a session layer 404(5), a presentation layer 404(6), and / or an application layer 404(7).

[0041] In some examples, one or more of the OSI layers 402 may include and / or represent a set of sublayers 406. For example, the physical layer 404(1) may include and / or represent the physical medium dependency layer 410(1), the physical medium connection layer 410(2), and / or the physical coding layer 410(3). Additionally or alternatively, the data link layer 404(2) may include and / or represent the MAC layer 408(1) and / or the logical link control layer 408(2). Thus, the data link 110 may carry, exchange, and / or provide traffic through the data link layer 404(2) and / or the MAC layer 408(1), and the clocks 112(1) and 112(2) may provide services to and / or associate with the data link layer 404(2) and / or the MAC layer 408(1).

[0042] In some examples, the various devices and / or systems described with respect to Figures 1 to 4 may include and / or represent one or more additional circuits, components and / or functions not necessarily shown and / or labeled in Figures 1 to 4. For example, computing devices 102(1) and 102(2) may include and / or represent additional analog and / or digital circuits, onboard logic, transistors, resistors, capacitors, diodes, inductors, switches, registers, flip-flops, connections, traces, buses, semiconductor (e.g., silicon) devices and / or structures, processing devices, storage devices, circuit boards, packages, substrates, housings, one or more combinations or variations thereof, and / or any other suitable components that facilitate and / or support the dynamic variation of the clock frequency for the data link layer without downtime. In certain embodiments, one or more of these additional circuits, components, devices and / or functions may be inserted and / or applied between any of the existing circuits, components and / or devices shown in Figures 1 to 4, in accordance with the purposes and / or objectives provided herein. Accordingly, the electrical and / or communication connections described with reference to Figures 1 to 4 can be direct connections without intermediate components, intermediate devices, and / or intermediate nodes, or indirect connections with one or more intermediate components, intermediate devices, and / or intermediate nodes.

[0043] In some examples, the phrases “to couple” and / or the term “coupling” can refer to direct and / or indirect connections as used herein. For example, a direct coupling between two components can constitute and / or represent a coupling in which these two components are directly connected to each other by a single node that provides electrical continuity from one of the two components to the other. In other words, a direct coupling can exclude and / or omit any additional components between those two components.

[0044] Additionally or alternatively, an indirect connection between two components can constitute and / or represent a connection in which these two components are indirectly connected to each other by a plurality of nodes that cannot provide electrical continuity from one of the two components to the other. In other words, an indirect connection can include and / or incorporate at least one additional component between those two components.

[0045] Figure 5 is a flowchart of an exemplary method 500 for dynamically changing the frequency of the data link layer clock without downtime. In one example, the steps shown in Figure 5 can be performed and / or carried out while the computing device and / or system is in operation. Additionally or alternatively, the steps shown in Figure 5 may incorporate and / or be accompanied by various substeps and / or variations that are consistent with the descriptions provided above in relation to Figures 1 to 4.

[0046] As shown in Figure 5, exemplary method 500 includes and / or involves step (510) switching multiple queues implemented at both ends of a data link from pacing mode to asynchronous mode. Step 510 can be carried out in various ways, including any of the techniques described above in relation to Figures 1 to 4. For example, computing devices connected to each other via a data link can switch and / or change multiple queues implemented on those computing devices from pacing mode to asynchronous mode.

[0047] Furthermore, exemplary method 500 includes and / or involves the step (520) of changing the frequency of the clock associated with the data link. Step 520 can be carried out in various ways, including any of the techniques described above in relation to Figures 1 to 4. For example, computing devices connected to each other via a data link can reduce and / or decrease the frequency of the MAC clock associated with the data link.

[0048] Exemplary method 500 further includes the step (530) of changing the clock frequency and returning the multiple queues from asynchronous mode to pacing mode. Step 530 can be carried out in various ways, including any of the techniques described above in relation to Figures 1 to 4. For example, computing devices connected to each other via a data link can switch and / or change the multiple queues implemented on those computing devices from asynchronous mode back to pacing mode.

[0049] While the above disclosures describe various embodiments using specific block diagrams, flowcharts, and examples, the components, flowchart steps, operations, and / or components of each block diagram described and / or shown herein can be implemented individually and / or collectively using a wide range of hardware, software, or firmware (or any combination thereof) configurations. In addition, since many other architectures can be implemented to achieve the same functionality, any disclosure of components contained within other components should be considered illustrative in nature. Furthermore, the various steps, events, and / or features performed by such components should be considered illustrative in nature, since many alternative examples and / or variations can be implemented within the scope of this disclosure to achieve the same functionality.

[0050] The process parameters and the order of steps described and / or shown herein are given only as examples and may be changed as desired. For example, the steps shown and / or shown herein are illustrated or described in a particular order, but these steps do not necessarily have to be performed in the shown or described order. Various exemplary methods described and / or shown herein may omit one or more of the steps described or shown herein, or may include additional steps in addition to those disclosed.

[0051] The above description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to limit to any specific form disclosed. Many modifications and variations are possible without departing from the spirit and scope of this disclosure. The embodiments disclosed herein should be considered in all respects to be exemplary and not restrictive. In determining the scope of this disclosure, the appended claims and their equivalents should be referenced.

[0052] Unless otherwise stated, the terms “connected” and “joined” (and their derivatives) as used herein and in the claims should be interpreted to allow both direct and indirect connections (i.e., through other elements or components). In addition, the terms “a” or “an” as used herein and in the claims should be interpreted to mean “at least one of.” Finally, for ease of use, the terms “including” and “having” (and their derivatives) as used herein and in the claims are interchangeable with the term “comprising” and have the same meaning.

Claims

1. It is a method, Switching the first queue at the first end of the data link and the second queue at the second end of the data link from pacing mode to asynchronous mode, Changing the frequency of the clock associated with the aforementioned data link, Changing the frequency of the clock includes returning the first queue and the second queue from the asynchronous mode back to the pacing mode, method.

2. This includes exchanging traffic on the data link at a specific time, Changing the frequency of the clock includes changing the frequency of the clock at the specific time. The method according to claim 1.

3. Changing the frequency of the clock includes reducing the frequency of the clock without deactivating the data link. The method according to claim 1.

4. This includes detecting the activation of a power management function that affects the data link, Changing the frequency of the clock includes reducing the frequency of the clock in response to detecting the activation of the power management function. The method according to claim 1.

5. To detect the deactivation of the aforementioned power management function, This includes increasing the frequency of the clock in response to detecting the deactivation of the power management function, The method according to claim 4.

6. Reducing the frequency of the clock includes suppressing the occurrence of an overflow or underflow condition in at least one of the first queue and the second queue as a result of activating the power management function. The method according to claim 4.

7. Reducing the frequency of the clock includes keeping the data link active while the frequency of the clock is reduced. The method according to claim 4.

8. The first queue includes a first-in, first-out (FIFO) queue implemented in the data path of a first computing device representing the first end of the data link, The second queue includes a second FIFO queue implemented in the data path of a second computing device representing the second end of the data link. The method according to claim 1.

9. Changing the frequency of the aforementioned clock means Setting a first clock associated with a media access control (MAC) layer implemented on the computing device to a lower frequency than a reference clock available on the computing device, This includes setting a second clock associated with an additional MAC layer implemented on an additional computing device to a lower frequency than an additional reference clock available on the additional computing device, The method of claim 8.

10. Before changing the frequency of the first clock, confirm that the first FIFO queue has switched to the asynchronous mode, This includes, before changing the frequency of the second clock, confirming that the second FIFO queue has switched to the asynchronous mode, The method of claim 9.

11. Switching the first queue and the second queue to the asynchronous mode includes switching the first queue and the second queue to the asynchronous mode via firmware implemented at the first and second ends of the data link, or via a data link layer implemented throughout the entire data link. Changing the frequency of the clock includes changing the frequency of the clock via the firmware or the data link layer. This includes returning the first queue and the second queue from the asynchronous mode to the pacing mode via the firmware or the data link layer. The method according to claim 1.

12. It is a system, Data link and A plurality of computing devices connected to communicate via the aforementioned data link, The aforementioned multiple computing devices are Switching the first queue at the first end of the data link and the second queue at the second end of the data link from pacing mode to asynchronous mode, On the aforementioned multiple computing devices, the frequency of the clock associated with the data link is changed, Changing the frequency of the clock returns the first queue and the second queue from the asynchronous mode back to the pacing mode, It is configured to do, system.

13. The aforementioned multiple computing devices are Exchanging traffic on the aforementioned data link at a specific time, Changing the frequency of the clock at the aforementioned specific time, It is configured to do, The system according to claim 12.

14. The plurality of computing devices are configured to reduce the clock frequency without deactivating the data link. The system according to claim 12.

15. At least one of the aforementioned computing devices is To detect the activation of a power management function that affects the aforementioned data link, In response to the activation of the power management function, the frequency of the clock is reduced, It is configured to do, The system according to claim 12.

16. At least one of the aforementioned computing devices is To detect the deactivation of the aforementioned power management function, The frequency of the clock is increased in response to the deactivation of the power management function, It is configured to do, The system according to claim 15.

17. At least one of the plurality of computing devices is configured to suppress the occurrence of an overflow or underflow condition in at least one of the first queue and the second queue as a result of activating the power management function. The system according to claim 15.

18. The plurality of computing devices are configured to keep the data link active while the clock frequency is reduced. The system according to claim 15.

19. The first queue includes a first-in, first-out (FIFO) queue implemented in the data path of any of the plurality of computing devices, The second queue includes a second FIFO queue implemented in the data path of another computing device among the plurality of computing devices. The system according to claim 12.

20. A computing device, A communication interface configured to establish a data link with an additional communication interface of a remote device, It comprises at least one processor, The aforementioned at least one processor is Switching at least one queue implemented in relation to the aforementioned communication interface from pacing mode to asynchronous mode, Changing the frequency of at least one clock associated with the data link, Changing the frequency of the at least one clock causes the at least one queue to return from the asynchronous mode to the pacing mode, It is configured to do, Computing device.

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