broadband photodetector

Abstract

The optical communication system (20) includes an optical waveguide (38) and a photodetector (PD-40). The optical waveguide is arranged to receive and guide an optical signal. The PD is configured to receive an optical signal from the optical waveguide and convert the optical signal into an electrical signal. The PD includes a stack of layers including at least (i) a first layer (68, 72, 76) comprising two or more semiconductor layers forming a reverse-biased semiconductor junction configured to generate an electrical signal in response to an optical signal incident thereon, and (ii) a second layer (64, 68) forming a capacitive element connected in series with the reverse-biased semiconductor junction. The PD further includes a first electrode (80) and a second electrode (84) configured to (i) apply one or more voltages to reverse-bias the reverse-biased semiconductor junction and (ii) output an electrical signal.

Description

TECHNICAL FIELD

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 543,276 filed on October 9, 2023, the disclosure of which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates generally to optical communications, and in particular to photodetector design.

BACKGROUND ART

[0003] A photodetector (PD) is a fundamental component in optical communication devices and other optoelectronic systems. Some PDs are fabricated using III-V semiconductors such as gallium arsenide (GaAs). Other PDs are implemented using Silicon-On-Insulator (SOI) technology.

[0004] A general review of silicon-based PDs is provided by Gupta and Kedia in "A Review on Silicon-Based Photodetectors", International Journal of Innovative Research in Science, Engineering and Technology, Vol. 5, No. 2, February 2016.

[0005] Some SOI-based photodetectors (PDs) use germanium as the light-absorbing layer. Si-Ge PDs are described, for example, in "Waveguide-Integrated Vertical Pin Photodiodes of Ge Fabricated on p+ and n+ Si-on-Insulator Layers" by Ito and Ishikawa, Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials, Tsukuba, Japan, 2016; and in "High-speed and high-power germanium photodetector with a lateral silicon nitride waveguide" by Hu et al., Photonics Research, Vol. 9, No. 5, May 2021.

[0006] The above description is presented as a general overview of the relevant technologies in this field, and none of the information contained herein should be interpreted as an acknowledgment of prior art to this patent application. [Overview of the Initiative]

[0007] One embodiment described herein provides an optical communication system including an optical waveguide and a photodetector (PD). The optical waveguide is arranged to receive and guide an optical signal. The PD is configured to receive an optical signal from the optical waveguide and convert the optical signal into an electrical signal. The PD includes a stack of layers including at least a first layer comprising two or more semiconductor layers configured to form a reverse-biased semiconductor junction configured to generate an electrical signal in response to an optical signal incident thereto, and a second layer forming a capacitive element connected in series with the reverse-biased semiconductor junction. The PD further includes a first electrode and a second electrode configured to (i) apply one or more voltages to reverse-bias the reverse-biased semiconductor junction and (ii) output an electrical signal.

[0008] In some embodiments, the first layer includes at least a silicon layer and a germanium layer. In some embodiments, the stack of layers is adapted for manufacturing by a complementary metal-oxide-semiconductor (CMOS) manufacturing process. In some embodiments, at least one of the layers in the stack belongs to both the first and second layers.

[0009] In some embodiments, the second layer forms a forward-biased semiconductor junction, and one or more voltages are set to bias both the forward-biased and reverse-biased semiconductor junctions. In exemplary embodiments, the optical communication system further includes a third electrode, which is connected between the forward-biased and reverse-biased semiconductor junctions and configured to apply an additional voltage to impose further bias on the forward-biased and reverse-biased semiconductor junctions.

[0010] In an alternative embodiment, the second layer includes at least one dielectric layer and at least one metal layer that form a capacitor.

[0011] In one embodiment, the layer stack includes an N-doped silicon layer; a P-doped silicon layer placed on or within the N-doped silicon layer; an intrinsic (I) germanium layer placed on the P-doped silicon layer; and an additional N-doped silicon layer placed on the germanium layer. In another embodiment, the layer stack includes a P-doped silicon layer; an N-doped silicon layer placed on or within the P-doped silicon layer; an intrinsic (I) germanium layer placed on the N-doped silicon layer; and an additional P-doped silicon layer placed on the germanium layer.

[0012] A method for manufacturing an optical communication system is further provided according to one embodiment described herein. The method includes arranging a photodetector (PD) on a substrate that converts optical signals into electrical signals. Arranging the PD includes arranging a stack of layers including at least (i) a first layer comprising two or more semiconductor layers that form a reverse-biased semiconductor junction configured to generate an electrical signal in response to an optical signal incident thereon, and (ii) a second layer that forms a capacitive element connected in series with the reverse-biased semiconductor junction. Arranging the PD further includes arranging a first electrode and a second electrode configured to (i) apply one or more voltages that reverse-bias the reverse-biased semiconductor junction, and (ii) output an electrical signal. An optical waveguide is arranged on the substrate to receive optical signals and guide them to the PD.

[0013] This disclosure will be better understood in conjunction with the drawings, from the detailed description of the embodiments below. [Brief explanation of the drawing]

[0014] [Figure 1] This is a schematic block diagram illustrating an optical communication system using a multi-junction PD according to one embodiment described herein.

[0015] [Figure 2] This is a three-dimensional view of a multi-junction PD used in the system shown in Figure 1, according to one embodiment described herein.

[0016] [Figure 3A] This is a cross-sectional view of a multi-junction PD according to an alternative embodiment described herein. [Figure 3B] This is a cross-sectional view of a multi-junction PD according to an alternative embodiment described herein. [Figure 4A] This is a cross-sectional view of a multi-junction PD according to an alternative embodiment described herein. [Figure 4B] This is a cross-sectional view of a multi-junction PD according to an alternative embodiment described herein. [Figure 5A] FIG. 3 is a cross-sectional view of a multi-junction PD in accordance with alternative embodiments described in the present specification. [Figure 5B] FIG. 3 is a cross-sectional view of a multi-junction PD in accordance with alternative embodiments described in the present specification. [Figure 6A] FIG. 3 is a cross-sectional view of a multi-junction PD in accordance with alternative embodiments described in the present specification. [Figure 6B] FIG. 3 is a cross-sectional view of a multi-junction PD in accordance with alternative embodiments described in the present specification.

[0017] [Figure 7A] FIG. 4 is a graph illustrating the simulated performance of a multi-junction PD compared to a conventional PIN PD in accordance with embodiments described in the present specification. [Figure 7B] FIG. 4 is a graph illustrating the simulated performance of a multi-junction PD compared to a conventional PIN PD in accordance with embodiments described in the present specification. [Figure 8A] FIG. 4 is a graph illustrating the simulated performance of a multi-junction PD compared to a conventional PIN PD in accordance with embodiments described in the present specification. [Figure 8B] FIG. 4 is a graph illustrating the simulated performance of a multi-junction PD compared to a conventional PIN PD in accordance with embodiments described in the present specification. [Figure 9A] FIG. 4 is a graph illustrating the simulated performance of a multi-junction PD compared to a conventional PIN PD in accordance with embodiments described in the present specification. [Figure 9B] FIG. 4 is a graph illustrating the simulated performance of a multi-junction PD compared to a conventional PIN PD in accordance with embodiments described in the present specification. [Mode for Carrying Out the Invention]

[0018] A photodetector (PD) is an electro-optical (EO) device that converts light into an electric current. In optical communication systems, PDs typically convert modulated optical signals into modulated electrical signals.

[0019] PDs can be implemented, for example, using reverse-biased positive-intrinsic-negative (PIN) or negative-intrinsic-positive (NIP) semiconductor junctions (i.e., PIN or NIP diodes). The intrinsic (I) layer of the junction is an optically active layer that absorbs photons, causing the instantaneous current across the junction to follow the instantaneous light intensity.

[0020] Reverse-biased junctions can be implemented using III-V materials such as GaAs, or using silicon-on-insulator (SOI) technology in which the intrinsic layer is made of germanium. Si-Ge PDs are often suitable for mass production applications because they are compatible with complementary metal-oxide-semiconductor (CMOS) manufacturing processes. Although this disclosure primarily refers to Si-Ge PDs, the disclosed techniques are also applicable to PDs implemented with any other suitable semiconductor material.

[0021] Two key performance metrics in PD design are bandwidth and responsiveness. Responsiveness is defined as the current generated by the PD per unit of optical input power.

[0022] The bandwidth of the PD depends on (i) the transit time of charge carriers in Ge, and (ii) the resistance-capacitance (RC) time constant of the junction. This dependency can be expressed as follows:

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[0023] As you can see, the bandwidth is limited by the time of travel.

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[0024] Another important trade-off concerns the length of the photodiode (PD). Longer junctions (up to the limit where all input light is absorbed) typically exhibit better responsiveness but have greater capacitance, on the other hand, reducing the PD bandwidth.

[0025] The embodiments described herein provide improved optical communication systems and improved PD designs for use in such systems, overcoming the conventional trade-off between responsiveness and bandwidth. The disclosed PDs exhibit broad bandwidth without degrading responsiveness.

[0026] In some embodiments, the disclosed PD includes a stack of layers arranged on a substrate. The stack includes at least the following: • "Layer 1" - for example, a Si-Ge junction of a PIN or NIP, which is a reverse-biased semiconductor junction that generates an electrical signal in response to an optical signal incident upon it. • "Second layer" (which may have at least one common layer with "First layer") - for example, a forward-biased PN or NP silicon junction connected in series with a reverse-biased semiconductor junction, which is a capacitive element.

[0027] The capacitive elements in the stack, combined with the capacitance of the reverse-biased junction, form a series capacitance that results in a low total capacitance and therefore a wide bandwidth.

[0028] When implemented using a forward-biased semiconductor junction, the voltage drop across the capacitive element is small, for example, 0.7V for silicon. In conventional PD designs, the only way to reduce PD capacitance is to shorten the PD, i.e., reduce the PD length. However, this shortening increases the RC-limited bandwidth of the PD. Shortening the PD length increases the resistance of the PD, which is highly undesirable. When using a forward-biased semiconductor junction in the disclosed embodiments, the total capacitance of the PD is reduced without the need to shorten the device. Therefore, the RC-limited bandwidth of the PD can be increased without any increase in PD resistance. Low resistance is highly desirable, for example, in communication systems where a high-gain transimpedance amplifier (TIA) follows the PD. In such configurations, a PD with low resistance is important to ensure low noise levels.

[0029] Furthermore, incorporating forward-biased junctions into the stack increases the gain of the photodiode.

[0030] In summary, the disclosed technology provides a photodiode (PD) exhibiting broadband, high responsiveness, high gain, and low resistance. The disclosed PD is fully compatible with CMOS manufacturing processes and is therefore easily integrated with other optical communication system elements. Multiple implementations of the disclosed PD are described herein. Simulated performance is also presented and compared with conventional PD performance.

[0031] Figure 1 is a schematic block diagram showing an optical communication system 20 using multi-junction PDs according to one embodiment described herein. In this example, system 20 receives a dual-polarized optical signal, for example, from an optical fiber. System 20 mixes the optical signal with a local oscillator (LO) signal and separates the resulting optical signal into four differential signal components, namely, an in-phase (I) component and a quadrature (Q) component for each polarization. The system then detects the four differential signal components using eight multi-junction PDs. The structure and operation of the multi-junction PDs are described in more detail below. The resulting eight electrical signals are amplified, digitized, and output for further processing.

[0032] In the example shown in Figure 1, the input optical signal is split into X-polarized ("X-pol") and Y-polarized ("Y-pol") signals by a polarizing beam splitter (PBS) 24. The X-pol and Y-pol signals are supplied to a pair of receiving circuits 26, each labeled "X-pol" and "Y-pol". The receiver 26 is also supplied with an optical LO signal generated by a laser diode 32 via a beam splitter (BS) 36.

[0033] Each receiver 26 includes a 90-degree hybrid mixer 28 that performs quadrature mixing between the optical signal (X-pol or Y-pol) and the LO signal. The mixer 28 outputs two differential signal components corresponding to the I and Q components of the optical signal (X-pol or Y-pol). Each differential signal component is output via a pair of optical waveguides 38. Two pairs of multi-junction PDs 40 receive the two differential signal components from the waveguides 38 and convert them into two differential electrical signals. A pair of differential transimpedance amplifiers (TIAs) 44 amplify the two differential electrical signals. A pair of analog-to-digital converters (ADCs) 48 digitize the two differential electrical signals. The resulting digitized signals are provided to a digital signal processor (DSP) 52 for further processing, such as filtering, demodulation, and so on.

[0034] The configuration of the optical communication system 20 shown in Figure 1 is an illustrative configuration illustrated for clarity only. In alternative embodiments, one or more multi-junction PD40s may be applied to any other suitable optical communication system. Non-limiting examples of optical systems (whether communication or not) that may include a PD40 include coherent and non-coherent optical communication systems, radiometric systems, photonics systems, microscopes, televisions and other remote control devices, laser printing systems, displays, optical data recording systems, optical power and flux measurement systems, vision scanners, security systems, and many others.

[0035] Various elements of System 20 can be implemented in a System-on-Chip (SoC) that integrates optical and electronic components using dedicated hardware such as discrete or integrated optical components, or using any other suitable technology.

[0036] Figures 3A, 3B, 4A, 4B, 5A, 5B, 6A, and 6B are cross-sectional views of multi-junction PDs according to alternative embodiments described herein. These exemplary PDs can be used, for example, as PD40 in system 20 of Figure 1, or in any other suitable system or device.

[0037] Figure 2 is a three-dimensional view of a multi-junction PD40 according to one embodiment described herein. The PD40 is placed on a substrate 56, which is typically made of silicon. In one embodiment, the substrate 56 includes a silicon base on which a 2-3 μm buried oxide layer is placed, and a 220 nm silicon layer is placed on the buried oxide. The PD40 includes a stack of multiple semiconductor layers placed on top of each other.

[0038] In the embodiment shown in Figure 2, the stack, from bottom to top (i.e., from the layer directly attached to the substrate 56 to the layer furthest from the substrate 56), includes the following layers: • N-doped silicon (Si) layer 64. P-doped Si layer 68. In this example, layer 68 is implemented as a P-doped region within layer 64. An alternative implementation is described below. • Intrinsic (I) germanium (Ge) layer 72. P-doped Si cap layer 76.

[0039] Furthermore, the PD40 includes two aluminum (Al) electrodes, namely, electrode 80 connected to layer 64 and electrode 84 connected to layer 76.

[0040] Light (e.g., a modulated optical signal) is coupled to the PD40 from an optical waveguide 38 laid on the substrate 56. The waveguide 38 has a tapered section 60 that couples the light to the layer 64. In one example implementation, the PD40 has the following dimensions: ·Overall width: 4μm~9μm. • Overall length: 5 μm to 30 μm. ·Layer thickness: layer 64-220nm; layer 68-220nm; layer 72-100nm~500nm; layer 76-50nm~100nm.

[0041] Alternatively, any other suitable dimensions can be used.

[0042] Figure 3A is a cross-sectional view of PD40 of Figure 2, focusing on the stack of layers 64, 68, 72, and 76 and the electrical bias using electrodes 80 and 84, according to one embodiment described herein.

[0043] In one embodiment, electrode 80 is connected to a predetermined voltage, for example, 0V, and electrode 84 is connected to a higher voltage, for example, 2V.

[0044] This bias causes layers 76, 72, and 68 to form a reverse-biased NIP junction; and layers 64 and 68 to form a forward-biased PN junction. The two junctions are shown in the figure using diodes. As can be seen, layer 68 is common to both junctions.

[0045] The reverse-biased NIP junctions (layers 76, 72, and 68) are configured to perform actual photodetection. The current generated by the photodetection is output through electrodes 80 and 84.

[0046] The forward-biased junctions (layers 64 and 68) function as capacitive elements connected in series with the reverse-biased NIP junction. The capacitance of the two junctions is shown as a capacitor in the figure.

[0047] By connecting the capacitors in series, the total capacitance of PD40 is smaller than that of the reverse-biased NIP junction alone. In various embodiments, the capacitance reduction ranges from 5% to 30%. Therefore, the bandwidth of PD40 is larger than that of the reverse-biased NIP junction alone. At the same time, the responsiveness of the reverse-biased NIP junction alone is not impaired.

[0048] Another important characteristic of the PD40 stems from the fact that the voltage drop across the forward-biased junctions (layers 64 and 68) is small, at 0.7 volts in this example. As mentioned above, this allows for a reduction in the capacitance of the PD and thus an increase in bandwidth without an undesirable increase in its resistance. Low resistance is important for reducing noise levels (especially in systems such as system 20, where the output of the PD40 is amplified by a high-gain TIA44).

[0049] Figure 3B is a cross-sectional view of a multi-junction PD according to an alternative embodiment described herein. The PD in Figure 3B is structurally similar to the PD in Figure 3A, but with the opposite doping polarity. In the PD in Figure 3B, the Si layer 64 is P-doped, the Si layer (region) 68 is N-doped, and the Si cap layer 76 is P-doped. In other words, the stack of layers in Figure 3A is a "NIPN" stack, while the stack of layers in Figure 3B is a "PINP" stack.

[0050] In the configuration shown in Figure 3B, the voltage applied to electrode 80 (e.g., 2V) is higher than the voltage applied to electrode 84 (e.g., 0V). This bias causes layers 76, 72, and 68 to form a reverse-biased PIN junction; layers 64 and 68 to form a forward-biased NP junction. The performance of this photodiode is substantially equivalent to that of the photodiode in Figure 3A.

[0051] Figure 4A is a cross-sectional view of a multi-junction PD according to another embodiment described herein. The PD in Figure 4A is structurally similar to the PD in Figure 3A, except that the Si layer 68 is a separate layer located on top of the Si layer 64, rather than being an inversely doped region within the layer 64. In this configuration, layer 68 is typically grown selectively on top of layer 64. Fabricating layer 68 as a separate layer may be simpler because doping of layer 68 is initiated from neutral silicon rather than from an inversely doped layer as in Figure 3A.

[0052] Figure 4B is a cross-sectional view of a multi-junction PD according to an alternative embodiment described herein. The PD in Figure 4B is structurally similar to the PD in Figure 4A, but with opposite doping polarity.

[0053] Figure 5A is a cross-sectional view of a multi-junction PD according to yet another embodiment described herein. The PD in Figure 5A is structurally similar to the PD in Figure 3A, except that an additional aluminum electrode 88 (labeled “base contact”) is added. The electrode 88 is configured to apply an adjustable voltage to the Si layer 68. This adjustable voltage can be used to better control the voltage drop across the reverse-biased junctions (layers 76, 72, and 68) and the forward-biased junctions (layers 64 and 68). By adjusting the base voltage applied to the electrode 88, the gain and bandwidth of the PD can be adjusted.

[0054] Figure 5B is a cross-sectional view of a multi-junction PD according to an alternative embodiment described herein. The PD in Figure 5B is structurally similar to the PD in Figure 5A, but with opposite doping polarity.

[0055] Figure 6A is a cross-sectional view of a multi-junction PD according to another embodiment described herein. The PD in Figure 6A is structurally similar to the PD in Figure 5A, except that the Si layer 68 is a separate layer selectively grown on top of the Si layer 64.

[0056] Figure 6B is a cross-sectional view of a multi-junction PD according to an alternative embodiment described herein. The PD in Figure 6B is structurally similar to the PD in Figure 6A, but with opposite doping polarity.

[0057] The PD configurations shown in Figures 3A, 3B, 4A, 4B, 5A, 5B, 6A, and 6B are illustrative configurations shown for conceptual clarity only. In alternative embodiments, any other suitable configuration may be used.

[0058] For example, in an alternative embodiment, the forward-biased junction of the PD may be replaced by any other suitable structure of one or more layers forming a capacitive element. For instance, the PD may include at least one dielectric layer and at least one metal layer forming a capacitor (instead of the forward-biased junction). Such layers may be placed on top of the reverse-biased junction.

[0059] As another example, the PD configuration described is vertically stacked and uses vertical doping. In an alternative embodiment, the PD according to the disclosed technique may also be manufactured using lateral doping, resulting in a stack of layers orthogonal to the substrate 56.

[0060] In various embodiments, the various photodiodes (PDs) shown in Figures 3A, 3B, 4A, 4B, 5A, 5B, 6A, and 6B can be manufactured using various processes. Typically, the various layers within a stack of PDs are epitaxially grown on top of each other. The manufacturing process is typically adapted to a CMOS process and can be carried out in a CMOS fab.

[0061] Figures 7A, 7B, 8A, 8B, 9A, and 9B are graphs showing the simulated performance of multi-junction PDs according to the embodiments described herein compared to conventional PIN PDs. The vertical axis in the figures represents performance metrics such as responsiveness, dark current, photocurrent, and gain. The horizontal axis in all figures represents the bias voltage across the reverse-biased junctions (layers 76, 72, and 68), i.e., the bias between electrodes 80 and 84. The forward-biased junction accounts for only about 0.7V of the total bias.

[0062] Figures 7A and 7B compare the responsiveness of the disclosed multi-junction PD (Figure 7B) with that of a comparable conventional PD (Figure 7A). Figures 8A and 8B compare the dark current and photocurrent of the disclosed multi-junction PD (Figure 8B) with that of a comparable conventional PD (Figure 8A). In Figure 8A, plots 92 and 96 show the photocurrent and dark current, respectively, for the conventional PD. In Figure 8B, plots 100 and 104 show the photocurrent and dark current, respectively, for the disclosed multi-junction PD.

[0063] As can be seen, the responsiveness, dark current, and photocurrent are similar within the normal operating range (voltage bias between -1 volt and -6 volt). However, the capacitance of the disclosed multi-junction PD is approximately 18% smaller than that of the conventional PD in this example. This capacitance difference translates to an 18% increase in bandwidth.

[0064] Because the forward-biased junction subtracts 0.7 volts from the overall bias, the "knee" point in the PD response occurs at a slightly higher voltage in multi-junction PDs.

[0065] Figures 9A and 9B compare the gain of the disclosed multi-junction PD (Figure 9B) with that of an equivalent conventional PD (Figure 9A). The gain is defined as follows:

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[0066] As can be seen, the disclosed multi-junction PD (Figure 9B) exhibits a gain of approximately 6 times, while the conventional PD (Figure 9A) exhibits a gain of approximately 1, i.e., no gain. This increase in gain is due to the increase in bandwidth, as mentioned above.

[0067] Although the embodiments described herein primarily concern PDs in optical communication systems, the methods and systems described herein can also be used in other applications, such as lidar systems, avalanche PDs, and others.

[0068] It should be noted that the embodiments described above are cited as examples, and the present invention is not limited to those specifically shown and described above. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described above, as well as variations and modifications thereof not disclosed in the prior art, which a person skilled in the art, having read the foregoing description, would conceive. Documents incorporated by reference in this patent application should be considered an integral part of the application, but to the extent that any term is defined in such incorporated documents in a manner that contradicts the definitions made expressly or implicitly herein, only the definitions herein should be considered.

Claims

1. An optical waveguide arranged to receive and guide optical signals; and, A photodetector (PD) configured to receive the optical signal from the optical waveguide and convert the optical signal into an electrical signal. The PD is equipped with, at least, A first layer comprising two or more semiconductor layers that form a reverse-biased semiconductor junction configured to generate the electrical signal in response to the optical signal incident thereon; and, A second layer forming a capacitive element connected in series with the reverse-biased semiconductor junction. A stack of layers including; and, (i) Applying one or more voltages to reverse bias the reverse-biased semiconductor junction, and (ii) First and second electrodes configured to output the electrical signal. An optical communication system having [a certain feature].

2. The optical communication system according to claim 1, wherein the first layer comprises at least a silicon layer and a germanium layer.

3. The optical communication system according to claim 1, wherein the stack of the layers is suitable for manufacturing by a complementary metal-oxide-semiconductor (CMOS) manufacturing process.

4. The optical communication system according to claim 1, wherein at least one of the layers in the stack belongs to both the first layer and the second layer.

5. The optical communication system according to any one of claims 1 to 4, wherein the second layer forms a forward-biased semiconductor junction, and the one or more voltages are set to bias both the forward-biased semiconductor junction and the reverse-biased semiconductor junction.

6. The optical communication system according to claim 5, further comprising a third electrode connected between the forward-biased semiconductor junction and the reverse-biased semiconductor junction, configured to apply an additional voltage to apply further bias to the forward-biased semiconductor junction and the reverse-biased semiconductor junction.

7. The optical communication system according to any one of claims 1 to 4, wherein the second layer includes at least one dielectric layer and at least one metal layer that form a capacitor.

8. The stack of the aforementioned layers N-doped silicon layer; A P-doped silicon layer disposed on or within the aforementioned N-doped silicon layer; An intrinsic (I) germanium layer disposed on the P-doped silicon layer; and An additional N-doped silicon layer is placed on the germanium layer. An optical communication system according to any one of claims 1 to 4, including the above.

9. The stack of the aforementioned layers P-doped silicon layer; An N-doped silicon layer disposed on or within the P-doped silicon layer; An intrinsic (I) germanium layer disposed on the N-doped silicon layer; and An additional P-doped silicon layer is placed on the germanium layer. An optical communication system according to any one of claims 1 to 4, including the above.

10. A method for manufacturing an optical communication system, wherein the manufacturing method is: In the step of placing a photodetector (PD) that converts optical signals into electrical signals on a substrate, at least, A first layer comprising two or more semiconductor layers that form a reverse-biased semiconductor junction configured to generate the electrical signal in response to the optical signal incident thereon; and A second layer forming a capacitive element connected in series with the reverse-biased semiconductor junction. A stack of layers including; and (i) Applying one or more voltages to reverse bias the reverse-biased semiconductor junction, and (ii) First and second electrodes configured to output the electrical signal. A step having the step of arranging; and The step of arranging an optical waveguide on the substrate for receiving the optical signal and guiding it to the PD. A manufacturing method that includes the following features.

11. The manufacturing method according to claim 10, wherein the step of arranging the first layer includes a step of arranging at least a silicon layer and a germanium layer.

12. The manufacturing method according to claim 10, wherein the step of arranging the stack of the aforementioned layers is performed in a complementary metal-oxide-semiconductor (CMOS) manufacturing process.

13. The manufacturing method according to claim 10, wherein at least one of the layers in the stack belongs to both the first layer and the second layer.

14. The manufacturing method according to any one of claims 10 to 13, wherein the step of arranging the second layer includes the step of forming a forward-biased semiconductor junction, and the one or more voltages bias both the forward-biased semiconductor junction and the reverse-biased semiconductor junction.

15. The manufacturing method according to claim 14, further comprising the step of arranging a third electrode connected between the forward-biased semiconductor junction and the reverse-biased semiconductor junction for applying an additional voltage to apply further bias to the forward-biased semiconductor junction and the reverse-biased semiconductor junction.

16. The manufacturing method according to any one of claims 10 to 13, wherein the step of arranging the second layer includes the step of arranging at least one dielectric layer and at least one metal layer that form a capacitor.

17. The step of arranging the stack of the aforementioned layers is, The step of placing an N-doped silicon layer on the substrate; The step of placing a P-doped silicon layer on or within the N-doped silicon layer; The step of placing an intrinsic (I) germanium layer on the P-doped silicon layer; and The step of placing an additional N-doped silicon layer on the germanium layer. A manufacturing method according to any one of claims 10 to 13, including the method described in any one of claims 10 to 13.

18. The step of arranging the stack of the aforementioned layers is, The step of placing a P-doped silicon layer on the substrate; The step of placing an N-doped silicon layer on or within the P-doped silicon layer; The step of placing an intrinsic (I) germanium layer on the N-doped silicon layer; and The step of placing an additional P-doped silicon layer on the germanium layer. A manufacturing method according to any one of claims 10 to 13, including the method described in any one of claims 10 to 13.

19. The manufacturing method according to any one of claims 10 to 13, wherein the step of arranging the stack of the layers includes a step of growing the layers epitaxially on top of each other.

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