Driver circuits, display devices, and electronic devices

Abstract

A driver circuit for driving a radiating semiconductor device (LD) comprises a first current path including a series connection of a first transistor (Msw) and a second transistor (Mx). The source terminal of the first transistor (Msw) is coupled to a first reference potential terminal (VDDA), the gate terminal of the first transistor (Msw) is coupled to a second reference potential terminal (VSSA), and the drain and gate terminals of the second transistor (Mx) are commonly coupled to the second reference potential terminal (VSSA) via a current source. The radiating semiconductor device (LD) is connectable between a first output terminal and a second output terminal (OT1, OT2), the second output terminal (OT2) being coupled to a second reference potential terminal (VSSA). The second current path includes a series connection of a third transistor (Msw') and a fourth transistor (Mx'). The source terminal of the third transistor (Msw') is coupled to the first reference potential terminal (VDDA), the gate terminal of the fourth transistor (Mx') is coupled to the gate terminal of the second transistor (Mx), and the drain terminal of the fourth transistor (Mx') is coupled to the first output terminal (OT1). A control terminal (CIN) for supplying a control signal to control the current through the second current path is coupled to the gate terminal of the third transistor (Msw').

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a driver circuit for driving a radiation-emitting semiconductor device. The present disclosure further relates to a display apparatus including such a driver circuit and an electronic apparatus including such a display apparatus.

[0002] RELATED APPLICATIONS This patent application claims the priority of German Patent Application Nos. 102023128919.5 and 102023135940.1, the disclosures of which are incorporated herein by reference in their entirety. BACKGROUND ART

[0003] Radiation-emitting semiconductor devices, such as LEDs or laser diodes, are sensitive with respect to the actual color of the emitted radiation depending on the energy supplied to them. This is particularly true for short radiation pulses, which are used for example when a plurality of devices are combined in a display.

[0004] For accurate color, it is necessary to minimize energy fluctuations in the red, green, or blue light pulses. In high-speed drivers for wearable devices, parasitic charge injection into the output current pulses of the driver can cause significant fluctuations in light pulse energy, especially under low-luminance or dark color conditions. In such cases, the color definition of the displayed pixels is highly dependent on the variations of the red, green, and blue light pulse components. Furthermore, high current spikes can cause EMC (Electromagnetic Compatibility) issues and inter-channel crosstalk in multi-channel systems.

[0005] In conventional solutions, this problem is addressed by current steering techniques, which however have high power consumption even at low luminance emission. Therefore, they cannot be efficiently used for low power consumption applications. SUMMARY OF THE INVENTION

[0006] The objective to be achieved is to provide an improved driver concept that enables more efficient driving of radiant semiconductor devices.

[0007] This objective is achieved by the subject matter of the independent claim. Embodiments and variations are derived from the dependent claims.

[0008] The improved driver concept is based on the idea that current modulation can be performed by a switch, such as a transistor located on the source terminal side of the current mirror transistor, in contrast to the conventional solution where the switch is located on the drain terminal side of the current mirror transistor. Furthermore, a discharge switch can be used to rapidly stop the current flowing through the current mirror transistor.

[0009] For example, according to the improved driver concept, a current source or current sink is used to supply current to a radiating semiconductor device. A switch at the source terminal of the current mirror transistor indirectly provides current feedback that acts to reduce high instantaneous current spikes at the driver output. Furthermore, placing the switch at the source reduces other switch-related effects that are related to the power supply rather than the load.

[0010] In an exemplary implementation of a driver circuit for driving an emitting semiconductor device using an improved driver concept, the driver circuit comprises a first and a second current path. The first current path includes a series connection of a first transistor and a second transistor. The source terminal of the first transistor is coupled to a first reference potential terminal, the gate terminal of the first transistor is coupled to a second or third reference potential terminal, and the drain and gate terminals of the second transistor are commonly coupled to the second reference potential terminal via a current source. The driver circuit further comprises a first output terminal and a second output terminal for which an emitting semiconductor device is connected, the second output terminal being coupled to a second or further reference potential terminal. The emitting semiconductor device may or may not be included in the driver circuit.

[0011] The second current path includes a series connection of a third transistor and a fourth transistor. The source terminal of the third transistor is coupled to the first reference potential terminal, the gate terminal of the fourth transistor is coupled to the gate terminal of the second transistor, and the drain terminal of the fourth transistor is coupled to the first output terminal. The driver circuit further includes a control terminal for supplying a control signal to control the current through the second current path, and the control terminal is coupled to the gate terminal of the third transistor. For example, the fourth transistor is the current mirror transistor described above.

[0012] Control via the third transistor results in inherent overcurrent control through feedback, for example, in that large instantaneous currents each reduce the gate-source voltage of the fourth transistor (i.e., the current mirror transistor), thereby reducing the current overshoot present in conventional approaches.

[0013] In some implementations, the driver circuit further includes a discharge potential terminal and a discharge switch, the discharge switch connected between the discharge potential terminal and a common connection point of a third and a fourth transistor, and the discharge switch is configured to be controlled based on a control signal. For example, the common connection point of the third and fourth transistors is formed by the drain terminal of the third transistor and the source terminal of the fourth transistor. During the operation of the driver circuit, the third transistor and the discharge switch are mutually exclusive in conduction; that is, the discharge switch is closed when the third transistor is not conducting, and vice versa.

[0014] The potential at the discharge potential terminal is lower than, for example, the potential obtained by adding or subtracting the threshold voltage of the fourth transistor from the potential at the gate terminal of the fourth transistor. For example, if the fourth transistor is a p-channel type, the potential at the discharge potential terminal is lower than the potential obtained by adding the threshold voltage of the fourth transistor. In a complementary implementation where the fourth transistor is an n-channel type, the potential at the discharge potential terminal is lower than, for example, the potential obtained by subtracting the threshold voltage of the fourth transistor from the potential at the gate terminal of the fourth transistor.

[0015] The discharge switch addresses the problem of a long switch-off time, for example, because the common connection of the third and fourth transistors may discharge slowly and appear as a long current tail. The discharge switch further ensures that the charge from the common connection of the third and fourth transistors is removed by an alternative path, lowering the potential at the connection to a level sufficient to deconduct the fourth transistor and thus stop the current.

[0016] In some implementations, a capacitive element is connected between the discharge potential terminal and the first reference potential terminal. This capacitive element provides intermediate storage of charge from the common connection of the third and fourth transistors, which can then be slowly removed.

[0017] In some implementations, the discharge potential terminal is coupled to a first reference potential terminal via a level shifter.

[0018] For example, the driver circuit further includes an additional current path, which includes a series connection of a fifth transistor and a sixth transistor. The source terminal of the fifth transistor is coupled to the first reference potential terminal, the gate terminal of the fifth transistor is coupled to the second reference potential terminal, and the drain and gate terminals of the sixth transistor are commonly coupled to the second reference potential terminal via an additional current source. The level shifter is formed from the path from the source terminal of the fifth transistor to the gate terminal of the sixth transistor. A dedicated additional current path, which may have essentially the same configuration as the first current path, allows for the isolation of the discharge potential terminal from the first current path while achieving matched operation.

[0019] In some implementations, the discharge potential terminal is coupled to the gate terminal of the second transistor. For example, the discharge potential terminal is directly connected to the gate terminal of the second transistor.

[0020] In some implementations, the driver circuit further comprises a voltage buffer having an input connected to the gate terminal of a second transistor and an output connected to the gate terminal of a fourth transistor, and an additional capacitive element connected between the first reference potential terminal and the output of the voltage buffer. The voltage buffer allows, for example, a reduction in feedback from the fourth transistor to the second transistor.

[0021] In such an implementation, the discharge potential terminal may be directly connected, for example, to the output of a voltage buffer. Alternatively, such an implementation may be combined with an exemplary implementation having the further current paths disclosed above, where a portion of the further current paths forms a level shifter.

[0022] In some implementations, the discharge switch is implemented as a transistor of the same channel type as the third transistor, the third transistor is controlled using a control signal, and the discharge switch is controlled using a complementary version of the control signal. The control signal and its complementary version are, for example, non-overlapping.

[0023] For example, the driver circuit includes a circuit for generating a complementary version of the control signal from the control signal.

[0024] In some alternative implementations, the discharge switch is implemented as a transistor of a channel type complementary to the channel type of the third transistor. Here, the third transistor and the discharge switch are controlled using a control signal.

[0025] In some further alternative implementations, the discharge switch is implemented as a transistor of a channel type complementary to the channel type of the third transistor, and the third transistor and the discharge switch are controlled using a control signal. The gate terminal of the first transistor is coupled to the third reference potential terminal, the discharge potential terminal is connected to the third reference potential terminal, and the third transistor and the discharge switch are designed to operate at a lower voltage compared to the second transistor and the fourth transistor.

[0026] When the radiation-emitting semiconductor device requires a large voltage supply, controlling the transistor switch from a low voltage (LV) domain implies the use of a control signal level shifter. Therefore, such implementations that avoid a level shifter for control signals can be useful in high-speed applications.

[0027] The improved driver concept provides an implementation with two voltage supplies, where the third transistor and the LV device of the discharge switch are controlled from the LV domain, and the radiation-emitting semiconductor device is supplied from a high voltage (HV) power supply. As an effect, the LV switches provide lower resistance than their HV counterparts would be able to achieve. The control signals are supplied directly from the LV domain, mitigating the need for control signal level shifting.

[0028] In all the implementations described above, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth and sixth transistors if present, may be of the same channel type. For example, when the voltage at the first reference potential terminal is a positive voltage, particularly more positive than the voltage at the second reference potential terminal, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth and sixth transistors if present, can be implemented as p-channel transistors. On the other hand, when the voltage at the first reference potential terminal is more negative than the voltage at the second reference potential terminal, the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth and sixth transistors if present, can be implemented as n-channel transistors.

[0029] In some implementations, the driver circuit further comprises a dummy switch device connected to the common connection of the third transistor and the fourth transistor. For example, the dummy switch device can handle residual overshoot caused by charge injection or feedthrough of the third transistor. The use of the dummy switch device can be more effective, as the common connection of the third transistor and the fourth transistor is maintained by the fourth transistor, and the switching effect of the third transistor can be compensated more efficiently.

[0030] The dummy switch device is implemented, for example, with a transistor of the same channel type as the third transistor, whose source terminal and drain terminal are commonly connected to the common connection of the third transistor and the fourth transistor, and whose gate terminal is controlled by a complementary version of the control signal.

[0031] As described above, the light-emitting semiconductor device may or may not be included in the driver circuit. Accordingly, in some implementations, the driver circuit further includes a light-emitting semiconductor device connected between the first output terminal and the second output terminal.

[0032] The improved driver concept further provides a display device comprising multiple driver circuits according to any of the above implementations, where the driver circuit further comprises an emitting semiconductor device connected between a first output terminal and a second output terminal. For example, the emitting semiconductor device can be of different colors, such as red, green, or blue, without excluding other color combinations, and a set of driver circuits having each emitting semiconductor device can be used to represent a controllable color pixel, etc. A set may include multiple driver circuits having emitting semiconductor devices of the same color. For example, a display device may include multiple such sets to form a 2D display.

[0033] For example, radiant semiconductor devices (such as LEDs) directly form the pixels of a display.

[0034] The display device can be implemented as a lighting module. For example, the lighting module may be combined with other components, such as a MEMS mirror that scans and reflects the light emitted from the lighting module onto a screen, and the MEMS mirror is movable.

[0035] The improved driver concept further provides electronic devices including display or lighting modules, implemented in one of the ways described above. These electronic devices could be, to name a few examples, head-mounted displays, augmented reality (AR) wearable devices, or pico projectors.

[0036] Driver circuits based on the improved driver concept can be used in applications such as high-speed optical communications, optical pulse generators, laser projection systems, head-up displays, and LiDAR, to name a few examples.

[0037] In the improved driver concept, parasitic charge injection is kept under control by feedback, thus significantly improving control over optical pulse energy and pixel color. Furthermore, the improved driver concept yields the following additional effects: - For example, high-speed current switching capability at 200MHz can be maintained with low power consumption and low headroom voltage. - The chip area can be used efficiently. - To better control the total charge supplied to a light source, such as a laser, current spikes caused by parasitic components can be reduced. - The di / dt, which affects cross-coupling and EMC compliance in multi-channel implementations, can be reduced. -By ensuring high output current while reducing the switch size through a large gate-source voltage swing, the silicon area can be minimized.

[0038] The improved driver concept can be widely applied to applications such as pulse amplitude driving (PAM), laser (EEL, VCSEL) and LED driving, or resistive loads.

[0039] The improved driver concept is described in more detail below with reference to the drawings. Elements and functional blocks with the same or similar functions are given the same reference numerals throughout the drawings. Therefore, their descriptions are not necessarily repeated in subsequent drawings. [Brief explanation of the drawing]

[0040] [Figure 1] An illustrative block diagram of the driver circuit is shown. [Figure 2] Further illustrative block diagrams of the driver circuit are shown. [Figure 3] Further illustrative block diagrams of the driver circuit are shown. [Figure 4] An illustrative block diagram of a dummy switch device is shown. [Figure 5]Further illustrative block diagrams of the driver circuit are shown. [Figure 6] Further illustrative block diagrams of the driver circuit are shown. [Figure 7] Further illustrative block diagrams of the driver circuit are shown. [Figure 8] Further illustrative block diagrams of the driver circuit are shown. [Figure 9] Further illustrative block diagrams of the driver circuit are shown. [Figure 10] Further illustrative block diagrams of the driver circuit are shown. [Figure 11] Further illustrative block diagrams of the driver circuit are shown. [Figure 12] This shows illustrative timing diagrams of signals in various implementations of the driver circuit. [Figure 13] An exemplary implementation of the display device is shown. [Figure 14] Figure 13 shows an example implementation of an electronic device equipped with a display device. [Modes for carrying out the invention]

[0041] Figure 1 shows an exemplary implementation of a driver circuit according to an improved driver concept for driving a radiant semiconductor device (LD). The driver circuit includes a first current path coupled between a first reference potential terminal VDDA and a second reference potential terminal VSSA. The first current path includes a series connection of a first transistor Msw and a second transistor Mx. The source terminal of the first transistor Msw is coupled to the first reference potential terminal VDDA, the gate terminal of the first transistor Msw is coupled to the second reference potential terminal VSSA, and the drain and gate terminals Vgx of the second transistor Mx are commonly coupled to the second reference potential terminal VSSA via a current source CS1. The drain terminal of the first transistor Msw and the source terminal of the second transistor Mx are connected.

[0042] The driver circuit further includes a second current path, which includes a series connection of a third transistor Msw' and a fourth transistor Mx'. The source terminal of the third transistor Msw' is coupled to a first reference potential terminal VDDA, the gate terminal of the fourth transistor Mx' is coupled to the gate terminal of the second transistor Mx, and the drain terminal of the fourth transistor Mx' is coupled to a first output terminal OT1. The second output terminal OT2 is connected to a second reference potential terminal VSSA. A radiating semiconductor device LD, which is not necessarily part of the driver circuit, is connected between the first output terminal OT1 and the second output terminal OT2. The drain terminal of the third transistor Msw' and the source terminal of the fourth transistor Mx' are connected by a common connection nsx.

[0043] The driver circuit further includes a control terminal CIN for supplying a control signal to control the current through the second current path, and therefore the current through the emitting semiconductor device LD. The control terminal CIN is coupled to the gate terminal of a third transistor Msw'.

[0044] In the driver circuit of Figure 1, the fourth transistor Mx' functions as a current mirror transistor for the second transistor Mx. Placing the third transistor Msw' on the source terminal side of the fourth transistor Mx' indirectly provides current feedback that acts to reduce high instantaneous current spikes at the driver output. Furthermore, placing the switch Msw' on the source side reduces other switch-related influences that are related to the power supply rather than the load.

[0045] Figure 2 shows a further illustrative implementation of the driver circuit, which is an evolution of the driver circuit shown in Figure 1. Therefore, only the differences will be explained in more detail.

[0046] The driver circuit further comprises a discharge potential terminal Vr and a discharge switch DQSW, the discharge switch DQSW being connected between the discharge potential terminal Vr and the common connection nsx of the third transistor Msw' and the fourth transistor Mx'. The discharge switch DQSW is controlled based on a control signal supplied to the control input CIN. During operation of the driver circuit, the third transistor Msw' and the discharge switch DQSW are mutually exclusive in conduction; that is, when the third transistor Msw' is not conducting, the discharge switch DQSW is closed, and vice versa.

[0047] The potential of the discharge potential terminal Vr is lower than, for example, the potential obtained by adding the threshold voltage of the fourth transistor Mx' to the potential of the gate terminal of the fourth transistor Mx' when the fourth transistor Mx' is a p-channel type. In a complementary implementation where the transistor is an n-channel type, the potential of the discharge potential terminal Vr is lower than, for example, the potential obtained by subtracting the threshold voltage of the fourth transistor Mx' from the potential of the gate terminal of the fourth transistor Mx'. Such a complementary implementation is described below with reference to Figure 11.

[0048] The discharge switch DQSW addresses the problem of extended switch-off time, for example, because the connection nsx may discharge slowly and manifest as a long current tail. The discharge switch DQSW further ensures that the charge from the connection nsx is removed by an alternative path, lowering the potential of the connection to a level sufficient to deconduct the fourth transistor Mx', and thus the current ILD can be stopped.

[0049] Figure 3 shows a further exemplary implementation of the driver circuit based on the exemplary implementation shown in Figure 2. Here, the driver circuit further includes a level shifter VQ connected between a first reference potential terminal VDDA and a discharge potential terminal Vr. Furthermore, a capacitive element CBFR is connected between the discharge potential terminal Vr and the first reference potential terminal VDDA. The capacitive element CBFR may provide intermediate storage for charge from the connection nsx.

[0050] The level shifter VQ provides the desired potential at the discharge potential terminal Vr during operation.

[0051] To perform mutually exclusive closing of the third transistor Msw' and the discharge switch DQSW, the clocking circuit generates a first control signal Φ and a second control signal which is a complementary version of the first control signal Φ, based on the control signal supplied to the control input CIN.

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[0052] The clocking circuit may receive voltage potentials from a first reference potential terminal VDDA and a second reference potential terminal VSSA, thereby applying the same potential to the gate terminals of the first transistor Msw and the third transistor Msw', particularly when controlling the third transistor Msw' to conduct at the potential of the second reference potential terminal VSSA. In some slightly different implementations, instead of the second reference potential terminal VSSA, a third reference potential terminal may be provided, connected to the gate terminal of the first transistor Msw and supplying power to the clocking circuit. In such implementations as well, the same potential is applied to the gate terminals of the first transistor Msw and the third transistor Msw', particularly when controlling the third transistor Msw' to conduct. For example, the voltage potential of the third reference potential terminal is between the voltage potential of the first reference potential terminal VDDA and the voltage potential of the second reference potential terminal VSSA.

[0053] Optionally, the driver circuit further includes an additional capacitive element CBFX connected between the first reference potential terminal VDDA and the gate terminal Vgx of the second transistor Mx, which stabilizes the potential of the gate terminal Vgx, for example.

[0054] The driver circuit in Figure 3 further includes an optional dummy switch device DYSW connected to the common junction nsx. For example, the dummy switch device DYSW may handle residual overshoot due to charge injection or feedthrough of the third transistor Msw'. The use of the dummy switch device DYSW may be more effective because the junction nsx is held by the fourth transistor Mx', which can more efficiently compensate for the switching effect of the third transistor Msw'. Nevertheless, the presence of the dummy switch device DYSW in this implementation example and the implementation examples below is optional.

[0055] Referring to Figure 4, the dummy switch device DYSW is implemented, for example, with a transistor of the same channel type as the third transistor Msw', its source and drain terminals are commonly connected to the common connection part nsx, and its gate terminal is connected to the second control signal.

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[0056] Figure 5 shows a further exemplary implementation of the driver circuit, which is an evolution of the implementation described above, particularly the implementation in Figure 3. In this exemplary implementation, the driver circuit further includes an additional current path, which includes a series connection of a fifth transistor Mswr and a sixth transistor Mr. The source terminal of the fifth transistor Mswr is coupled to the first reference potential terminal VDDA, the gate terminal of the fifth transistor Mswr is coupled to the same reference potential terminal as the gate of the first transistor Msw, i.e., the second reference potential terminal VSSA in this example, and the drain and gate terminals of the sixth transistor MR are commonly coupled to the second reference potential terminal VSSA via an additional current source CS2. The gate terminal of the sixth transistor Mr is connected to the discharge potential terminal Vr.

[0057] The level shifter VQ, explained in relation to Figure 3, is formed here from the source terminal of the fifth transistor Mswr to the gate terminal of the sixth transistor Mr. A dedicated additional current path, which can have essentially the same configuration as the first current path, makes it possible to isolate the discharge potential terminal Vr from the first current path while achieving matched operation.

[0058] Figure 6 shows a further exemplary implementation of the driver circuit, which is an evolution of the implementation described above, particularly the implementation in Figure 3. In this example implementation, the driver circuit further includes a voltage buffer BUF whose input is connected to the gate terminal Vgx of a second transistor Mx and whose output is connected to the gate terminal of a fourth transistor Mx'. In this exemplary implementation, the voltage buffer BUF is formed from a differential amplifier in a voltage follower configuration, with the first input connected to the gate terminal Vgx and the second input connected to the output of the differential amplifier.

[0059] Here, the discharge potential terminal Vr is formed from the output of the voltage buffer BUF.

[0060] The voltage buffer allows for, for example, reducing feedback from the fourth transistor Mx' and / or the discharge switch DQSW to the second transistor Mx.

[0061] Figure 7 shows a further exemplary implementation of the driver circuit, which is an evolution of the above implementation, for example, a combination of the implementations in Figures 5 and 6.

[0062] In the exemplary implementation shown in Figure 7, a further current path exists in the driver circuit having transistors Mswr and Mr, as described in connection with Figure 5, which provides a voltage to the discharge potential terminal Vr. Furthermore, the driver circuit includes a voltage buffer BUF, as described in connection with Figure 6, whose input is connected to the gate terminal Vgx of a second transistor Mx and whose output is connected to the gate terminal of a fourth transistor Mx'. Here, the voltage buffer BUF simply buffers the voltage at the gate terminal Vgx and provides it to the gate terminal Vgx' of the fourth transistor Mx'.

[0063] Figure 8 shows a further exemplary implementation of the driver circuit, which is an evolution of the implementation in Figure 3. In this exemplary implementation, the discharge potential terminal Vr is formed from or directly connected to the gate terminal Vgx. Thus, a simple and efficient implementation is achieved.

[0064] Figure 9 shows a further exemplary implementation of the driver circuit, which is an evolution of the implementation in Figure 8. In this exemplary implementation, the discharge switch DQSW is implemented with an n-channel transistor, which is complementary to the channel type of the other transistor, which is a p-channel transistor. Thus, mutually exclusive conduction can be achieved using the same control signal for both the discharge switch DQSW and the third transistor Msw'. As a result, no circuit is required to generate complementary control signals. The discharge switch DQSW can be a native n-channel transistor or a depleted n-channel transistor.

[0065] Figure 10 shows a further exemplary implementation of the driver circuit, which is an evolution of the implementation in Figure 3. In this exemplary implementation, the radiating semiconductor device LD is powered, for example, from a high-voltage (HV) power supply, while the first and third transistors Msw, Msw' and the discharge switch DQSW are controlled from a low-voltage LV domain. Thus, as in the implementation example described above, the second reference potential terminal VSSA is used. However, in this exemplary implementation, the low-voltage first reference potential terminal VDDA_LV is used. Furthermore, the gate terminal of the first transistor Msw is connected to the third reference potential terminal VSSA_LV, which is also in the LV domain. In addition, the discharge switch DQSW is connected to the third reference potential terminal VSSA_LV as the discharge terminal.

[0066] In some implementations based on the example in Figure 10, the second output terminal OT2 is coupled to a further reference potential terminal, which receives a further voltage potential that is negative with respect to the voltage potential at the second reference potential terminal VSSA. Such a further voltage potential may be provided by an external power supply circuit. The voltage potential at the second reference potential terminal VSSA may be generated internally by the corresponding circuit. For example, both the voltage potential at the second reference potential terminal VSSA and the further voltage potential may be negative with respect to the main ground potential.

[0067] Since the third transistor Msw' and the discharge switch DQSW are complementary channel types, mutually exclusive conduction can be achieved using the same control signal provided to the control input CIN.

[0068] In the implementation described above, the first, second, third, and fourth transistors, as well as the fifth and sixth transistors, if present, are of the same channel type, specifically p-channel type. However, the improved driver concept also allows for the use of complementary implementations in which the first, second, third, and fourth transistors, as well as the fifth and sixth transistors, if present, are n-channel type.

[0069] For example, Figure 11 shows an exemplary implementation of a driver circuit using an n-channel transistor, which is based on the implementation shown in Figure 3, but with the channel type and voltage supply reversed, as will be apparent to those skilled in the art from a comparison of the two.

[0070] Figure 12 shows examples of signal timing diagrams in various implementations of the driver circuit. For example, the top of the figure shows the first control signal Φ and the second control signal.

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[0071] Figure 13 shows an exemplary implementation of a display device 1300 having multiple driver circuits as described above. For example, one or more sets of driver circuits, each having a different emitting semiconductor device, are included in the display device 1300, as indicated by the dashed boxes. In the example shown, such a set includes, for example, three driver circuits B1, B2, and B3 designed for blue light emission, a driver circuit R designed for red light emission, and a driver circuit G designed for green light emission, which together enable the emission of controllable colors. The number of colors in a set and the number of sets in the display device should not be limited by this example.

[0072] For example, a radiant semiconductor device, such as an LED, directly forms the pixels of the display of the display device 1300.

[0073] The display device 1300 can be implemented as a lighting module. For example, the lighting module can be combined with other components such as a MEMS mirror that reflects light emitted from the lighting module onto a screen in a scanning manner, and the MEMS mirror is movable.

[0074] Figure 14 shows an exemplary implementation of the electronic device 1400, which includes the display device 1300 or lighting module described above. Such an electronic device could be one of the following: a head-mounted display, an augmented reality (AR) wearable device, or a pico projector. [Explanation of symbols]

[0075] VDD, GND reference potential terminals LD (Laser Diode) Semiconductor Devices Mx, Mx' transistors Msw, Msw' transistor Mswr, Mr. Transistor VDDA, VSSA reference potential terminals VDDA_LV, VSSA_LV Reference potential terminal Vgx, Vgx' gate terminals Vr discharge potential terminal OT1, OT2 output terminals DQSW Discharge Switch NSX connection CBFR, CBFX capacitive elements CS1, CS2 current source VQ Level Shifter CIN control input Φ, Φ￣ Control signal

Claims

1. A driver circuit for driving a light-emitting semiconductor device (LD), - A first current path including a series connection of a first transistor (Msw) and a second transistor (Mx), wherein the source terminal of the first transistor (Msw) is coupled to a first reference potential terminal (VDDA), the gate terminal of the first transistor (Msw) is coupled to a second reference potential terminal (VSSA) or a third reference potential terminal, and the drain terminal and gate terminal of the second transistor (Mx) are commonly coupled to the second reference potential terminal (VSSA) via a current source, - A first output terminal and a second output terminal (OT1, OT2) to which the emitting semiconductor device (LD) is connected, wherein the second output terminal (OT2) is coupled to the second reference potential terminal (VSSA) or a further reference potential terminal, - A second current path including a series connection of a third transistor (Msw') and a fourth transistor (Mx'), wherein the source terminal of the third transistor (Msw') is coupled to the first reference potential terminal (VDDA), the gate terminal of the fourth transistor (Mx') is coupled to the gate terminal of the second transistor (Mx), and the drain terminal of the fourth transistor (Mx') is coupled to the first output terminal (OT1), - A control terminal (CIN) for supplying a control signal for controlling the current passing through the second current path, wherein the control terminal is coupled to the gate terminal of the third transistor (Msw'), A driver circuit equipped with the above.

2. It further includes a discharge potential terminal (Vr) and a discharge switch (DQSW), The discharge switch (DQSW) is connected between the discharge potential terminal (Vr) and the common connection point (nsx) of the third transistor (Msw') and the fourth transistor (Mx'), and the discharge switch (DQSW) is configured to be controlled based on the control signal. The driver circuit according to claim 1.

3. The potential of the discharge potential terminal (Vr) is lower than the potential obtained by adding or subtracting the threshold voltage of the fourth transistor (Mx') from the potential at the gate terminal of the fourth transistor (Mx'). The driver circuit according to claim 2.

4. A capacitive element (CBFR) is connected between the discharge potential terminal (Vr) and the first reference potential terminal (VDDA). The driver circuit according to claim 2 or 3.

5. The discharge potential terminal (Vr) is coupled to the first reference potential terminal (VDDA) via a level shifter (VQ). The driver circuit according to any one of claims 2 to 4.

6. - Further current paths including a series connection of a fifth transistor (Mswr) and a sixth transistor (Mr), wherein the source terminal of the fifth transistor (Mswr) is coupled to the first reference potential terminal (VDDA), the gate terminal of the fifth transistor (Mswr) is coupled to the second reference potential terminal (VSSA), and the drain and gate terminals of the sixth transistor (Mr) are commonly coupled to the second reference potential terminal (VSSA) via a further current source, - The level shifter (VQ) is formed from a path from the source terminal of the fifth transistor (Mswr) to the gate terminal of the sixth transistor (Mr). The driver circuit according to claim 5.

7. The discharge potential terminal (Vr) is coupled to the gate terminal of the second transistor (Mx). The driver circuit according to any one of claims 2 to 4.

8. The discharge potential terminal (Vr) is directly connected to the gate terminal of the second transistor (Mx). The driver circuit according to claim 7.

9. - A voltage buffer having an input connected to the gate terminal of the second transistor (Mx) and an output connected to the gate terminal of the fourth transistor (Mx'), - Further comprising a further capacitive element (CBFX) connected between the first reference potential terminal (VDDA) and the output of the voltage buffer, A driver circuit according to any one of claims 2 to 7.

10. The discharge potential terminal (Vr) is connected to the output of the voltage buffer. The driver circuit according to claim 9.

11. - The discharge switch (DQSW) is implemented as a transistor of the same channel type as the third transistor (Msw'), - The third transistor (Msw') is controlled using the control signal, - The discharge switch (DQSW) is controlled using a complementary version of the control signal. A driver circuit according to any one of claims 2 to 10.

12. The aforementioned control signal and its complementary version are non-overlapping. The driver circuit according to claim 11.

13. - The discharge switch (DQSW) is implemented as a channel-type transistor complementary to the channel-type of the third transistor (Msw'), - The third transistor (Msw') and the discharge switch (DQSW) are controlled using the control signal. A driver circuit according to any one of claims 2 to 10.

14. - The discharge switch (DQSW) is implemented as a channel-type transistor complementary to the channel-type of the third transistor (Msw'), - The third transistor (Msw') and the discharge switch (DQSW) are controlled using the control signal. - The gate terminal of the first transistor (Msw) is connected to the third reference potential terminal. - The discharge potential terminal (Vr) is connected to the third reference potential terminal, - The third transistor (Msw') and the discharge switch (DQSW) are designed to operate at a lower voltage compared to the second transistor (Mx) and the fourth transistor (Mx'). The driver circuit according to claim 2 or 3.

15. The first transistor, the second transistor, the third transistor, and the fourth transistor, as well as the fifth and sixth transistors, if present, are of the same channel type. A driver circuit according to any one of claims 1 to 14.

16. The present invention further comprises a dummy switch device (DYSW) connected to the common connection (nsx) of the third transistor (Msw') and the fourth transistor (Mx'), A driver circuit according to any one of claims 1 to 15.

17. The device further comprises the emission semiconductor device (LD) connected between the first output terminal and the second output terminal (OUT1, OUT2), A driver circuit according to any one of claims 1 to 16.

18. A display device comprising a plurality of driver circuits as described in claim 17.

19. An electronic device comprising the display device described in claim 18.

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