Selective etching of stacks under a metal mask using oxygen and fluorine

Abstract

A method is provided for etching concave features in a silicon-containing stack beneath a metal-containing mask. An etching gas containing oxygen and fluorine is provided. The etching gas is converted into a plasma. The stack is exposed to the plasma to selectively etch the concave features within the stack relative to the metal-containing mask.

Description

TECHNICAL FIELD

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority of U.S. Patent Application No. 63 / 588,089, filed on October 5, 2023, which is hereby incorporated herein by reference for all purposes. BACKGROUND ART

[0002] One process frequently used during the manufacture of semiconductor devices is forming recessed features in a stack under a carbon-containing mask. The stack may be alternating / repeating layers of material in which recessed features are formed, or a single layer thick film. An example of a situation where such a process may occur is in memory applications such as dynamic random access memory (DRAM) and "not and" devices (NAND). In the fabrication of some semiconductor devices, metals or other materials may be etched under the carbon-containing mask. As the semiconductor industry advances and device dimensions shrink, such recessed features become increasingly difficult to etch uniformly, especially for high aspect ratio features having narrow widths and / or great depths.

[0003] The description of the background art provided herein is for the purpose of generally presenting the context of the present disclosure. The work of the inventors, to the extent described in this Background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, is neither expressly nor implicitly admitted to be prior art to the present disclosure. SUMMARY OF THE INVENTION

[0004] To achieve the above, a method for etching concave features in a silicon-containing stack beneath a metal-containing mask is provided in accordance with the purposes of this disclosure. An etching gas containing oxygen and fluorine is provided. The etching gas is converted into a plasma. The stack is exposed to the plasma to selectively etch concave features within the stack against the metal-containing mask.

[0005] Another embodiment provides a method for etching concave features within a silicon-containing stack beneath a metal-containing mask. An etching gas containing oxygen and fluorine is provided. The etching gas is converted into a plasma by supplying multi-state pulsed RF power, which includes two or three states. The stack is exposed to the plasma to etch the concave features.

[0006] In another embodiment, an apparatus is provided for etching concave features within a silicon-containing stack beneath a metal-containing mask. A substrate support supports the substrate within the processing chamber. An RF power supply provides RF power to the processing chamber. A gas source includes an oxygen and fluorine source. A controller is controllably connected to the RF power supply and gas source and is configured to supply an etching gas containing oxygen and fluorine, convert the etching gas into a plasma, and expose the stack to the plasma to selectively etch concave features within the stack against the metal-containing mask.

[0007] These and other features of this disclosure will be described in more detail in the following detailed description, in conjunction with the following figures.

[0008] This disclosure is shown as an example, not as an limitation, in the figures of the attached drawings, where similar reference numbers refer to similar elements. [Brief explanation of the drawing]

[0009] [Figure 1] This flowchart illustrates methods for etching concave features within a stack beneath a carbon-containing mask, using various implementation configurations. [Figure 2A] This is a schematic cross-section of a stack processed according to several implementation configurations. [Figure 2B] This is a schematic cross-section of a stack processed according to several implementation configurations. [Figure 3] This figure shows a semiconductor processing system that may be used in several implementation forms. [Figure 4] This figure shows a computer system for implementing a controller used in several different implementation forms. [Modes for carrying out the invention]

[0010] In drawings, similar reference numbers may be used to indicate similar structural elements. Please understand that the depictions in the drawings are approximate and not to scale.

[0011] This disclosure is described in detail with reference to several preferred implementations thereof, as shown in the accompanying drawings. Numerous specific details are included in the following description to provide a complete understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be carried out without some or all of these specific details. In other examples, well-known process steps and / or structures are not described in detail so as not to unnecessarily obscure this disclosure.

[0012] The manufacture of certain semiconductor devices involves etching features into a stack of materials. In various packaging configurations described herein, the stack of materials comprises one or more layers of one or more materials under a carbon-containing mask. In some packaging configurations, at least one layer of the stack comprises at least one of silicon, germanium, and metal. The silicon-containing layer may contain silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbide, polysilicon, or silicon germanium. In one example, the stack comprises alternating layers of silicon oxide and polysilicon. In some packaging configurations, the stack comprises alternating silicon oxide and silicon nitride films, or a single silicon oxide layer, or a single silicon layer. In some packaging configurations, the stack may be a conductive layer or a dielectric layer, which may be a metal or silicon-containing layer.

[0013] Features etched within the stack may be cylinders, trenches, or other concave features. The aspect ratio of such features is defined as the lateral limiting dimension divided by the depth. As the aspect ratio of such features continues to increase, several problems arise, including (1) insufficient mask selectivity, (2) etching resolution, (3) twisting of features, (4) non-circularity of features, (5) aspect ratio-dependent etching rate, and (6) bowing of the etching profile, and (7) slow etching rate.

[0014] When the etching process removes an excess amount of mask, the problem lies in insufficient mask selectivity, resulting in either no mask remaining at the end of the process, or insufficient mask residue to properly transfer the pattern from the mask to the stack. One common consequence of insufficient mask selectivity is degradation of the feature profile near the tops of concave features. To compensate for insufficient mask selectivity, a thicker mask may be formed. However, a thicker mask results in lower mask resolution and a higher overall aspect ratio, causing more problems during etching of both the mask material and the underlying material.

[0015] Torsion refers to a random deviation between the intended bottom position of a feature and the actual final bottom position of the feature (for example, the final position of the feature corresponding to the bottom position of the feature after etching). For example, in some cases, cylindrical features are intended to be etched in a regular pattern. If some or all of the features deviate randomly at the bottom from this pattern, they are understood to be torn.

[0016] The non-circularity of a feature refers to a deviation of the bottom hole shape from a circular hole shape. This issue is relevant when etching circular features, such as cylinders, where a circular bottom is desirable for concave features. When the bottom hole shape deviates from circularity, it often forms an ellipse, triangle, or a shape close to an irregular polygon. In many cases, these non-circular shapes are undesirable.

[0017] Aspect ratio-dependent etching rate refers to the problem where the etching rate slows down as the aspect ratio of a feature increases. In other words, the etching process slows down as more features are etched into the stack. This is a problem because it can result in low throughput and associated high processing costs.

[0018] Etching profile bowing refers to the tendency for a feature to etch laterally within a stack, causing the final profile to bulge excessively outward somewhere along the feature's depth. In other words, the actual maximum limiting dimension of a feature may exceed the desired maximum limiting dimension of the feature, potentially compromising the integrity of the resulting structure or limiting the electrical performance of the final device.

[0019] A low etching rate refers to an etching rate that is slower than what is desirable for a particular application. A low etching rate is problematic because it leads to longer etching times, reduced throughput, and higher processing costs.

[0020] Unfortunately, techniques that improve some of these problems, such as insufficient mask selectivity, often exacerbate others. Therefore, these problems must be balanced when designing etching operations. For example, conventional commercially implemented dielectric etching processes often result in substantial boeing. Previously, avoiding such trade-offs was difficult.

[0021] In prior art NAND ONON (silicon oxide-silicon nitride stack) etching, etching is performed using plasmas containing fluorine, hydrogen and / or carbon, producing byproducts of silicon hexafluoride (SiF4), ammonia (NH3), water / hydroxide (H2O / OH) or carbon monoxide / carbon dioxide (CO / CO2). At cryogenic temperatures, when the etch rate is high, a high density of etching byproducts accumulates at the etching forefront. NH3 can react with SiF4 in the presence of hydrogen and fluorine to form ammonium salt (NH4)2SiF6 (AFS). The formation of AFS salts causes many different issues such as sharp etching forefront, profile twisting, and non-circularity. In current NAND integration, a carbon-containing mask is used to pattern the ONON stack. Due to the low selectivity of less than 1 to 10, the carbon mask must be deposited very thickly so that the pattern can be successfully transferred. The thick mask layer increases the aspect ratio of both mask etching and ONON stack etching, causing further high aspect ratio related issues such as aspect ratio dependent etching, etch stop, taper, bowing, and twisting.

[0022] The techniques described herein may be used to etch recessed features into the stack under the mask without some or all of the problems identified above. In other words, the disclosed techniques may be used to etch recessed features into the stack under the mask with high stack-to-mask selectivity, reduced mask twist, reasonably circular features, an acceptable degree of aspect ratio dependent etch rate, acceptable bowing, and sufficient etch rate.

[0023] For ease of understanding, Figure 1 is a high-level flowchart of a method that may be used in several implementation configurations. A silicon-containing stack including a metal-containing mask is provided (step 104). Figure 2A is a schematic cross-sectional view of a stack 204 that may be processed according to several implementation configurations, where the stack is beneath a metal-containing mask 212, such as a titanium nitride (TiN) mask. In some implementation configurations, the stack 204 may be formed on a substrate 208. In some implementation configurations, the stack 204 may include a silicon-containing layer such as silicon oxide, silicon nitride, or silicon. In some implementation configurations, the stack 204 may be a conductive metal layer of pure metal or alloy, or a metal-containing layer such as metal nitride or metal oxide. In some implementation configurations, the stack 204 may include a germanium-containing layer. In some implementation configurations, the stack is a single bulk layer. In some implementation configurations, the stack is multiple layers. In some implementation configurations, the stack is multiple double layers, triple layers, or more multilayers.

[0024] An etching process is provided for etching the stack 204. The substrate support supporting the stack is cooled to a cryogenic temperature (step 108). In some mounting configurations, the substrate support is cooled to a cryogenic temperature below 0°C. In some mounting configurations, the substrate support is cooled to a temperature below -20°C. In some mounting configurations, the substrate support is cooled to a temperature below -40°C. In some mounting configurations, the substrate support is cooled to a temperature below -60°C.

[0025] Supplying an etching gas containing oxygen and fluorine (step 112). In some implementations, the etching gas comprises at least one of oxygen difluoride (OF₂), and a mixture of oxygen gas (O₂) and fluorine gas (F₂). In some implementations, the etching gas comprises OF₂ and a phosphorus-containing component. In some implementations, the phosphorus-containing component comprises at least one of phosphorus trifluoride (PF₃) and phosphorus pentafluoride (PF₅). In some implementations, the etching gas may further comprise a carrier gas such as argon (Ar), xenon (Xe), helium (He), and nitrogen gas (N₂). In some implementations, the etching gas may comprise an additional fluorocarbon gas.

[0026] Converting the etching gas into plasma (step 116). In some implementations, radio frequency (RF) power is used to convert the etching gas into plasma. In some implementations, the plasma is formed within the process chamber. In some implementations, the plasma is formed remotely outside the process chamber and then supplied into the process chamber.

[0027] Plasma in various implementation configurations may be generated with radio frequency (RF) power between approximately 5 and 200 kilowatts (kW), for example between approximately 10 and 100 kW, or in some implementation configurations between approximately 10 and 65 kW. In some cases, dual-frequency RF may be used to generate the plasma. Thus, the RF power may be supplied in two or more frequency components, for example, a first frequency component at approximately 400 kilohertz (kHz) and a second frequency component at approximately 60 megahertz (MHz). Different power may be supplied to each frequency component. For example, the first frequency component (e.g., approximately 400 kHz) may be supplied with power at approximately 10 to 65 kW, and the second frequency component (e.g., approximately 60 MHz) may be supplied with a different power, for example, approximately 0.5 to 8 kW. In some implementation configurations, the first frequency component (e.g., approximately 400 kHz) may be supplied with power exceeding 65 kW. These power levels assume that the RF power is supplied to a single 300 mm wafer. The power level can be linearly scaled based on the substrate area of ​​additional substrates and / or other sizes of substrates (therefore, a uniform power density supplied to the substrate is maintained). In other cases, three-frequency RF power may be used to generate the plasma.

[0028] In some implementations, the applied RF power is continuous RF power. In some implementations, the applied RF power may be pulsed. In some implementations, the pulsed RF may have two or three states, providing multi-state pulsed RF power. In three-state pulsing, pulsing occurs between three different (high, medium, low) power levels. In some implementations, the high power level has a duty cycle of 1% to 20%, the medium power level has a duty cycle of 10% to 90%, and the low power level has a duty cycle of 20% to 90%. In some implementations, one of the three power levels is 0 watts. In some implementations, the high power level is 2 to 20 times the low power level, and the medium power level is between the high and low power levels. In some implementations, the RF power is pulsed at a repetition rate of 1 to 50,000 Hz. The RF power may be pulsed between two non-zero values ​​(e.g., between a higher power state and a lower power state) or between zero and a non-zero value (e.g., between an off state and an on state). When the RF power is pulsed between two non-zero values, the power may be in a higher power state and a lower power state. The lower power state may correspond to RF power of approximately 4 kW or less. The duty cycle of the pulse may be in the range of 1 to 50%. The pulsed state may have a repetition rate in the range of 100 Hz to 20 kHz. The maximum ion energy in the substrate may be relatively high, for example, approximately 1 to 30 kiloelectron volts (keV). The maximum ion energy is determined by the applied RF power in combination with the RF excitation frequency, electrode size, electrode arrangement, chamber shape, and plasma interaction details.

[0029] In some implementations, a bias ranging from 0 watts (W) to 100 kilowatts (kW) is provided to accelerate ions toward the top surface of stack 204. In some implementations, a bias ranging from 100 W to 100 kW is provided.

[0030] Stack 204 is exposed to plasma (step 120), and the concave features are selectively etched into the stack 204 relative to the metal-containing mask 212. Figure 2B is a schematic cross-sectional view of stack 204 after the concave features 220 have been etched.

[0031] The use of stacks containing metal-containing masks provides higher selectivity and therefore thinner masks. Thinner masks result in improved etching resolution, and the mask contributes less to the aspect ratio. Providing etching at cryogenic temperatures increases the adsorption of the etchant. Higher etching rates are provided by supplying etching gases containing oxygen and fluorine. Etching SiN or SiO using such etching gases forms one or more byproducts from several cryogenically volatile compounds: nitric oxide (NO), CO, SiF4, O2, nitrogen dioxide (NO2), carbonyl fluoride (COF2), and CO2. Such etching gases do not form byproducts of ammonia (NH3) salts, which do not volatilize at cryogenic temperatures. The addition of phosphorus-containing components produces POF2 such as phosphoryl fluoride (POF3), which is cryogenically volatile. x This causes the formation of...

[0032] Compared to using hydrogen fluoride (HF), OF2 has twice as many fluorine atoms per molecule as HF, enabling faster etching. Faster etching rates of the stack allow for less etching of the mask. Furthermore, oxygen from OF2, along with nitrogen, forms volatile molecules that facilitate the etching of silicon nitride (SiN). While NH3 may be volatile at cryogenic temperatures, some NH3 salts, such as ammonium fluorosilicate (AFS), ammonium fluoride (AF), ammonium chloride, and ammonium bromide, are not volatile at cryogenic temperatures. Removal of nitrogen reduces or eliminates the formation of NH3 salts that are not volatile at cryogenic temperatures. Using OF2 has been shown to enable faster etching of silicon oxide and silicon nitride with reduced filtration. In some implementations, the etching gas is hydrogen-free and NH3-free. In some implementations, the etching gas may contain small amounts of hydrogen.

[0033] One application of the disclosed method relates to forming a vertical NAND device. In this case, the material on which the features are etched may have a repeating layer structure. For example, the material may include alternating layers of silicon oxide and silicon nitride. In other configurations, the stack may include alternating layers of silicon oxide and polysilicon. The alternating layers form pairs or repeating groups of material. In various cases, the number of pairs or repeating groups may be about 10 to 500 (e.g., about 20 to 1000 individual layers). Features etched into the stack of layers may have a depth of about 2 to 15 μm, for example, about 5 to 9 μm. Features may have a width between about 40 to 450 nm, for example, between about 50 to 100 nm or between about 40 to 85 nm. In some configurations, features have a width of less than 100 nm. In some configurations, features have a width of less than 85 nm.

[0034] As used herein, “high aspect ratio” applied to features within a substrate refers to an aspect ratio of approximately 60:1 or greater. More preferably, this range may include ratios exceeding 100:1, 120:1, 140:1, etc., or higher. However, the processes described herein may be beneficial for lower aspect ratios such as 30:1 or 10:1.

[0035] The dimensional / parametric details provided herein, such as aspect ratio, thickness, width, and depth, are for illustrative purposes only. It should be understood that various other dimensions / parameters may also be applicable or usable based on the disclosures herein.

[0036] Device The various hardware and method implementations described above may be used in conjunction with lithography patterning tools or processes for the fabrication or manufacture of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, but not always, such tools / processes are used or performed together in a common manufacturing facility.

[0037] Film lithography patterning typically involves some or all of the following steps, each of which can be made possible using several possible tools: (1) coating a photoresist onto a workpiece, e.g., a substrate on which a silicon-containing film is formed, using a spin-on or spray-on tool; (2) curing the photoresist using a hot plate or furnace or other suitable curing tool; (3) exposing the photoresist to visible light, ultraviolet (UV) light, or X-ray light using a tool such as a wafer stepper; (4) selectively removing the resist and thereby developing the resist for patterning using a tool such as a wet bench or spray developer; (5) transferring the resist pattern to the underlying film or workpiece by using a dry or plasma-assisted etching tool; and (6) removing the resist using a tool such as an RF or microwave plasma resist stripper. In some packaging configurations, an ashingable hard mask layer (e.g., an amorphous carbon layer) and other suitable hard masks (e.g., an anti-reflective layer) may be deposited before coating the photoresist.

[0038] In this application, the terms “semiconductor wafer,” “wafer,” “substrate,” “wafer substrate,” and “partially manufactured integrated circuit” are used interchangeably. Those skilled in the art will understand that the term “partially manufactured integrated circuit” can refer to a silicon wafer in any of the many stages of integrated circuit manufacturing on which it is manufactured. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm, or 450 mm. The above detailed description assumes that the mounting configuration is carried out on a wafer. However, the mounting configuration is not limited in this way. Workpieces may vary in shape, size, and material. In addition to semiconductor wafers, other workpieces that may utilize the disclosed mounting configuration include a variety of articles such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical elements, and micromechanical devices.

[0039] Unless otherwise specifically defined for a particular parameter, the terms “about” and “approximately” as used herein are intended to mean ±10% of the relevant value.

[0040] Figure 3 is a schematic diagram of a plasma processing chamber 300 for plasma processing of a substrate in one mounting configuration. In one or more mounting configurations, the plasma processing chamber 300 comprises a gas distribution plate 306 providing a gas inlet and an electrostatic chuck (ESC) 316 within a plasma processing chamber 304 enclosed by chamber walls 350. Within the plasma processing chamber 304, the substrate 208 is positioned on the ESC 316, so that the ESC 316 also serves as a substrate support. The ESC 316 may be biased from an ESC power supply 348. A gas source 310 is connected to the plasma processing chamber 304 via the gas distribution plate 306. In some mounting configurations, the gas source includes an oxygen and fluorine source 312 such as an OF2 gas source, a phosphorus-containing component source such as a PF3 or PF5 gas source, and other gas sources. An ESC temperature controller 351 is connected to the ESC 316 and provides temperature control of the ESC 316, enabling the ESC 316 to be cooled to cryogenic temperatures. The radio frequency (RF) power supply 330 supplies RF power to the ESC 316 and the upper electrode. The RF power may be supplied in a sinusoidal or other tuned waveform. In this implementation, the upper electrode is the gas distribution plate 306. In a preferred implementation, power supplies of 400 kHz, 13.56 MHz, 1 MHz, 2 MHz, 60 MHz and / or optionally 27 MHz constitute the RF power supply 330 and the ESC power supply 348 to supply RF power at the RF frequencies. The controller 335 is controllably connected to the RF power supply 330, the ESC power supply 348, the exhaust pump 320, and the gas source 310. The high-flow liner 360 is a liner within the plasma processing chamber 304 that confines the gas from the gas source and has slots 362. The slots 362 maintain a controlled flow of gas passing from the gas source 310 to the exhaust pump 320. An example of such a plasma processing chamber is the Flex® etching system manufactured by Lam Research Corporation in Fremont, California. The process chamber can be a CCP (capacitance-coupled plasma) reactor or an ICP (inductively coupled plasma) reactor.

[0041] Figure 4 is a high-level block diagram showing a computer system 400 for implementing a controller 335 used in an implementation of the present invention. The computer system may have many physical forms, ranging from integrated circuits, printed circuit boards, and small handheld devices to massive supercomputers. The computer system 400 may include one or more processors 402, and may further include an electronic display device 404 (for displaying graphics, text, and other data), main memory 406 (e.g., random access memory (RAM)), storage device 408 (e.g., hard disk drive), removable storage device 410 (e.g., optical disc drive), user interface device 412 (e.g., keyboard, touchscreen, keypad, mouse, or other pointing device), and / or communication interface 414 (e.g., wireless network interface). The communication interface 414 may allow software and / or data to be transferred between the computer system 400 and external devices via a link. The system may also include a communication infrastructure 416 (e.g., communication bus, crossover bar, or network) to which the aforementioned devices / modules may be connected.

[0042] The information transmitted via the communication interface 414 may be in the form of electronic signals, electromagnetic signals, optical signals, or other signals that can be received by the communication interface 414 via a communication link that carries signals, and may be implemented using wires or cables, optical fibers, telephone lines, mobile phone links, radio frequency links, and / or other communication channels. Using such a communication interface, one or more processors 402 may receive information from or output information to the network during the process of performing the method steps described above. Furthermore, the implementation of the method may be performed by a single processor or by a network such as the Internet with a remote processor that shares a portion of the processing.

[0043] The term “non-temporary computer-readable medium” is generally used to refer to media such as main memory, secondary memory, removable storage devices, and storage devices such as hard disks, flash memory, disk drive memory, CD-ROMs, and other forms of persistent memory, and should not be interpreted as covering temporary subjects such as carrier waves or signals. Examples of computer code include machine code, such as that generated by a compiler, and files containing higher-level code executed by a computer using an interpreter. Computer-readable medium may also be computer code transmitted by computer data signals, which are embodied in carrier waves and represent sequences of instructions executable by a processor.

[0044] The configurations and / or techniques described herein are essentially illustrative, and numerous variations are possible; therefore, it should be understood that these particular implementations or examples should not be considered in an exclusive sense. The specific routines or methods described herein may represent one or more of any number of processing strategies. Accordingly, the various operations illustrated may be performed in the illustrated order, in other orders, in parallel, or, in some cases, omitted. Similarly, the order of the processes described above may be changed. Certain references are incorporated herein by reference. Any waiver or denial made in such references should be understood not necessarily apply to the implementations described herein. Similarly, any features described as necessary in such references may be omitted in the implementations herein. The subject matter of this disclosure includes all novel and non-trivial combinations and partial combinations of the various processes, systems and configurations disclosed herein, as well as other features, functions, operations and / or characteristics, and all their equivalents.

[0045] conclusion While this disclosure describes several preferred implementations, there are many variations, modifications, substitutions, and various equivalents that fall within the scope of this disclosure. It should also be noted that there are many alternative ways of implementing the methods and apparatus of this disclosure. Accordingly, the following appended claims are intended to be interpreted as including all such variations, modifications, substitutions, and various equivalents that fall within the true intent and scope of this disclosure. Where used in this disclosure, the phrase "A, B, or C" should be interpreted as meaning a logic ("A OR B OR C") using the non-exclusive logic "OR", and not as meaning "only one of A, B, or C". Each step in the process may be an optional step, not mandatory. Different implementations may have one or more steps removed, and may provide the steps in a different order. Furthermore, different implementations may provide different steps simultaneously rather than sequentially. [Explanation of Symbols]

[0046] 204 stacks 208 circuit boards 212 Metal-containing masks 220 concave features 300, 304 Plasma Processing Chambers 306 Gas Distribution Plate 310 Gas sources 312 Oxygen and Fluorine Sources 316 Electrostatic Chuck 320 Exhaust Pump 330 Radio Frequency (RF) Power Supply 335 Controller 348 ESC power supply 350 Chamber Wall 351 ESC Temperature Controller 360 High-flow Liner 362 slots 400 Computer Systems 402 Processors 404 Electronic Display Devices 406 Main Memory 408 Storage Devices 410 Removable Storage Devices 412 User Interface Devices 414 Communication Interface 416 Communication Infrastructure

Claims

1. A method for etching a concave feature in a silicon-containing stack beneath a metal-containing mask, a. A step of supplying an etching gas containing oxygen and fluorine, b. The step of converting the etching gas into plasma, c. The step of exposing the stack to the plasma in order to selectively etch the concave features within the stack with respect to the metal-containing mask. Methods that include...

2. The method according to claim 1, wherein the etching gas comprises at least one of oxygen difluoride and a mixture of oxygen gas and fluorine gas.

3. The steps include: placing the aforementioned stack on the substrate support portion, The steps include: cooling the substrate support portion to a temperature below 0°C; The method according to claim 1, further comprising:

4. The method according to claim 1, wherein the etching gas does not contain hydrogen.

5. The method according to claim 1, wherein the stack includes at least one of SiN, SiO, and SiON.

6. The method according to claim 1, wherein the step of converting the etching gas includes a step of supplying RF power, and the step of supplying RF power includes a step of providing at least one of a step of supplying continuous RF power and a step of supplying multi-state pulsed RF power.

7. The method according to claim 1, wherein the step of converting the etching gas includes the step of supplying multi-state pulsed RF power having two or three states.

8. The method according to claim 1, wherein the etching gas further comprises at least one of phosphorus trifluoride and phosphorus pentafluoride.

9. The etching gas does not contain hydrogen fluoride (HF) and does not contain ammonia (NH ３ The method according to claim 1, which does not include ).

10. The method according to claim 1, wherein the step of converting the etching gas includes the step of supplying pulsed RF power having a duty cycle in the range of 1% to 50%.

11. A method for etching a concave feature in a silicon-containing stack beneath a metal-containing mask, a. A step of supplying an etching gas containing oxygen and fluorine, b. A step of converting the etching gas into a plasma, comprising the step of supplying multi-state pulsed RF power having two or three states, c. The step of exposing the stack to the plasma in order to etch the concave features, A method that includes this.

12. The method according to claim 11, wherein the etching gas comprises at least one of oxygen difluoride and a mixture of oxygen gas and fluorine gas.

13. The steps include: placing the aforementioned stack on the substrate support portion, The steps include: cooling the substrate support portion to a temperature below 0°C; The method according to claim 11, further comprising:

14. The method according to claim 11, wherein the etching gas does not contain hydrogen.

15. The method according to claim 11, wherein the stack includes at least one of SiN, SiO, and SiON.

16. The method according to claim 11, wherein the etching gas further comprises at least one of phosphorus trifluoride and phosphorus pentafluoride.

17. Apparatus for etching concave features in a silicon-containing stack beneath a metal-containing mask, process chamber and A substrate support section that supports the substrate within the processing chamber, An RF power supply for supplying RF power to the processing chamber, A gas source containing oxygen and fluorine, A controller that is controllably connected to the RF power supply and the gas source, a. Provide an etching gas containing oxygen and fluorine, b. Convert the etching gas into plasma, c. Exposing the stack to the plasma in order to selectively etch the concave features within the stack against the metal-containing mask. A controller and A device equipped with the following features.

18. The apparatus according to claim 17, wherein the oxygen and fluorine sources are at least one of oxygen difluoride and a mixture of oxygen gas and fluorine gas.

19. The apparatus according to claim 17, further comprising a temperature controller for controlling the temperature of the substrate support portion, wherein the controller is further configured to cool the substrate support portion to a temperature of less than 0°C.

Images