Multi-format operand circuit

Abstract

The disclosed processing circuit can directly use the first operand having the first numeric form and the second operand having the second numeric form to perform operations on the first operand having the first numeric form and the second operand having the second numeric form, and generate an output result. Various other methods, systems, and computer-readable media are also disclosed.

Description

Technical Field

[0001] (Cross-Reference to Related Applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 591,963 filed on October 20, 2023, and U.S. Utility Patent Application No. 18 / 399,659 filed on December 28, 2023, the disclosures of which are hereby incorporated by reference in their entirety.

Background Art

[0002] Floating-point numbers are commonly used by computing devices to represent a wide range of real values for computation. Various floating-point number formats may be configured with respect to various considerations, such as storage space / bandwidth considerations, computational considerations, and mathematical properties. Furthermore, various computing devices may be configured to support different formats of floating-point numbers. As computing devices become more complex (e.g., having various types of hardware that operate in cooperation using networked devices, etc.) and as computing demands increase (e.g., by implementing machine learning models, especially for high-speed decision-making), support for various floating-point number formats may be desirable. While it is possible to support various floating-point number formats in a software-based manner, software support often involves additional latency, or may even be infeasible for specific application requirements.

[0003] The accompanying drawings illustrate several exemplary embodiments and form part of the present specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

Brief Description of the Drawings

[0004] [Figure 1] 1 is a block diagram of an exemplary system of a multi-format operand circuit. [Figure 2A] FIG. 2 is a diagram illustrating an exemplary floating-point number format. [Figure 2B] This figure shows an example of a floating-point number format. [Figure 2C] This figure shows an example of a floating-point number format. [Figure 3] This is a simplified block diagram of a circuit for multi-format operands. [Figure 4] This is a flowchart illustrating an example method for multi-format source operands. [Modes for carrying out the invention]

[0005] Throughout the drawings, the same reference numerals and designations indicate similar but not necessarily identical elements. The exemplary embodiments described herein are open to various modifications and alternative forms, but specific embodiments are shown in the drawings as examples and are described in detail herein. However, the exemplary embodiments described herein are not intended to limit to any particular form disclosed. Rather, this disclosure covers all modifications, equivalents and alternative forms that fall within the appended claims.

[0006] This disclosure generally pertains to multi-format source operand circuits. As will be described in more detail below, embodiments of the present invention directly perform operations on a first operand having a first numerical format and a second operand having a second numerical format. By generating output results without first converting either the first or second operand to a common numerical format, the systems and methods described herein improve computational efficiency and further enhance flexibility when performing calculations on values ​​from different sources (other processing components and / or devices, etc.). Furthermore, the systems and methods provided herein can improve the field of machine learning by maintaining high-speed processing while reducing the overhead of converting values ​​to a common numerical format, enabling improved decision-making and enhanced hardware compatibility.

[0007] In one embodiment, a device for multi-format operands includes a processing circuit configured to perform operations on a first operand having a first numeric format and a second operand having a second numeric format by directly using a first operand having a first numeric format and a second operand having a second numeric format, and to generate an output result.

[0008] In some examples, the first and second numeric formats correspond to different numeric formats among several numeric formats having similar precision. In some examples, the processing circuit is configured to perform an operation for each of several possible combinations of the several numeric formats of the first and second operands. In some examples, the processing circuit includes a circuit for performing an operation for each of the several possible combinations. In some examples, the processing circuit includes an instruction set for performing an operation for each of the several possible combinations.

[0009] In some examples, the processing circuit is further configured to decode the operation into microoperations using a first numerical format and a second numerical format. In some examples, the microoperations include microoperations that normalize the first sign, first exponent, and first mantissa of the first operand based on the first numerical format, and further normalize the second sign, second exponent, and second mantissa of the second operand based on the second numerical format. In some examples, the microoperations include microoperations to combine the first sign and the second sign, the first mantissa and the second mantissa, and the first exponent and the second exponent according to the operation to produce an output result.

[0010] In one embodiment, a system for multiformat operands comprises memory, a processor, and a processing circuit, the processing circuit being configured to (i) receive a first operand having a first numeric format and a second operand having a second numeric format for an operation, (ii) decode the operation into a microoperation using the first numeric format and the second numeric format, and (iii) execute the operation via the decoded microoperation using the first operand of the first numeric format and the second operand of the second numeric format directly to generate an output result.

[0011] In some examples, the first and second numeric formats correspond to different numeric formats among several numeric formats having similar precision. In some examples, the processing circuit is configured to decode the operation into a microoperation by selecting a microoperation corresponding to one of several possible combinations of several numeric formats relating to the first and second operands. In some examples, the processing circuit is further configured to select a microoperation based on a first source for the first operand and a second source for the second operand. In some examples, the processing circuit includes circuits corresponding to each of several possible combinations for performing the operation.

[0012] In some examples, the microoperation includes a microoperation that normalizes the first sign, first exponent, and first mantissa of a first operand based on a first numeric format, and further normalizes the second sign, second exponent, and second mantissa of a second operand based on a second numeric format. In some examples, the microoperation includes a microoperation to combine the first sign and the second sign, the first mantissa and the second mantissa, and the first exponent and the second exponent according to the operation to produce an output result.

[0013] In one embodiment, a method for multiformat operands includes (i) identifying a first numeric format for a first operand of an operation and a second numeric format for a second operand of an operation, wherein the first and second numeric formats correspond to different numeric formats having similar precision; (ii) selecting a set of instructions to perform an operation using the first and second numeric formats based on the first and second numeric formats; and (iii) performing an operation and generating an output result by directly using the first and second operands together with the selected set of instructions.

[0014] In some examples, selecting a set of instructions is based on a first numeric format and a second numeric format. In some examples, selecting a set of instructions is based on a first source for a first operand and a second source for a second operand. In some examples, performing an operation further includes normalizing the first sign, first exponent, and first mantissa of a first operand based on a first numeric format, and normalizing the second sign, second exponent, and second mantissa of a second operand based on a second numeric format. In some examples, performing an operation further includes concatenating the first sign and the second sign, the first mantissa and the second mantissa, and the first exponent and the second exponent according to the operation in order to produce an output result.

[0015] Any feature of the embodiments described herein can be used in combination with one another in accordance with the general principles described herein. These and other embodiments, features and advantages will be better understood by reading the following detailed description in conjunction with the accompanying drawings and claims.

[0016] The hardware-based multi-format operand processing will be described in detail below with reference to Figures 1 to 4. A detailed description of the exemplary system and circuitry is provided in relation to Figures 1 and 3. A detailed description of the floating-point format is provided in relation to Figures 2A to 2C. A detailed description of the corresponding computer execution method is also provided in relation to Figure 4.

[0017] Figure 1 is a block diagram of an exemplary system 100 for hardware-based stochastic rounding of floating-point numbers. System 100 corresponds to computing devices such as desktop computers, laptop computers, servers, tablet devices, mobile devices, smartphones, wearable devices, augmented reality devices, virtual reality devices, network devices, and / or electronic devices. As illustrated in Figure 1, system 100 includes one or more memory devices, such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical disk drive, cache, one or more variations or combinations thereof, and / or any other suitable storage memory.

[0018] As illustrated in Figure 1, the exemplary system 100 includes one or more physical processors, such as a processor 110, which can correspond to one or more processors (for example, a host processor with a coprocessor, which may be a separate processor in some examples). The processor 110 generally represents any type or form of hardware implementation processing unit capable of interpreting and / or executing computer-readable instructions. In some examples, the processor 110 accesses and / or modifies data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, one or more examples of chiplets (e.g., smaller, and in some examples, more specialized processing units that can work together as a single chip), microprocessors, microcontrollers, Central Processing Units (CPUs), graphics processing units (GPUs), field-programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), system-on-chip (SoCs), coprocessors such as digital signal processors (DSPs), neural network engines (NNEs), accelerators, parts of one or more of these, one or more variations or combinations of these (e.g., host processor and coprocessor), and / or any other suitable physical processor(s).

[0019] In some embodiments, the term "instruction" refers to computer code that can be read and executed by a processor. Examples of instructions include, but are not limited to, macroinstructions (e.g., program code that requires a processor to decode into processor instructions directly executable by the processor) and micro-operations (e.g., low-level processor instructions that are decodable from macroinstructions and form part of a macroinstruction). In some embodiments, micro-operations correspond to the most basic operations achievable by a processor, and thus can be further organized into microinstructions (e.g., sets of micro-operations that are executed concurrently).

[0020] As further illustrated in Figure 1, processor 110 includes processing circuitry 112, multi-format operand instructions 114, and registers 116. Processing circuitry 112 corresponds to processing components, and in some examples, includes circuitry and / or instructions for floating-point number conversion operations and / or portions thereof, and further, in some examples, may correspond to and / or interface with a floating point unit (FPU) for performing floating-point operations. Multi-format operand instructions 114 correspond to circuitry and / or instructions for performing floating-point operations using operands in various floating-point formats. In some examples, multi-format operand instructions 114 may correspond to micro-operations that may be loaded into and / or hardwired to processing circuitry 112. Registers 116 correspond to local storage of processor 110, such as for temporarily holding data for processing. As will be described further below, processing circuitry 112 can directly perform floating-point operations using two operands without needing to convert either of the two operands to a common floating-point format.

[0021] Each of Figure 2A to Figure 2C illustrates a numeric format 200, a numeric format 202, and a numeric format 204, each corresponding to a floating-point format of different precision (e.g., bit width). For example, Figure 2A shows an exemplary 8-bit precision floating-point number format, Figure 2B shows an exemplary 16-bit precision floating-point number format, and Figure 2C shows an exemplary 32-bit precision floating-point number format.

[0022] A floating-point number corresponds to a real value represented by a significant digit and a floating radix point. For example, the decimal (real number) 432.1 can be obtained by moving (e.g., floating) the decimal radix point (e.g., decimal point, etc.) to get 4321 * 10 -1 , so a real value can be represented by an integer (mantissa or significand) scaled by an integer exponent of the base. Since computing systems store bit sequences that are easily converted to binary (e.g., base 2) numbers, computing systems often use a base-2 radix point. For example, 0.5 can be expressed as 1 * 2 -1 . Therefore, in the binary representation of a floating-point number, the real value Value can be represented by the following formula. Value=(-1) Sign* Normalized_Mantissa * 2 Exponent-Bias (Equation 1)

[0023] Sign can indicate whether the value is positive (e.g., Sign=0) or negative (e.g., Sign=1). Normalized_Mantissa can correspond to the mantissa normalized according to the floating-point number format (e.g., stored in the bit sequence). Non-zero binary numbers can have their mantissa always have a leading 1 by floating their base (e.g., "1.01"). Therefore, many floating-point number formats do not explicitly store this leading 1 so that it can be understood (e.g., when normalized). Exponent-Bias corresponds to the final exponent of the value after subtracting Bias from Exponent. Many floating-point number formats use bias to avoid using the sign bit (e.g., for negative exponents), which can further enable efficient handling between two floating-point numbers. Therefore, Exponent can correspond to the stored exponent value, and Bias can be a value defined for a particular floating-point number format. Furthermore, the floating-point number format can define how bits within an allocated bit width can be decoded or interpreted. Thus, certain bits can be reserved to represent the Sign, certain bits can be reserved to represent the Exponent, and certain bits can be reserved to represent the Mantissa, which may require normalization.

[0024] Referring to Figure 2A, numeric format 200 represents an example of an 8-bit floating-point number format (e.g., with a width of 8 bits or precision such as 1 / 4 precision). Numeric format 200 can define what each bit position in the 8-bit format represents. As illustrated in Figure 2A, one bit (e.g., bit 7) may correspond to the sign bit (e.g., Sign), four bits (e.g., bits 3-6 from least significant to most significant) may correspond to the exponent (e.g., Exponent), and three bits (e.g., bits 0-2 from least significant to most significant) may correspond to the mantissa. In other numeric formats, the number and / or order of bits for various elements may change. In addition, a bias (e.g., Bias) may be defined for numeric format 200. For example, the bias is 7, corresponding to the exponent in the range of -6 to 7, which is derived by subtracting the bias of 7 from the range of 1 to 14 for four bits (leaving "0" i.e., all 0s and "15" i.e., all 1s for special values). Bias can be based on the number of exponent bits. In some examples, bias allows a particular bit sequence (e.g., a bit sequence with an exponent that is all zeros, and other particular bit sequences that are all zeros, etc.) to represent special values ​​(e.g., non-normal values, positive / negative zeros, positive / negative infinity, undefined / not-a-number (NaN), etc.).

[0025] Figure 2B illustrates a numeric format 202 representing an example of a 16-bit floating-point number format (e.g., half-precision). As illustrated in Figure 2B, one bit (e.g., bit 15) may correspond to the sign bit (e.g., Sign), five bits (e.g., bits 10-14 from least significant to most significant) may correspond to the exponent (e.g., Exponent), and ten bits (e.g., bits 0-9 from least significant to most significant) may correspond to the mantissa. The bias can be based on the number of exponent bits, such as 15, and certain bit sequences can be further reserved as special values, as described herein. In other examples, numeric format 202 may have different numbers and / or orders of bits for various elements.

[0026] Figure 2C illustrates numeric format 204, representing an example of a 32-bit floating-point number format (e.g., single precision). As illustrated in Figure 2C, one bit (e.g., bit 31) may correspond to the sign bit (e.g., Sign), eight bits (e.g., bits 23-30 from least significant to most significant) may correspond to the exponent (e.g., Exponent), and 23 bits (e.g., bits 0-22 from least significant to most significant) may correspond to the mantissa. The bias can be based on the number of exponent bits, such as 127, and certain bit sequences can be further reserved as special values, as described herein. In other examples, numeric format 204 may have different numbers and / or orders of bits for various elements.

[0027] In some examples, system 100 (e.g., processor 110) can be configured with circuits and / or instructions for specific floating-point number formats. For example, certain elements of a numeric format (e.g., bias, sequence of special values, etc.) can be incorporated into circuits and / or instructions without explicitly storing such elements in the floating-point number (e.g., bit sequence) itself. In some embodiments, processor 110 can include circuits and / or instructions for each supported floating-point number format (e.g., processing circuit 112 and / or multi-format operand instruction 114 can accommodate multiple iterations).

[0028] In some cases, the processor 110 can be configured to accept and process values ​​in various floating-point formats. As described above, non-floating-point formats can have similar precision (e.g., bit width) for various elements, but can have different numbers of bits and / or bit order. For example, numeric format 200 has four exponent bits followed by three mantissa bits. Another similar bit-width format can be defined with three exponent bits followed by four mantissa bits. Furthermore, even if the numeric formats are essentially the same, the bias values ​​may differ. Therefore, when the processor 110 processes two operands in different floating-point formats, the processor 110 can process these two operands in the same format by converting the first operand to the format of the second operand. In some cases, the processor 110 converts the operands to a format that is directly configured for processing by the processor 110.

[0029] However, there may be cases where it is desirable to avoid converting values ​​between different numeric formats. For example, processor 110 can receive and process data from a first source (e.g., as a first operand) and receive / process data from a second source (e.g., as a second operand). The first source may correspond to a first dataset having data encoded in a first numeric format, and the second source may correspond to a second dataset having data encoded in a second numeric format. In some cases, processor 110 can pre-convert the second dataset to the first numeric format, but such pre-conversion may be unavailable (e.g., for dynamically generated data) or may result in high latency. Alternatively, processor 110 can convert the second operand before each operation, but this may result in undesirable latency, such as in common repetitive operations.

[0030] Figure 3 illustrates a processor 310 (corresponding to processor 110) that can directly perform operations with operands of various numerical formats. Figure 3 includes a first operand register 332 (corresponding to an iteration of register 116), a second operand register 334 (corresponding to another iteration of register 116), an output register 336 (corresponding to yet another iteration of register 116), a floating-point unit 312 (corresponding to processing circuit 112), and a multi-format operand instruction 314 (corresponding to multi-format operand instruction 114).

[0031] The first operand register 332 may be configured to load values ​​in a first floating-point number format. In some embodiments, the first operand register 332 may be configured to load data from a first source, such as a specific device, component, and / or a portion of memory (e.g., memory 120). Furthermore, in some embodiments, the first floating-point number format is linkable to the first source, while in other embodiments, the first floating-point number format may be identified at load time. Similarly, the second operand register 334 may, in some embodiments, be configured to load values ​​in a second floating-point number format that may correspond to a second source. In some examples, the first and second floating-point numbers may vary. Furthermore, in some examples, the first and second floating-point numbers may correspond to different numeric formats with similar precision (e.g., bit width), while in other examples, they may correspond to different precisions.

[0032] The floating-point unit 312 can perform floating-point operations on the values ​​stored in the first operand register 332 and the second operand register 334. The floating-point unit 312 can be loaded with instructions (e.g., microoperations) for performing various floating-point operations, such as arithmetic operations with floating-point numbers, as operands, or it can be hardwired in other ways (e.g., as circuitry). Rather than converting the values ​​stored in the first operand register 332 and / or the second operand register 334, as described herein, the floating-point unit 312 can directly use the values ​​in their respective original forms.

[0033] When decoding floating-point operations into microoperations, the floating-point unit 312 can select appropriate microoperations (e.g., multi-format operand instructions 314) for the operation based on first and second floating-point number formats. In some examples, the multi-format operand instructions 314 may include, or be selected from, multiple sets of microoperations corresponding to possible combinations of numeric formats as operands. For example, any combination of selecting input and output formats (e.g., at least two formats for two operands and at least one output format) for all floating-point number formats that the floating-point unit 312 can support can be represented by a set of microoperations further applied to each supported floating-point unit operation. In some embodiments, different operand orders may require different sets of microoperations. The floating-point unit 312 can identify floating-point number formats (e.g., based on the source of the value and / or, in some examples, based on register identification). Therefore, the floating-point unit 312 can use an appropriate set of microoperations (e.g., multi-format operand instructions 314) from among the possible combinations that directly use the values ​​from the first operand register 332 and the second operand register 334 without requiring intermediate conversion operations.

[0034] A set of microoperations may include microoperations to complete floating-point operations. In some examples, the multi-format operand instruction 314 may include microoperations to normalize the sign, exponent, and mantissa of two operands, and further may combine the sign, exponent, and / or mantissa according to the operation to produce an output result that can be stored in the output register 336. In some examples, the output result may be in one of the operand formats, such as a first floating-point format or a second floating-point format, while in other examples, the output result may be in another desired floating-point format. Thus, in some embodiments, the multi-format operand instruction 314 may include instructions (e.g., microoperations) that enable the output to be generated in a desired floating-point format.

[0035] In addition, in some embodiments, the floating-point unit 312 can perform operations using three operands. For example, the floating-point unit 312 can read a third operand from a third operand register 333 (corresponding to register 116) in a third floating-point format (which may be similar to and / or different from the format of the first or second operand). In some examples, the multi-format operand instruction 314 can include microoperations to perform operations using the three operands directly. In some examples, the floating-point unit 312 can perform operations using three operands by dividing them into suboperations, such as a primary operation that directly uses the first and second operands to produce an initial result, and a secondary operation that directly uses the third operand and the initial result (e.g., as an operand) to produce a final output result.

[0036] Furthermore, although not shown in Figure 3, the floating-point unit 312 can be configured to perform operations on any number of input operands in any numeric format (e.g., any floating-point number format, integer number format, etc., with similar or different precisions) and to produce one or more output results in any numeric format. In other words, the multi-format operand instruction 314 can include microoperations to directly perform arithmetic / logical operations on any desired number of operands in any desired combination of numeric formats to produce any desired number of desired output results in any desired combination of numeric formats.

[0037] Figure 4 is a flowchart of an exemplary computer execution method 400 for hardware-based multi-format operand processing. The steps shown in Figure 4 can be performed by any suitable circuit, device and / or computing system, including the system(s) illustrated in Figure 1 and / or Figure 3. In one example, each of the steps shown in Figure 4 represents an algorithm whose structure includes and / or is represented by multiple sub-steps, examples of which are provided in more detail below.

[0038] As illustrated in Figure 4, in step 402, one or more of the systems described herein identify a first numeric format for a first operand of an operation and a second numeric format for a second operand of an operation, which is a different numeric format having similar precision. For example, processing circuit 112 can identify the numeric formats for the first and second operands of an operation. The identified numeric formats may be different floating-point formats having similar precision. In other examples, the numeric formats may correspond to other scalar numeric formats, such as integer formats.

[0039] In step 404, one or more of the systems described herein select a set of instructions that perform operations using the first and second numeric formats, based on the first and second numeric formats. For example, processing circuit 112 may select a multi-format operand instruction 114 that performs operations using two identified floating-point formats.

[0040] The systems described herein can perform step 404 in various ways. In some examples, the selection of a set of instructions is based on a first numeric form and a second numeric form. In some examples, the selection of a set of instructions is based on a first source for the first operand and a second source for the second operand.

[0041] As illustrated in Figure 4, in step 406, one or more of the systems described herein perform an operation and produce an output result by directly using the first and second operands together with the selected instruction set. For example, the processing circuit 112 can perform an operation by directly using the first and second operands with the multi-format operand instruction 114.

[0042] The systems described herein can perform step 406 in various ways. In one example, performing the operation may further include normalizing the first sign, first exponent, and first mantissa of the first operand based on a first numeric format, and normalizing the second sign, second exponent, and second mantissa of the second operand based on a second numeric format. The processing circuit 112 may further perform the operation and produce an output result by combining the first sign and the second sign, the first mantissa and the second mantissa, and the first exponent and the second exponent according to the operation. Furthermore, in some examples, the processing circuit 112 may further perform the operation and produce an output result by directly using a third operand of a third numeric format. For example, as described above, the processing circuit 112 can use the multi-format operand instruction 114 to have three operands of any combination of numeric formats. Alternatively, as described above, the processing circuit 112 can perform a primary operation to generate an initial result by directly using the first operand of the first numerical form and the second operand of the second numerical form, and then perform a secondary operation to generate an output result by directly using the third operand of the third numerical form and the initial result.

[0043] As mentioned above, specific arithmetic operations such as D = C + A × B are commonly used (e.g., for address translation), where D is the final destination, C is the partial sum, and A and B are the operands. Typically, operands A and B are of the same form in the operation, such as FP32, BF8, and FP8. However, certain forms are variations of each other; for example, BF8 and FP8 are both commonly used 8-bit floating-point formats, but many architectures only support one 8-bit floating-point format. Therefore, in some architectures, if the operands are not of the same form, the operation cannot be performed, or one or both operands must be converted to a format suitable for the operation. For example, for a dataset for inference or training, half of the dataset values ​​are in BF8 (e.g., generated by a first data source or device, or provided in another way), and the other half are in FP8 (e.g., generated by a second data source or device, or provided in another way), so half of the values ​​need to be converted / stored first.

[0044] The systems and methods described herein enable a processor to complete operation in a mixed operand format for related variants of the same width (e.g., BF8 and FP8). For example, in the case of BF8 and FP8, the provided systems and methods enable four possible combinations of A and B for the two formats (e.g., BF8 and BF8, BF8 and FP8, FP8 and FP8, FP8 and BF8), and in some embodiments, if bias mode switching can be used for floating-point formats, the number of combinations may double to eight. By covering all combinations, the systems and methods described herein offer greater flexibility in terms of formats. Thus, the systems and methods described herein enable the use of operands of different formats without the need to first convert one or both operands. This is advantageous in that it enables faster convergence, overall reduction in power consumption, increased efficiency, etc.

[0045] As described above, the computing devices and systems described and / or illustrated herein represent a broad range of computing devices or systems of any type or form that enable the execution of computer-readable instructions. In their most basic configurations, each of these computing devices includes at least one memory device and at least one physical processor.

[0046] In some instances, the term “memory device” generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device stores, loads, and / or maintains one or more modules and / or circuits described herein. Examples of memory devices include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drives (HDD), solid-state drives (SSD), optical disk drives, caches, one or more variations or combinations thereof, or any other suitable storage memory.

[0047] In some cases, the term “physical processor” generally refers to any type or form of hardware implementation processing unit that interprets and / or executes computer-readable instructions. In one example, a physical processor accesses and / or modifies one or more modules stored in the memory devices described above. Examples of physical processors include, but are not limited to, microprocessors, microcontrollers, central processing units (CPUs), field-programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), systems-on-a-chip (SoCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), one or more of these, one or more variations or combinations of these, or any other suitable physical processor.

[0048] In some embodiments, the term “computer-readable medium” generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable mediums include, but are not limited to, transmission media such as carrier waves, as well as non-transient media such as magnetic storage media (e.g., hard disk drives, tape drives, floppy disks), optical storage media (e.g., Compact Disks (CDs), Digital Video Disks (DVDs), Blu-ray Discs), electronic storage media (e.g., solid-state drives and flash media), and other distribution systems.

[0049] The process parameters and steps described and / or illustrated herein are given only as examples and may be changed as desired. For example, the steps illustrated and / or described herein are illustrated or described in a particular order, but these steps do not necessarily have to be performed in the illustrated or described order. Various exemplary methods described and / or illustrated herein may omit one or more of the steps described or described herein, or may include additional steps in addition to those disclosed.

[0050] The above description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to limit to any specific form disclosed. Many modifications and variations are possible without departing from the spirit and scope of this disclosure. The embodiments disclosed herein should be considered in all respects to be exemplary and not restrictive. In determining the scope of this disclosure, the appended claims and their equivalents should be referenced.

[0051] Unless otherwise stated, the terms “connected to” and “coupled to” (and their derivatives) as used herein and in the claims should be interpreted to allow both direct and indirect connections (i.e., connections through other elements or components). In addition, the terms “a” or “an” as used herein and in the claims should be interpreted to mean “at least one of.” Finally, for ease of use, the terms “including” and “having” (and their derivatives) as used herein and in the claims are interchangeable with the term “comprising” and have the same meaning.

Claims

1. It is a device, The system includes a processing circuit configured to perform operations on the first operand having the first numerical format and the second operand having the second numerical format by directly using the first operand having the first numerical format and the second operand having the second numerical format, thereby generating an output result. device.

2. The first numerical format and the second numerical format correspond to different numerical formats among a plurality of numerical formats having similar precision, and the processing circuit is configured to perform the operation for each of the plurality of possible combinations of the first operand and the second operand and the plurality of numerical formats. The device according to claim 1.

3. The processing circuit includes a circuit for performing the operation for each of the plurality of possible combinations. The device according to claim 2.

4. The processing circuit includes an instruction set for performing the operation for each of the plurality of possible combinations, The device according to claim 2.

5. The processing circuit is configured to decode the operation into a microoperation using the first numerical format and the second numerical format. The device according to claim 2.

6. The microoperation includes a microoperation that normalizes the first sign, first exponent, and first mantissa of the first operand based on the first numerical format, and a microoperation that normalizes the second sign, second exponent, and second mantissa of the second operand based on the second numerical format. The device according to claim 5.

7. The microoperation includes a microoperation for generating the output result by combining the first sign and the second sign, the first mantissa and the second mantissa, and the first exponent and the second exponent, in accordance with the operation. The device according to claim 6.

8. The processing circuit is configured to perform the operation on the third operand having the third numerical format by directly using the third operand having the third numerical format, and to generate the output result. A device according to any one of claims 1 to 7.

9. The aforementioned processing circuit is To perform a primary operation using the first operand of the first numerical format and the second operand of the second numerical format directly to generate an initial result, The output result is generated by performing a secondary operation using the third operand of the third numerical format and the initial result directly, The system is configured to perform the operation using the first operand, the second operand, and the third operand. The device according to claim 8.

10. It is a system, Memory and A processing circuit is provided, The aforementioned processing circuit is For operation, a first operand having a first numerical format and a second operand having a second numerical format are received from the memory, Decoding the aforementioned operation into microoperations using the first numerical format and the second numerical format, The operation is performed via the decoded microoperation that directly uses the first operand in the first numerical format and the second operand in the second numerical format to generate an output result, It is configured to do, system.

11. The first and second numerical formats mentioned above correspond to different numerical formats among a plurality of numerical formats having similar precision. The system according to claim 10.

12. The processing circuit is configured to decode the operation into a microoperation by selecting the microoperation corresponding to any of the multiple possible combinations of the multiple numerical formats of the first operand and the second operand. The system according to claim 11.

13. The processing circuit is configured to select the microoperation based on the first source of the first operand and the second source of the second operand. The system according to claim 12.

14. The aforementioned micro-operation is, Based on the first numerical format, the first sign, first exponent, and first mantissa of the first operand are normalized, Based on the second numerical format, the second sign, second exponent, and second mantissa of the second operand are normalized, In accordance with the above operation, the first sign and the second sign, the first mantissa and the second mantissa, and the first exponent and the second exponent are combined to generate the output result, Including microoperations to perform, The system according to claim 10.

15. The processing circuit is configured to perform the operation on the third operand having the third numerical format by directly using the third operand having the third numerical format, and to generate the output result. A system according to any one of claims 10 to 14.

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