System and method for interleaved power converters

Abstract

Disclosed is an interleaved power conversion system and method comprising an interleaved power conversion module and a control system. The conversion module includes a plurality of DC link nodes, a first transistor pair and a second transistor pair coupled between the DC link nodes, an LC filter circuit, and a plurality of alternating current (AC) nodes. The control system comprises a central controller and one or more local controllers. Each local controller receives a corresponding reference target from the central controller, generates a variable frequency soft-switching (VFSS) control signal to drive the first transistor pair and outputs a first AC signal, generates a phase-shifted VFSS control signal to drive the second transistor pair and outputs a second AC signal that is phase-shifted relative to the first AC signal. The interleaved power conversion module outputs an interleaved signal via the LC filter circuit, which includes the first AC signal interleaved into the second AC signal.

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application claims the benefit of U.S. Provisional Application No. 63 / 544,739, filed on 18 October 2023, entitled “System and Method for Interleaved Power Converters,” all of which are incorporated herein by reference.

[0002] (Statement regarding research funded by the federal government) Not applicable. [Background technology]

[0003] Various types of power converters are manufactured and used in numerous industries and applications. Examples of power converters include AC-to-DC rectifiers, DC-AC inverters, and DC-DC converters. AC-to-DC rectifiers (also called AC / DC rectifiers) convert alternating current (AC) power to direct current (DC) power. DC-to-AC inverters (also called DC / AC inverters) convert direct current (DC) power to alternating current (AC) power. Power converters can be used for a variety of purposes, such as rectifying DC power from an AC power source to charge batteries, converting DC power from a battery to AC power to drive motors, or supplying AC power to an AC power grid. Furthermore, power converters can be installed in or connected to various devices such as electric vehicles, engine generators, and solar panels. [Overview of the project]

[0004] Power converters are described by characteristics such as power conversion efficiency, power density, and cost. Generally, power converters with high power efficiency, high power density, and low cost are desirable. High-efficiency power converters can convert power without significant energy loss (e.g., AC to DC, DC to AC, and / or DC to DC). Low-efficiency power converters experience significant energy loss during power conversion. Such energy loss can manifest, for example, as heat generated by the power converter during power conversion. The power efficiency of power converters, inductors, or other electronic components is expressed as a percentage between 0 and 100%. The formula JPEG2026536541000002.jpg2186 is used to determine the power input to and power output from the component. A power converter with high power density is a power converter in which the ratio of the power output by the power converter to the physical space occupied by the power converter is high. Power density is, It can be calculated using the formula JPEG2026536541000003.jpg21107.

[0005] In many industries that incorporate power converters, energy costs, including monetary and environmental costs, remain significant factors. Therefore, even a slight improvement in the power efficiency of power converters (e.g., around 0.1%) has a significant impact and is highly desirable. Similarly, reducing the materials and size of power converters also has a significant impact and is highly desirable as it leads to cost reductions and a reduction in installation space in systems that incorporate power converters.

[0006] Some of the embodiments disclosed herein address these or other problems. For example, some of the embodiments disclosed herein relate to interleaved power converters. By making the power converter interleaved, it is ultimately possible to improve the efficiency and / or power density of the power converter.

[0007] In one embodiment, an interleaved power conversion system is provided. This system includes an interleaved power conversion module and a control system. The interleaved power conversion module includes a plurality of direct current (DC) link nodes, a first transistor pair and a second transistor pair coupled between the DC link nodes, an LC filter circuit, and a plurality of alternating current (AC) nodes. The control system controls the interleaved power conversion module and comprises a central controller and local controllers. The central controller is configured to generate a reference target based on the detection characteristics of the interleaved power conversion module. The local controllers are configured to receive the reference target and, based on the reference target and the detection characteristics, generate a variable frequency soft switching (VFSS) control signal to drive the first transistor pair that outputs a first AC signal, and based on the reference target and the detection characteristics, generate a phase-shift VFSS control signal to drive the second transistor pair that outputs a second AC signal that is phase-shifted relative to the first AC signal. The interleaved power conversion module outputs an interleaved signal that includes the first AC signal interleaved with the second AC signal via the LC filter circuit.

[0008] In one embodiment, a method for interleaved power conversion is provided. The method includes a local controller receiving a reference target from a central controller based on the detection characteristics of an interleaved power conversion module, the interleaved power conversion module comprising a plurality of direct current (DC) link nodes, a first transistor pair and a second transistor pair coupled between the DC link nodes, an LC filter circuit, and a plurality of alternating current (AC) nodes. The method further includes generating a variable frequency soft switching (VFSS) control signal to drive the first transistor pair that outputs a first AC signal based on the reference target and the detection characteristics, and generating a phase-shift VFSS control signal to drive the second transistor pair that outputs a second AC signal that is phase-shifted relative to the first AC signal based on the reference target and the detection characteristics. The method further includes outputting an interleaved signal via the LC filter circuit, which includes the first AC signal interleaved into the second AC signal.

[0009] The above and other aspects and advantages of this disclosure will become apparent from the following description. The description will refer to the accompanying drawings, which constitute part of this specification. The drawings show one or more exemplary embodiments. However, these embodiments do not necessarily represent the entire scope of the invention; therefore, the claims and this specification should be referred to in order to interpret the scope of the invention. In the following description, the same reference numerals will be used in each figure to refer to the same part. [Brief explanation of the drawing]

[0010] [Figure 1A-1B] Figure 1A shows a half-bridge power converter. Figure 1B shows the inductor current waveform of the half-bridge power converter in Figure 1A. [Figure 2] This figure shows a power conversion system according to several embodiments. [Figure 3A-3B] Figure 2 shows an example configuration of the power conversion system. [Figure 3C] Figure 2 shows an example configuration of the power conversion system. [Figure 4A] This is a control system diagram implemented by a power converter (for example, the power converter in Figure 1, Figure 3A, Figure 3B, or Figure 3C) according to some embodiments. [Figure 4B] This is a control system diagram implemented by a power converter (for example, the power converter in Figure 1, Figure 3A, Figure 3B, or Figure 3C) according to some embodiments. [Figure 5A-5B] This figure shows an example of a switching circuit for one or more interleaved power conversion modules of a power converter according to several embodiments. [Figure 5C-5D] This figure shows an example of a switching circuit for one or more interleaved power conversion modules of a power converter according to several embodiments. [Figure 5E-5F] This figure shows an example of a switching circuit for one or more interleaved power conversion modules of a power converter according to several embodiments. [Figure 5G-5H] This figure shows an example of a switching circuit for one or more interleaved power conversion modules of a power converter according to several embodiments. [Figure 6A-6B] Figure 6A shows inductor current waveforms for interleaved power conversion modules according to several embodiments. Figure 6B shows soft switching operating regions and constant power curves for interleaved power conversion modules according to several embodiments. [Figure 7] This figure shows inductor current plots, phase current plots, and frequency plots for interleaved power conversion modules according to several embodiments. [Figure 8] This figure shows an interleaved power conversion method according to several embodiments. [Figure 9] This figure shows a model of a coupled inductor interleaved power converter according to several embodiments. [Figure 10] Figure 4B shows an example of a local controller that implements model predictive control according to several embodiments. [Modes for carrying out the invention]

[0011] The following description and accompanying drawings illustrate one or more embodiments. These embodiments are not limited to the specific details described herein and can be modified in various ways. Furthermore, other embodiments not described herein may also exist. Functions performed by multiple components can also be integrated and performed by a single component. Similarly, functions described herein as being performed by one component can also be performed in a distributed manner by multiple components. Furthermore, a component described as performing a particular function can also perform additional functions not described herein. For example, a device or structure "configured" in a particular way is at least configured in that way, but can also be configured in ways not described herein.

[0012] As used in this application, "non-volatile computer-readable media" encompasses all computer-readable media that do not contain transient propagating signals. Therefore, non-volatile computer-readable media can include, for example, hard disks, CD-ROMs, optical storage devices, magnetic storage devices, ROM (read-only memory), RAM (random access memory), register memory, processor cache, or any combination thereof.

[0013] Furthermore, the expressions and terminology used herein are for illustrative purposes only and should not be considered restrictive. For example, “includes,” “equips,” “contains,” “has,” and their variations as used herein are intended to encompass the items listed below and their equivalents, as well as any additional items. In addition, the terms “connected” and “joined” are used broadly and include both direct and indirect connections and combinations, and may refer to physical or electrical connections or combinations. Furthermore, the expression “and / or” used with two or more items is intended to cover the individual items and both items together. For example, “a and / or b” is intended to cover a (but not b), b (but not a), and a and b.

[0014] In active power converters, power switching elements (also called transistors) are switched on / off at high frequencies in response to control signals to implement the conversion. Control techniques for power switching elements are referred to as hard switching or soft switching. In hard switching, the current and voltage in the power switching element become relatively high during the transition when switching from an on state to an off state, or from an off state to an on state. This scenario results in significant power loss during the transition. As the switching frequency increases, power loss and electromagnetic interference (EMI) can increase, as each additional switching event generates power loss and noise. Therefore, when controlling power switching elements, hard switching should generally be avoided at all operating points of the converter to prevent or mitigate the problems of large switching losses and EMI.

[0015] Soft switching refers to a switching control technique that controls the voltage of a power switching element to be zero (or close to zero) at the point of switching it on or off. In some cases, hard switching (as opposed to switching it off) accounts for the majority of switching losses. Therefore, in some cases, soft switching, which enables turning the switch on at zero voltage, becomes more important to reduce power loss and EMI noise.

[0016] Referring to Figure 1A, the power converter 100 is shown. In the power converter 100, the inductor current i before the upper switch is turned on L When the polarity is reversed (to a sufficient extent), a zero-voltage turn-on (soft switching) occurs. This can be achieved by a large current ripple in the inductor. If the peak-to-peak ripple is greater than twice the average output current, this ripple will reverse the polarity in each cycle, as shown in Figure 1B. To achieve this situation, a controller that controls the switching of the top and bottom switching elements controls the output current i o As the value changes, this guarantees that it is true. This can be achieved by always generating a large ripple, but excessive ripple increases resistive losses. Therefore, generally, the ripple needs to be controlled to a size sufficient to ensure soft switching, but not larger.

[0017] Generally, controllers cannot control the rise and fall slopes of the current because these slopes are fixed by the input and output voltages that the controller does not select. However, controllers can adjust the switching frequency. Lowering the frequency allows for longer rise and fall times of the current, increasing the ripple amplitude. This feature allows the controller to maintain the desired ripple at all operating points. An example waveform is shown in Figure 1B. The solid sinusoidal curve represents the average inductor current (average i L) and after the ripple is removed by the filter, at the output node, i o is recognized. As illustrated, the actual inductor current i L crosses the x-axis by a certain amount in each cycle to ensure soft switching.

[0018] Zero-voltage switching occurs during the dead time when both switches are off and the current is reversed. During this period (when the average current is positive), the inductor current i L charges the output capacitance of the lower switch and discharges the output capacitance of the upper switch. When the capacitance of the upper switch is completely discharged, the voltage across the upper switch becomes zero, and the upper switch can be turned on without loss. When the average current is negative, the same process can occur, but the upper switch and the lower switch swap roles, and the lower switch is turned on at zero voltage.

[0019] The switching frequency for realizing such zero-voltage switching can be calculated from the shape of the current waveform. When the switching frequency is derived, it is as follows. [Formula] Here, i o is the output current, α is the ripple amplitude, which is always a value greater than 2 (for example, 2.2 to 2.4 is common), and αI o =Δi L which is the peak-to-peak ripple of the inductor current. The controller that drives the switches implements this formula (for example, to determine f SW ) to control the switching of the switches at the determined switching frequency f SW .

[0020] The maximum and minimum switching frequencies of f SW have practical limits. For example, the switching frequency f SWThe upper limit of the switching frequency can be set by losses. High-speed switching with low current reduces resistive losses but increases switching losses. At certain frequencies, the additional switching losses due to high-speed switching are greater than the reduction in resistive losses. Another upper limit on the switching frequency is due to the dead time when both switches are off. At high frequencies and high or low duty cycles, the average switch node voltage can be distorted.

[0021] Switching frequency f SW The lower limit may be set by the resonant frequency of the output LC filter. For example, the control equation can assume that the current waveform is triangular. If the switching frequency approaches the resonant frequency too closely (approximately twice as high), the triangular shape of the current waveform begins to appear as sinusoidal segments (with rounded peaks and troughs). When this occurs, the converter may cease to function properly.

[0022] Lowering the switching frequency increases the ripple amplitude, and as a result, the average inductor current (average i L This increases the average inductor current. This average inductor current is observed at the load behind the output filter. Therefore, the minimum switching frequency also corresponds to the maximum load current. If this limit is too low for the desired implementation of a particular converter, there are several options.

[0023] First, it is possible to reduce the inductance of an inductor. This reduction in inductance increases the slope of the current waveform, increases the ripple at a given frequency, and consequently increases the output current. However, when inductance is reduced, the resonant frequency also increases proportionally to the square root of the inductance, thus diminishing the benefit. This has the effect of increasing the switching frequency at all operating points, potentially reducing overall efficiency. Therefore, there is a limit to the amount of inductance that can actually be reduced.

[0024] Another option for reducing the minimum switching frequency and, consequently, increasing the maximum load current, is to implement an interleaved power converter. In an interleaved power converter, the outputs of at least one pair of transistors are typically interleaved with the outputs of at least another pair of transistors. To generate the interleaved outputs, the control signals to the transistor pairs can be phase-shifted relative to each other.

[0025] In converter design, the interleaved configuration can be counterintuitive because, generally, it is desirable to minimize ripple in the inductor. However, to achieve soft switching, the ripple must exceed a certain level. Therefore, the interleaved concept presented here can be configured to maintain sufficient current ripple in the inductor at each operating point to maintain soft switching, thereby (primarily) canceling out the ripple in the capacitor.

[0026] Various converter circuit topologies that enable the control and generation of such interleaved outputs are provided herein. Thus disclosed herein are systems and methods relating to interleaved power converters, also called voltage converters, which can provide power conversion with various advantages such as improved power efficiency, improved power density, and / or reduced cost.

[0027] Figure 2 shows a power conversion system 100 according to several embodiments. The power conversion system 100 includes a control system 105, a first DC power supply 110, a power converter 115, an AC load 130, and one or more sensors 140. The control system 105 includes a central controller 150 with an electronic processor 155 and memory 157, and also, in some embodiments, optionally includes one or more local controllers 160, each having an electronic processor 165 and memory 167. The power conversion system 100 and other power conversion systems provided herein may be non-isolated power conversion systems. That is, the power conversion system may be connected to an AC power supply (e.g., a single-phase or three-phase power grid) or an AC load (e.g., a single-phase or three-phase motor) without a transformer. The use of transformers is common in electrical circuits to ensure isolation between the power converter and the AC power supply or load. However, such transformers can result in reduced efficiency, increased size, or increased volume for the power converter. Therefore, the power conversion systems provided herein may be non-isolated (also called transformerless) for the purpose of improving the efficiency and / or reducing the size of the power conversion system. Since the power converter does not have isolation provided by a transformer, the power converter may have additional features to prevent unwanted signals or currents (e.g., leakage currents) from being transmitted between the power converter and other circuit components (e.g., DC power supplies, DC loads, AC power supplies, AC loads, and other structures that contact or support the power converter). These additional features may include LC filters, zero-sequence control of common-mode voltage, harmonic injection, model predictive control, variable frequency critical soft switching, etc. However, in some examples, a transformer is used to couple one of the disclosed power converters to other circuit components and provide isolation.

[0028] Generally, during operation, the control system 105 uses a control signal (e.g., a pulse-width modulated (PWM) signal) to control the power switching elements of the power converter 115, converting power from the DC power supply 110, which functions as a power source, to the AC load 130, which functions as a load. In some examples, the power conversion system 100 operates as a rectifier, and the control system 105 uses a control signal (e.g., a PWM signal) to control the power switching elements of the power converter 115, converting power from the AC load 130, which functions as a power source, to the DC power supply 110, which functions as a load. In some examples, the power conversion system 100 operates as a DC-DC converter, and the control system 105 uses a control signal (e.g., a PWM signal) to control the power switching elements of the power converter 115, converting power from the DC power supply 110, which functions as a power source, to the DC load (located in the position of the AC load 130 in Figure 2).

[0029] In some examples, the DC power supply 110 is a battery. In other examples, the DC power supply 110 may be a capacitor, an ultracapacitor, a DC power supply from a rectified AC power source (e.g., AC grid power converted to DC power by a diode bridge rectifier), or similar. In some examples, the AC load 130 may be an electric (AC) motor, an AC power grid, or similar. The AC load 130 may be a single-phase AC load, a three-phase AC alternating current load, or an AC load of any other number of phases.

[0030] The DC power supply 110 is coupled to the first (AC) side or section of the power converter 115, and the AC load 130 is coupled to the second (DC) side or section of the power converter 115. The first side may also be called the input side or DC side of the power converter 115. The second side may also be called the input side or AC side of the power converter 115. In some embodiments, the AC side of the power converter 115 may be an AC side having single-phase AC power, three-phase AC power, or AC power of a different number of phases.

[0031] In some embodiments, the power converter 115 operates at high DC voltage levels. For example, when operating, the DC side of the power converter 115 has a DC voltage (e.g., between the input terminals of the power converter 115) in the range of at least 200V, at least 600V, at least 800V, at least 1000V, at least 1200V, between 200V and 1200V, between 600V and 1200V, between 800V and 1200V, or other ranges. Such high DC voltage levels may be desirable in certain situations, such as in some electric vehicles. For example, some current electric vehicles (e.g., passenger cars and hybrid electric vehicles) operate with DC bus voltages between approximately 200V and 400V. This DC bus voltage for passenger electric vehicles may increase in the future. Furthermore, some current electric vehicles (e.g., Class 4-8, off-road vehicles, or other large electric vehicles) are capable of operating with DC bus voltages exceeding 1000V.

[0032] The multiple possible sensors 140 include, for example, one or more current sensors and / or one or more voltage sensors. For example, sensor 140 may include corresponding current sensors and / or voltage sensors for monitoring the current and / or voltage of one or more DC load sources 110, each phase of an AC load 130, or other nodes or components of the power converter 115. For example, when an interleaved power converter 115 includes LC filters in each phase or leg of the converter, sensor 140 may include one or more current sensors for each phase or leg to detect the current in each phase or leg (e.g., at the inductors and / or output nodes of each phase or leg). In some embodiments, additional or fewer sensors 140 are included in the system 100. For example, sensor 140 may also include one or more vibration sensors, temperature sensors, etc. In some examples, the control system 105 does not directly detect the characteristics (e.g., current or voltage) of the power converter 115, but rather infers those characteristics. Sensor 140 can provide the control system 105 with sensor data that indicates the detection characteristics of system 100. Thus, such sensor data can indicate the electrical operating characteristics of system 100. In some examples, the control system 105 infers or estimates characteristics (e.g., current or voltage) at one or more nodes of the power converter 115 based on sensor data from sensor 140, which detects different types of characteristics or different components, rather than directly detecting the characteristics. However, unless otherwise specified, detected characteristics can refer to either directly detected characteristics or characteristics inferred from other detected characteristics.

[0033] The input-output (I / O) interface 142 is configured to have or receive inputs from one or more input units (e.g., one or more buttons, switches, touchscreens, keyboards, etc.) and / or to have or provide outputs to one or more output units (e.g., LEDs, display screens, speakers, haptic generators, etc.). Other electronic devices and / or users can communicate with the system 100, in particular the control system 105, via the I / O interface 142. For example, the control system 105 can receive commands for the power converter system 100 (e.g., from a user or other device) indicating target torque, target speed, target power level, conversion type, etc. The control system 105 can then drive the power converter 115 to obtain the target values ​​and / or conversion type indicated by the commands.

[0034] The control system 105 generally monitors the system 100, including the power converter 115 (for example, based on sensor data from sensor 140), receives commands (for example, via input / output interface 142), and controls the power switching elements of the power converter 115 by transmitting control signals (e.g., pulse-width modulation (PWM) signals) to convert power (for example, according to sensor data and / or commands). In some embodiments, the control system 105 is a cascaded control system including a central controller 150 and one or more local controllers 160. The cascaded control system allows for real-time communication (e.g., per control cycle) of monitoring information (e.g., sensor data) and control information between the central controller 150 and one or more local controllers 160. In some examples, each of the local controllers 160 performs model predictive control (MPC) or other control schemes (e.g., PID control, PI control, etc.). In some cases, the central controller implements non-MPC control schemes such as proportional integral derivative (PID) control or proportional integral (PI) control.

[0035] Each controller in the control system 105, including the central controller 150 and the local controllers 160, is an electronic controller including an electronic processor. Such electronic controllers may further include memory (e.g., memory 157 or 167). The memory is, for example, one or more of read-only memory (ROM), random access memory (RAM), or other non-volatile computer-readable media. The electronic processors 155, 165, among other things, receive instructions and data from memory 157, 167 and are configured to execute the instructions described above, for example, including the processes described herein and to perform the functions of the associated controllers described herein. For example, the memory may include control software. In some embodiments, instead of, or in addition to, executing software from memory to perform the functions of the controllers described herein, the electronic processor includes one or more hardware circuit elements configured to perform some or all of these functions. Additionally, while certain controllers, electronic processors, and memories may each be referred to as single units, in some embodiments one or more of these components are distributed components. For example, in some embodiments, the electronic processor comprises one or more microprocessors and / or hardware circuit elements. In some examples, both the central controller 150 and the local controller 160 are implemented by a shared electronic processor (e.g., electronic processor 155).

[0036] Figures 3A-3C show an exemplary configuration of the power conversion system 100, identified as power converters 300, 330, and 360, respectively. In other examples, the power conversion system 100 is implemented in a different configuration. In Figures 3A-3C, the DC power supply 110, sensor 140, and input / output unit 145 are not shown for simplification of the diagram. In Figure 3A, power converter 300 is a half-bridge single-phase converter. Power converter 300 comprises a central controller 150, a local controller 160, and an interleaved power converter 115. In this example, the interleaved power converter 115 includes one interleaved power converter module 305. In this example, the interleaved power converter module 305 includes a half-bridge single-phase converter circuit and is coupled to two terminals of a (single-phase) AC load 130. The interleaved power conversion module 305 can be implemented, for example, as one of the switching circuits shown in Figures 5A-5H, which will be described in detail later.

[0037] In Figure 3B, the power converter 330 is a full-bridge single-phase converter. The power converter 330 comprises a central controller 150, two local controllers 160, and an interleaved power converter 115. In this example, the interleaved power converter 115 comprises two interleaved power converter modules 305. In this example, each interleaved power converter module 305 comprises a half-bridge single-phase converter circuit coupled to the respective terminals of the (single-phase) AC load 130. Generally, each of the two interleaved power converter modules 305 is driven to output an AC signal that is 180 degrees phase-shifted relative to the other interleaved power converter module 305. Each interleaved power converter module 305 can be implemented as one of the switching circuits shown in Figures 5A-5H, for example, which will be described in detail later.

[0038] In Figure 3C, the power converter 360 is a three-phase converter. The power converter 360 includes a central controller 150, three local controllers 160, and an interleaved power converter 115. In this example, the interleaved power converter 115 comprises three interleaved power converter modules 305. In this example, each interleaved power converter module 305 includes a half-bridge single-phase converter circuit coupled to the corresponding phase legs 130a, 130b, and 130c of a (three-phase) AC load 130. Generally, each interleaved power converter module 305 is driven to output an AC signal that is 120 degrees phase-shifted relative to the other interleaved power converter modules 305. Each interleaved power converter module 305 can be implemented as one of the switching circuits shown in Figures 5A-5H, for example, which will be described in detail later.

[0039] Referring to Figures 4A-4B, schematic diagrams of control systems that can be implemented by power converters such as power conversion system 100, power converter 300, power converter 330, and / or power converter 360 are shown.

[0040] Figure 4A shows a control system 400 comprising a central controller 150, three local controllers 160a, 160b, and 160c (each an example of the aforementioned local controller 160), and interleaved power conversion modules 305a, 305b, and 305c (each an example of the aforementioned interleaved power conversion module 305). The local controllers 160a-c can be collectively referred to as local controller 160, or each local controller 160. The interleaved power conversion modules 305a-c can be collectively referred to as interleaved power conversion module 305, or each interleaved power conversion module 305. When implemented by a power conversion module 300 (half-bridge, single-phase), the control system 400 may include local controller 160a and interleaved power conversion module 305a, but the components of the control system shown by the dashed lines (local controllers 160b-c, and modules 305b-c) may not be present. When implemented with power converter 330 (full bridge, single phase), the control system 400 may include local controllers 160a and 160b and interleaved power conversion modules 305a and 305b, although the components of the control system indicated by the dashed lines (local controller 160c and module 305c) may not be present. When implemented with power converter 360 (three phase), the control system 400 may include local controllers 160a, 160b, and 160c and interleaved power conversion modules 305a, 305b, and 305c.

[0041] Figure 4A shows the communication between components of the control system 400 during its operation (for example, when a power converter utilizing the control system 400 is operating for power conversion). As shown, each interleaved power conversion module 305 sends sensor data (for example, sensor data) to its respective local controller 160. abc) provides. The interleaved power conversion module 305 may incorporate one or more of the aforementioned sensors 140 (see Figure 1). In some examples, the sensor data includes one or more of the inductor current of the LC filter of the interleaved power conversion module 305, the capacitor voltage of the LC filter of the interleaved power conversion module 305, and / or the output current of the LC filter of the interleaved power conversion module 305. Each local controller 160 further provides sensor data to the central controller 150. Thus, the central controller 150 receives sensor data from each interleaved power conversion module 305 present in the control system 400. The central controller 150 provides each local controller 160 with a reference target (e.g., Ref abc This generates a baseline target, which is unique to each local controller 160.

[0042] The central controller 150 may be a PID controller that generates several possible reference targets based on received sensor data and overall power requests or commands (e.g., received via the I / O interface 142 or memory). In some examples, the central controller 150 converts the sensor data from a stationary reference coordinate system (e.g., the abc reference coordinate system) to a rotating reference coordinate system (e.g., the dq (DQ or DQN) reference coordinate system). For the conversion, the central controller 150 can use Park and Clarke transformations. The central controller 150 generates reference targets for each leg of the rotating reference coordinate system (e.g., voltage target value for D, voltage target value for Q, voltage target value for N (null component)). The reference targets are set based on the detected values ​​(i.e., values ​​indicated by the sensor data) relative to the target values ​​of these characteristics, and it is possible to make the detected values ​​approach the target values ​​(e.g., using PID control techniques). In some examples, the N component is set to half of the DC link voltage to control leakage current in the system. In some embodiments, the central controller further injects harmonics (e.g., sinusoidal or triangular voltage signals as harmonic injections) into the N component (e.g., added to the half-DC link voltage). These harmonics may be the third harmonic of the fundamental frequency of the output AC signal or AC grid to which the converter is coupled. The central controller 150 can use the Park-Clark inverse transform to convert the reference target from the DQN reference coordinate system to the stationary (abc) reference coordinate system. The central controller 150 outputs the reference target (Ref) to each local controller 160 present in the system 400 (e.g., Ref to local controllers 160a, 160b, 160c). a ,Ref b ,Ref c (Outputs output).

[0043] In some examples, the reference target is the voltage value across the capacitor of the LC filter in the interleaved power conversion module 305. In other examples, the reference target is another electrical characteristic of the interleaved power conversion module 305 (e.g., another voltage target or current target).

[0044] Each local controller 160 receives a corresponding reference target from the central controller 150. Based on the received reference target, each local controller 160 generates a control signal to control the corresponding interleaved power conversion module 305. By generating an appropriate control signal, each local controller 160 can regulate the electrical characteristics of the reference target (e.g., capacitor voltage) to approach the value indicated by the reference target.

[0045] Referring to Figure 4B, a more detailed diagram 415 of the local controller 160a and the interleaved power conversion module 305a is shown. This diagram is similarly applicable to the other local controllers 160b and 160c, as well as the interleaved power conversion modules 305b and 305c.

[0046] As shown in the figure, the local controller 160a comprises an electronic processor 165 and a gate driver 410, and the interleaved power conversion module 305a comprises a switching circuit 420 and a sensor 430. During operation, the electronic processor 165 receives reference targets (Ref) from the central controller 150. a ) receives sensor data 435 (sensor data 430) from sensor 430. a The sensor data 435 may be as described above with respect to Figure 4A. The electronic processor 165 receives the reference target and sensor data, and the duty cycle reference (d a * ), phase shift duty cycle criterion (d shift_a * ), and switching frequency (f SWDetermine the phase-shifted duty cycle reference value (d shift_a * ) is expressed, for example, by directly indicating the amount of phase shift (e.g., as an angle between 0 and 360 degrees), or by the duty cycle reference value (d) which is phase-shifted. a * This shows the amount of phase shift relative to ). These values ​​d a * d shift_a * , and f SW The calculation will be explained in more detail below.

[0047] The gate driver 410 is based on a duty cycle standard (d a * ), phase-shifted duty cycle reference (d shift_a * ), and switching frequency (f SW The system receives the signal and generates a variable frequency soft switching (VFSS) control signal 450 and a phase-shifted VFSS control signal 455. The VFSS control signal 450 controls the switching frequency (f SW A frequency equal to (d), and a duty cycle reference (d a * The VFSS control signal 450 may include a first pulse-width modulation (PWM) signal having a duty cycle equal to ) and a second PWM signal which is the inverse of the first PWM signal. SW A frequency equal to (d), and a duty cycle reference (d a * A first pulse-width modulated (PWM) signal 450a having a duty cycle equal to ) and the inverted first PWM signal 450a, and therefore the same switching frequency (f SW ) and duty cycle (d a * It is possible to include a second PWM signal 450b having ).

[0048] The phase shift VFSS control signal 455 controls (i) the switching frequency (f SW) is equal to the frequency and duty cycle reference (d a * It has a duty cycle equal to ), but the duty cycle reference (d) is phase-shifted. shift_a * (ii) The first PWM signal 455a is phase-shifted with respect to the VFSS control signal 450a by the phase shift amount shown by (ii) and the inverted first PWM signal 455a, and therefore the same switching frequency (f SW ) and duty cycle (d a * ) has a phase-shifted duty cycle criterion (d shift_a * It is possible to include a second PWM signal 455b that is phase-shifted relative to the VFSS control signal 450b by the phase shift amount shown in ). The inverter gate that provides signals 450b and 455b is shown outside the gate driver 410 in Figure 4B, but the inverter gate may be inside the gate driver 410.

[0049] As will be described in more detail later, the VFSS control signal 450 and the phase-shift VFSS control signal 455 control the switching of corresponding pairs of power switching elements in the switching circuit 420, respectively, so that each pair of power switching elements is controlled by a PWM signal at a switching frequency selected to obtain soft switching (zero voltage switching), and the outputs of the power switching element pairs are interleaved. Generally, as shown in Figures 5A-5H, each pair of power switching elements is controlled by a first control signal (e.g., PWM or PWM shift A first transistor receives the signal (e.g., inverted PWM or inverted PWM), and the first control signal is inverted (e.g., inverted PWM or inverted PWM). shiftIt includes a second transistor that receives the signal. Therefore, during operation, when the first transistor of the pair is enabled (ON), the second transistor of the pair is disabled (OFF), and vice versa. Here, the terms power switching element and transistor are used synonymously. In some examples, a transistor is a type of field-effect transistor (FET), such as a metal oxide semiconductor (MOS) FET, a silicon carbide (SiC) FET, or a gallium nitride transistor (GaN) FET.

[0050] Figures 5A-5H show examples of switching circuits that function as switching circuits 420 in one or more interleaved power conversion modules 305 present in a power converter (e.g., power conversion system 100, power converters 300, 330, 360).

[0051] Figure 5A shows a multi-inductor interleaved converter 500. The converter 500 comprises a DC link node 502, a first transistor pair 504a and 504b and a second transistor pair 506a and 506b coupled between the DC link nodes 502, an LC filter circuit 508, and AC nodes 510a-510b. The first transistor pair comprises a first upper transistor 504a coupled to a first lower transistor 504b via a first midpoint node 512. The second transistor pair comprises a second lower transistor 506b coupled via a second midpoint node 514. The LC filter 508 comprises a first inductor 516a coupled between the first midpoint node 512 and the output node 510a of the AC node, and a second inductor 516b coupled between the second midpoint node 514 and the output node 510a of the AC node. The LC filter 508 further comprises an upper capacitor 518a coupled between the output node 510a and the positive DC node 502, and a lower capacitor 518b coupled between the output node 510a and the negative DC node 502.

[0052] Since inductors 516a and 516b are connected in parallel to output node 510a, the current from the two inductors (i L1 and i L2 ) are added at output node 510a. When the two transistor pairs operate with a 180-degree phase shift, the triangular wave inductor current is also phase shifted by 180 degrees. The two inductor currents (i L1 and i L2 When these are added at output node 510a, the peak of one coincides with the low point of the other, resulting in the ripple currents canceling each other out (the average value is not affected by this cancellation). This results in the effect of small current ripple amplitudes being filtered by output capacitors 518a and 518b, allowing for smaller capacitor sizes.

[0053] Another effect is frequency doubling. Two currents (i L1 and iL2 The sum of the fundamental frequencies of the currents is twice the fundamental frequency of each individual current (or n times in the case of n interleaved inductors). The ripple reduction effect provided by the output filter capacitors 518a and 518b increases with the frequency of the filtered current. Therefore, the frequency doubling effect makes it possible to further reduce the filter size.

[0054] Figure 6A shows these effects. Two inductor currents i1 and i2 (each inductor current i L1 and i L2 The corresponding ( ) is shown, and there is a 180-degree phase shift. In this example, the average current through each inductor is 0.5A, and is shown by the dashed line. The sum of the two currents (i1 + i2) flowing through the output filter capacitor is also shown, and its average is 1.0A. The average value of 1.0A is the individual inductor current i L1 and i L2 This is the sum of the averages of the individual currents. However, in this example, the peak-to-peak ripple of the total current has been reduced from 1A to approximately 0.4A. Furthermore, the total current has a frequency that is twice the frequency of the individual currents.

[0055] By using interleaving, the soft-switching operating region of the interleaved inverter is expanded, increasing the current and voltage, resulting in peak power achievable by the converter. Referring to Figure 6B, a plot is shown showing the soft-switching operating region defined by curve 605 of an interleaved inverter (e.g., converter 500 in Figure 5A), and a constant power curve 610 indicating the inverter's peak power. In this example, the use of interleaving shifts the upper right corner of the boundary to the right (as indicated by the arrow) so that the power requirement shown in power curve 610 is exceeded. In this example, with the soft-switching converter 500, a 640V battery (as a DC power source connected to DC node 502), and third harmonic injection into null-sequence target reference generation by the central controller 150, a power curve 610 of 240kW overlaps with the switching boundary curve 605 and is therefore achievable by the power converter.

[0056] To implement variable frequency soft switching, the control system 105 (e.g., the electronic processor 165) can determine the switching frequency required to achieve soft switching using the following equation.

number

[0057] Referring to Figure 5B, a coupled inductor interleaved transducer 520 is shown. Transducer 520 in Figure 5B has several components similar to those of transducer 500 in Figure 5A, and these components are given similar reference numerals. In contrast to transducer 500, transducer 520 has an LC filter 522 comprising a coupled inductor 524, an upper capacitor 518a, and a lower capacitor 518b. The coupled inductor 524 comprises windings 524a and 524b wound on a single magnetic core. The coupled inductor 524 is supplied by a transformer (coupling transformer) with a turns ratio of 1:-1. The coupled inductor 524 is coupled between a first midpoint node 512, a second midpoint node 514, and an output node 510a.

[0058] Similar to the converter 500, in the converter 520, the first transistor pair 504 and the second transistor pair 506 are driven by a PWM signal and a phase-shifted PWM signal (e.g., signals phase-shifted by 180 degrees relative to each other), respectively. Similar to the interleaved converter 500 with multiple inductors, the interleaved converter 520 with coupled inductors provides an interleaved output with twice the frequency and reduced current ripple, enabling it to provide the same advantages as those described above for the converter 500. Thus, the diagrams in Figures 6A-6B are applicable similarly. Furthermore, the core of the coupled inductor 524 of the LC filter 522 receives a higher frequency interleaved output. This result is in contrast to the converter 500 in Figure 5A, where each inductor receives a (lower) base switching frequency. Thus, the coupled inductor 524 of the LC filter 522 of the converter 520 can have a smaller size than the inductors 516a, 516b of the LC filter 508 of the converter 500.

[0059] In some examples, individual discrete inductors (not shown) are provided between the coupled inductor 524 and each corresponding midpoint 512, 514. In some examples, the leakage inductance at the connection of the coupled inductor 524 to each midpoint 512, 514 performs a similar function, forming a single magnetic structure.

[0060] This topology yields a new equation for inductor ripple that includes both the switching frequency fsw and the normalized phase shift φ (which varies between 0 and 1). When the duty cycle D > 0.5 and the phase shift φ < 0.5, the following equation is satisfied.

number

[0061] A similar equation is obtained when D < 0.5 and / or φ > 0.5, resulting in a set of four equations that cover all cases. For simplicity, this equation is written in terms of a duty cycle D that varies between 0 and 1. In a steady state, V out =DV in The following equation is satisfied. When φ=D, the ripple Δi L This becomes zero. Therefore, if φ is fixed at 0.5 (or 180 degrees), the ripple becomes zero when D passes 0.5. This means that both the switching frequency and phase are adjusted by the controller (e.g., the local controller 160 controlling the transducer 520) to ensure sufficient ripple across all operating points.

[0062] This equation can be solved for either the switching frequency or the phase, showing how each affects the ripple.

number

[0063] One such control method involves setting φ=0.5 to obtain sufficient ripple, and under all conditions f sw There is a way to control it. When the required switching frequency falls below the minimum value, f sw is f min It is fixed to and φ is controlled instead. Experimentally, this method was applied to simulations and its effectiveness was confirmed, as shown in the inductor current plot 700, phase current plot 705, and frequency plot 710 in Figure 7. More specifically, in the frequency plot 710, the calculated switching frequency required for soft switching is shown as curve 715, and the actually selected frequency is shown as a stepped line 720. This simulation uses frequencies that are integer multiples of 50 kHz, but in other examples, the frequency is not so limited. In this example, the minimum switching frequency is 100 kHz. Desired frequency f sw When the phase falls below a minimum value (see plot 710), the phase φ is adjusted to maintain the desired ripple (see plot 700) (see plot 705). The ripple envelope 722 with respect to the inductor current is shown in plot 700, where the average current is shown as a sinusoidal signal 725, and the ripple inverse boundaries 730 and 735 are shown as straight lines slightly offset from the x-axis. Boundary 730 is below the x-axis when the average current is positive, and boundary 735 is above the x-axis when the average current is negative. In some examples, other control schemes, such as controlling the phase until a minimum value is reached and then controlling the frequency, are used, where the phase φ is the switching frequency f sw Control to ensure sufficient ripple Δi L Used to maintain [something].

[0064] In some cases, the phase φ is generally static during operation rather than being dynamically controlled. For example, the control scheme sets the phase φ to 0.5, and f swBy controlling this, the ripple required for soft switching is obtained. Furthermore, the inductance of the coupled inductor 524 can be intentionally designed to have characteristics that enable sufficient ripple, and thus soft switching, even at low switching frequencies. For example, Figure 9 shows Model 900 of a coupled inductor interleaved transducer 520, which can be used to select the characteristics of the coupled inductor 524 that enable sufficient ripple. In Model 900, the coupled inductor 524 has an ideal inductance L and a magnetized inductance L m , and leakage inductance L lk It is modeled as having the following characteristics, where the ideal inductance L is equal to the inductance L1 of winding 524a of the coupled inductor and equal to the inductance L2 of winding 524b of the coupled inductor. The relationship between these inductances can be defined by the following equation.

number

[0065] As mentioned above, Model 900 can be used to select the characteristics of the coupled inductor 524 that allow for sufficient ripple to achieve soft switching even at low switching frequencies. For example, to select the characteristics, the leakage inductance and magnetization inductance can be selected, and each of the above formulas can be used to find the inductance L equal to the inductance of windings 524a and 524b of the coupled inductor 524. Leakage inductance L lk It can be selected to supply the maximum AC current with the minimum (and maximum) duty cycle, minimum DC voltage, and minimum switching frequency. Furthermore, the magnetization inductance L mcan be selected to supply the maximum alternating current at a duty cycle of 0.5, a minimum DC voltage, and a switching frequency greater than or equal to the minimum switching frequency. For example, the following equation relates to the leakage inductance L lk and the magnetizing inductance L m can be used for calculation. [Formula]

[0066] When the desired switching frequency is below the minimum allowable frequency, the current ripple due to the leakage inductance may be too small for soft switching to occur. However, at such a low switching frequency, while the ripple current due to the leakage inductance becomes zero, the ripple in the magnetizing inductance reaches its maximum value. Therefore, by selecting a sufficiently small magnetizing inductance to allow sufficient ripple amplitude while minimizing the bus voltage at low switching frequencies, the converter performs soft switching when passing through the zero-crossing point.

[0067] In this example, the switching frequency can be calculated (for example, by the local controller 160) using the following equation. [Formula]

[0068] The variable m represents the slope of the inductor current, and the equation for solving m can take three different forms depending on the state of the switch. More specifically, the slope m of the inductor current i can take three forms corresponding to when the top switch (i=1), the diagonal switch (i=2), and the bottom switch (i=3) are turned on. [Formula]

[0069] As described above, the multi-inductor interleaved converter 500 and the coupled inductor interleaved converter 520 enable a reduction in the size of the inductors and capacitors in the LC filters of these converters, thereby increasing the power density of these power converters. Experimental results of exemplary embodiments of these converters 500, 520 demonstrate such size reductions, as shown in Table 1 below. More specifically, Table 1 shows the parameters of the multi-inductor interleaved converter 500 (referred to as "interleaved"), the coupled inductor interleaved converter 520 (referred to as "coupled inductor"), and a non-interleaved uncoupled inductor converter comprising a parallel inductor coupled between the power switching element and the output node. In these examples, the maximum switching frequency is limited to 500 kHz, the selectable switching frequency is limited to a 50 kHz bin, the converters are designed to supply 80 kW of three-phase power at 128 amps / phase and a 700 V DC input, and the output capacitance is selected for equivalent worst-case output voltage ripple. Although not shown in the table, the inductance L of interleaved converters is smaller than that of parallel inverters, and even smaller in coupled inductor converters (1 / 4.5 times smaller than that of parallel converters). [Table 1]

[0070] Referring to Figure 5C, a flying capacitor type multilevel interleaved transducer 530 is shown. Transducer 530 in Figure 5C is similar to transducer 500 in Figure 5A and comprises several elements that are given the same reference numerals. In contrast to transducer 500, transducer 530 comprises an LC filter 532 including an inductor 534, an upper capacitor 518a, and a lower capacitor 518b. Additionally, the first transistor pair 504a and 504b and the second transistor pair 506a and 506b are interconnected in the circuit in different ways. More specifically, the first transistor pair 504a and 504b is an inner pair connected at an intermediate node 536, and the second transistor pair 506a and 506b is an output pair coupled between the DC link node 502 and the first (inner) transistor pair 504a and 504b. For example, the upper transistor 506a is coupled between the (positive) DC link node 502 and the upper transistor 504a, and the lower transistor 506b is coupled between the (negative) DC link node 502 and the lower transistor 504b. Additionally, the converter 530 includes a flying capacitor 538 coupled between the first (inner) transistor pair 504a and 504b at (i) the connection node 539a between the upper transistors 504a and the upper transistor 506a, and (ii) the connection node 539b between the lower transistors 504b and the lower transistor 506b. The inductor 534 of the LC filter is coupled between the first midpoint node 536 and the output node 510a.

[0071] Similar to transducer 500, in transducer 520, the first and second transistor pairs 504 and 506 are driven by a PWM signal and a phase-shifted PWM signal (e.g., signals shifted 180 degrees in phase from each other), respectively. Similar to the multi-inductor interleaved transducer 500, the flying capacitor multi-level interleaved transducer 530 provides the same advantages as described above with respect to transducer 500 by providing an interleaved output with twice the frequency and reduced current ripple. Thus, the diagrams in Figures 6A-6B are similarly applicable. Additionally, the inductor 534 of the LC filter 532 receives a higher frequency interleaved output. This result is in contrast to transducer 500 in Figure 5A, where each inductor receives a (lower) fundamental switching frequency. Thus, compared to the inductors 516a and 516b of the LC filter 508 of transducer 500, the coupled inductor 534 of the LC filter 532 of transducer 530 can have a reduced size. Furthermore, connecting the upper transistors 504a and 506a in series allows for voltage sharing between these transistors, enabling a reduction in transistor size and / or rated voltage compared to the transistors of converters 500 and 520. Similar advantages are obtained for the lower transistors 504b and 506b connected in series.

[0072] Referring to Figure 5D, a neutral-point connected multilevel interleaved transducer 540 is shown. Transducer 540 in Figure 5D is similar to transducer 530 in Figure 5C and comprises several components that are given the same reference numerals. In contrast to transducer 530, transducer 540 includes a neutral-point connection 542 between the upper and lower capacitors and the DC link node 502. Furthermore, instead of a flying capacitor, diodes 544a and 544b are connected between connection nodes 539a and 539b, and the neutral-point connection 542 is an intermediate node between diodes 544a and 544b.

[0073] Similar to the multi-inductor interleaved transducer 500, the neutral-point connected multi-level interleaved transducer 540 provides an interleaved output with twice the frequency and reduced current ripple, offering the same advantages as described above with respect to transducer 500. Therefore, the diagrams in Figures 6A-6B also apply. Furthermore, the inductor 534 of the LC filter 532 receives a higher frequency interleaved output. This result is in contrast to transducer 500 in Figure 5A, where each inductor receives a (lower) fundamental switching frequency. Thus, compared to the inductors 516a and 516b of the LC filter 508 of transducer 500, the coupled inductor 534 of the LC filter 532 of transducer 540 can have a reduced size. Furthermore, similar to transducer 530, connecting the upper transistors 504a and 506a in series allows for voltage sharing between these transistors, enabling a reduction in transistor size and / or rated voltage compared to the transistors of transducers 500 and 520. Similar advantages can be obtained for the lower transistors 504b and 506b connected in series.

[0074] In some examples, the interleaved transducers 500, 520, 530, and / or 540 are modified to include additional transistor (or level) pairs in the horizontal or vertical direction. For example, with respect to transducer 500, two transistor pairs are shown, each pair driven with a phase shift of approximately 180 degrees relative to the other. In some examples, transducer 500 in Figure 5A includes one or more additional levels, e.g., a third transistor pair, a fourth transistor pair, etc., each transistor pair coupled via DC node 502 (similar to transistor pairs 504 and 506), and includes an intermediate node coupled via a separate inductor to output node 510a. In these examples, each transistor pair receives a PWM control signal that is phase-shifted relative to the other transistor pairs. The phase difference between transistor pairs can be set to 360 degrees / pair (e.g., 360 / 2 pairs = 180 degrees, 360 / 3 pairs = 120 degrees, 360 / 4 pairs = 90 degrees, etc.). This example can also be applied when adding transistor pairs horizontally.

[0075] Similarly, for the transducer 520, two transistor pairs are shown, each driven with a phase shift of approximately 180 degrees relative to the others. In some examples, the transducer 520 in Figure 5B includes one or more additional levels, e.g., a third transistor pair, a fourth transistor pair, etc., each transistor pair being coupled via a DC node 502 (similar to transistor pairs 504 and 506), and an intermediate node coupled to the output node 510a via a winding of a coupling inductor 524. In such examples, each transistor pair receives a PWM control signal that is phase-shifted relative to the other transistor pairs. The phase difference between transistor pairs can be set to 360 degrees / number of pairs (e.g., 360 / 2 pairs = 180 degrees, 360 / 3 pairs = 120 degrees, 360 / 4 pairs = 90 degrees, etc.). This example can also be applied when adding transistor pairs horizontally.

[0076] With respect to the transducer 530, two transistor pairs are shown, each pair driven with a phase shift of approximately 180 degrees relative to the others. In some examples, the transducer 530 in Figure 5C includes, for example, one or more additional levels, such as a third transistor pair, a fourth transistor pair, etc., where each transistor pair is coupled as an additional output pair to the existing pair, and additional flying capacitors are provided between each inner transistor pair. For example, when a third transistor pair is added to the transducer 530, the upper transistor of the third transistor pair is coupled between transistor 506a and the (positive) DC link node 502, and the lower transistor of the third transistor pair is coupled between transistor 506b and the (negative) DC link node 502. Additionally, in this example, another flying capacitor is coupled between transistors 506a and 506b (similar to how flying capacitor 538 is coupled between transistors 504a and 504b). In such examples, each transistor pair of the transducer 530 receives a PWM control signal that is phase-shifted relative to the other transistor pairs. The phase difference between transistor pairs can be set to 360 degrees / number of pairs (e.g., 360 / 2 pairs = 180 degrees, 360 / 3 pairs = 120 degrees, 360 / 4 pairs = 90 degrees, etc.). This example can also be applied when adding transistor pairs vertically.

[0077] With respect to the transducer 540, two transistor pairs are shown, each pair driven with a phase shift of approximately 180 degrees relative to each other. In some examples, the transducer 540 in Figure 5D includes, for example, one or more additional levels, such as a third transistor pair, a fourth transistor pair, etc., where each transistor pair is coupled as an additional output pair to the existing pair, and an additional flying capacitor is provided between each inner transistor pair. For example, when a third transistor pair is added to the transducer 540, the upper transistor of the third transistor pair is coupled between transistor 506a and the (positive) DC link node 502, and the lower transistor of the third transistor pair is coupled between transistor 506b and the (negative) DC link node 502. Additionally, in this example, another group of diodes is coupled between transistors 506a and 506b (in a similar manner to how diode 544 is coupled between transistors 504a and 504b), where the midpoint of the multiple diodes is also coupled to the neutral point 542. In these examples, each transistor pair of the 540 converter receives a PWM control signal that is phase-shifted relative to other transistor pairs. The phase difference between transistor pairs can be set to 360 degrees / number of pairs (e.g., 360 / 2 pairs = 180 degrees, 360 / 3 pairs = 120 degrees, 360 / 4 pairs = 90 degrees, etc.). This example can also be applied when adding transistor pairs vertically.

[0078] Referring to FIGS. 5E-5H, hybrid topologies combining the features of the converter topologies described with reference to FIGS. 5A-5D are illustrated. Starting first from FIG. 5E, a flying-capacitor multilevel, multi-inductor interleaved converter 550, which is a hybrid of converters 500 and 530, is shown. In FIG. 5F, a neutral-point-clamped multilevel, multi-inductor interleaved converter 560, which is a hybrid of converters 500 and 540, is shown. In FIG. 5G, a flying-capacitor multilevel, coupled-inductor interleaved converter 570, which is a hybrid of converters 520 and 530, is shown. In FIG. 5H, a neutral-point multilevel, coupled-inductor interleaved converter 580, which is a hybrid of converters 520 and 540, is shown.

[0079] In the topologies of FIGS. 5E-5H, the hybrid converters 550-580 have four transistor pairs instead of the two transistor pairs shown in FIGS. 5A-5D. As illustrated, according to this grouping, the first transistor pair receives a PWM signal (VFSS control signal 450, see FIG. 4B), the second transistor pair receives a first phase-shifted PWM signal (PWM shift_1 ), the third transistor pair receives a second phase-shifted PWM signal (PWM shift_2 ), and the fourth transistor pair receives a third phase-shifted PWM signal (PWM shift_3 ). The PWM, PWM shift_1 , PWM shift_2 , and PWM shift_3 signals are generally similar to those described with reference to FIGS. 4A-4B and FIGS. 5A-5D, and more specifically, each transistor pair driven by any of these signals includes a first transistor that receives a signal (e.g., a non-inverted PWM signal) and a second transistor that receives an inversion of that signal (e.g., an inverted PWM signal). Further, the phase difference between each PWM signal can be set to a value obtained by dividing 360 degrees by the number of transistor pairs (e.g., 90 degrees in the example of FIGS. 5E-5H). For example, the phase of the PWM signal is 0 degrees, and the PWMshift_1 The signal is shifted 90 degrees in phase with respect to the PWM signal. shift_2 The signal is PWM shift_1 The signal is shifted by another 90 degrees in phase (for example, the PWM signal is shifted by 180 degrees in phase), PWM shift_3 The signal is PWM shift_2 The phase of the signal is shifted by an additional 90 degrees (for example, the phase of a PWM signal is shifted by 270 degrees). By increasing the number of transistor pairs and the number of signal phases to 4, the output frequency can be made four times the fundamental frequency, providing a further ripple current cancellation effect. Various phase-shifted VFSS control signals (e.g., PWM) shift_1 PWM shift_2 PWM shift_3 Although it has a different phase shift, it can be generated by the local controller 160a (for example, by the gate driver 410), similar to the phase shift VFSS control signal 455 (see Figure 4B) described above.

[0080] Figure 8 shows an interleaved power conversion method 800. This method 800 can be implemented by a system 100. For example, the method 800 can be implemented by a system 100 comprising an interleaved power converter 115 including one or more interleaved power conversion modules 305 (see Figures 3A-3C and 4A-4B). In some examples, such an interleaved power conversion module 305 comprises a switching circuit 420 having a conversion circuit topology as illustrated and described with respect to one or more of Figures 5A-5H. In other examples, the method 800 is implemented by another power conversion system or a power conversion system 100 implementing another conversion circuit topology. In some examples, the system 100 implementing the method 800 may include a control system as shown in Figure 4A and / or Figure 4B. Additionally, although the blocks of Method 800 are illustrated in a specific order, in some embodiments, one or more blocks may be executed partially or completely in parallel, in an order different from that shown in Figure 8, or bypassed.

[0081] In block 805, the local controller receives a reference target from the central controller. The central controller generates a reference target based on the detection characteristics of an interleaved power conversion module having a DC link node, a first and second transistor pair connected between the DC link nodes, an LC filter circuit, and an AC node. For example, referring to Figure 4A-4B, the local controller 160a receives a reference target (Ref a ) receives. Here, as described above, the central controller 150 receives sensor data (e.g., Sensor Data) generated by the sensor 430 of the interleaved power conversion module 305 and provided via the local controller 160. a Sensor Data b , and / or Sensor Data c ) generates baseline targets.

[0082] In block 810, the local controller generates a variable frequency soft switching (VFSS) control signal to drive a first transistor pair to output a first AC signal, based on a reference target and detection characteristics. For example, referring to Figure 4B, the local controller 160a generates a VFSS control signal 450 and provides the VFSS control signal 450 to the interleaved power conversion module 305a. The VFSS control signal 450 may include a first PWM signal 450a and a second PWM signal 450b. The first PWM signal 450a has a switching frequency (f SW A frequency equal to ) and a duty cycle reference (d a * It is possible to have a duty cycle equal to ). The second PWM signal 450b is the inverse of the first PWM signal 450a and therefore has the same switching frequency (f SW ) and duty cycle (d a * The first PWM signal 450a can drive the first transistor of the first transistor pair (e.g., transistor 504a), and the second PWM signal 450b can drive the second transistor of the first transistor pair (e.g., transistor 504b).

[0083] The VFSS control signal 450 can be called a variable frequency soft switching control signal. This is because the switching frequencies of the first PWM signal 450a and the second PWM signal 450b change or change over time to ensure soft switching by the transistor pair driven by the PWM signals. For example, as described above, the switching frequency can be varied. Lowering the switching frequency increases the rise and fall times of the current and increases the ripple, while increasing the switching frequency shortens the rise and fall times of the inductor current and decreases the ripple. This controllability allows the local controller to maintain a desired ripple across the x-axis by a certain amount (see, for example, Figure 7 and boundaries 730, 735) to ensure soft switching of the first transistor pair. In some examples, the local controller can determine the maximum switching frequency that enables soft switching, although this may be limited by the maximum switching frequency associated with high switching losses. Generally, the duty cycle of the PWM control signal controls the output voltage of the converter, while the phase and frequency do not. Therefore, the duty cycle is determined based on the desired voltage conversion ratio to achieve the desired output voltage, and the frequency and / or phase can be used to adjust the current ripple.

[0084] Referring to Figure 4B, the electronic processor 165 can determine (for example, continuously during operation) the switching frequency and duty cycle of the PWM signals 450a and 450b of the VFSS control signal 450. As previously mentioned, the first transistor pair may be part of an interleaved power conversion module, as shown in any of Figures 5A-5G. Examples of specific formulas that the electronic processor 165 can use to determine the switching frequency and duty cycle of the VFSS control signal 450 are shown above in relation to the description of the coupled inductor interleaved converter 520 in Figure 5B. In some examples, the electronic processor 165 uses the above-described technique to determine the switching frequency of the VFSS control signal 450 with the aim of minimizing switching losses; therefore, this control technique is sometimes called critical variable frequency soft switching.

[0085] In block 815, the local controller generates a phase-shift VFSS control signal to drive a second transistor pair to output a second AC signal that is phase-shifted relative to the first AC signal, based on the reference target and detection characteristics. For example, referring to Figure 4B, the local controller 160a generates a phase-shift VFSS control signal 455 and supplies this phase-shift VFSS control signal 455 to the interleaved power conversion module 305a. The phase-shift VFSS control signal 455 is a first phase-shift PWM signal (PWM shift )455a and the second phase-shifted PWM signal (PWM shift )455b can be included. First PWM shift Signal 455a has a switching frequency (f SW A frequency equal to ) and a duty cycle reference (d a * The second PWM may have a duty cycle equal to ). shift Signal 455b is the first PWM shift This is the inversion of signal 455a, and therefore has a similar switching frequency (f SW ) and duty cycle (d a* ) also has the first PWM. shift Signal 455a drives the first transistor of the second transistor pair (e.g., transistor 506a) and the second PWM. shift Signal 455b can drive the second transistor of the second transistor pair (e.g., transistor 506b). Additionally, the VFSS control signal 450 and the phase-shift VFSS control signal 455 have similar switching frequencies (f SW ) and duty cycle (d a * It is possible to have )

[0086] 1st PWM shift Signal 455a and the second PWM shift The switching frequency of signal 455b changes or changes over time, PWM shift To ensure soft switching by a signal-driven transistor pair, the phase-shifted VFSS control signal 455 can be called a variable-frequency soft-switching control signal. For example, as mentioned above, the switching frequency can be varied to ensure soft switching without excessive switching loss. Referring to Figure 4B, the electronic processor 165 controls the PWM of the phase-shifted VFSS control signal 450. shift It is possible to determine the switching frequency and duty cycle for signals 455a and 455b (for example, by continuously determining them during operation). Furthermore, in some examples, a phase shift α(d) is used to ensure soft switching by the first and second transistor pairs. shift_a *The phase shift (shown as shown) changes. In some examples, the phase shift may be set, at least initially, to a value obtained by dividing 360 by the number of levels in the interleaved power conversion module (e.g., 180 degrees for converter 500 shown in Figure 5A and converter 520 shown in Figure 5B, and 90 degrees for converters 550, 560, 570, and 580 shown in Figures 5E-5H). During operation, the phase shift may change from this initial value, for example, in converters incorporating coupled inductors (e.g., see Figure 5B), as shown in plot 705 of Figure 7. For example, as the switching frequency decreases, the phase shift decreases.

[0087] As mentioned above, the second transistor pair may be part of an interleaved power conversion module, as shown in any of Figures 5A-5G. In relation to the description of the coupled inductor interleaved converter 520 in Figure 5B, examples of specific formulas that can be used by the electronic processor 165 to determine the switching frequency, duty cycle, and phase shift of the phase-shift VFSS control signal 455 are shown above. In some examples, the electronic processor 165 using the above-described technique determines the switching frequency of the phase-shift VFSS control signal 455 with the aim of minimizing switching losses, so this control technique can be called critical variable frequency soft switching.

[0088] In block 820, the interleaved power conversion module outputs an interleaved signal containing a first AC signal interleaved with a second AC signal via an LC filter circuit. For example, referring to Figures 5A-5D, converters 500, 520, 530, and 540 output the interleaved signal to output node 510a via either LC filter 508 (converter 500), LC filter 522 (converter 520), or LC filter 532 (converters 530 and 540). An example of such an interleaved signal is shown in Figure 7 as a sinusoidal signal 725 (plot 700), and an example of a pre-filtered version of the interleaved signal is shown in Figure 6A(i1+i2). Similarly, referring to Figures 5A-5D, as shown in Figures 5E-H, converters 550, 560, 570, and 580 output the interleaved signal to the output node via their respective LC filters (illustrated but not individually labeled).

[0089] Although Method 800 has been described in relation to a single local controller and interleaved power conversion module, in some examples, a system 100 implementing Method 800 may include additional local controllers and interleaved power conversion modules. For example, in some examples, a system 100 implementing Method 800 may include two local controllers 160 and two interleaved power conversion modules 305 (if local controllers 160a, 160b and interleaved power conversion modules 305a, 305b are included), as shown in Figure 3B and / or Figure 4A, or three local controllers 1260 and three interleaved power conversion modules 305 (if local controllers 160a, 160b, 160c and interleaved power conversion modules 305a, 305b, 305c are included), as shown in Figure 3C and / or Figure 4A. In such an example, each local controller executes blocks 805, 810, 815, and 820 (for example, each local controller operates in parallel or at least partially parallel with one another), and finally outputs its respective interleaved signal through an LC filter.

[0090] Therefore, in some examples, Method 800 further involves a second local controller (e.g., local controller 160b in Figure 4A) controlling the detection characteristics of the second interleaved power conversion module (e.g., Sensor Data b A second baseline objective (e.g., Ref) generated based on ) bThe method includes receiving a signal from a central controller 150, where the second interleaved power conversion module comprises a second DC link node, a third and fourth transistor pair coupled between a plurality of DC link nodes, a second LC filter circuit, and a second AC node. The method may further include the second local controller generating a second variable frequency soft-switching (VFSS) control signal that drives a third transistor pair (using the same technique as described with respect to block 810) to output a third AC signal based on a second reference target and sensing characteristics, and generating a second phase-shifted VFSS control signal that drives a fourth transistor pair (using the same technique as described with respect to block 815) to output a fourth AC signal that is phase-shifted relative to the third AC signal, based on a second reference target and sensing characteristics. Furthermore, the method may include the second interleaved power conversion module (e.g., module 305b) outputting a second interleaved signal that includes a third AC signal interleaved into a fourth AC signal via an LC filter circuit.

[0091] Furthermore, in some examples, Method 800 further transmits the detection characteristics (e.g., Sensor Data) of the third interleaved power conversion module from the central controller 150 via a third local controller (e.g., local controller 160c, see Figure 4A). c ) generated based on the third criterion objective (e.g., Ref cThe method includes receiving a signal, where the third interleaved power conversion module comprises a third DC link node, a fifth and sixth transistor pair coupled between a plurality of third DC link nodes, a third LC filter circuit, and a third AC node. The method further includes the third local controller generating a third variable frequency soft-switching (VFSS) control signal that drives the fifth transistor pair to output a fifth AC signal based on a third reference target and sensing characteristics, and generating a third phase-shifted VFSS control signal that drives the sixth transistor pair to output a sixth AC signal that is phase-shifted relative to the fifth AC signal, based on a third reference target and sensing characteristics (using techniques similar to those described with respect to block 815). Furthermore, the method 800 may include the third interleaved power conversion module (e.g., module 305b) outputting a third interleaved signal via a third LC filter circuit, which includes a fifth AC signal interleaved by the sixth AC signal.

[0092] In some cases, the interleaved power conversion system 100 selectively implements interleaving. For example, a control system 105 can control the interleaved power converter 115 to perform interleaving based on the operating characteristics of the system 100. For example, the control system 105 (e.g., a central controller 150 or several possible local controllers 160) can determine whether one or more power characteristics of the power conversion system 100 (e.g., output voltage, current, and / or power) exceed their respective thresholds. If one or more power characteristics exceed their respective thresholds, the control system 105 decides to perform interleaving. If one or more power characteristics fall below their respective thresholds, the control system 105 decides not to perform interleaving.

[0093] If it is decided to perform interleaving, the control system 105 controls the system 100 to perform interleaving by operating as described herein (for example, by performing the method in Figure 8). If it is decided not to perform interleaving, the control system 105 controls the system and outputs non-interleaved signals (there may be several) (for example, from each power conversion module 305 of the interleaved power converter 115). For example, each topology in Figures 5A-5H includes at least two transistor pairs that can be controlled to output interleaved signals. To output non-interleaved signals, the control system 105 (for example, the local controller 160 of each conversion module 305) controls one transistor pair as described above (for example, supplying PWM control signals 450a, 450b) and the control signal of the other transistor pair (for example, PWM shift The control signals 455a and 455b are kept at zero to prevent switching of the other transistor pair.

[0094] By selectively disabling interleaving (for example, when soft switching is possible without interleaving, or when the current, voltage, or power is low), the power conversion system 100 can reduce switching losses by not switching certain transistors (for example, transistors controlled by a phase-shifted PWM control signal). By selectively enabling interleaving, the power conversion system 100 can gain additional voltage margins compared to operation without interleaving and non-interleaving designs. Additionally, the ability to selectively enable interleaving allows for a reduction in the size of the inductors and capacitors in the LC filter compared to non-interleaving designs. In some examples, the transition between interleaved and non-interleaved operation (and vice versa) may involve a transition phase to smoothly move between them (for example, by gradually decreasing (or increasing) the switching frequency and / or duty cycle of the transistor pair(s) being turned off (or on), rather than rapidly disabling (or enabling) the pair(s) being turned off (or on).

[0095] In some examples, the interleaved power conversion system 100 can selectively operate in additional conversion modes. For example, in some examples, the power conversion system 100 may be selectively controlled and operated in one of the following modes: parallel (non-interleaved), cascaded (non-interleaved), parallel-interleaved, or cascaded-interleaved. The aforementioned modes include parallel (non-interleaved) and parallel (interleaved). In parallel non-interleaved mode, each of the conversion modules 305 present in the power conversion system 100 operates in a non-interleaved manner. For example, referring to Figure 3C, each of the interleaved power conversion modules 305 is controlled to operate in a non-interleaved manner. In such an example, referring to the topology in Figures 5A-5H, the first transistor pair operates with a PWM control signal, and the other transistor pairs are disabled. In parallel interleaved mode, each of the conversion modules 305 present in the power conversion system 100 operates in an interleaved manner. For example, referring to Figure 3C, each of the interleaved power conversion modules 305 is controlled to operate in an interleaved manner. In such an example, referring to the topology in Figures 5A-5H, the first transistor pair may be operated by a PWM control signal, and each of the other transistor pairs may be operated by a phase-shifted PWM control signal (as described, for example, with respect to method 800 in Figure 8).

[0096] In cascaded-interleaved mode, the conversion modules 305 can be selectively enabled and disabled (for example, based on power demand). Each of the conversion modules 305 present in and enabled in the power conversion system 100 operates in an interleaved manner (for example, as described here with respect to method 800 in Figure 8). The number of conversion modules 305 to be enabled is controlled based on the system's power demand. For example, when power demand is low, one or more conversion modules 305 can be disabled. By disabling, some conversion modules are not actively switched, and the enabled conversion modules 305 operate near their capacity, resulting in a more efficient conversion system. When power demand increases, the disabled conversion modules 305 can be brought online and enabled to meet the demand. Such cascaded connections of conversion modules can result in a more efficient power conversion system.

[0097] In cascaded (non-interleaved) mode, the converter modules 305 can again be selectively enabled and disabled based on power demand. Each of the converter modules 305 present in and enabled in the power conversion system 100 operates in a non-interleaved manner. The number of converter modules 305 to be enabled is controlled based on the system's power demand. For example, if power demand is low, one or more converter modules 305 can be disabled. By disabling them, some converter modules are not actively switched, and the enabled converter modules 305 operate close to their capacity, resulting in a more efficient conversion system. When power demand increases, disabled converter modules 305 can be brought online and enabled to meet the demand. Such cascaded connection of converter modules enables a more efficient power conversion system.

[0098] In some examples, the control system 105 can determine which of the four operating modes to operate in, for example, based on power demand. As power demand changes from low to high, the control system 105 controls the power conversion system 100 to transition between the four modes. For example, the control system 105 transitions the power conversion system from cascaded non-interleaved mode to cascaded interleaved mode (when a first threshold is exceeded), and then, when a second threshold is exceeded, activates another conversion module 305 to transition back to cascaded non-interleaved mode. As conversion modules 305 are activated, the control system 105 can continue the cycle of back and forth between these cascaded modes until eventually all conversion modules 305 are activated and the control system 105 transitions to parallel non-interleaved mode (when another threshold is exceeded). Finally, the control system 105 transitions to parallel interleaved mode (when another threshold is exceeded) to achieve the maximum output level of the power conversion system. Similarly, as power demand changes from high to low, the control system 105 can control the power conversion system 100 to cycle through four modes, for example, from parallel interleaved mode to parallel non-interleaved mode (when demand falls below a first threshold), then to cascaded interleaved mode (when demand falls below a second threshold), then to cascaded non-interleaved mode (when demand falls below a third threshold), then to cascaded mode by disabling each conversion module 305 (the opposite operation to the control when power demand increases), and finally to operate in cascaded non-interleaved mode for low-power operation. In other examples, the control system 105 switches between these four operating modes according to a different algorithm and / or based on additional parameters other than power demand. Switching between such operating modes can improve the efficiency of the power conversion system 100 across a wide range of power output levels.

[0099] Although described here primarily as a DC-AC inverter, the power conversion system 100 can additionally or alternatively function as an AC-DC rectifier and / or DC-DC converter, including the various examples and topologies described with respect to Figures 3A-5H. In some examples, the power conversion system 100 operates only as an inverter, only as a rectifier, or only as a DC-DC converter. In other examples, the power conversion system 100 operates as two or more of the inverter, rectifier, or DC-DC converter. In some examples, at various points in time, the power conversion system can operate in inverter mode to convert DC to AC, in rectifier mode to convert AC to DC, or in DC converter mode to convert DC from one voltage level to another. Therefore, in some examples (for example, when used in an electric vehicle), the power conversion system 100 can be used in one or more of the following modes: in inverter mode, to drive a motor with an AC signal generated from a DC signal received from a battery; in rectifier mode, to implement regenerative braking and charge the battery by converting AC power from the (brake) motor; in rectifier mode, to charge the battery by charging converted AC power from an external source (e.g., a grid); and in inverter mode, to convert DC power from the battery into an AC signal and output it to another AC load (e.g., a local microgrid or utility grid).

[0100] Returning to method 800 in Figure 8, in some examples (e.g., after block 820), if the power conversion system 100 (see Figure 2) is bidirectional, the control system 105 transitions the power conversion system 100 to operate in rectification mode. In such examples, the local controller 160 converts the first input AC signal received through the LC filter of the conversion module 305 to a first DC output on the DC link node of the conversion module 305 by generating a second variable frequency soft switching (VFSS) control signal to drive a first transistor pair, based on a reference target (Ref) from the central controller 150 and the corresponding sensing characteristics of the conversion module 305. The local controller 160 further converts the second input AC signal received through the LC filter to a second DC output on the DC link node by generating a second phase-shift VFSS control signal to drive a second transistor pair, based on the reference target and sensing characteristics. The converter module (and thus the power conversion system 100) then outputs a DC signal via the DC link node, which includes the first DC output added at the second DC output.

[0101] Returning to method 800 in Figure 8, in some examples (e.g., after block 820), the control system 105 (see Figure 2) transitions the power conversion system 100 to operate in DC-DC conversion mode. In such examples, the local controller 160 outputs a first variable signal by generating a second variable frequency soft-switching (VFSS) control signal to drive a first transistor pair based on a reference target (Ref) and the sensing characteristics of the corresponding conversion module 305. The local controller 160 further outputs a second variable signal that is phase-shifted relative to the first variable signal by generating a second phase-shifted VFSS control signal to drive a second transistor pair based on the reference target and sensing characteristics. Furthermore, the conversion module 305 outputs a DC signal containing the first variable signal interleaved into the second variable signal via an LC filter. The capacitors in the LC filter (which may be combined with one or more additional capacitors) can smooth the fluctuating signal to provide a DC output.

[0102] In some examples, the power conversion system 100 (e.g., control system 105) in Figure 1 includes applying operating boundaries within the constraints of a given converter module design and includes additional methods and control techniques for applying soft switching to a given converter module topology. During operation, the control system 105 applies these constraints using, for example, continuous variable frequency soft switching, variable frequency critical soft switching, and / or variable frequency discrete soft switching. These control techniques can be deployed as firmware protection of the conversion system 100 (e.g., as part of the control system 105) to provide further soft switching assurance for a given converter module design (interleaved or otherwise).

[0103] In some examples, the power conversion system 100 (e.g., the control system 105) controls the interleaved power converter 115 without dynamically changing the switching frequency during operation in order to achieve soft switching. For example, the control system 105 may have or be able to select a switching frequency for a given operation such that soft switching occurs at most or all of the interleaved power converter 115's potential operating points. In such an example, when performing method 800 in Figure 8, the control system 105 may generate a soft-switching (SS) control signal to drive a first pair of transistors and output a first AC signal (block 810), and may generate a phase-shift SS control signal to drive a second pair of transistors and output a second AC signal (block 815). The control system 105 may perform these modified blocks 810 and 815 in the same manner as described in other examples, except that a predetermined or static switching frequency is used.

[0104] Figure 10 shows a local controller 1000 as an example of a local controller 160. In the illustration, local controller 1000 functions as local controller 160a, but additionally, multiple local controllers 1000 may function as local controllers 160b and local controller 160c, respectively.

[0105] From the reference target and sensor data, the duty cycle (d a *To generate the ), the local controller 1000 (e.g., via the electronic processor 165) can implement or utilize model predictive control (MPC) using the model predictive controller 1005. As used herein, MPC can refer to a control algorithm that depends on or is aware of the dynamic characteristics of the system (e.g., implements or utilizes a dynamic model representing a transducer under control) and predicts input commands or reference values ​​for controlling the operation of the system by calculations based on the electrical characteristics and dynamic model of the transducer. Thus, as used herein, MPC can refer not only to model predictive control algorithms in a more strict sense (which will be explained in more detail below) but also to other dynamic predictive algorithms (e.g., linear-quadratic regulator (LQR) control algorithms).

[0106] In one example, to implement the MPC algorithm, the model predictive controller 1005 can solve the cost function using the electrical characteristics of its phase and the control reference objective during each control period. By solving the cost function, the model predictive controller 1005 can calculate the duty cycle (d a * By predicting future steps of ) and operating the power switching elements, the power conversion of the corresponding interleaved power converter 305 is controlled, and the control reference target (Ref a The model prediction controller 1005 can approach the duty cycle (d a * Based on the first step in a future step of ), the duty cycle of that particular interleaved power converter 305 (d a *) can be generated. Therefore, in contrast to the PI control algorithm, the MPC algorithm derives the optimal duty cycle by linearly processing the state variables and tracking errors with specific coefficients. Since integration is not required in MPC, the dynamics of MPC can be improved compared to PI control in that there is less overshoot and faster tracking speed. Furthermore, because MPC has a wide control bandwidth, the model prediction controller 1005 can provide an active damping term to mitigate (reduce or eliminate) any LC or LCL resonances that may be present in the filter circuit of the interleaved power converter 305 under control.

[0107] In some examples, to implement MPC, the model prediction controller 1005 uses "Sensor Data a (For example, inductor current i L,a Lower capacitor voltage v Cf,a , grid current i g,a ) and baseline targets (Ref a The model prediction controller 1005 receives the desired duty cycle d. a * To generate switching modulation, the MPC algorithm can be explicitly executed using a pre-configured piecewise affine function. For the digital execution of the MPC algorithm, a general state-space form, as shown below, can be described and applied to the various embodiments described herein.

number

[0108] The standardized matrix form can be represented as follows:

number

number

number

[0109] As shown below, the cost function consists of two terms.

number

number

[0110] In other examples, the local controller 160a implements non-MPC control technologies, such as PID control technology.

[0111] As previously mentioned with respect to Figure 4B, the model prediction controller 1005 uses a duty cycle criterion (d a * Based on the phase shift duty cycle criterion (d shift_a ) can be further generated. The model prediction controller 1005, as described above with respect to Figure 4B, uses a duty cycle criterion (d a * ) and phase shift duty cycle criteria (d shift_a ) can be supplied to the gate driver 410a. The model prediction controller 1005 has a duty cycle criterion d a *The frequency can also be supplied to the frequency generation controller 1010. The frequency generation controller 1010 uses the duty cycle reference (d) generated by the model prediction controller 1005. a * ) and "Sensor Data a Based on this (for example, using one of the switching frequency formulas above), the switching frequency (f SW The frequency generation controller 1010 can generate or calculate the switching frequency (f SW ) can be provided to the gate driver 410a.

[0112] This specification describes one or more electronic controllers (e.g., a central controller 150, and possibly more local controllers 160). An electronic controller comprises one or more processors (e.g., one or more microprocessors) configured to facilitate power conversion (e.g., by controlling the switching devices of an interleaved power conversion system, as described herein), and one or more memory or storage devices. The potentially more than one storage device may include a computer program product, when running on the electronic controller (which may be a processor-based device as described above), that causes the processor-based device to perform operations to facilitate the implementation of the procedures and operations described herein. The electronic controller may further include peripherals for implementing input / output functions. Such peripherals may include, for example, a flash drive (e.g., a removable flash drive) or a network connection (e.g., implemented using a USB port and / or wireless receiver) for downloading relevant content to a connected system. Such peripherals may also be used to download software containing computer instructions that enable the general operation of the respective system / device. Alternatively or additionally, in some embodiments, special-purpose logic circuits such as FPGAs (Field-Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), DSP processors, graphics processing units (GPUs), application processing units (APUs), and composite programmable logic devices (CPLDs) can also be used to implement the electronic controller. Other modules accompanying the electronic controller include user interfaces for providing or receiving input and output data. The electronic controller may also include an operating system.

[0113] Computer programs (also called programs, software, software applications, or code) contain machine language instructions for programmable processors and can be implemented in high-level procedural and / or object-oriented programming languages ​​and / or assembly / machine languages. As used herein, the term “machine-readable medium” refers to non-volatile computer program products, apparatus, and / or devices (e.g., magnetic disks, optical disks, memory, programmable logic devices (PLDs)) used to provide machine language instructions and / or data to a programmable processor, and includes non-volatile machine-readable mediums that receive machine language instructions as machine-readable signals.

[0114] In some embodiments, any suitable computer-readable medium can be used to store instructions for performing the processes / operations / procedures described herein. For example, in some embodiments, the computer-readable medium may be volatile or non-volatile. For example, non-volatile computer-readable media may include magnetic media (hard disks, floppy disks, etc.), optical media (compact disks, digital video disks, Blu-ray disks, etc.), semiconductor media (flash memory, electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc.), any suitable medium that is not transient during transmission and has no indication of persistence whatsoever, and / or any suitable tangible medium. As another example, volatile computer-readable media may include networks, wires, conductors, optical fibers, signals on circuits, any suitable medium that is transient during transmission and has no indication of persistence whatsoever, and / or any suitable intangible medium.

[0115] While specific embodiments have been disclosed in detail here, this is for illustrative purposes only and is not intended to limit the scope of the attached claims. Features of the disclosed embodiments can be combined and rearranged within the scope of the invention to derive more embodiments. Other aspects, advantages, and modifications are also considered to be included within the claims provided below. The presented claims represent at least some of the embodiments and features disclosed herein. Other embodiments and features not described in the claims are also conceivable.

[0116] (Additional example) Example 1: A method, apparatus, and / or a non-volatile computer-readable medium for storing processor-processable instructions for a power conversion system, the power conversion system comprising an interleaved power conversion module and a control system for controlling the interleaved power conversion module. The interleaved power conversion module comprises a plurality of direct current (DC) link nodes, a first transistor pair and a second transistor pair coupled between the DC link nodes, an LC filter circuit, and a plurality of alternating current (AC) nodes. The control system comprises a central controller and local controllers. The central controller is configured to generate a reference target based on the detection characteristics of the interleaved power conversion module. The local controllers are configured to receive the reference target and, based on the reference target and the detection characteristics, generate a variable frequency soft-switching (VFSS) control signal to drive the first transistor pair that outputs a first AC signal, and based on the reference target and the detection characteristics, generate a phase-shift VFSS control signal to drive the second transistor pair that outputs a second AC signal that is phase-shifted relative to the first AC signal. The interleaved power conversion module outputs an interleaved signal including the first AC signal interleaved into the second AC signal via the LC filter circuit, and a non-volatile computer-readable medium for storing a method, apparatus, and / or processor-processable instructions.

[0117] Example 2: The method, apparatus, and / or non-volatile computer-readable medium according to Example 1, wherein the local controller is configured to determine the duty cycle of the VFSS control signal and the frequency of the VFSS control signal, and the phase-shifted VFSS control signal has the same duty cycle and frequency as the VFSS control signal.

[0118] Example 3: The method, apparatus, and / or non-volatile computer-readable medium according to either Example 1 or 2, wherein the local controller is configured to generate the duty cycle for the VFSS control signal using model predictive control.

[0119] Example 4: The method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 3, wherein the VFSS control signal comprises a first PWM signal for the upper transistor of the first transistor pair and a second PWM signal for the lower transistor of the first transistor pair, the second PWM signal being the inverse of the first PWM signal.

[0120] Example 5: Phase shift relative to the VFSS control signal The phase shift of the VFSS control signal is set to 360 degrees divided by the number of levels of the interleaved power conversion module, the method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 4.

[0121] Example 6: The method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 5, further comprising: a second interleaved power conversion module including a plurality of second direct current (DC) link nodes, a third and fourth transistor pair coupled between the DC link nodes, a second LC filter circuit, and a plurality of second alternating current (AC) nodes; and a second local controller configured to receive a second reference target from the central controller, generate a second VFSS control signal to drive the third transistor pair that outputs a third AC signal based on the second reference target, and generate a second phase-shifted VFSS control signal to drive the fourth transistor pair that outputs a fourth AC signal that is phase-shifted relative to the third AC signal based on the second reference target, wherein the second interleaved power conversion module outputs a second interleaved signal including the third AC signal interleaved into the fourth AC signal via the second LC filter circuit.

[0122] Embodiment 7: A third interleaved power conversion module comprising a plurality of third direct current (DC) link nodes, a fifth and sixth transistor pair coupled between the DC link nodes, a third LC filter circuit, and a plurality of third alternating current (AC) nodes; and a third local controller configured to receive a third reference target from the central controller, generate a third VFSS control signal to drive the fifth transistor pair that outputs a fifth AC signal based on the third reference target, and generate a third phase-shifted VFSS control signal to drive the sixth transistor pair that outputs a sixth AC signal that is phase-shifted relative to the fifth AC signal based on the third reference target, wherein the third interleaved power conversion module outputs a third interleaved signal via the third LC filter circuit, the sixth AC signal being interleaved to the fifth AC signal, and the first interleaved signal, the second interleaved signal, and the third interleaved signal provide a three-phase AC output; further comprising the method, apparatus, and / or non-volatile computer-readable medium according to Embodiment 6.

[0123] Example 8: The method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 7, wherein the first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first intermediate node, the second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second intermediate node, and the LC filter circuit comprises a first inductor coupled between the first intermediate node and the output node of the AC node, and a second inductor coupled between the second intermediate node and the output node of the AC node.

[0124] Example 9: The method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 8, wherein the first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first intermediate node, the second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second intermediate node, and the LC filter circuit comprises a coupling inductor coupled between the first intermediate node, the second intermediate node, and the output node of the AC node.

[0125] Example 10: The method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 9, wherein the first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first intermediate node, the second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second intermediate node, the first intermediate node is coupled to the second intermediate node by a capacitor, the first lower transistor is coupled to the second upper transistor by a third intermediate node, and the LC filter circuit comprises an inductor coupled between the third intermediate node and the output node of the AC node.

[0126] Example 11: The interleaved power conversion module further includes a pair of diodes coupled to a neutral point connection, the first transistor pair comprising a first upper transistor coupled to a first lower transistor via a first connection node, the second transistor pair comprising a second upper transistor coupled to a second lower transistor via a second connection node, the pair of diodes connected between the first and second connection nodes, the first lower transistor coupled to the second upper transistor via an intermediate node, and the LC filter circuit comprising an inductor coupled between the intermediate node and the output node of the AC node, the method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 10.

[0127] Example 12: The method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 11, wherein the interleaved power conversion module is a hybrid topology including a combination of (i) a multi-inductor interleaved converter or a coupled inductor interleaved converter, and (ii) a flying capacitor type multilevel interleaved converter or a neutral point connected multilevel interleaved converter.

[0128] Example 13: The interleaved power conversion module is bidirectional, and in rectifier mode, the local controller is configured to generate a second VFSS control signal that drives the first transistor pair to convert a first input AC signal received through the LC filter circuit to a first DC output on the DC link node based on the reference target and the detection characteristics, and to generate a second phase-shift VFSS control signal that drives the second transistor pair to convert a second input AC signal received through the LC filter circuit to a second DC output on the DC link node based on the reference target and the detection characteristics, and the interleaved power conversion module outputs a DC signal via the DC link node that includes the first DC output with the second DC output summed, the method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 12.

[0129] Example 14: The interleaved power conversion module operates in DC-DC conversion mode, the local controller is configured to generate a second VFSS control signal to drive the first pair of transistors that output a first variation signal based on the reference target and the detection characteristics, and a second phase-shift VFSS control signal to drive the second pair of transistors that output a second variation signal that is phase-shifted relative to the first variation signal based on the reference target and the detection characteristics, and the interleaved power conversion module outputs a DC signal via the LC filter circuit that includes the first variation signal interleaved with the second variation signal, the method, apparatus, and / or non-volatile computer-readable medium according to any one of Examples 1 to 13.

[0130] Example 15: A method, apparatus, and / or a non-volatile computer-readable medium for storing processor-processable instructions for a power conversion system, the power conversion system comprising an interleaved power conversion module and a control system for controlling the interleaved power conversion module. The interleaved power conversion module comprises a plurality of direct current (DC) link nodes on a first side, a first transistor pair and a second transistor pair coupled between the DC link nodes, an LC filter circuit, and a second side node on a second side. The control system comprises a central controller and local controllers. The central controller is configured to generate a reference target based on the detection characteristics of the interleaved power converter. The local controllers are configured to receive the reference target and, based on the reference target and the detection characteristics, generate a variable frequency soft-switching (VFSS) control signal to drive the first transistor pair to output a first variable signal, and based on the reference target and the detection characteristics, generate a phase-shifted VFSS control signal to drive the second transistor pair to output a second variable signal that is phase-shifted relative to the first variable signal. The interleaved power conversion module outputs a DC signal that includes the first variable signal interleaved by the second variable signal via the LC filter circuit.

[0131] Example 16: A method, apparatus, and / or a non-volatile computer-readable medium for storing processor-processable instructions for a power conversion system, the power conversion system comprising an interleaved power conversion module and a control system for controlling the interleaved power conversion module. The interleaved power conversion module comprises a plurality of direct current (DC) link nodes on a first side, a first transistor pair and a second transistor pair coupled between the DC link nodes, an LC filter circuit, and a second side node on a second side. The control system comprises a central controller and local controllers. The central controller is configured to generate a reference target based on the detection characteristics of the interleaved power converter. The local controller is configured to drive the first transistor pair by generating a variable frequency soft switching (VFSS) control signal based on the reference target and the detection characteristics, converting the first input AC signal received through the LC filter into a first DC output on the DC link node; to drive the second transistor pair by generating a phase-shift VFSS control signal based on the reference target and the detection characteristics, converting the second input AC signal received through the LC filter into a second DC output on the DC link node; and the interleaved power conversion module outputs a DC signal via the DC link node, including the first DC output which is added by the second DC output.

Claims

1. An interleaved power conversion module including multiple direct current (DC) link nodes, a first transistor pair and a second transistor pair coupled between the DC link nodes, an LC filter circuit, and multiple alternating current (AC) nodes, A control system for controlling the interleaved power conversion module, Includes, The control system is A central controller configured to generate a reference target based on the detection characteristics of an interleaved power conversion module, It is a local controller, Upon receiving the aforementioned reference target, Based on the aforementioned reference target and the aforementioned detection characteristics, a variable frequency soft switching (VFSS) control signal is generated to drive the first transistor pair that outputs the first AC signal. A local controller is configured to generate a phase-shift VFSS control signal to drive a second transistor pair that outputs a second AC signal that is phase-shifted relative to the first AC signal, based on the aforementioned reference target and the aforementioned detection characteristics. Includes, The interleaved power conversion module is an interleaved power conversion system that outputs an interleaved signal including the first AC signal interleaved into the second AC signal via the LC filter circuit.

2. In order to generate the VFSS control signal for driving the first transistor pair, the local controller, Determine the duty cycle of the VFSS control signal. The frequency of the VFSS control signal is determined by the configuration, The phase-shift VFSS control signal has the same duty cycle and frequency as the VFSS control signal. The interleaved power conversion system according to claim 1.

3. The interleaved power conversion system according to claim 2, wherein the local controller is configured to generate the duty cycle for the VFSS control signal using model predictive control.

4. The VFSS control signal comprises a first PWM signal for the upper transistor of the first transistor pair and a second PWM signal for the lower transistor of the first transistor pair. The second PWM signal is the inverse of the first PWM signal. The interleaved power conversion system according to claim 1.

5. The interleaved power conversion system according to claim 1, wherein the phase shift of the VFSS control signal relative to the VFSS control signal is set to 360 degrees divided by the number of levels of the interleaved power conversion module.

6. A second interleaved power conversion module including multiple second direct current (DC) link nodes, a third transistor pair and a fourth transistor pair coupled between the DC link nodes, a second LC filter circuit, and multiple second alternating current (AC) nodes, The second local controller, The second reference target is received from the central controller. Based on the second reference target, a second VFSS control signal is generated to drive the third transistor pair that outputs the third AC signal. A second local controller is configured to generate a second phase-shift VFSS control signal to drive the fourth transistor pair that outputs a fourth AC signal that is phase-shifted relative to the third AC signal, based on the second reference target, It further includes, The interleaved power conversion system according to claim 1, wherein the second interleaved power conversion module outputs a second interleaved signal including the third AC signal interleaved into the fourth AC signal via the second LC filter circuit.

7. A third interleaved power conversion module including multiple third direct current (DC) link nodes, a fifth and sixth transistor pair coupled between the DC link nodes, a third LC filter circuit, and multiple third alternating current (AC) nodes, The third local controller is, The third reference target is received from the aforementioned central controller. Based on the third reference target, a third VFSS control signal is generated to drive the fifth transistor pair that outputs the fifth AC signal. A third local controller is configured to generate a third phase-shift VFSS control signal to drive the sixth transistor pair that outputs a sixth AC signal that is phase-shifted relative to the fifth AC signal based on the third reference target, It further includes, The third interleaved power conversion module outputs a third interleaved signal including the sixth AC signal interleaved with the fifth AC signal via the third LC filter circuit. The interleaved power conversion system according to claim 6, wherein the first interleaved signal, the second interleaved signal, and the third interleaved signal provide a three-phase AC output.

8. The first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first intermediate node, The second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second intermediate node, The interleaved power conversion system according to claim 1, wherein the LC filter circuit comprises a first inductor coupled between the first intermediate node and the output node of the AC node, and a second inductor coupled between the second intermediate node and the output node of the AC node.

9. The first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first intermediate node, The second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second intermediate node, The interleaved power conversion system according to claim 1, wherein the LC filter circuit comprises a coupling inductor coupled between the first intermediate node, the second intermediate node, and the output node of the AC node.

10. The first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first intermediate node, The second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second intermediate node, The first intermediate node is coupled to the second intermediate node by a capacitor. The first lower transistor is coupled to the second upper transistor by a third intermediate node. The interleaved power conversion system according to claim 1, wherein the LC filter circuit comprises an inductor coupled between the third intermediate node and the output node of the AC node.

11. The interleaved power conversion module further includes a pair of diodes coupled to a neutral point connection, The first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first connection node, The second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second connection node, The pair of diodes is connected between the first connection node and the second connection node. The first lower transistor is coupled to the second upper transistor via an intermediate node. The interleaved power conversion system according to claim 1, wherein the LC filter circuit comprises an inductor coupled between the intermediate node and the output node of the AC node.

12. The aforementioned interleaved power conversion module is (i) Multi-inductor interleaved converter, or coupled inductor interleaved converter, and (ii) The interleaved power conversion system according to claim 1, which is a hybrid topology including a combination of a flying capacitor type multilevel interleaved converter or a neutral point connected multilevel interleaved converter.

13. The aforementioned interleaved power conversion module is bidirectional, In rectifier mode, the local controller, Based on the aforementioned reference target and the aforementioned detection characteristics, a second VFSS control signal is generated to drive the first transistor pair to convert the first input AC signal received through the LC filter circuit into a first DC output on the DC link node. Based on the aforementioned reference target and the aforementioned detection characteristics, the system is configured to generate a second phase-shift VFSS control signal that drives the second transistor pair to convert the second input AC signal received through the LC filter circuit into a second DC output on the DC link node. The interleaved power conversion system according to claim 1, wherein the interleaved power conversion module outputs a DC signal via the DC link node that includes the first DC output obtained by summing the second DC outputs.

14. The interleaved power conversion module operates in DC-DC conversion mode, and the local controller operates as follows: Based on the aforementioned reference target and the aforementioned detection characteristics, a second VFS control signal is generated to drive the first transistor pair that outputs the first fluctuation signal. The system is configured to generate a second phase-shift VFS control signal to drive a second transistor pair that outputs a second fluctuation signal that is phase-shifted relative to the first fluctuation signal, based on the aforementioned reference target and the aforementioned detection characteristics. The interleaved power conversion system according to claim 1, wherein the interleaved power conversion module outputs a DC signal including the first fluctuating signal interleaved with the second fluctuating signal via the LC filter circuit.

15. The local controller receives a reference target from the central controller based on the detection characteristics of the interleaved power conversion module, the interleaved power conversion module includes a plurality of direct current (DC) link nodes, a first transistor pair and a second transistor pair coupled between the DC link nodes, an LC filter circuit, and a plurality of alternating current (AC) nodes. Based on the aforementioned reference target and the aforementioned detection characteristics, a variable frequency soft switching (VFSS) control signal is generated to drive the first transistor pair that outputs the first AC signal. Based on the aforementioned reference target and the aforementioned detection characteristics, a phase-shift VFS control signal is generated to drive the second transistor pair that outputs a second AC signal that is phase-shifted relative to the first AC signal. An interleaved power conversion method, comprising outputting an interleaved signal including the first AC signal interleaved with the second AC signal via the LC filter circuit.

16. Generating the VFS control signal for driving the first transistor pair is: Determine the duty cycle of the VFSS control signal. This includes determining the frequency of the VFSS control signal, The phase-shift VFSS control signal has the same duty cycle and frequency as the VFSS control signal. The method according to claim 15.

17. The method according to claim 16, wherein generating the duty cycle for the VFSS control signal includes generating the duty cycle using model predictive control.

18. The method further includes providing a first PWM signal of the VFSS control signal to the upper transistor of the first transistor pair, and providing a second PWM signal of the VFSS control signal to the lower transistor of the first transistor pair. The method according to claim 15, wherein the second PWM signal is the inversion of the first PWM signal.

19. The method according to claim 15, wherein the phase shift of the VFSS control signal relative to the VFSS control signal is set to 360 degrees divided by the number of levels of the interleaved power conversion module.

20. The second local controller receives a second reference target from the central controller, and the second reference target is generated based on the detection characteristics of a second interleaved power conversion module, which includes a plurality of second direct current (DC) link nodes, a third and fourth transistor pair coupled between the DC link nodes, a second LC filter circuit, and a plurality of second alternating current (AC) nodes. Based on the second reference target, a second VFSS control signal is generated to drive the third transistor pair that outputs the third AC signal. A second phase-shift VFS control signal is generated to drive the fourth transistor pair that outputs a fourth AC signal that is phase-shifted relative to the third AC signal, based on the second reference target. The method according to claim 15, further comprising the second interleaved power conversion module outputting a second interleaved signal including the third AC signal interleaved into the fourth AC signal via the second LC filter circuit.

21. The third local controller receives a third reference target from the central controller, and the third reference target is generated based on the detection characteristics of a third interleaved power conversion module, which includes a plurality of third direct current (DC) link nodes, a fifth and sixth transistor pair coupled between the DC link nodes, a third LC filter circuit, and a plurality of third alternating current (AC) nodes. Based on the third reference target, a third VFSS control signal is generated to drive the fifth transistor pair that outputs the fifth AC signal. A third phase-shift VFS control signal is generated to drive the sixth transistor pair that outputs a sixth AC signal that is phase-shifted relative to the fifth AC signal, based on the third reference target. The third interleaved power conversion module further includes outputting a third interleaved signal, which includes the fifth AC signal interleaved into the sixth AC signal, via the third LC filter circuit. The method according to claim 20, wherein the first interleaved signal, the second interleaved signal, and the third interleaved signal provide a three-phase AC output.

22. The first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first intermediate node, The second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second intermediate node, The method according to claim 15, wherein the LC filter circuit comprises a first inductor coupled between the first intermediate node and the output node of the AC node, and a second inductor coupled between the second intermediate node and the output node of the AC node.

23. The first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first intermediate node, The second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second intermediate node, The method according to claim 15, wherein the LC filter circuit comprises a coupling inductor coupled between the first intermediate node, the second intermediate node, and the output node of the AC node.

24. The first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first intermediate node, The second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second intermediate node, The first intermediate node is coupled to the second intermediate node by a capacitor. The first lower transistor is coupled to the second upper transistor by a third intermediate node. The method according to claim 15, wherein the LC filter circuit comprises an inductor coupled between the third intermediate node and the output node of the AC node.

25. The interleaved power conversion module further includes a pair of diodes coupled to a neutral point connection, The first transistor pair comprises a first upper transistor coupled to a first lower transistor via a first connection node, The second transistor pair comprises a second upper transistor coupled to a second lower transistor via a second connection node, The pair of diodes is connected between the first connection node and the second connection node. The first lower transistor is coupled to the second upper transistor via an intermediate node. The method according to claim 15, wherein the LC filter circuit comprises an inductor coupled between the intermediate node and the output node of the AC node.

26. The aforementioned interleaved power conversion module is (i) Multi-inductor interleaved converter, or coupled inductor interleaved converter, and (ii) The method according to claim 15, wherein the hybrid topology includes a combination of a flying capacitor type multilevel interleaved converter or a neutral point connected multilevel interleaved converter.

27. The aforementioned interleaved power conversion module is bidirectional, In rectifier mode, the method further includes: Based on the aforementioned reference target and the aforementioned detection characteristics, a second VFSS control signal is generated to drive the first transistor pair to convert the first input AC signal received through the LC filter circuit into a first DC output on the DC link node. Based on the aforementioned reference target and the aforementioned detection characteristics, a second phase shift VFS control signal is generated to drive the second transistor pair to convert the second input AC signal received through the LC filter circuit into a second DC output on the DC link node. The method according to claim 15, comprising outputting a DC signal via the DC link node that includes the first DC output which is the sum of the second DC outputs.

28. The interleaved power conversion module operates in DC-DC conversion mode, The above method further, Based on the aforementioned reference target and the aforementioned detection characteristics, a second VFS control signal is generated to drive the first transistor pair that outputs the first fluctuation signal. A second phase-shift VFS control signal is generated to drive the second transistor pair that outputs a second fluctuation signal that is phase-shifted relative to the first fluctuation signal, based on the aforementioned reference target and the aforementioned detection characteristics. The method according to claim 15, further comprising outputting a DC signal including the first fluctuating signal interleaved with the second fluctuating signal via the LC filter circuit.

Images