Systems and methods for switching

Abstract

A system and method for switching are disclosed. In one example, the switching system comprises a photonic integrated circuit (PIC) having an optical port, an electrical integrated circuit (EIC) stacked on the PIC and having a switching circuit, and a photonic transceiver optically coupled to the optical port of the PIC and electrically coupled to the switching circuit of the EIC, wherein the switching circuit is configured to transfer a digital signal generated from an optical signal received by a first photonic transceiver of the photonic transceiver to a second photonic transceiver of the photonic transceiver based on information in the digital signal, the first photonic transceiver being optically coupled to a first optical port of the PIC, and the second photonic transceiver being optically coupled to a second optical port of the PIC.

Description

TECHNICAL FIELD

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 592,509 filed on October 23, 2023, which is hereby incorporated herein by reference in its entirety. SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0002] Background Demand for artificial intelligence (AI) computing, such as machine learning (ML) and deep learning (DL), is growing faster than can be met by increases in available processing power. This growing demand and the increasing complexity of AI models drive the need to move large volumes of data between compute and / or memory nodes in data centers. In many conventional systems, data movement results in significant power consumption, insufficient performance, and excessive latency. Accordingly, a multi-node computing system capable of processing and transmitting data quickly and efficiently between nodes may be advantageous for AI computing implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Brief Description of the Drawings [Figure 1A] FIG. 1 is a perspective view of an example of a circuit package including an EIC stacked on a PIC for manufacturing a multi-port network switch.

[0004] [Figure 1B] FIG. 1B is a side view of the circuit package of FIG. 1A including the EIC and the PIC, where the PIC is mounted on a substrate.

[0005] [Figure 2A]This is a side view of an exemplary photonic transceiver for a multiport network switch, where part of the photonic transceiver is implemented in an EIC and part of the photonic transceiver is implemented in a PIC.

[0006] [Figure 2B] Figure 2A is an enlarged side view of the photonic transceiver.

[0007] [Figure 3A] This is a top view of an example of a multiport network switch coupled between four different nodes located outside the multiport network switch.

[0008] [Figure 3B] Figure 3A is a bottom perspective view of the EIC.

[0009] [Figure 3C] Figure 3A is a side view of a multiport network switch.

[0010] [Figure 4] This illustrates the communication of digital data between a multiport network switch and a node.

[0011] [Figure 5A] This is an exemplary top view of a multiport network switch configured for use in a leaf-spine network architecture.

[0012] [Figure 5B] Figure 5A is a bottom perspective view of the EIC.

[0013] [Figure 5C] Figures 5A and 5B are side cross-sections of the multiport network switch.

[0014] [Figure 6]This is an example of a leaf-spine network architecture in which the multi-port network switch described with reference to FIG. 5A to FIG. 5C is used as a switch within the leaf-spine network architecture.

[0015] [Figure 7] This is a top view of the multi-port network switch described with reference to FIG. 5A to FIG. 5C, where the optical ports of the multi-port network switch are labeled with the nodes or spine switches to which the optical ports are optically coupled, and the photonic transceivers are labeled with the corresponding optical port numbers to which the photonic transceivers are optically coupled.

[0016] [Figure 8] This is an example of a switching circuit that may be implemented in a multi-port network switch.

[0017] [Figure 9] This is an example of a MAC table that may be maintained and utilized by the switching circuit.

[0018] [Figure 10A] This is an example of a multi-port network switch in which photonic transceivers are arranged on both sides of the switching circuit.

[0019] [Figure 10B] This is an example of a multi-port network switch in which photonic transceivers are arranged in a mesh configuration relative to the switching circuit.

[0020] [Figure 11A] This is a top view of an example of a multi-port network switch configured with a matrix of photonic transceiver cells.

[0021] [Figure 11B] This is a bottom perspective view of the EIC of FIG. 11A.

[0022] [Figure 11C] This is a top view of the multiport network switch described with reference to Figures 11A and 11B, where the optical ports and photonic transceivers are labeled with their corresponding optical port numbers.

[0023] [Figure 12] For example, this is a process flow diagram of a method for switching network traffic using the multiport network switch described herein.

[0024] [Figure 13] For example, this is a process flow diagram of a method for switching network traffic using an integrated circuit device (e.g., EIC) described herein.

[0025] Throughout the description, similar reference numbers may be used to identify similar elements. [Modes for carrying out the invention]

[0026] Detailed explanation Multiport network switches are used to direct network traffic from the input ports to the output ports of a multiport network switch based on some information within the network traffic, such as some header information within the data packets of the network traffic. With a higher level of integration, many of the functions of a multiport network switch can be integrated into a single chip, such as a single IC device. While various examples of single-chip multiport network switches exist, in many cases, the data interface to and from the IC device, called a media-independent interface (MII), is physically located at the edge or beachfront of the IC device, and the physical layer "PHY" device (e.g., fiber optic PHY device and / or copper wire PHY device) is typically located outside the chip near the periphery of the IC device, on the same plane as the IC device. For example, a single-chip switch is typically mounted on a printed circuit board (PCB), and the PHY device is connected to the PCB at the periphery of the single-chip switch. In particular, for switches with multiple optical ports, the conversion of signals from the optical domain to the electrical domain and from the electrical domain to the optical domain occurs only at the beachfront or periphery of the IC device. As the desired number of ports on a multiport network switch increases and / or the size of the IC device decreases, the physical mounting area at the edge of the IC device can become a limiting factor in the number of ports that can be supported by a single-chip multiport network switch. However, to realize a multiport network switch that can switch data between the optical ports of a multiport network switch without being limited to the beachfront of the EIC, it has been recognized that photonic transceivers formed by electronic integrated circuits (EICs) stacked on a photonic integrated circuit (PIC) can be coupled with switching circuits within the EIC.In one example, in contrast to conventional single-chip switches where the data interface to the IC device (e.g., MII) is located only on the periphery of the IC device, at least some of the photonic transceivers are physically located within the internal region of the EIC. Such multi-port network switches enable high-speed network switching with previously unattainable port density and power efficiency.

[0027] For example, a multiport network switch can be deployed in a data center implementing, for instance, machine learning (ML) models and / or artificial neural networks (ANNs). In one specific example, a multiport network switch can be deployed as a top-of-rack (ToR) switch in a data center that utilizes a leaf-spine network architecture to connect nodes, such as compute nodes and / or memory nodes running ANN workloads, across multiple racks of such nodes.

[0028] Figure 1A is a perspective view of an example of a circuit package 100 including an EIC 102 stacked on a PIC 104 to manufacture a multiport network switch including multiple photonic transceivers (not shown). In this example, both the EIC and PIC are planar structures having two main surfaces, referred to herein as the upper main surface and the lower main surface. In the perspective view of Figure 1A, the upper main surfaces 106 and 108 of both the EIC and PIC are visible, and the lower main surface of the EIC is directly adjacent to the upper main surface of the PIC and is parallel to its plane. Note that the EIC and PIC are not to scale, and their sizes relative to each other may differ from those shown in Figure 1A. Furthermore, the PIC may be mounted on a planar substrate including electrical connections to the PIC and EIC. In one example, the EIC and PIC are physically and electrically connected to each other by electrical interconnections, e.g., solder bumps, and the distance between the lower main surface of the EIC and the upper main surface of the PIC is less than 2 mm, often less than 50 microns.

[0029] Figure 1B is a side view of the circuit package 100 of Figure 1A, which includes the EIC 102 and PIC 104, with the PIC mounted on a substrate 110. Figure 1B also shows optical elements, including an optical interface such as a fiber array unit (FAU) 112 on the PIC corresponding to the optical port 116 of a multiport network switch, and an external waveguide 114 (e.g., optical fiber) connected to the FAU. Again, note that the elements shown in Figure 1B may not be to scale. In the examples of Figures 1A and 1B, the EIC and PIC are formed on separate semiconductor chips, typically silicon chips, but other semiconductor materials can also be used. In the example of Figure 1B, the PIC is mounted directly to the substrate, which includes solder bumps 118 for subsequent mounting to, for example, a printed circuit board (PCB). In the example of Figure 1B, other means of connecting the optical waveguide to the PIC are also possible, but the FAU connecting the PIC to an external waveguide (e.g., optical fiber) is positioned on top of the PIC and optically connected to the PIC. If necessary, the circuit package 100 shown in Figures 1A and 1B may further include other elements such as memory attached to the PIC.

[0030] For example, a fiber array unit (FAU) is a device used in optical communication systems to couple or separate optical signals from multiple fibers into a single optical signal or multiple optical signals, respectively. FAUs can be used in a variety of applications, including wavelength division multiplexing (WDM), parallel optical interconnects, and optical sensing. There are two main types of fiber array units that can be used: linear and circular. Linear FAUs couple or separate optical signals along a straight line, while circular fiber array units couple or separate optical signals in a circular configuration. Both types of FAUs are typically made from precision-molded optical plastic or ceramic material and can have from a few to several hundred fibers arranged in a specific pattern. The choice of FAU depends on the specific requirements of the application, such as the number of fibers, the arrangement of the fibers, the wavelength of light used, and the desired coupling efficiency.

[0031] For example, EIC102 includes a high-speed integrated circuit configured to support photonic transceivers and data switching. The EIC may be an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or system-on-a-chip (SoC) designed and fabricated using state-of-the-art CMOS nodes. The EIC may include circuits for serialization / deserialization, clocking and data recovery, modulator drivers, and circuits for implementing amplifiers and switching circuits that implement the photonic transceivers.

[0032] A waveguide may be a structure that guides and / or confines light waves to facilitate the propagation of light along a desired path to a desired location. For example, the waveguide may be an optical fiber, a planar waveguide, a glass-etched waveguide, a photonic crystal waveguide, a free-space waveguide, any other suitable structure for guiding optical signals, and a combination thereof. In some embodiments, one or more internal waveguides are formed within the PIC 104. In some embodiments, one or more external waveguides, such as an optical fiber 114 or a ribbon containing multiple optical fibers, are mounted outside the PIC.

[0033] The PIC104 may include one or more internal waveguides optically coupled to the optical port 116 of the multiport network switch. For example, as will be described in more detail below, one or more optical ports may be optically coupled to another optical port on another computing device. In some examples, the internal waveguides of the PIC are implemented (e.g., formed) in the PIC to connect photonic elements within the PIC. In other examples, one or more optical ports of the PIC may be optically coupled to an optical port of another computing device located in a separate circuit package or on a separate chip to form an inter-chip connection. In some embodiments, an external waveguide is implemented in relation to the PIC to connect photonic ports across multiple chips. For example, the optical ports of the PIC may be connected across multiple chips via optical fibers. In some embodiments, the external waveguide (e.g., optical fiber) connects directly to the photonic ports of each computing device across multiple chips. In some embodiments, the external waveguide is implemented in relation to one or more internal waveguides formed within the PIC on one or more chips. For example, one or more internal waveguides may internally connect one or more photonic ports to one or more additional optical components located in another part of the circuit package (e.g., another part of the PIC) to facilitate coupling with an external waveguide. For example, an internal waveguide in the PIC may be connected to one or more optical coupling structures, including FAUs, located on a grating coupler (GC), or to an edge coupler. In some embodiments, one or more FAUs are implemented to facilitate coupling between the external waveguide and the internal waveguide to facilitate inter-chip interconnection to another circuit package for both transmission and reception of optical signals. In some embodiments, one or more FAUs are implemented to supply optical power to the PIC from an external laser source to drive photonics within the PIC (e.g., to provide one or more optical carrier signals).

[0034] In one example, the EIC102 and PIC104 may be manufactured using standard wafer manufacturing processes, such as photolithography patterning, etching, and ion implantation. Furthermore, in some embodiments, heterogeneous material platforms and integrated processes are used. For example, various active photonic components used in photonic transceivers, such as laser light sources and optical modulators and / or photodetectors, may be implemented using III-V semiconductor components.

[0035] As those skilled in the art will understand, the structure of the illustrated circuit package 100 is just one of several possible ways of assembling and packaging various components. In some examples, some or all of the EIC 102 is mounted on a substrate 110. In some examples, it is also possible to create the EIC and PIC 104 on different layers of a single semiconductor chip. In some examples, the photonic circuit layer contains or consists of multiple PICs. Multiple layers of PICs, or multilayer PICs, can help reduce waveguide crossing. Furthermore, the structures shown in Figures 1A and 1B may be modified to include multiple EICs connected to a single PIC. For example, multiple EICs may be connected to each other via photonic channels within the PIC.

[0036] In one example, one or more light sources are optically coupled to a circuit package 100, for example, a multiport network switch. The one or more light sources may include laser light sources mounted either inside or outside the circuit package. If externally mounted, connection to the circuit package may be optically made using a grating coupler in the PIC 104 under the FAU 112 and / or using an edge coupler. In some embodiments, the lasers are mounted within the circuit package by using an interposer containing several lasers that can be simultaneously packaged and edge-coupled with the PIC. In some embodiments, the lasers are directly integrated into the PIC using heterogeneous or homogeneous integration. Homogeneous integration allows the lasers to be directly mounted within the silicon substrate on which the waveguides of the PIC are formed, enabling lasers of different materials such as indium phosphide (InP) and architectures such as quantum dot lasers. Heterogeneous assembly of lasers on the PIC allows III-V semiconductors or other materials to be precisely mounted on the PIC and optically coupled to waveguides mounted on the PIC.

[0037] In one example, data is communicated between EIC102 and PIC104 using a photonic transceiver that includes a first portion in the EIC and a second portion in the PIC. Figure 2A is a side view of an exemplary photonic transceiver 220 for a multiport network switch to EIC202 and PIC204, where part of the photonic transceiver is embodied in the EIC and part of the photonic transceiver is embodied in the PIC. Although not shown in Figure 2A, in the exemplary multiport network switch, the photonic transceiver is optically coupled to the optical port of the PIC and electrically coupled to the switching circuit of the EIC. Digital data can be passed from the electrical domain of the EIC to the optical domain of the PIC (arrow 222), and digital data can be passed from the optical domain of the PIC to the electrical domain of the PIC (arrow 224), as indicated by arrows and further described below. An example of how a multiport network switch is formed using photonic transceivers is described below.

[0038] Figure 2B is an enlarged side view of the photonic transceiver 220 from Figure 2A, in which the first part 226 of the photonic transceiver in the EIC202 includes a driver 230 and an amplifier 232 (e.g., a transimpedance amplifier (TIA)), and the second part 228 of the photonic transceiver in the PIC204 includes a modulator 234 (e.g., an electroabsorption modulator (EAM)) and a photodetector 236. The first and second parts of the photonic transceiver are electrically connected to each other by an electrical interconnect 238. In one example, the electrical interconnect is a copper pillar less than 2 millimeters in diameter, often less than 50 microns. In other examples, the electrical interconnect may be a solder bump formed of a material such as tin, silver, or copper. When a solder bump is used for the electrical interconnect, the solder bump may be a flip-chip bump. In yet another example, the interconnection may be an element of a ball grid array (BGA), a pin of a pin grid array (PGA), an element of a land grid array (LGA), or some other type of electrical interconnection. Generally, an electrical interconnection may physically and electrically couple a portion of a photonic transceiver in an EIC to a portion of a photonic transceiver in a PIC. For example, one or more electrical interconnections may physically couple a conductive pad in the EIC to a conductive pad in the PIC, allowing electrical signals to pass between the conductive pads of the EIC and the PIC. Electrical interconnections do not have to have a uniform size, shape, or pitch. A finer-pitch interconnection may be desirable to allow for higher density communication paths between elements coupled to the PIC. In some implementations, the size, shape, pitch, or type of one or more electrical interconnections may differ from those shown in the figure or from other electrical interconnections. The specific type, size, shape, or pitch of an electrical interconnection may be based on one or more factors such as the use case, materials used, design considerations, and manufacturing considerations.

[0039] In one example, the driver 230 and amplifier 232 of the first part 226 of the photonic transceiver 220 include electronic circuits fabricated within the EIC 202. In one example, the first part of the photonic transceiver is an analog / mixed signal (AMS) block including circuits for processing analog signals or circuits for processing analog signals and circuits for processing digital signals. The driver of the first part of the photonic transceiver may include a digital control circuit and an analog amplification circuit. In one example, the driver includes a driver interface (not shown) exposed on the lower main surface 240 of the EIC. The amplifier of the first part of the photonic transceiver may include a transimpedance amplifier (TIA). In one example, the amplifier includes an amplifier interface (not shown) also exposed on the lower main surface of the EIC. In one example, the driver interface and the amplifier interface are electrically coupled to the electronic circuits of their respective components and include one or more conductive contacts or pads exposed on the lower main surface of the EIC.

[0040] The modulator 234 of the second portion 228 of the photonic transceiver 220 may include an electroabsorption modulator (EAM) fabricated on the PIC 204, for example, the EAM may be a germanium silicon (GeSi) EAM. Other examples of optical modulators include, but are not limited to, a microring resonator (MRR) or any suitable optical component having sufficient thermal stability over the operating range of the photonic transceiver. In one example, the modulator includes a modulator interface (not shown) exposed on the upper main surface 242 of the PIC. For example, the modulator interface may include one or more conductive contacts or pads electrically coupled to the modulator and exposed on the upper main surface of the PIC.

[0041] The photodetector 236 of the second part 228 of the photonic transceiver 220 includes electronic circuitry fabricated on the PIC 204, and for example, the photodetector may be a GeSi photodetector. In one example, the photodetector includes a photodiode and a photodetector interface (not shown) fabricated on the PIC. For example, the photodetector interface may include one or more conductive contacts exposed on the upper main surface of the PIC.

[0042] Figure 2B also illustrates the transfer of data from the electrical domain of the EIC 202 to the optical domain of the PIC 204 (e.g., entering the driver 230 via the arrow 222 pointing "down" and exiting the modulator 234), and the transfer of data from the optical domain of the PIC to the electrical domain of the EIC (e.g., entering the photodetector 236 via the arrow 224 pointing "up" and exiting the amplifier 232). Referring to the left side of Figure 2B, in an exemplary operation, a signal representing digital data is applied to the driver in the EIC, causing the driver to generate a signal that drives the modulator in the PIC through the interconnect 238. In one example, the optical carrier 244 is modulated by the modulator in response to the signal from the driver, and the modulated optical carrier propagates through the optical waveguide (not shown) of the PIC. Thus, the left side of Figure 2B illustrates the conversion of signals from the electrical domain to the optical domain between the stacked EIC and PIC. Referring to the right side of Figure 2B, the modulated optical carrier is received by the photodetector via the optical waveguide (not shown) of the PIC. The photodetector converts the modulated optical carriers into electrical signals that are passed through the interconnect to the amplifiers in the EIC. The amplifiers in the EIC amplify the electrical signals and provide the amplified electrical signals to other components of the EIC, such as the analog-to-digital converter (ADC) in the EIC. Thus, the right side of Figure 2B illustrates the conversion of signals from the optical domain to the electrical domain between the stacked EIC and the PIC.

[0043] As described above, in order to form a multiport network switch that can switch data between the optical ports of a multiport network switch without being limited to the beachfront of the IC device, it is recognized that a photonic transceiver formed by an EIC stacked on a PIC can be coupled with a switching circuit within the EIC, as described with reference to Figures 2A and 2B. According to an exemplary embodiment, the multiport network switch includes an EIC having a switching circuit stacked on a PIC having multiple optical ports, and a photonic transceiver optically coupled to the optical ports of the PIC and electrically coupled to the switching circuit of the EIC. The multiport network switch enables switching data from a first optical port of the multiport network switch to a second optical port of the multiport network switch via the photonic transceiver and switching circuit based on information in the data received at a first optical port. In one example, in contrast to a conventional single-chip switch where the data interface to the IC device is located only at the edge of the IC device, at least some of the photonic transceivers can be physically located in the internal region of the EIC. Because multiport network switches use photonic transceivers formed by EICs stacked on a PIC microcontroller, signal conversion from the optical domain to the electrical domain and from the electrical domain to the optical domain does not need to occur at the beachfront or edge of the EIC; instead, it can occur wherever the drivers and amplifiers are fabricated on the EIC. Therefore, the number of ports that can be included in a multiport network switch is not limited to the beachfront or edge dimensions of the EIC. In one particularly useful example, a multiport network switch is configured for use in a leaf-spine network architecture.In one example, the photonic transceiver includes a spine photonic transceiver and a leaf photonic transceiver, and in another example, the photonic transceiver includes a spine photonic transceiver surrounded by a switching circuit, and a leaf photonic transceiver surrounding a switching circuit.

[0044] In one example, as described with reference to Figures 2A and 2B, the first portion of each photonic transceiver is located within the EIC, the second portion of each photonic transceiver is located within the PIC, and the interface of the first portion of each photonic transceiver within the EIC is vertically aligned with the interface of the corresponding second portion of the photonic transceiver within the PIC. For example, the first portion of the photonic transceiver within the EIC includes a driver and an amplifier, the second portion of the photonic transceiver within the PIC includes a modulator and a photodetector, the interface of the driver within the EIC is vertically aligned with the interface of the modulator within the PIC, and the interface of the amplifier within the EIC is vertically aligned with the interface of the photodetector within the PIC. An example of a multiport network switch including an EIC stacked on a PIC is described with reference to Figures 3A-3C. In one example, the EIC is stacked on the PIC as described with reference to Figures 1, 2A, and 2B.

[0045] Figure 3A is a top view of an example of a multiport network switch 300 coupled between four different nodes 348 located outside the multiport network switch: Node A, Node B, Node C, and Node D. In this example, the nodes may include computing components, memory components, or a combination thereof, and the multiport network switch can switch network traffic from the input optical ports of the multiport network switch to the output optical ports of the multiport network switch based on information in the network traffic received at the input optical ports of the multiport network switch. For example, the multiport network switch can determine where to switch the received network traffic based on header information in the received network traffic. In the example of Figure 3A, the multiport network switch includes an EIC302 stacked on a PIC304, as shown in the top view. The multiport network switch has four optical ports 316 (e.g., ports P1, P2, P3, P4), but it should be understood that the number of optical ports of a multiport network switch can vary. In one example, a multiport network switch includes four photonic transceivers 320, each photonic transceiver having a first part 326 in the EIC (e.g., driver and amplifier) ​​and a second part 328 in the PIC (e.g., modulator and photodetector), and the EIC includes a switching circuit 350. For example, the switching circuit may include a switch fabric, arbiter, scheduler, and media access control (MAC) table. In one example, the switch fabric is a crosspoint matrix in which each photonic transceiver can be individually connected to each of the other photonic transceivers. In one example, each optical port of the multiport network switch includes two optical interfaces in the PIC: one optical interface 352 for receiving optical signals from an external device and one optical interface 354 for outputting optical signals to an external device, for example, to the same node.In one example, each optical interface of an optical port is part of a unidirectional optical channel in the PIC, which includes an optical interface, an optical waveguide 356, and a second part of a photonic transceiver component, such as a modulator or photodetector. Two unidirectional optical channels of an optical port are combined to form a bidirectional optical channel between the multiport network switch and another node, such as a compute node or memory node.

[0046] As shown in the top view of Figure 3A, for each photonic transceiver 320, the first portion 326 of the photonic transceiver located in the EIC 302 is vertically aligned with the corresponding second portion 328 of the photonic transceiver located in the PIC 304. Furthermore, as shown in the top view of Figure 3A, the EIC has a footprint, and the photonic transceivers are located in the internal region of the EIC footprint, rather than on one or more edges of the EIC as in the conventional case. For example, when other circuits of the EIC are located between the photonic transceiver circuit and the edge of the EIC, the photonic transceiver is located in the internal region of the EIC, and when other circuits of the EIC are not located between the photonic transceiver circuit and the edge of the EIC, the photonic transceiver is located in the external region of the EIC.

[0047] As shown in the top view of Figure 3A, the optical engine 319 is optically connected to the PIC 304 via the optical port 317. The optical engine may include, but is not limited to, one or more lasers, such as a distributed feedback (DFB) laser or other laser diode mounted on a III-V compound semiconductor material, to generate optical carriers. Multiple lasers emitting at the same wavelength may be used to generate light for multiple photonic circuits at one or more wavelengths. Alternatively or additionally, the optical engine may include multiple lasers emitting at different wavelengths and a wavelength multiplexer, for example, mounted as an array waveguide grating, to couple the different wavelengths into a single multiplexed optical carrier signal. In one example, the optical engine generates light in the range of 980–1,580 nm, and in another example, the optical engine generates L-band light (e.g., 1,570–1,580 nm), but other wavelength ranges are also possible.

[0048] Figure 3B is a bottom perspective view of the EIC 302 of Figure 3A. The dashed boxes in the bottom perspective view of the EIC represent the locations of the first portion 326 of each photonic transceiver within the EIC and the switching circuit 350, projected onto the lower main surface 340 of the EIC. As described above, the first portion of the photonic transceiver has a driver and an amplifier that are mounted via electronic circuits fabricated on the substrate of the EIC. However, in the example of Figure 3B, only the driver interface 331 and amplifier interface 333 of each photonic transceiver are exposed to the lower main surface of the EIC and are, for example, visible. In one example, the driver interface and amplifier interface of each photonic transceiver are conductive elements that can be electrically connected to an electrical interconnect, such as the electrical interconnect described above. In one example, the driver interface and amplifier interface may each include one or more conductive pads.

[0049] Figure 3C is a side cross-section of the multiport network switch 300 of Figure 3A, showing the components of the multiport network switch, including a photonic transceiver formed across an EIC 302 stacked on a PIC 304, and a switching circuit 350 of the EIC. Referring to Figure 3C, the left side shows the elements of the photonic transceiver (e.g., FAU 312) corresponding to optical port P4 optically connected to node A, and the right side shows the elements of the photonic transceiver (e.g., FAU 312) corresponding to optical port P2 optically connected to node D. Figure 3C also shows the switching of network traffic from node A to node D, and from node D to node A. However, Figure 3C does not show optical engines, optical ports for optical engines, or other optical components that may be fabricated on the PIC, such as splitters, multiplexers, and demultiplexers, or that may be connected to the PIC, such as FAUs or optical fibers.

[0050] Referring to the left side of Figure 3C, the photonic transceiver corresponding to optical port P4 includes a first part 326 in the EIC 302 and a second part 328 in the PIC 304. The first part of the photonic transceiver in the EIC includes a driver 330 and an amplifier 332, and the second part of the photonic transceiver in the PIC includes a modulator 334 and a photodetector 336. Similarly, referring to the right side of Figure 3C, the photonic transceiver corresponding to optical port P2 includes a first part 326 in the EIC and a second part 328 in the PIC. The first part of the photonic transceiver in the EIC includes a driver 330 and an amplifier 332, and the second part of the photonic transceiver in the PIC includes a modulator 334 and a photodetector 336. In this example, the driver of each photonic transceiver is aligned perpendicularly to the corresponding modulator so that the electrical interconnect 338 can electrically connect the driver interface (not shown) and the modulator interface (not shown) over a very short distance (e.g., less than 50 microns), and the amplifier of each photonic transceiver is aligned perpendicularly to the corresponding photodetector so that the electrical interconnect can electrically connect the amplifier interface (not shown) and the photodetector interface (not shown) over a very short distance (e.g., less than 50 microns). The EIC also includes switching circuitry 350 which may include a switch fabric, arbiter, scheduler, and MAC table, and interface components 358 which may include, for example, an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a serializer, a deserializer, and / or media access control (MAC) logic. The EIC may also include circuitry configured to perform other operations, for example, power supply, power management, and management communications. Such circuitry may include, for example, one or more processing cores and memory.

[0051] The PIC304 may include a grating coupler (GC) 360, a multiplexer, a demultiplexer, and waveguides connecting the optical ports to the modulator 334 and photodetector 336. In the example in Figure 3C, the waveguides support unidirectional photonic channels that can be coupled together to form bidirectional photonic channels.

[0052] Figure 4 shows the communication of digital data between the multiport network switch 400 and node 448, where the multiport network switch 400 and node 448 are similar to the multiport network switch and node in Figures 3A and 3C, for example node D. In particular, Figure 4 shows the photonic transceiver 420 in the multiport network switch and the photonic transceiver 420 in node D, but it should be understood that node D does not necessarily include a photonic transceiver formed from an EIC stacked on a PIC, as in the case of the multiport network switch. The photonic transceiver in the multiport network switch includes an electrical-optical (EO) interface 462 (e.g., driver / modulator) and an optical-electrical (OE) interface 464 (e.g., photodetector / amplifier), while the photonic transceiver in node D includes an OE interface 464 (e.g., photodetector / amplifier) ​​and an EO interface 462 (e.g., driver / modulator). As described above, the driver and modulator are electrically connected by an electrical interconnect between the stacked EIC and PIC, and the photodetector and amplifier are electrically connected by an electrical interconnect between the stacked EIC and PIC. A one-way photonic link 466 is formed between the EO interface of the multiport network switch and the OE interface of node D, and a separate one-way photonic link 468 in the opposite direction is formed between the EO interface of node D and the OE interface of the multiport network switch. Together, the two one-way photonic links form a bidirectional photonic link 470. In one example, the one-way photonic link includes an optical fiber connecting the multiport network switch and node D, but the multiport network switch and node D can be optically connected, for example, via the PIC or through air.

[0053] Photonic transceivers can facilitate the conversion of messages or signals between electronic domains and photonic domains. For example, each photonic transceiver may include an EO interface for converting electronic signals to optical (e.g., photonic) signals, and an OE interface for converting optical signals to electronic signals. Figure 4 shows only photonic transceivers having EO and OE interfaces, but it should be understood that each photonic interface on a multiport network switch may include one or both of these interfaces, and typically may include multiple of each to support multiple bidirectional unidirectional photonic links connected to the optical ports to support, for example, wavelength division multiplexing (WDM) or other schemes. Referring again to Figure 3A, in some embodiments, each of the optical ports 316 of the multiport optical switch 300 is associated with and optically coupled to a photonic transceiver 320 of the multiport optical switch via an optical waveguide 356.

[0054] Here, referring again to Figure 3C, an example of switching data from node A to node D and from node D to node A is explained.

[0055] First, an example of switching data from node A to node D via a multiport network switch 300 is described. In this example, some digital data at node A is transmitted to node D, but the digital data intended to reach node D passes through the multiport network switch. During operation, the digital data is transmitted via optical signals from node A to optical port P4 of the multiport network switch in optical path 351, for example, via optical fiber. The optical signals enter the multiport network switch via FAU312 and GC360 corresponding to optical port P4 and proceed through optical path 351 in the optical waveguide within the PIC to the photodetector 336 of the photonic transceiver corresponding to optical port P4. The photodetector converts the optical signal into an electrical signal, which is conducted to the amplifier 332 of the photonic transceiver via electrical interconnect 338. The amplifier of the photonic transceiver amplifies the electrical signal and provides the amplified electrical signal to the interface 358 corresponding to the photonic transceiver via electrical path 353. The interface converts electrical signals into digital signals, for example, binary digital data, and the switching circuit 350 determines where to forward the digital signals based on the information within the digital signals. For example, the switching circuit determines where to forward the digital signals from a 12-bit value in the header portion of the digital signals. In one example, the digital signals are transmitted as digital data in protocol data units (PDUs), also called packets, and each PDU includes a header. The header contains information used to determine where to forward the digital data within a multiport network switch.

[0056] In the example in Figure 3C, the switching circuit 350 determines that a digital signal should be transferred to a photonic transceiver corresponding to optical port P2 of a multiport network switch 300. In one example, a 12-bit value in the header portion of the digital signal indicates node D, and the 12-bit value is mapped within the switching circuit (e.g., in the MAC table of the switching circuit) to node D and the output port on the multiport optical switch corresponding to node D. The electrical path 353 through the switching circuit in Figure 3C represents the digital signal transferred through the switching circuit from the photonic transceiver corresponding to optical port P4 to the photonic transceiver corresponding to optical port P2. After passing through the switching circuit, the digital signal is received at the interface 358 of the photonic transceiver corresponding to optical port P2, and the digital signal may be deserialized and / or converted from a digital signal to an analog signal. In another example, a driver 330 is controlled by a digital signal from the interface to drive the driver. In either case, in response to the signal from the interface, the driver generates an electrical signal, which is output to the modulator 334 via the electrical interconnect 338. The modulator modulates an optical carrier (not shown) supplied to the modulator (e.g., from an external light source) in response to an electrical signal from a driver. The modulated optical carrier propagates through an optical waveguide in the PIC on optical path 355 to the GC360 and the FAU312 corresponding to optical port P2. The modulated optical carrier is output from the multiport network switch at optical port P2 and provided to node D via optical path 355, for example, via optical fiber.

[0057] Similar operation is performed for digital data transmitted from node D to node A via the multiport network switch 300. In this example, some digital data at node D is transmitted to node A, but intended to reach node A, the data passes through the multiport network switch. During operation, the digital data is transmitted via optical signals from node D to optical port P2 of the multiport network switch in optical path 357, for example, via optical fiber. The optical signals enter the multiport network switch via FAU312 and GC360 corresponding to optical port P2 and proceed through optical path 357 in the optical waveguide within PIC304 to photodetector 336 of the photonic transceiver corresponding to port P4. The photodetector converts the optical signals into electrical signals, which are conducted to the amplifier 332 of the photonic transceiver via electrical interconnect 338. The amplifier of the photonic transceiver amplifies the electrical signals and provides the amplified electrical signals to the interface 358 corresponding to the photonic transceiver via electrical path 359. The interface converts an electrical signal into a digital signal, for example, binary digital data, and the switching circuit 350 determines where to forward the digital signal based on the information in the digital signal. For example, the switching circuit determines where to forward the digital signal from a 12-bit value in the header portion of the PDU. In the example in Figure 3C, the switching circuit determines that the digital signal should be forwarded to the photonic transceiver corresponding to optical port P4 of the multiport network switch. The electrical path 359 through the switching circuit in Figure 3C represents the digital signal being forwarded from the photonic transceiver corresponding to optical port P2 to the photonic transceiver corresponding to optical port P4 via the switching circuit. After passing through the switching circuit, the digital signal is received at the interface 358 of the photonic transceiver corresponding to optical port P4, and the digital signal may be deserialized and / or converted from a digital signal to an analog signal to drive the driver 330. In another example, the driver is controlled by a digital signal.In either case, in response to a signal from the driver, the driver generates an electrical signal, which is output to the modulator 334 via the electrical interconnect 338. The modulator modulates the optical carrier (not shown) supplied to the modulator in response to the electrical signal from the driver, and the modulated optical carrier propagates through the optical waveguide in the PIC on the optical path 361 to the GC360 and the FAU312 corresponding to optical port P4. The modulated optical carrier is output from the multiport network switch at optical port P4 and provided to node A via the optical path 361, for example, via optical fiber.

[0058] In the example illustrated with reference to Figures 3A-3C, the photonic transceiver 320 is located in the internal region of the EIC 302, close to the switching circuit 350. Since photonic transceivers can be located anywhere within the EIC, the number of photonic transceivers that can be included in the EIC is not limited by the EIC's beachfront (e.g., perimeter dimensions). Therefore, if necessary, more photonic transceivers can be included in the EIC than if their location were limited only to the EIC's beachfront (e.g., edges). Furthermore, because photonic transceivers are not limited to the EIC's beachfront, they can be strategically positioned closer to switching circuits to reduce the physical distance that signals must travel through switching circuits to transfer from one photonic transceiver to another in order to perform multi-port network switching. Therefore, since multiport network switches use photonic transceivers formed by an EIC stacked on a PIC, signal conversion from the optical domain to the electrical domain and from the electrical domain to the optical domain does not need to occur at the beachfront or edge of the EIC, but can instead be performed wherever the drivers and amplifiers are fabricated on the EIC. Thus, the number of optical ports that can be included in such a multiport network switch is not limited to the beachfront or edge dimensions of the EIC. Furthermore, photonic transceivers can be strategically placed within the EIC to shorten the transmission distance across the switching circuitry, which can reduce the power consumption and latency of the multiport network switch.

[0059] A common data center architecture includes a leaf-spine configuration of end nodes and switches. A leaf-spine network architecture is efficient for providing resilient connectivity between clusters of nodes, which may include, for example, compute and / or memory resources. In one example, a multiport network switch is configured for use in a leaf-spine network architecture connecting multiple racks of nodes, such as compute and / or memory nodes, to each other. In a specific example, the multiport network switch consists of 20 optical ports for communicating data between nodes in a leaf-spine network architecture, 16 of which are configured as leaf ports and 4 as spine ports. An example of a multiport network switch configured for use in a leaf-spine network architecture is illustrated with reference to Figures 5A–5C and Figure 6.

[0060] Figure 5A is a top view of an example of a multiport network switch 500 configured for use in a leaf-spine network architecture. Similar to the multiport network switches described with reference to Figures 3A-3C, the multiport network switch includes an EIC 502 stacked on a PIC 504, with multiple photonic transceivers 520 located in the internal region of the EIC.

[0061] In the example in Figure 5A, the multiport network switch 500 may be optically connected to network nodes (not shown) and switch nodes, which may include compute / memory nodes. Examples of applications of multiport network switches in a leaf-spine network architecture are described below. As described with reference to Figures 3A to 3C, a multiport network switch can switch network traffic from the input optical ports of the multiport network switch to the output optical ports of the multiport network switch based on information in the network traffic received at the input optical ports of the multiport network switch. For example, a multiport network switch can determine where to switch the received network traffic based on header information in the received network traffic. In the example in Figure 5A, the multiport network switch includes an EIC 502 stacked on a PIC 504 as shown in the top view, and the PIC includes an optical port 516 that can be optically connected to other network nodes. For example, a multiport optical switch includes 20 optical ports optically coupled to other nodes in a leaf-spine network architecture and one optical port 517 optically connected to an optical engine (e.g., a laser light source). A multiport network switch has 21 optical ports, but it should be understood that the number of optical ports on a multiport network switch can vary. In one example, a multiport network switch includes 20 photonic transceivers 520, each photonic transceiver having a first part 526 in the EIC (e.g., driver and amplifier) ​​and a second part 528 in the PIC (e.g., modulator and photodetector), and the EIC includes switching circuitry 550. For example, the switching circuitry may include a switch fabric, arbiter, scheduler, and MAC table. In one example, the switch fabric is a crosspoint matrix in which each photonic transceiver can be individually connected to each of the other photonic transceivers.In one example, each of the 20 optical ports 516 of the multiport network switch is optically connected to a corresponding photonic transceiver 520, and the PIC includes two optical interfaces: one optical interface 552 for receiving optical signals from an external device, for example, a network node, and one optical interface 554 for outputting optical signals to an external device, for example, the same node. In this example, each optical interface of the optical port is part of a unidirectional optical channel in the PIC, which includes an optical interface, an optical waveguide, and a second part of the photonic transceiver components, such as a modulator or a photodetector. The two unidirectional optical channels of the optical port are combined to form a bidirectional optical channel between the multiport network switch and another node, for example, a computing node or a memory node. Furthermore, it should be understood that the multiport network switch may utilize WDM (for example, by using multiple optical channels in parallel) to increase channel density and therefore overall data switching capacity.

[0062] As shown in the top view of Figure 5A, the first portion 526 of the photonic transceiver 520 located within the EIC 502 is vertically aligned with the corresponding second portion 528 of the photonic transceiver located within the PIC 504. Furthermore, as shown in the top view of Figure 5A, the photonic transceiver is located within the internal region of the EIC, rather than on one or more edges of the EIC as in the conventional configuration.

[0063] Figure 5B is a bottom perspective view of the EIC 502 of Figure 5A. The dashed boxes in the bottom perspective view of the EIC represent the locations of the first portion 526 of each photonic transceiver within the EIC and the switching circuit 550 within the EIC, projected onto the lower main surface 540 of the EIC. As described above, the first portion of the photonic transceiver has a driver and an amplifier that are mounted via electronic circuits fabricated on the substrate of the EIC. However, in the example of Figure 5B, only the driver interface 531 and amplifier interface 533 of each photonic transceiver are exposed to the lower main surface of the EIC and are, for example, visible. In one example, the driver interface and amplifier interface of each photonic transceiver are conductive elements that can be electrically connected to an electrical interconnect, such as the electrical interconnect described above. In one example, the driver interface and amplifier interface of each photonic transceiver may each include one or more conductive pads.

[0064] Figure 5C is a side cross-section of the multiport network switch 500 shown in Figures 5A and 5B, and shows the components of the multiport network switch, including the first part 526 and the second part 528 of the photonic transceiver formed over the EIC 502 stacked on the PIC 504, and the switching circuit 550 of the EIC. In particular, Figure 5C shows the elements of two photonic transceivers corresponding to two leaf optical ports (e.g., driver 530, amplifier 532, modulator 534, photodetector 536) and the elements of two photonic transceivers corresponding to two spine optical ports (e.g., driver 530, amplifier 532, modulator 534, photodetector 536).

[0065] Referring to Figure 5C, the left and right photonic transceivers of the multiport network switch correspond to leaf optical ports, and each photonic transceiver includes a first part in the EIC 502 and a second part in the PIC 504. The first part of each photonic transceiver in the EIC includes a driver 530 and an amplifier 532, and the second part of the photonic transceiver in the PIC includes a modulator 534 and a photodetector 536. The central photonic transceiver of the multiport network switch corresponds to a spine optical port, and each photonic transceiver includes a first part in the EIC and a second part in the PIC. The first part of each photonic transceiver in the EIC includes a driver and an amplifier, and the second part of each photonic transceiver in the PIC includes a modulator and a photodetector. In this example, the driver of each photonic transceiver is aligned perpendicularly to its corresponding modulator so that the electrical interconnect 538 between the EIC and the PIC can electrically connect the driver interface (not shown) and the modulator interface (not shown) over a very short distance (e.g., less than 50 microns), and the amplifier of each photonic transceiver is aligned with its corresponding photodetector so that the electrical interconnect between the EIC and the PIC can electrically connect the amplifier interface (not shown) and the photodetector interface (not shown) over a very short distance (e.g., less than 50 microns). The EIC also includes switching circuitry 550 which may include a switch fabric, arbiter, scheduler, and MAC table, and interface components which may include, for example, an ADC, DAC, serializer, deserializer, and / or MAC logic. The EIC may also include circuitry configured to perform other operations such as power supply, power management, and management communications. Such circuitry may include, for example, one or more processing cores and memory.

[0066] The PIC504 may also include optically coupled grating couplers (GCs), splitters, multiplexers, demultiplexers, and waveguides between the optical ports and the modulators and photodetectors. In the example in Figure 5C, waveguides within the PIC (not shown) support unidirectional photonic channels that can be coupled together to form bidirectional photonic channels. Furthermore, it should be understood that multiport network switches may utilize WDM to increase channel density and therefore overall data switching capacity.

[0067] In one example, the multiport network switch 500 described with reference to Figures 5A-5C is configured to be used as a multiport network switch in a leaf-spine network architecture. Figure 6 is an example of a leaf-spine network architecture 676 in which the multiport network switch 600 described with reference to Figures 5A-5C is used as a switch often called a top-of-rack (ToR) switch within the leaf-spine network architecture. In the exemplary leaf-spine network architecture of Figure 6, there are four spine switches 678 and four racks 680 containing end nodes 648, each end node may contain computing and / or memory resources. In this example, each rack contains 16 end nodes, but the number of racks and the number of end nodes may differ. In a leaf-spine network architecture, end nodes are considered leaf nodes. Each rack also contains the ToR switch 600, which is the multiport network switch described above with reference to Figures 5A-5C.

[0068] In the example in Figure 6, four spine switches 678 are connected to each of the racks 680 via a ToR switch 600, the ToR switch in each rack is connected to each of the four spine switches via a spine port, and the ToR switches in the racks are connected to each of the 16 nodes 648 in the rack via leaf ports. Using the leaf-spine network architecture shown in Figure 6, any node in a rack can communicate with any node in another rack in the network via any one of the four spine switches, providing a high level of redundancy that can be useful for resilience against spine switch failures and for supporting load balancing of traffic between spine switches. In some leaf-spine network architectures, each rack may include at least two ToRs to provide resilience against ToR switch failures.

[0069] For example, referring again to Figure 5A, a photonic transceiver 520 surrounding a switching circuit (e.g., a leaf photonic transceiver) is used to connect to an end node (leaf node), and a photonic transceiver surrounded by a switching circuit (e.g., a spine photonic transceiver) is used to connect to a spine switch. Figure 7 is a top view of the multiport network switch 700 described with reference to Figures 5A to 5C, where the optical ports 716 of the multiport network switch are labeled with the node or spine switch to which the optical ports are optically coupled, and the photonic transceivers 720 are labeled with the corresponding optical port number to which the photonic transceivers are optically coupled. Referring to Figure 7, to the left of the PIC 704 of the multiport network switch are 10 optical ports labeled as ports 1 to 10, and to the right of the PIC of the multiport network switch are 10 optical ports labeled as ports 11 to 20. Each optical port is optically coupled to a photonic transceiver, and each optical port has a bidirectional optical channel (not shown) which includes one unidirectional optical channel for receiving optical signals from outside the multiport network switch and one unidirectional optical channel for transmitting optical signals from the multiport network switch. For example, port 1, which is an optical port, is optically coupled to a photonic transceiver labeled P1, port 2, which is an optical port, is optically coupled to a photonic transceiver labeled P2, and so on. Figure 7 also identifies the nodes or spine switches to which the optical ports are optically coupled. For example, the coupling from an optical port to a node / spine switch is as follows:

[0070] Port 1: Node 1;

[0071] Port 2: Node 2;

[0072] Port 3: Node 3;

[0073] Port 4: Node 4;

[0074] Port 5: Spine switch 1;

[0075] Port 6: Spine switch 2;

[0076] Port 7: Node 5;

[0077] Port 8: Node 6;

[0078] Port 9: Node 7;

[0079] Port 10: Node 8;

[0080] Port 11: Node 9;

[0081] Port 12: Node 10;

[0082] Port 13: Node 11;

[0083] Port 14: Node 12;

[0084] Port 15: Spine switch 3;

[0085] Port 16: Spine switch 4;

[0086] Port 17: Node 13;

[0087] Port 18: Node 14;

[0088] Port 19: Node 15;

[0089] Port 20: Node 16.

[0090] In the leaf-spine network architecture 676 shown in Figure 6, a large amount of network traffic is expected to travel between racks 680. Network traffic traveling between racks must pass through the ToR switch 600, either entering the ToR switch at the leaf port and exiting it at the spine port, or entering the ToR switch at the spine port and exiting it at the leaf port. For example, network traffic may be received from leaf node 4 on optical port 4 and forwarded to spine switch 2 via optical port 6. In this example, network traffic is forwarded from photonic transceiver P4 (leaf photonic transceiver) to photonic transceiver P6 (spine photonic transceiver) via switching circuit 750. In this case, the transfer of data from the leaf photonic transceiver (e.g., P4) to the spine photonic transceiver (e.g., P6) may be beneficial if the corresponding electronic signals pass through the switching circuit, as the distance traveled through the switching circuit may be relatively small. In another example moving in the opposite direction, network traffic may be received from spine switch 2 on optical port 6 and forwarded to leaf node 4 via optical port 4. In this example, network traffic is forwarded from spine photonic transceiver (e.g., P6) to leaf photonic transceiver (e.g., P4) via switching circuit 750. Thus, in one example, by moving the spine node closer to the leaf node, the amount of physical distance that electrical signals must travel across the switching circuit of the EIC to reach the photonic transceiver corresponding to the input optical port of the multiport network switch from the photonic transceiver corresponding to the output optical port of the multiport network switch can be reduced.

[0091] In the example described with reference to Figures 5A-5C, 6, and 7, the spine photonic transceivers (photonic transceivers P5, P6, P15, and P16) are grouped together and surrounded by the switching circuit 750, while the leaf photonic transceivers (photonic transceivers P1-P4, P7-P14, and P17-P20) surround the switching circuit and the spine photonic transceivers. Therefore, both the leaf and spine photonic transceivers are located in the internal region of the EIC and are in close proximity to the switching circuit. Since the multiport network switch uses photonic transceivers formed by the EIC stacked on the PIC, the conversion of signals from the optical domain to the electrical domain and from the electrical domain to the optical domain does not need to be performed on the beachfront or edge of the EIC, but can instead be performed wherever drivers and amplifiers can be fabricated on the EIC. Therefore, the number of ports that can be included in such a multiport network switch is not limited to the beachfront or edge dimensions of the EIC, and more photonic transceivers can be included in the EIC than if the location of the photonic transceivers were limited to the beachfront (e.g., edge) of the EIC. Furthermore, because photonic transceivers are not limited to the beachfront of the EIC, they can be strategically placed closer to the switching circuit to reduce the physical distance that electrical signals must travel through the switching circuit to transfer from one photonic transceiver to another in order to perform multiport network switching.For example, by placing spine photonic transceivers closer to leaf photonic transceivers on the EIC, the amount of physical distance that electrical signals must travel across the EIC's switching circuitry to reach photonic transceivers corresponding to the input optical ports of a multiport network switch from the photonic transceivers corresponding to the output optical ports of the multiport network switch can be reduced, thereby reducing power consumption and latency across the multiport network switch.

[0092] An example of a multiport network switch with 20 optical ports (16 leaf ports and 4 spine ports) is described, but other numbers of optical ports are also possible. In one example, the multiport network switch may have an EIC in which some photonic transceivers are located in the internal region of the EIC and some other photonic transceivers are located at the edge of the EIC (e.g., the beachfront). Furthermore, the photonic transceivers can be located on the EIC in positions different from those shown in Figure 5A.

[0093] For example, the ability to place photonic transceivers in the internal region of the EIC rather than the periphery of the EIC may allow the photonic transceivers to be spaced apart from each other to improve temperature stability around them.

[0094] In the examples described herein, the optical ports are shown in specific locations on the PIC. While several examples are provided, the location of the optical ports on the PIC is not limited to those shown herein. For example, all optical ports may be located on the same side of the PIC, or the optical ports may be located in an internal area of ​​the PIC.

[0095] In one example, a photonic transceiver supports bidirectional photonic channels with a data transmission rate of 56 Gbps in each direction, although other data transmission rates are also possible. In another example, multiple photonic channels are combined to provide a data transmission rate of 1.8 terabits per second (Tbps) for each optical port. In yet another example, a multi-port network switch has 64 optical ports with a total bandwidth capacity of 115.2 Tbps (e.g., 64 ports × 1.8 Tbps).

[0096] In this specification, photonic paths may be implemented within an optical transmission medium. The optical transmission medium may include optical waveguides in PICs, optical fibers, or other optical transmission mediums (such as free-space optical systems or glass-etched waveguides), or any combination thereof.

[0097] As used herein, the primary surface of an EIC or PIC is a large plane of the EIC and PIC distinct from the edge surfaces of the EIC or PIC. Typically, each EIC and PIC has a rectangular shape with two primary surfaces and a periphery containing four edge surfaces. The primary surfaces of an EIC and PIC may be referred to as the upper primary surface and lower primary surface, the upper primary surface and the lower primary surface, and / or the first primary surface and the second primary surface. In one example, the upper primary surface and lower primary surface are terms referring to the upper and lower planes of the EIC and PIC relative to the ground or floor, since the multiport network switch is intended to be installed in a rack unit in a data center.

[0098] The switching circuit is configured to direct PDUs (e.g., data packets) from one photonic transceiver corresponding to an optical port in a multiport network switch to another photonic transceiver corresponding to another optical port. Figure 8 shows an example of a switching circuit 850 that may be implemented in a multiport network switch. As shown in Figure 8, the switching circuit includes a switch fabric 884, an arbiter 886, a scheduler 888, and a MAC (Media Access Control) table 890. In one example, the switch fabric forms the core of the switching circuit and provides a non-blocking matrix that enables multiple simultaneous data paths between the optical ports of the multiport network switch. The arbiter is configured to resolve contention scenarios by determining the order of access to the switch fabric, for example, using a traffic management algorithm to ensure fair and efficient allocation of resources. The scheduler is configured to optimize traffic flow through the switching circuit by coordinating the timing and sequence of PDU transmissions through the switching circuit based on a given priority level. The MAC table stores the addresses of network nodes and enables accurate packet forwarding by mapping each incoming PDU to its appropriate output optical port. In one example, the switch fabric is a crosspoint matrix switch fabric, which includes a grid of switches, or crosspoints, or crossbars, that directly connect the circuitry corresponding to each input optical port to the circuitry corresponding to each output optical port. The crosspoint switch fabric architecture is configured to enable multiple simultaneous data transfers between photonic transceivers (and ultimately between optical ports) of a multiport network switch, as each crosspoint operates independently. Crosspoint matrix switch fabrics can provide high throughput and low latency. Furthermore, the non-blocking characteristics of the crosspoint matrix ensure that PDUs can always find a path through the EIC's switching circuitry to their destinations, even under heavy traffic loads.In one example, the switch fabric is a shared-memory switch fabric that stores incoming PDUs using a central memory buffer before forwarding them to the appropriate output optical port. The circuitry of the EIC corresponding to each input optical port writes packets to the shared memory, and the circuitry of the EIC corresponding to each output optical port reads packets from the shared memory. The shared-memory architecture can simplify the switching process, enable efficient handling of variable-length PDUs, and ensure that memory is used optimally. Shared-memory switch fabrics are superior in environments where traffic patterns are unpredictable and high levels of data contention can occur. Shared memory can also facilitate advanced features such as quality of service (QoS) and congestion management. In another example, the switch fabric is a shared-bus switch fabric that uses a common communication bus to connect multiple input ports to multiple output ports. When an input port needs to transmit a PDU to an output port, the input port gains control of the bus and forwards the data directly onto the shared bus. In one example, the switching circuit may include input and / or output queues. While several examples of switching circuits have been described, other embodiments of switching circuits are possible.

[0099] In one example, some of the switching functionality may be supported by interfaces corresponding to each of the photonic transceivers (e.g., 358 in Figure 3C and 558 in Figure 5C). For example, the interface corresponding to each photonic transceiver may include buffers that can be used for input and / or output buffering. In one example, the interface may decompose the PDU into smaller flow control units (FLITs) for transfer through the switching circuit. In one example, a FLIT is a fixed-size digital data unit. In some examples, the interface and / or switching circuit may be configured to decompose the PDU into FLITs and / or reassemble the FLITs into a PDU.

[0100] Figure 9 shows an example of a MAC table 990 that can be maintained and used by a switching circuit. In the example in Figure 9, the MAC table is stored in the EIC's memory and includes columns for header values ​​(e.g., 12-bit values), node identifiers (IDs), and optical port identifiers (IDs). In this example, the switching circuit obtains a mapping of the 12-bit header values ​​to specific node IDs of nodes in the network (e.g., nodes in a data center's leaf-spine network) and to specific optical port IDs of optical ports on a multiport network switch (or to the photonic transceiver corresponding to the optical port). In one example, the 12-bit value corresponds to the node ID of a node in the network. In one example, the node ID may be an Internet Protocol (IP) address associated with the node. The node ID is mapped to a specific optical port (or photonic transceiver corresponding to the optical port) on a multiport optical switch so that the 12-bit value of the received PDU can be used to look up the desired optical port (or the desired photonic transceiver corresponding to the optical port) on the multiport optical switch to which the PDU should be forwarded. In one example, the mappings in the MAC table may be learned by the switching circuitry of each multiport network switch via a switching protocol, while in another example, the mappings in the MAC table may be provided to each multiport network switch by a management server. An example of a MAC table is provided, but other configurations of the MAC table are also possible.

[0101] In the examples described above with reference to Figures 3A and 5A, the photonic transceivers are located in specific locations on the EIC relative to the switching circuit. Other locations for the photonic transceivers on the EIC relative to the switching circuit are also possible. Figure 10A is an example of a multiport network switch 1000A in which a photonic transceiver 1020 formed across EIC 1002 and PIC 1004 is positioned on both sides of the switching circuit 1050, and Figure 10B is an example of a multiport network switch 1000B in which the photonic transceiver 1020 formed across EIC 1002 and PIC 1004 is arranged in a mesh configuration relative to the switching circuit 1050. In the examples of Figures 10A and 10B, certain elements of the multiport network switch are not shown for clarity. In the example of a ToR switch used in a leaf-spine network, it may be desirable to position the spine photonic transceivers in a location where heat can be easily dissipated, as the spine optical ports (and their corresponding photonic transceivers) are expected to handle a larger volume of network traffic than the leaf optical ports (and their corresponding photonic transceivers).

[0102] While several configurations of photonic transceivers and switching circuits have been described above, other configurations of photonic transceivers and switching circuits are also possible. In another example, the photonic transceiver cells are configured in a matrix, and each photonic transceiver cell contains at least one photonic transceiver, an interface, and a switching circuit. Figure 11A shows an example of a multiport network switch 1100 containing a 4x4 matrix of photonic transceiver cells 1180. In one example, each photonic transceiver cell contains a photonic transceiver 1120 (having a first part 1126 in the EIC 1102 and a second part 1128 in the PIC 1104), an interface in the EIC (not shown), and a switching circuit 1150 in the EIC. As shown in Figure 11A, the switching circuit of each photonic transceiver cell is coupled to the switching circuit of an adjacent photonic transceiver cell by a signal path 1182 (e.g., a conductive path in the EIC). During operation, data is received at optical port 1116 in the optical domain, converted to the electrical domain, electrically switched to the target photonic transceiver cell, converted back from the electrical domain to the optical domain by the corresponding photonic transceiver, and optically transmitted via the PIC to the output optical port of the multiport network switch.

[0103] Figure 11A is a top view of an example of a multiport network switch 1100, which consists of a matrix of photonic transceiver cells. Similar to the multiport network switch described with reference to Figures 3A-3C, the multiport network switch includes an EIC 1102 stacked on a PIC 1104, with multiple photonic transceivers 1120 located in the internal region of the EIC. In the example of Figure 11A, the multiport network switch 1100 may be optically connected to network nodes (not shown) and / or other switch nodes, which may include compute / memory nodes. As described with reference to Figures 3A-3C, the multiport network switch 1100 can switch network traffic from the input optical port of the multiport network switch to the output optical port of the multiport network switch based on information in the network traffic received at the input optical port of the multiport network switch. For example, the multiport network switch can determine where to switch the received network traffic based on header information in the received network traffic. In the example in Figure 11A, the multiport optical switch includes 16 optical ports that can be optically coupled to other nodes in the network architecture, and one optical port 1117 that is optically connected to an optical engine (e.g., a laser light source). A multiport network switch has 17 optical ports, but it should be understood that the number of optical ports in a multiport network switch can vary. In one example, the multiport network switch includes 16 photonic transceivers 1120, each photonic transceiver having a first part 1126 in the EIC (e.g., driver and amplifier) ​​and a second part 1128 in the PIC (e.g., modulator and photodetector), and the EIC includes switching circuitry 1150. In the example in Figure 11A, each photonic transceiver includes switching circuitry specifically corresponding to that photonic transceiver. The switching circuitry may include a switch fabric, arbiter, scheduler, and MAC table, as described herein.In one example, a switching circuit is configured to transfer data to a switching circuit corresponding to another photonic transceiver, or to transfer data to that corresponding photonic transceiver. For example, if data is received on a photonic transceiver from the optical domain (e.g., from the PIC), the switching circuit transfers the data in the electrical domain to a switching circuit corresponding to another photonic transceiver. In one example, the switching circuit consists of a matrix (e.g., a 4x4 matrix), and the switching circuit transfers data directly to the switching circuit of an adjacent photonic transceiver cell. In one example, each of the 16 optical ports 1116 of a multiport network switch is optically connected to a corresponding photonic transceiver 1120, and the PIC includes two optical interfaces: one optical interface 1152 for receiving optical signals from an external device, e.g., a network node, and one optical interface 1154 for outputting optical signals to an external device, e.g., the same node. In one example, each optical interface of an optical port is part of a unidirectional optical channel in a PIC, which includes the optical interface, an optical waveguide, and a second part of a photonic transceiver component, such as a modulator or photodetector. Two unidirectional optical channels of an optical port are combined to form a bidirectional optical channel between the multiport network switch and another node, such as a compute node or memory node. Furthermore, it should be understood that the multiport network switch may utilize WDM (e.g., by using multiple optical channels in parallel) to increase channel density and therefore overall data switching capacity.

[0104] As shown in the top view of Figure 11A, the first portion 1126 of the photonic transceiver 1120 located within the EIC 1102 is vertically aligned with the corresponding second portion 1128 of the photonic transceiver located within the PIC 1104. Furthermore, as shown in the top view of Figure 11A, the photonic transceiver is located within the internal region of the EIC, rather than on one or more edges of the EIC as in the conventional configuration.

[0105] Figure 11B is a bottom perspective view of the EIC 1102 of Figure 11A. The dashed boxes in the bottom perspective view of the EIC represent the locations of the first portions 1126 of each photonic transceiver within the EIC, projected onto the lower main surface 1140 of the EIC. The switching circuits corresponding to each photonic transceiver are not shown in Figure 11B. As described above, the first portions of the photonic transceivers have drivers and amplifiers that are implemented via electronic circuits fabricated on the substrate of the EIC. However, in the example of Figure 11B, only the driver interface 1131 and amplifier interface 1133 of each photonic transceiver are exposed to the lower main surface 1140 of the EIC and are, for example, visible. In one example, the driver interface and amplifier interface of each photonic transceiver are conductive elements that can be electrically connected to electrical interconnects such as the electrical interconnects described above. In one example, the driver interface and amplifier interface of each photonic transceiver may each include one or more conductive pads.

[0106] Figure 11C is a top view of the multiport network switch 1100 described with reference to Figures 11A and 11B, where the optical ports 1116 and photonic transceivers 1120 are labeled with their corresponding optical port numbers. Referring to Figure 11C, to the left of the PIC 1104 of the multiport network switch are eight optical ports labeled Port 1 to Port 8, and to the right of the PIC of the multiport network switch are eight optical ports labeled Port 9 to Port 16. Each optical port is optically coupled to a photonic transceiver, and each optical port has a bidirectional optical channel (not shown) which includes one unidirectional optical channel for receiving optical signals from outside the multiport network switch and one unidirectional optical channel for transmitting optical signals from the multiport network switch. For example, optical port 1 is optically coupled to a photonic transceiver labeled P1, optical port 2 is optically coupled to a photonic transceiver labeled P2, and so on.

[0107] In one example, network traffic may be received at optical port 4 and transmitted from a multiport network switch on optical port 6. In this example, network traffic is converted from the optical domain to the electrical domain by photonic transceiver P4 and forwarded in the electrical domain of the EIC from the switching circuit corresponding to photonic transceiver P4 to the switching circuit corresponding to photonic transceiver P6 via an electrical path within the EIC running between the switching circuits of adjacent photonic transceiver cells. The network traffic is then converted from the electrical domain to the optical domain by photonic transceiver P6 and transmitted from optical port P6. In another example, network traffic may be received at optical port 5 and transmitted from a multiport network switch on optical port 10. In this example, network traffic is converted from the optical domain to the electrical domain by photonic transceiver P5 and forwarded in the electrical domain of the EIC from the switching circuit corresponding to photonic transceiver P5 to the switching circuit corresponding to photonic transceiver P10 via an electrical path within the EIC running between the switching circuits of adjacent photonic transceiver cells. For example, network traffic may be transmitted along a path that hops from a switching circuit corresponding to photonic transceiver cell P5 to a switching circuit corresponding to photonic transceiver cell P6, to a switching circuit corresponding to photonic transceiver cell P13, to a switching circuit corresponding to photonic transceiver cell P14, to a switching circuit corresponding to photonic transceiver cell P12, and finally to a switching circuit corresponding to photonic transceiver cell P10. The network traffic is then converted from the electrical domain to the optical domain by photonic transceiver P10 and transmitted from optical port P10.Since a multiport network switch uses a matrix of photonic transceiver cells 1180 formed by an EIC 1102 stacked on a PIC 1104, signal conversion from the optical domain to the electrical domain and from the electrical domain to the optical domain does not need to take place on the beachfront or edge of the EIC, but can instead take place wherever drivers and amplifiers can be fabricated on the EIC. Therefore, the number of ports that can be included in such a multiport network switch is not limited to the beachfront or edge dimensions of the EIC, and more photonic transceivers can be included in the EIC than if the location of the photonic transceivers were limited only to the beachfront (e.g., edge) of the EIC. Furthermore, because photonic transceivers are not limited only to the beachfront of the EIC, they can be strategically placed close to each other to reduce the physical distance that electrical signals must travel through the EIC to transfer from one photonic transceiver to another in order to perform multiport network switching. For example, by having a narrowly spaced matrix of photonic transceiver cells, the amount of physical distance that electrical signals must travel across the EIC to reach a photonic transceiver corresponding to an input optical port of a multiport network switch from that corresponding to an output optical port of the multiport network switch can be reduced, thereby reducing power consumption and latency across the multiport network switch.

[0108] Figure 12 is a process flow diagram of a method for switching network traffic using, for example, a multi-port network switch as described herein. In block 1202, an optical signal is received at a first optical port of a PIC having multiple optical ports. In block 1204, the optical signal is processed by a first photonic transceiver, which is optically coupled to the first optical port of the PIC and electrically coupled to an EIC stacked on the PIC, to generate an electrical signal. In block 1206, the electrical signal is converted to a digital signal within the EIC. In block 1208, the digital signal is transferred to a second photonic transceiver via the switching circuit of the EIC based on the information in the digital signal, and the second photonic transceiver is optically coupled to a second optical port of the PIC. In block 1210, based on the digital signal transferred to the second photonic transceiver, an optical signal is output from the second optical port of the PIC.

[0109] Figure 13 is a process flow diagram of a method for switching network traffic using, for example, an integrated circuit device (e.g., EIC) as described herein. In block 1302, an analog electrical signal received at the amplifier interface of the first part of the first photonic transceiver of the integrated circuit device is amplified, the amplifier interface is exposed on the main surface of the integrated circuit device and connected to the amplifier of the first photonic transceiver. In block 1304, the amplified analog electrical signal is converted into a digital signal within the integrated circuit device. In block 1306, the digital signal is transferred to a second photonic transceiver of the integrated circuit device via the switching circuit of the integrated circuit device based on the information in the digital signal. In block 1308, the driver of the second photonic transceiver is driven in response to the digital signal to generate an analog electrical signal at the driver interface of the first part of the second photonic transceiver, the driver interface is exposed on the main surface of the integrated circuit device.

[0110] As described above, the EIC and PIC may be fabricated as separate devices and then physically and electrically coupled to each other via electrical interconnections. In one example, the EIC alone includes novel features of a switching circuit and multiple first parts of a photonic transceiver, each first part of the photonic transceiver including a driver interface exposed on the main surface of the integrated circuit device and an amplifier interface exposed on the main surface of the integrated circuit device, and the switching circuit is configured to transfer a digital signal generated from an electrical signal received from the first part of the first photonic transceiver to the first part of the second photonic transceiver based on information in the digital signal. In one example, a first set of multiple first parts of the photonic transceiver corresponds to a spine photonic transceiver, and a second set of multiple first parts of the photonic transceiver corresponds to a leaf photonic transceiver. In another example, a first set of multiple first parts of a photonic transceiver corresponds to a spine photonic transceiver, a second set of multiple first parts of the photonic transceiver corresponds to a leaf photonic transceiver, a switching circuit surrounds the spine photonic transceiver, and the leaf photonic transceiver surrounds the switching circuit. In yet another example, a first set of multiple first parts of a photonic transceiver corresponds to an internal photonic transceiver, a second set of multiple first parts of the photonic transceiver corresponds to an external photonic transceiver, and the external photonic transceiver surrounds the internal photonic transceiver. In yet another example, the EIC has a footprint, and the first part of the photonic transceiver includes a set of first parts located in the internal region of the footprint of the integrated circuit device and a set of first parts located in the external region of the footprint of the integrated circuit device.

[0111] The connections described herein may be any type of connection suitable for transferring signals or power to or from each node, unit, or device, including through intermediate devices. Connections may be illustrated or described with reference to single connections, multiple connections, unidirectional connections, or bidirectional connections. However, different embodiments may change the configuration of the connection. For example, a single connection carrying multiple signals may be separated into various different connections carrying subsets of these signals. The term “combined” or similar language may include direct physical connections or connections through other intermediate components, even if those intermediate components alter the form of the source-to-destination coupling.

[0112] This disclosure provides a computing system implemented by one or more circuit packages (e.g., SIPs) that achieve reduced power consumption and / or increased processing speed. According to various embodiments, power consumed in particular for data movement is reduced by maximizing the locality of data within the circuit package and reducing energy loss when data movement is required. Power-efficient data movement can then be achieved by leveraging photonic channels for data movement in scenarios where resistance within the electronic domain and / or the speed at which data can move within the electronic domain result in bandwidth limitations that cannot be overcome using existing electronic technologies, while moving data over small distances within the electronic domain. Thus, in some embodiments, each circuit package includes an electronic integrated circuit (EIC) comprising switching circuits and photonic transceivers connected by a bidirectional photonic channel (e.g., implemented in a separate layer of the package or on a PIC within a chip) to a hybrid electronic photonic (or electrophotonic) multiport network switch. The multiport network switch may be connected by the bidirectional photonic channel to other multiport network switches and / or network nodes (e.g., compute nodes and / or memory nodes). The computing systems and their various novel embodiments described are generally applicable to a wide range of networking applications, but the computing systems are particularly well suited to data centers implementing ML models, especially ANNs. For example, the computing systems are particularly well suited to data centers utilizing leaf-spine network architectures.

[0113] As described herein, this disclosure includes several practical applications having the features described herein that provide advantages related to providing a multiport network switch having sufficient port density, data processing speed, and energy efficiency for effective operation in a data center, for example, a data center for processing AI and / or ML models, and / or solve problems. Some exemplary advantages are described herein in relation to the various features and functionalities provided by the computing system as described. It will be understood that the advantages explicitly described herein in relation to one or more embodiments described herein are provided as examples and are not intended to be an exhaustive list of all possible advantages of the computing system.

[0114] The various network topologies enabled by multiport network switches can provide significant speed and energy savings. For example, photonic data transport is typically more efficient than equivalent high-bandwidth electrical interconnects within the EIC itself. Implementing one or more multiport network switches in a data center can significantly reduce the electricity costs of transmitting data. A further additional benefit is that the system's power density can be controlled by spacing out the photonic transceivers on the EIC to optimize cooling efficiency, as distance and alignment are not dictated by the electrical interface.

[0115] Specific Embodiments

[0116] The embodiments described in the subject may include one or more features, either individually or in combination, as described in the following clauses.

[0117] Clause 1. A switching system, A photonic integrated circuit (PIC) having an optical port, An electrical integrated circuit (EIC) stacked on a PIC and having a switching circuit, A photonic transceiver is optically coupled to the PIC's optical port and electrically coupled to the EIC's switching circuit. Equipped with, A switching circuit configured to transfer a digital signal generated from an optical signal received by a first photonic transceiver of a photonic transceiver to a second photonic transceiver of the photonic transceiver based on information in the digital signal, wherein the first photonic transceiver is optically coupled to a first optical port of the PIC, and the second photonic transceiver is optically coupled to a second optical port of the PIC.

[0118] Clause 2. Each photonic transceiver is a switching system as described in Clause 1, comprising a first portion in the EIC, a second portion in the PIC, and an electrical interconnection electrically coupling the first portion in the EIC and the second portion in the PIC.

[0119] Clause 3. The first part of each photonic transceiver in the EIC includes a driver and an amplifier. A switching system as described in Clause 1 or Clause 2, wherein the second portion of each photonic transceiver in the PIC includes a modulator and a photodetector.

[0120] Clause 4. The driver for each photonic transceiver includes a driver interface on the lower main surface of the EIC. The amplifier of each photonic transceiver includes an amplifier interface on the lower main surface of the EIC. Each photonic transceiver modulator includes a modulator interface on the upper main surface of the PIC. Each photonic transceiver's photodetector includes a photodetector interface on the upper main surface of the PIC. A switching system according to any one of clauses 1 to 3, wherein the driver interface is coupled to the modulator interface by a first electrical interconnection, and the amplifier interface is coupled to the photodetector by a second electrical interconnection.

[0121] Clause 5. The switching system according to any one of Clauses 1 to 4, wherein the first part of each photonic transceiver is vertically aligned with the second part of the corresponding photonic transceiver.

[0122] Clause 6. The second part of each photonic transceiver in the PIC is a switching system as described in any of Clauses 1 to 5, including an electroabsorption modulator.

[0123] Clause 7. Each photonic transceiver includes a first part in the EIC, a second part in the PIC, and an electrical interconnect that electrically couples the first part in the EIC and the second part in the PIC. The first part of each photonic transceiver in the EIC includes a driver and an amplifier. The second part of each photonic transceiver in the PIC includes a modulator and a photodetector. A switching system according to any one of clauses 1 to 6, wherein the first portion of each photonic transceiver is aligned perpendicularly with the second portion of the corresponding photonic transceiver.

[0124] Clause 8. A switching system as described in any of Clauses 1 to 7, in which a photonic transceiver is located in the internal region of the EIC.

[0125] Clause 9. A switching system according to any one of Clauses 1 to 8, wherein the EIC has a footprint, and the photonic transceiver includes a photonic transceiver located in the internal area of ​​the footprint of the EIC.

[0126] Clause 10. A switching system according to any one of Clauses 1 to 9, comprising a first set of photonic transceivers enclosed by a switching circuit and a second set of photonic transceivers enclosing a switching circuit.

[0127] Clause 11. Photonic transceivers are switching systems as described in any of Clauses 1 to 10, including spine photonic transceivers and leaf photonic transceivers.

[0128] Clause 12. A switching system according to any one of Clauses 1 to 11, comprising a spine photonic transceiver surrounded by a switching circuit and a leaf photonic transceiver surrounding a switching circuit.

[0129] Clause 13. A switching system as described in any of Clauses 1 to 12, where the electrical interconnections are less than 50 microns.

[0130] Clause 14. A switching circuit is a switching system as described in any of Clauses 1 to 13, including a switch fabric.

[0131] Clause 15. The switching system according to claim 14, wherein the switch fabric is a crosspoint matrix.

[0132] Clause 16. The PIC is part of the switching system described in Clause 15, including an optical port configured to connect to an optical engine.

[0133] Clause 17. Receiving an optical signal at the first optical port of a photonic integrated circuit (PIC) having multiple optical ports, In a first photonic transceiver, which is optically coupled to the first optical port of the PIC and electrically coupled to an electrical integrated circuit (EIC) stacked on the PIC, the optical signal is processed and an electrical signal is generated. The process of converting electrical signals to digital signals within the EIC, The digital signal is transferred to a second photonic transceiver via the EIC's switching circuit based on information within the digital signal, and the second photonic transceiver is optically coupled to the PIC's second optical port. Based on the digital signal transferred to the second photonic transceiver, an optical signal is output from the second optical port of the PIC. Methods that include...

[0134] Clause 18. Processing an optical signal in the first photonic transceiver includes converting the optical signal to an electrical signal in the PIC and amplifying the electrical signal in the EIC. The method according to Clause 17, wherein outputting an optical signal in the second photonic transceiver includes generating a driver signal in the EIC and modulating an optical carrier in the PIC in response to the driver signal.

[0135] Clause 19. The method of Clause 17 or Clause 18, wherein each optical port of the PIC includes a corresponding photonic transceiver, each photonic transceiver including a first part in the EIC, a second part in the PIC, and an electrical interconnection electrically coupling the first part in the EIC and the second part in the PIC.

[0136] Article 20.

[0137] The first part of each photonic transceiver in the EIC includes a driver and an amplifier.

[0138] The method according to any one of the clauses 17 to 19, wherein the second part of each photonic transceiver in the PIC includes a modulator and a photodetector.

[0139] Clause 21. The method according to any one of Clauses 17 to 20, wherein the first portion of each photonic transceiver is aligned perpendicularly with the second portion of the corresponding photonic transceiver.

[0140] Clause 22. The second part within the PIC of each photonic transceiver includes an electroabsorption modulator, as described in any of Clauses 17 to 21.

[0141] Clause 23. The driver for each photonic transceiver includes a driver interface on the lower main surface of the EIC. The amplifier of each photonic transceiver includes an amplifier interface on the lower main surface of the EIC. Each photonic transceiver modulator includes a modulator interface on the upper main surface of the PIC. Each photonic transceiver's photodetector includes a photodetector interface on the upper main surface of the PIC. The method according to any one of the clauses 17 to 22, wherein the driver interface is coupled to the modulator interface by a first electrical interconnection, and the amplifier interface is coupled to the photodetector by a second electrical interconnection.

[0142] Clause 24. The EIC comprises a spine photonic transceiver and a leaf photonic transceiver, wherein the first photonic transceiver is a leaf photonic transceiver and the second photonic transceiver is a spine photonic transceiver, as described in any of Clauses 17 to 23.

[0143] Clause 25. The EIC comprises a spine photonic transceiver and a leaf photonic transceiver, wherein the first photonic transceiver is a spine photonic transceiver and the second photonic transceiver is a leaf photonic transceiver, as described in any of Clauses 17 to 24.

[0144] Clause 26. The method in any of Clauses 17 to 25, wherein the EIC includes a first set of photonic transceivers surrounded by a second set of photonic transceivers, the first photonic transceivers being within the second set of photonic transceivers, and the second photonic transceivers being within the first set of photonic transceivers.

[0145] Clause 27. The method in any of Clauses 17 to 26, wherein the EIC includes a first set of photonic transceivers surrounded by a second set of photonic transceivers, the first photonic transceivers being within the first set of photonic transceivers and the second photonic transceivers being within the second set of photonic transceivers.

[0146] Clause 28. Transferring a digital signal to a second photonic transceiver via a switching circuit based on information in the digital signal, the method of any one of Clauses 17 to 27, which includes identifying an output optical port based on a medium access control (MAC) table in the switching circuit.

[0147] The method described in any of the clauses 17 to 28, further comprising receiving an optical carrier in the PIC.

[0148] Clause 30. Integrated circuit device, Switching circuit and A plurality of first parts of a photonic transceiver, each first part of the photonic transceiver including a driver and a driver interface exposed on the main surface of the integrated circuit device, and an amplifier and an amplifier interface exposed on the main surface of the integrated circuit device. Equipped with, An integrated circuit device in which a switching circuit is configured to transfer a digital signal generated from an electrical signal received from a first part of a first photonic transceiver to a first part of a second photonic transceiver, based on information in the digital signal.

[0149] Clause 31. The integrated circuit device according to Clause 30, wherein the main surface of the integrated circuit device is the lower main surface of the integrated circuit device.

[0150] Clause 32. The main surface of the integrated circuit device is the lower main surface of the integrated circuit device. The driver interface for each photonic transceiver is located on the lower main surface of the integrated circuit device so as to be aligned with the modulator interface on the photonic integrated circuit (PIC). The integrated circuit device according to Clause 30 or Clause 31, wherein the amplifier interface of each photonic transceiver is located on the lower main surface of the integrated circuit device so as to be aligned with the photodetector interface on the PIC.

[0151] Clause 33. The driver interface of each photonic transceiver shall be located on the integrated circuit device so as to be aligned with the modulator interface on the photonic integrated circuit (PIC). The amplifier interface of each photonic transceiver is positioned on the integrated circuit device so as to be aligned with the photodetector interface on the PIC, as described in any of the integrated circuit devices in any of the clauses 30 to 32.

[0152] Clause 34. A switching circuit is an integrated circuit device as described in any of Clauses 30 to 33, including a switch fabric.

[0153] Clause 35. The switch fabric is a crosspoint matrix, as described in any of Clauses 30 to 34 of the integrated circuit device.

[0154] Clause 36. An integrated circuit device according to any one of Clauses 30 to 35, wherein the switching circuit is configured to identify a photonic transceiver of the integrated circuit device for transferring a digital signal based on information in a medium access control (MAC) table stored in the integrated circuit device.

[0155] Clause 37. An integrated circuit device as described in any of Clauses 30 to 36, wherein a first set of multiple first parts of a photonic transceiver surrounds a second set of multiple first parts of a photonic transceiver.

[0156] Clause 38. A switching system according to any one of Clauses 30 to 37, wherein the integrated circuit device has a footprint, and the first part of the photonic transceiver is located in an internal area of ​​the footprint of the integrated circuit device.

[0157] Clause 39. An integrated circuit device according to any one of Clauses 30 to 38, wherein a first set of multiple first parts of the photonic transceiver corresponds to a spine photonic transceiver, and a second set of multiple first parts of the photonic transceiver corresponds to a leaf photonic transceiver.

[0158] Clause 40. An integrated circuit device according to any one of Clauses 30 to 39, wherein a first set of multiple first parts of the photonic transceiver corresponds to a spine photonic transceiver, a second set of multiple first parts of the photonic transceiver corresponds to a leaf photonic transceiver, a switching circuit surrounds the spine photonic transceiver, and the leaf photonic transceiver surrounds the switching circuit.

[0159] Clause 41. Amplifying an analog electrical signal received at an amplifier interface of a first portion of a first photonic transceiver of an integrated circuit device, wherein the amplifier interface is exposed on the main surface of the integrated circuit device and is electrically coupled to the amplifier of the first photonic transceiver. Converting amplified analog electrical signals into digital signals within an integrated circuit device, Transferring a digital signal to a second photonic transceiver of an integrated circuit device via a switching circuit of the integrated circuit device based on information within the digital signal, The driver interface of the first part of the second photonic transceiver is driven in response to a digital signal to generate an analog electrical signal, wherein the driver interface is exposed on the main surface of the integrated circuit device. Methods that include...

[0160] Clause 42. The method according to Clause 41, wherein transferring a digital signal to a second photonic transceiver of an integrated circuit device via a switching circuit based on information in the digital signal includes identifying an output optical port based on a medium access control (MAC) table in the switching circuit.

[0161] Clause 43. The method of Clause 41 or Clause 42, wherein the EIC includes a spine photonic transceiver and a leaf photonic transceiver, the first photonic transceiver being a leaf photonic transceiver and the second photonic transceiver being a spine photonic transceiver.

[0162] Clause 44. The method according to any one of Clauses 41 to 43, wherein the EIC includes a spine photonic transceiver and a leaf photonic transceiver, the first photonic transceiver being a spine photonic transceiver and the second photonic transceiver being a leaf photonic transceiver.

[0163] Clause 45. The method according to any of Clauses 41 to 44, wherein the EIC includes an internal photonic transceiver surrounded by an external photonic transceiver, the first photonic transceiver being an external photonic transceiver and the second photonic transceiver being an internal photonic transceiver.

[0164] Clause 46. The method according to any one of Clauses 41 to 45, wherein the EIC includes an internal photonic transceiver surrounded by an external photonic transceiver, the first photonic transceiver being an internal photonic transceiver and the second photonic transceiver being an external photonic transceiver.

[0165] Although the operations of the methods described herein are shown and described in a specific order, the order of operations of each method may be modified so that certain operations may be performed in reverse order, or so that certain operations may be performed at least partially concurrently with other operations. In another embodiment, instructions or suboperations of separate operations may be performed intermittently and / or alternately.

[0166] It should also be noted that at least some of the operations for the methods described herein may be performed using software instructions stored on a computer-readable storage medium for execution by a computer. As an example, one embodiment of a computer program product includes a computer-readable storage medium for storing a computer-readable program.

[0167] It will be readily apparent that the components of the embodiments generally described herein and shown in the figures can be arranged and designed in a wide variety of different configurations. Therefore, the following more detailed description of various examples, such as those shown in the figures, is not intended to limit the scope of this disclosure, but merely to be representative of various embodiments. While various aspects of the examples are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0168] The disclosed technology may be embodied in other specific forms without departing from its spirit or essential features. The examples described should be considered in all respects as illustrative only and not limiting. Accordingly, the scope of the disclosed technology is indicated not by this detailed description but by the attached claims. All modifications that fall within the meaning and scope of the equivalents of the claims should be encompassed within their scope.

[0169] Throughout this specification, references to features, advantages, or similar terms do not imply that all features and advantages that may be realized in the disclosed technology should be or are any single example. Rather, terms referring to features and advantages are understood to mean that the particular features, advantages, or characteristics described in relation to the examples are included in at least one example of the disclosed technology. Thus, throughout this specification, descriptions of features and advantages, as well as similar terms, may refer to the same examples, though not necessarily.

[0170] Furthermore, the described features, benefits, and characteristics of the disclosed technology may be combined in any suitable manner in one or more examples. A person skilled in the art will recognize, in light of the description herein, that the disclosed technology can be implemented without one or more of the specific features or benefits of a particular example. In other cases, additional features and benefits may be recognized in a particular example that may not be present in all examples of the disclosed technology.

[0171] Throughout this specification, any reference to “example,” “example,” or similar wording means that a particular feature, structure, or characteristic described in relation to the example shown is included in at least one example of the disclosed technology. Thus, throughout this specification, “in an example,” “in an example,” and similar wording may all, though not necessarily, refer to the same example.

[0172] While specific examples of the disclosed technology have been described and illustrated, the disclosed technology is not limited to specific forms or arrangements of the components thus described and illustrated. The scope of the disclosed technology should be defined by the appended claims and their equivalents.

Claims

1. A switching system, wherein the switching system is A photonic integrated circuit (PIC) having an optical port, An electrical integrated circuit (EIC) having a switching circuit is stacked on the PIC, A photonic transceiver is optically coupled to the optical port of the PIC and electrically coupled to the switching circuit of the EIC. Equipped with, The switching circuit is configured to transfer a digital signal generated from an optical signal received by a first photonic transceiver of the photonic transceiver to a second photonic transceiver of the photonic transceiver based on information in the digital signal, the first photonic transceiver is optically coupled to a first optical port of the PIC, and the second photonic transceiver is optically coupled to a second optical port of the PIC, in a switching system.

2. The switching system according to claim 1, wherein each photonic transceiver includes a first portion within the EIC, a second portion within the PIC, and an electrical interconnect that electrically couples the first portion within the EIC and the second portion within the PIC.

3. The first portion of each photonic transceiver in the EIC includes a driver and an amplifier. The switching system according to claim 2, wherein the second portion of each photonic transceiver in the PIC includes a modulator and a photodetector.

4. The driver of each photonic transceiver includes a driver interface on the lower main surface of the EIC. The amplifier of each photonic transceiver includes an amplifier interface on the lower main surface of the EIC. The modulator of each photonic transceiver includes a modulator interface on the upper main surface of the PIC. The photodetector of each photonic transceiver includes a photodetector interface on the upper main surface of the PIC. The switching system according to claim 3, wherein the driver interface is coupled to the modulator interface by a first electrical interconnection, and the amplifier interface is coupled to the photodetector by a second electrical interconnection.

5. The switching system according to claim 2, wherein the first portion of each photonic transceiver is aligned perpendicularly with the second portion of the corresponding photonic transceiver.

6. The switching system according to claim 2, wherein the second portion of each photonic transceiver in the PIC includes an electroabsorption modulator.

7. Each photonic transceiver includes a first portion within the EIC, a second portion within the PIC, and an electrical interconnect that electrically connects the first portion within the EIC and the second portion within the PIC. The first portion of each photonic transceiver in the EIC includes a driver and an amplifier. The second portion of each photonic transceiver in the PIC includes a modulator and a photodetector. The switching system according to claim 1, wherein the first portion of each photonic transceiver is aligned perpendicularly with the second portion of the corresponding photonic transceiver.

8. The switching system according to claim 1, wherein the photonic transceiver is located in the internal region of the EIC.

9. The switching system according to claim 1, wherein the EIC has a footprint, and the photonic transceiver includes a photonic transceiver located in the internal region of the footprint of the EIC.

10. The switching system according to claim 1, wherein the photonic transceiver includes a first set of photonic transceivers surrounded by the switching circuit and a second set of photonic transceivers surrounding the switching circuit.

11. The switching system according to claim 1, wherein the photonic transceiver includes a spine photonic transceiver and a leaf photonic transceiver.

12. The switching system according to claim 1, wherein the photonic transceiver includes a spine photonic transceiver surrounded by the switching circuit and a leaf photonic transceiver surrounding the switching circuit.

13. The switching system according to claim 2, wherein the electrical interconnection is less than 50 microns.

14. The switching system according to claim 1, wherein the switching circuit includes a switch fabric.

15. The switching system according to claim 14, wherein the switch fabric is a crosspoint matrix.

16. The switching system according to claim 1, wherein the PIC includes an optical port configured to connect to an optical engine.

17. It is a method, Receiving an optical signal at the first optical port of a photonic integrated circuit (PIC) having multiple optical ports, In a first photonic transceiver optically coupled to the first optical port of the PIC and electrically coupled to an electrical integrated circuit (EIC) stacked on the PIC, the optical signal is processed and an electrical signal is generated. The EIC converts the electrical signal into a digital signal, The digital signal is transferred to a second photonic transceiver via the switching circuit of the EIC based on the information in the digital signal, wherein the second photonic transceiver is optically coupled to the second optical port of the PIC. Based on the digital signal transferred to the second photonic transceiver, an optical signal is output from the second optical port of the PIC. Methods that include...

18. Processing the optical signal in the first photonic transceiver includes converting the optical signal into an electrical signal in the PIC and amplifying the electrical signal in the EIC. The method according to claim 17, wherein outputting an optical signal in the second photonic transceiver includes generating a driver signal in the EIC and modulating an optical carrier in the PIC in response to the driver signal.

19. The method according to claim 17, wherein each optical port of the PIC includes a corresponding photonic transceiver, each photonic transceiver includes a first portion within the EIC, a second portion within the PIC, and an electrical interconnection that electrically couples the first portion within the EIC and the second portion within the PIC.

20. The first portion of each photonic transceiver in the EIC includes a driver and an amplifier. The method according to claim 19, wherein the second portion of each photonic transceiver in the PIC includes a modulator and a photodetector.

21. The method according to claim 19, wherein the first portion of each photonic transceiver is aligned perpendicularly with the second portion of the corresponding photonic transceiver.

22. The method according to claim 19, wherein the second portion of the PIC in each photonic transceiver includes an electroabsorption modulator.

23. The driver of each photonic transceiver includes a driver interface on the lower main surface of the EIC. The amplifier of each photonic transceiver includes an amplifier interface on the lower main surface of the EIC. The modulator of each photonic transceiver includes a modulator interface on the upper main surface of the PIC. The photodetector of each photonic transceiver includes a photodetector interface on the upper main surface of the PIC. The method according to claim 17, wherein the driver interface is coupled to the modulator interface by a first electrical interconnection, and the amplifier interface is coupled to the photodetector by a second electrical interconnection.

24. The method according to claim 17, wherein the EIC includes a spine photonic transceiver and a leaf photonic transceiver, the first photonic transceiver being a leaf photonic transceiver and the second photonic transceiver being a spine photonic transceiver.

25. The method according to claim 17, wherein the EIC includes a spine photonic transceiver and a leaf photonic transceiver, the first photonic transceiver being a spine photonic transceiver and the second photonic transceiver being a leaf photonic transceiver.

26. The method according to claim 17, wherein the EIC includes a first set of photonic transceivers surrounded by a second set of photonic transceivers, the first photonic transceivers being within the second set of photonic transceivers, and the second photonic transceivers being within the first set of photonic transceivers.

27. The method according to claim 17, wherein the EIC includes a first set of photonic transceivers surrounded by a second set of photonic transceivers, the first photonic transceivers being located within the first set of photonic transceivers, and the second photonic transceivers being located within the second set of photonic transceivers.

28. The method according to claim 17, wherein transferring the digital signal to the second photonic transceiver via the switching circuit based on information in the digital signal includes identifying an output optical port based on a medium access control (MAC) table in the switching circuit.

29. The method according to claim 17, further comprising receiving an optical carrier in the PIC.

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