Enhanced HEMT devices, chips, and equipment with GaN insertion layer

Abstract

The present invention provides an enhanced HEMT device with a GaN insertion layer that achieves a balance between a high threshold voltage and low on-resistance, as well as a chip and equipment including the device. [Solution] The reinforced HEMT device includes a base layer 1, a transition layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5 sequentially located on the base layer, a GaN insertion layer 91 and a Mg-doped p-GaN layer 92 sequentially located on the barrier layer, an isolation structure 8 located on the side wall of the reinforced HEMT device, a TiN protective layer 93 located on the p-GaN layer, a passivation layer 10 located on the side wall of the p-GaN layer and the side wall of the TiN protective layer and also located on the barrier layer, a gate 95 penetrating the passivation layer and located on the TiN protective layer, and a source electrode 7 and a drain electrode 6 located on different sides of the p-GaN layer, respectively, the source electrode and drain electrode penetrating the passivation layer and located on the barrier layer.

Description

[Technical Field]

[0001] This application belongs to the field of semiconductor device technology, and more particularly to reinforced HEMT devices, chips, and equipment with a GaN insertion layer. [Background technology]

[0002] GaN, as a representative material for third-generation semiconductors, possesses advantages such as high voltage resistance, wide bandgap, and high electron mobility. High-electron-mobility enhanced HEMT devices manufactured using GaN offer advantages such as lower cost and higher performance compared to conventional Si-based power devices, and have enormous potential in high-voltage, high-power electronic power applications.

[0003] Currently, solutions for realizing reinforced devices using a p-GaN cap layer as a gate are basically commercialized. However, in actual applications, relatively low threshold voltages can lead to false conduction of the device, significantly threatening the reliability of the switching process of the entire circuit system. Conventional solutions to raise the threshold voltage typically involve increasing the Mg doping concentration or overactivating the Mg in the p-GaN cap layer. However, even with increased Mg concentration, high temperatures during activation cause a large amount of Mg to diffuse into the channel and barrier layers. This diffused Mg introduces impurity levels, trapping electrons in the channel and increasing the on-resistance of the device, which in turn increases the overall loss reduction efficiency of the system. Therefore, achieving a balance between a high threshold voltage and low on-resistance is extremely difficult. [Overview of the project] [Problems that the invention aims to solve]

[0004] The technical problem that this invention aims to solve is to provide an enhanced HEMT device, chip, and electronic device with a GaN insertion layer to solve the problems mentioned in the background art. [Means for solving the problem]

[0005] To solve the above technical problems, this application provides the following technical solution.

[0006] According to a first aspect, the present application provides an enhanced HEMT device with a GaN insertion layer, the enhanced HEMT device is The aforementioned underlying layers are sequentially located in the transition layer, buffer layer, channel layer, and barrier layer above the aforementioned underlying layer, A GaN insertion layer and an Mg-doped p-GaN layer are sequentially located in some of the aforementioned barrier layers. An isolation structure located on the side wall of the reinforced HEMT device, comprising an isolation structure that penetrates the barrier layer, the channel layer and a portion of the buffer layer, The TiN protective layer located in the aforementioned p-GaN layer, The passivation layer located on the sidewall of the p-GaN layer and the sidewall of the TiN protective layer, and in the barrier layer, A gate that penetrates the passivation layer and is located in the TiN protective layer, A source electrode located on one side of the p-GaN layer, which penetrates the passivation layer and is located in the barrier layer, The present invention includes a drain electrode located on the other side of the p-GaN layer, which penetrates the passivation layer and is located in the barrier layer.

[0007] Furthermore, the GaN insertion layer is made of undoped GaN, and its thickness range is 0.5 nm to 40 nm.

[0008] Furthermore, the thickness range of the p-GaN layer is 50 nm to 500 nm, and the Mg doping concentration range of the p-GaN layer is 10 18 cm -3 ~10 20 cm -3 That is the case.

[0009] Furthermore, the thickness range of the transition layer is 10 nm to 500 nm, and the material of the transition layer includes at least one of AlN, AlGaN, and GaN; the thickness range of the buffer layer is 300 nm to 6000 nm, and the material of the buffer layer includes at least one of high-resistivity GaN and high-resistivity AlGaN; the channel layer is intentionally undoped GaN and has a thickness range of 50 nm to 500 nm; the thickness range of the barrier layer is 10 nm to 40 nm, and the material of the barrier layer is Al x Ga 1-x N is included, and the range of values ​​for X is 0.1 to 0.5.

[0010] Furthermore, the thickness range of the TiN protective layer is 5 nm to 300 nm.

[0011] Furthermore, the thickness range of the passivation layer is 50 nm to 400 nm, and the material of the passivation layer includes at least one of AlN, SiN, AlON, Al2O3, HfO2, ZrO2, Y2O3, and SiO2.

[0012] Furthermore, the isolation structure includes either a mesa-type isolation structure or an ion implantation structure.

[0013] According to a second aspect, the present application further provides a chip comprising the enhanced HEMT device described in any one of the above paragraphs.

[0014] According to a third aspect, the present application further provides an electronic device, the electronic device including the chip. [Effects of the Invention]

[0015] The beneficial effects of the enhanced HEMT devices, chips, and electronic devices with GaN insertion layers according to this application are as follows:

[0016] 1. The enhanced HEMT device with a GaN insertion layer according to the present application inserts an undoped GaN insertion layer between the p-GaN layer and the AlGaN barrier layer to ensure a relatively high threshold voltage, avoid the diffusion of excessive Mg into the channel to capture free electrons, and adjust the thickness of the insertion layer to achieve a balance between the threshold voltage and the on-resistance.

[0017] 2. In the present application, by accurately controlling the thickness of the GaN insertion layer, the diffusion depth of Mg in the p-GaN can be effectively changed, and the hand structure of the device can be further changed, thereby increasing a relatively low hole barrier in the p-GaN layer and the AlGaN layer, restricting holes to a certain extent in the GaN insertion layer and the AlGaN barrier layer, effectively inducing a two-dimensional electron gas, and further realizing a relatively small on-resistance.

Brief Description of the Drawings

[0018] To more clearly describe the technical solution in the embodiments of the present invention, the following briefly introduces the attached drawings that need to be used in the description of the embodiments. Obviously, the attached drawings in the following description are only some embodiments of the present invention. For those skilled in the art, based on these attached drawings without creative efforts, other attached drawings can also be obtained. [Figure 1] It is a schematic structural diagram of the enhanced HEMT device with a GaN insertion layer in the embodiment of the present application. [Figure 2a] It is a detailed schematic diagram of the manufacturing process of the enhanced HEMT device with a GaN insertion layer in the embodiment of the present application. [Figure 2b] It is a detailed schematic diagram of the manufacturing process of the enhanced HEMT device with a GaN insertion layer in the embodiment of the present application. [Figure 2c] It is a detailed schematic diagram of the manufacturing process of the enhanced HEMT device with a GaN insertion layer in the embodiment of the present application. [Figure 2d] It is a detailed schematic diagram of the manufacturing process of the enhanced HEMT device with a GaN insertion layer in the embodiment of the present application. [Figure 2e]This is a detailed schematic diagram of the manufacturing process of an enhanced HEMT device with a GaN insertion layer according to an embodiment of this application. [Figure 2f] This is a detailed schematic diagram of the manufacturing process of an enhanced HEMT device with a GaN insertion layer according to an embodiment of this application. [Figure 2g] This is a detailed schematic diagram of the manufacturing process of an enhanced HEMT device with a GaN insertion layer according to an embodiment of this application. [Figure 2h] This is a detailed schematic diagram of the manufacturing process of an enhanced HEMT device with a GaN insertion layer according to an embodiment of this application. [Figure 3] This is a schematic diagram of the actual test results of a transfer test (ID&IG-VG) of an enhanced HEMT device having a different GaN insertion layer thickness tGaN according to the embodiments of this application. [Figure 4] This is a schematic diagram showing the actual test statistics of the threshold voltage VTH and on-resistance RON of reinforced HEMT devices having different GaN insertion layer thicknesses tGaN according to embodiments of this application. [Figure 5] This is a flowchart of the method for manufacturing an enhanced HEMT device with a GaN insertion layer according to an embodiment of this application. [Modes for carrying out the invention]

[0019] In the following, the technical concepts in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings of the embodiments of this application. It is clear that the embodiments described are only a subset of the embodiments of this application, not all of them. All other embodiments obtained based on the embodiments of this application without the creative effort of a person skilled in the art are all within the scope of protection of this application.

[0020] When an element is said to be "fixed" to another element, it may be directly positioned on the other element, or there may be an element in the middle. When an element is considered to be "connected" to another element, it may be directly connected to the other element, or there may be an element in the middle simultaneously. Conversely, when an element is said to be "directly" "on top of" another element, there is no intermediate element. The terms "vertical," "horizontal," "left," "right," and similar descriptions used herein are for illustrative purposes only.

[0021] In this application, terms such as “attachment,” “connection,” “bonding,” and “fixing” should be understood broadly unless otherwise explicitly specified or limited. For example, these may be fixed connections, removable connections, integrated connections, mechanical connections, electrical connections, direct connections, indirect connections via an intermediate medium, internal communication between two elements, or interaction relationships between two elements. Those skilled in the art will understand the specific meaning of these terms in this application depending on the specific circumstances.

[0022] Furthermore, the terms “first” and “second” are used solely for descriptive purposes and should not be understood as indicating or suggesting relative importance, or implicitly indicating the number of technical features being referred to. Thus, features limited by “first” and “second” may explicitly or implicitly include one or more of those features. In the description of this application, “multiple” means two or more unless otherwise specifically limited.

[0023] The terms used in one or more embodiments of this application are for the sole purpose of describing a particular embodiment and are not intended to limit one or more embodiments of this application. The singular forms “one,” “the said,” and “the said” used in one or more embodiments of this application are also intended to include plural forms unless the context clearly indicates otherwise.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art. In this specification, terms used in the template specification are solely for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more related listed items.

[0025] In one or more embodiments of this application, various pieces of information may be described using terms such as "First," "Second," etc., but it should be understood that this information should not be limited to these terms. These terms are used only to distinguish the same type of information. For example, without departing from the scope of one or more embodiments of this application, "First" may be called "Second," and similarly, "Second" may be called "First." Depending on the context, the word "case" as used herein may be interpreted as "when" or "at times."

[0026] Referring to Figure 1, the embodiment of this application provides a reinforced HEMT device with a GaN insertion layer, comprising: a base layer 1 sequentially located on a base layer, a transition layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5; a GaN insertion layer 91 and a Mg-doped p-GaN layer 92 sequentially located on the barrier layer 5; an isolation structure 8 located on the side wall of the reinforced HEMT device, the isolation structure 8 penetrating the barrier layer 5, the channel layer 4, and part of the buffer layer 3; a TiN protective layer 93 located on the p-GaN layer 92; and the p-GaN layer The circuit includes a passivation layer 10 located on the side wall of the 92 and the side wall of the TiN protective layer 93 and in the barrier layer 5, a gate 95 that penetrates the passivation layer 10 and is located in the TiN protective layer 93, a source electrode 7 located on one side of the p-GaN layer 92 that penetrates the passivation layer 10 and is located in the barrier layer 5, and a drain electrode 6 located on the other side of the p-GaN layer 92 that penetrates the passivation layer 10 and is located in the barrier layer 5.

[0027] Specifically, in the above-described reinforced HEMT device, a relatively high threshold voltage is secured by intentionally inserting an undoped GaN insertion layer 91 between the p-GaN layer 92 and the AlGaN barrier layer 5, while also preventing excess Mg from diffusing into the channel and trapping free electrons. By adjusting the thickness of the GaN insertion layer 91, a balance between the threshold voltage and on-resistance is achieved.

[0028] Below, we will describe each of the above structures in detail, referring to the attached diagrams.

[0029] Continuing to refer to Figure 1, a base layer 1 is provided, which may specifically be one of the following: a sapphire base layer, a Si base layer, a SiC base layer, a diamond base layer, a glass base layer, a ceramic base layer, and a polymer base layer, and serves as the support structure and carrier structure for the reinforced HEMT device.

[0030] Continuing to refer to Figure 1, when forming a transition layer 2, buffer layer 3, channel layer 4, and barrier layer 5 on a base layer 1 and determining the material of the transition layer 2, the material of the transition layer 2 may be at least one of AlN, AlGaN, and GaN. The thickness range of the transition layer 2 may be between 10 nm and 500 nm in order to ensure relatively good stress regulation between the base layer 1 and the buffer layer 3.

[0031] Continuing to refer to Figure 1, a buffer layer 3, a channel layer 4, and a barrier layer 5 are further formed on the transition layer 2. When determining the material of the buffer layer 3, in this example, the material of the buffer layer 3 may be at least one of high-resistivity GaN and high-resistivity AlGaN, and the thickness range of the buffer layer 3 can be controlled to 300 nm to 6000 nm, thereby allowing the buffer layer 3 to grow normally without being fractured in the longitudinal direction.

[0032] Continuing to refer to Figure 1, a channel layer 4 and a barrier layer 5 are further formed on top of the buffer layer 3. When determining the materials of the channel layer 4 and barrier layer 5, in this embodiment, the channel layer 4 is intentionally undoped GaN with a thickness range of 50 nm to 500 nm, and the material of the barrier layer 5 is Al x Ga 1-x It may be N, and the thickness range is 10 nm to 40 nm, where the range of values ​​for X is 0.1 to 0.5.

[0033] In this embodiment, the thickness range of the channel layer 4 is controlled to be between 50 nm and 500 nm, and the thickness range of the barrier layer 5 is controlled to be between 10 nm and 40 nm, ensuring that the channel layer 4 and the barrier layer 5 work together to generate a two-dimensional electron gas (2DEG) using the polarization effect.

[0034] To make it easier to understand, channel layer 4 provides a suitable space for the formation of a two-dimensional electron gas (2DEG). Due to the polarization effect, a very strong electric field is generated near the AlGaN-GaN interface. This electric field attracts electrons in the GaN channel layer 4 to the interface.

[0035] The presence of a barrier layer is crucial for the formation of 2DEGs. Due to the difference in polarization between AlGaN and GaN, polarization charges are generated at the interface. These polarization charges form a high-electric-field region near the interface, and because the band gap of AlGaN is wider than that of GaN, an energy barrier is formed at the interface. This barrier effectively restricts the motion of electrons perpendicular to the interface, confining them near the interface between the GaN channel layer and the AlGaN barrier layer. As a result, electrons can only move in a two-dimensional plane parallel to the interface, thereby promoting the formation of 2DEGs. At the same time, the barrier layer 5 prevents interference from impurities and other factors in the 2DEGs within the channel layer, improving the stability and electrical performance of the 2DEGs.

[0036] Continuing to refer to FIG. 1, a GaN insertion layer 91 grows above the barrier layer 5. In this embodiment, the GaN insertion layer 91 is GaN that is not intentionally doped, and the thickness range is 0.5 nm to 40 nm. As can be understood, in this embodiment, the lattice matching degree between the GaN insertion layer 91 and the p-GaN layer 92 (Mg-doped GaN) is high (almost no mismatch), and as a physical barrier, Mg atoms in the p-GaN layer 92 are prevented from diffusing into the lower barrier layer 5 and the channel layer 4 during a high-temperature process (such as activation annealing), and the capture of 2DEG by Mg impurities (reducing channel electron loss and reducing on-resistance) can be avoided.

[0037] Continuing to refer to FIG. 1, a p-GaN layer 92 grows above the GaN insertion layer 91. In this example, the doping concentration range of Mg in the p-GaN layer 92 is 10 18 cm -3 ~10 20 cm -3 which can be controlled, and the thickness range of the p-GaN layer 92 can be controlled between 50 nm and 500 nm. As can be understood, in this embodiment, the p-GaN layer 92 cooperates with the GaN insertion layer 91 to ensure the activation efficiency of Mg, and at the same time (with a reasonable annealing temperature), by preventing diffusion by the GaN insertion layer 91, a high threshold voltage (for example, rising from 1 to 2 V in the conventional case to 3 to 5 V) can be realized at a relatively low Mg concentration, and the harm of "high Mg concentration → high diffusion → high on-resistance" can be avoided.

[0038] Continuing to refer to FIG. 1, the sidewall of the enhancement-mode HEMT device further includes an isolation structure 8. The isolation structure 8 penetrates through the barrier layer 5, the channel layer 4, and a part of the buffer layer 3. As can be understood, by installing the isolation structure 8 on the sidewall of the enhancement-mode HEMT device, an isolation region can be formed to reduce the parasitic effect.

[0039] In a specific embodiment, the isolation structure 8 includes any one of a mesa-type isolation structure and an ion implantation structure.

[0040] Specifically, a mesa-type isolation structure is an isolation structure formed in the mesa region of a semiconductor device during the manufacturing process, such as etching. It is used to achieve electrical isolation between different device regions, reduce problems such as leakage current and crosstalk, and improve the performance and reliability of the device.

[0041] An ion implantation structure is a doping structure that uses an ion implanter to accelerate impurity ions and implant them into a semiconductor material. By controlling parameters such as the type, energy, amount, and angle of the implanted ions, it is possible to precisely change the electrical properties of the semiconductor material, such as carrier concentration and conductivity type, thereby enabling regulated control of semiconductor device performance.

[0042] Continuing to refer to Figure 1, a TiN protective layer 93 grows further above the p-GaN layer 92. In this embodiment, the thickness range of the TiN protective layer 93 is between 5 nm and 300 nm. As can be seen, the TiN protective layer 93 protects the p-GaN layer 92 from chemical corrosion during subsequent gate fabrication (e.g., photolithography, etching) and prevents gate leakage due to surface damage.

[0043] Continuing to refer to Figure 1, the passivation layer 10 grows further on the sidewalls of the p-GaN layer 92 and the TiN protective layer 93, as well as on the barrier layer. As can be seen, the passivation layer 10 can improve the electrical performance of the reinforced HEMT device and protect the surface of the device.

[0044] Specifically, in reinforced HEMT devices, the density of states at the semiconductor surface and interface significantly affects the electrical performance of the device. The passivation layer 10 can reduce the density of surface and interface states. In the absence of the passivation layer, the surface and interface states capture or release carriers (electrons or holes), increasing carrier scattering, decreasing mobility, and significantly affecting the dynamic characteristics of the device. For example, in AlGaN / GaN HEMT devices, the passivation layer 10 can improve electron mobility and enhance performance such as transconductance and output current of the device by filling defects at the surface and interface and reducing unexpected capture and scattering of carriers at these locations.

[0045] Continuing to refer to Figure 1, finally, a reinforced HEMT device with a GaN insertion layer 91 is obtained by forming a gate 95 on the TiN protective layer 93 and a source electrode 7 and a drain electrode 6 on both sides of the p-GaN layer 92.

[0046] Referring to Figures 3 and 4, Figure 3 shows HEMT devices fabricated with GaN insertion layers of thickness 0 nm, 5 nm, and 10 nm, clearly demonstrating that the threshold voltage gradually increases as the insertion layer thickness decreases. Figure 4 shows the threshold voltages V of insertion layer devices with three different thicknesses. TH and on-resistance R ON The statistical results show that as the thickness of the insertion layer decreases, the on-resistance gradually increases, and therefore, by adjusting the thickness of the insertion layer, a balance between the threshold voltage and on-resistance can be achieved.

[0047] Referring to Figures 2a-2h and Figure 5, the present application further provides a method for manufacturing an enhanced HEMT device with a GaN insertion layer, which is used in the manufacture of the above-mentioned enhanced HEMT device with a GaN insertion layer and includes at least the following steps.

[0048] S10 provides the base layer 1.

[0049] Specifically, the base layer 1 may be any one of the following: sapphire base, Si base, SiC base, diamond base, glass base, ceramic base, or polymer base.

[0050] S20, a transition layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, a GaN insertion layer 91, and a p-GaN layer 92 are sequentially grown on the base layer 1.

[0051] Specifically, referring to Figure 2a, in this embodiment, organometallic chemical vapor deposition is employed to sequentially grow a transition layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, a GaN insertion layer 91, and a p-GaN layer 92 on the substrate layer 1.

[0052] In one specific example, organometallic chemical vapor deposition was employed, with a base layer 1, a transition layer 2 with a thickness of 10 nm to 500 nm, a high-resistance AlGaN buffer layer 3 with a thickness of 300 nm to 6000 nm, an intentionally undoped GaN channel layer 4 with a thickness of 50 nm to 500 nm, and an Al layer with a thickness of 10 nm to 40 nm. x Ga 1-x N barrier layer 5, intentionally undoped GaN insertion layer 91 with a thickness of 0.5nm to 40nm, and Mg doping concentration 10 18 cm -3 ~10 20 cm -3 The p-GaN layer 92 is grown sequentially, where the value range of X is 0.1 to 0.5.

[0053] S30, TiN metal and SiN medium are sequentially deposited on the upper surface of the p-GaN layer 92 to form a TiN protective layer 93 and a SiN protective layer 94.

[0054] Specifically, referring to Figure 2b, before subsequent processes such as etching of the p-GaN layer 92, the surface is first protected and a protective layer is formed to prevent surface contamination. For example, when creating an isolated structure by ion implantation, the surface of the reinforced HEMT device becomes rough due to collisions with high-energy ions, so a protective layer is necessary to absorb the surface collisions and prevent damage to the semiconductor surface.

[0055] In one specific embodiment, a TiN protective layer is formed by depositing TiN metal on the upper surface of the p-GaN layer 92 by physical vapor deposition, and a SiN protective layer 94 is formed by depositing a SiN medium on the upper surface of the TiN protective layer 93 by chemical vapor deposition.

[0056] In S40, an isolation structure 8 is formed on the upper surface of the SiN protective layer 94 and outside the device active region, where the isolation structure 8 penetrates the SiN protective layer 94, the TiN protective layer 93, the p-GaN layer 92, the GaN insertion layer 91, the barrier layer 5, the channel layer 4, and a portion of the buffer layer 3.

[0057] Specifically, in this embodiment, the isolation structure 8 may be either a mesa-type isolation structure or an ion implantation structure. For example, using an ion implantation structure as an example, referring to Figure 2c, a plasma implantation process is used to implant N ions into both ends of the upper surface of the passivation layer, forming an N ion implantation region. The implantation depth is controlled to a portion of the buffer layer to achieve isolation of the planar device.

[0058] In S50, a gate region is formed on the upper surface of the SiN protective layer 94, and the SiN protective layer 94, the TiN protective layer 93, the p-GaN layer 92, and the GaN insertion layer 91 outside the gate region are etched until the etching depth reaches the upper surface of the barrier layer 5.

[0059] Specifically, referring to Figure 2d, in this embodiment, photolithography development technology is used to form a gate region on the upper surface of the TiN protective layer 93 using a photoresist as a mask layer, and the SiN protective layer 94, TiN protective layer 93, p-GaN layer 92, and GaN insertion layer 91 outside the gate region are etched up to the upper surface of the barrier layer 5.

[0060] S60, The SiN protective layer 94 on the upper surface of the reinforced HEMT device is removed by a wet method.

[0061] Specifically, referring to Figure 2e, in this embodiment, an inorganic solution, such as hydrofluoric acid or BOE, is used to corrode the SiN protective layer 94 on the material surface, and the purpose of this step is mainly to remove the protective layer on the surface.

[0062] In step S70, a medium material is deposited on the upper surface of the barrier layer 5, the upper surface of the TiN protective layer 93, the sidewalls of the TiN protective layer 93, the sidewalls of the p-GaN layer 92, and the sidewalls of the GaN insertion layer 91 to form a passivation layer 10.

[0063] Specifically, referring to Figure 2f, in this embodiment, one of the following processes is employed: plasma-excited atomic layer deposition, atomic layer deposition, plasma-excited chemical vapor deposition, and reduced-pressure chemical vapor deposition. A medium material is deposited on the upper surface of the barrier layer 5, the upper surface of the TiN protective layer 93, the sidewall of the TiN protective layer 93, the sidewall 62 of the p-GaN layer, and the sidewall of the GaN insertion layer 91 to form a passivation layer 10 with a thickness range of 50 nm to 400 nm. Here, the medium material includes at least one of AlN, SiN, AlON, Al2O3, HfO2, ZrO2, Y2O3, and SiO2.

[0064] S80, a gate opening region is formed on the upper surface of the passivation layer 10 of the gate region, the gate opening region medium layer is etched up to the upper surface of the TiN protective layer 93, and a gate 95 is formed in the gate opening region with gate metal.

[0065] Specifically, referring to 2g, in this example, photolithography development is used to form a gate region on the TiN protective layer using a paste as a mask layer, and the gate metal is deposited using magnetron sputtering or electron beam deposition technology.

[0066] S90, a source electrode region and a drain electrode region are formed on the upper surface of the passivation layer, the passivation layer 10 of the source electrode region and the drain electrode region is etched, etching down to the upper surface of the barrier layer 5 to form a source electrode etching region and a drain electrode etching region, and metal is deposited in the source electrode etching region and the drain electrode etching region to form a source electrode 7 and a drain electrode 6.

[0067] Specifically, referring to Figure 2h, in this embodiment, the photolithography development technique uses a photoresist as a mask layer to form a drain electrode region and a source electrode region on the upper surface of the passivation layer 10 of adjacent isolation structures 8. The passivation layer 10 in the drain electrode region is etched, and drain metal is deposited on the barrier layer 5 to form a drain electrode 6. The passivation layer 10 in the source electrode region is etched, and source metal is deposited on the barrier layer 5 to form a source electrode 7. Finally, the entire device is annealed to achieve ohmic contact between the source electrode 7 and the drain electrode 6.

[0068] This application further provides a chip comprising the enhanced HEMT device described in any one of the above paragraphs.

[0069] This application further provides an electronic device, the electronic device including the chip described above.

[0070] In all examples illustrated and described herein, any specific values ​​should be interpreted as illustrative and not limiting; other examples of the exemplary embodiments may have different values.

[0071] Furthermore, since the same symbols and characters represent the same items in the following attached drawings, once an item is defined in one attached drawing, it is not necessary to define or interpret it further in subsequent attached drawings.

[0072] The above describes only specific embodiments of this application; however, the scope of protection of this application is not limited thereto. Any modifications or substitutions that a person skilled in the art could easily conceive of within the technical scope disclosed in this application should be included within the scope of protection of this application. [Explanation of Symbols]

[0073] 1. Substrate layer, 2. Transition layer, 3. Buffer layer, 4. Channel layer, 5. Barrier layer, 6. Drain electrode, 7. Source electrode, 8. Isolation structure, 91. GaN insertion layer, 92. p-GaN layer, 93. TiN protective layer, 94. SiN protective layer, 95. Gate, 10. Passivation layer.

Claims

1. A reinforced HEMT device with a GaN insertion layer, The aforementioned underlying layers are sequentially located in the transition layer, buffer layer, channel layer, and barrier layer above the aforementioned underlying layer, The barrier layer is sequentially positioned with a GaN insertion layer and an Mg-doped p-GaN layer, An isolation structure located on the side wall of the reinforced HEMT device, comprising an isolation structure that penetrates the barrier layer, the channel layer and a portion of the buffer layer, A TiN protective layer located in the aforementioned p-GaN layer, The passivation layer located on the sidewall of the p-GaN layer and the sidewall of the TiN protective layer, and in the barrier layer, A gate that penetrates the passivation layer and is located in the TiN protective layer, A source electrode located on one side of the p-GaN layer, which penetrates the passivation layer and is located in the barrier layer, A reinforced HEMT device with a GaN insertion layer, characterized by including a drain electrode located on the other side of the p-GaN layer, which penetrates the passivation layer and is located in the barrier layer.

2. The enhanced HEMT device according to claim 1, characterized in that the GaN insertion layer is made of undoped GaN and has a thickness range of 0.5 nm to 40 nm.

3. The thickness range of the p-GaN layer is 50 nm to 500 nm, and the Mg doping concentration range of the p-GaN layer is 10 １８ cm －３ ~10 ２０ cm －３ The enhanced HEMT device according to claim 1, characterized in that it is the enhanced HEMT device according to claim 1.

4. The thickness range of the transition layer is 10 nm to 500 nm, and the material of the transition layer includes at least one of AlN, AlGaN, and GaN; the thickness range of the buffer layer is 300 nm to 6000 nm, and the material of the buffer layer includes at least one of high-resistivity GaN and high-resistivity AlGaN; the channel layer is undoped GaN and has a thickness range of 50 nm to 500 nm; the thickness range of the barrier layer is 10 nm to 40 nm, and the material of the barrier layer is Al ｘ Ga １－ｘ The enhanced HEMT device according to claim 1, characterized in that it includes N, where the range of X is 0.1 to 0.

5.

5. The enhanced HEMT device according to claim 1, characterized in that the thickness range of the TiN protective layer is 5 nm to 300 nm.

6. The thickness range of the passivation layer is 50 nm to 400 nm, and the material of the passivation layer is at least one of AlN, SiN, AlON, Al ２ O ３ , HfO ２ , ZrO ２ , Y ２ O ３ , and SiO ２ . The enhanced HEMT device according to claim 1, characterized by this.

7. The enhanced HEMT device according to claim 1, characterized in that the isolation structure includes one of a mesa-type isolation structure and an ion implantation structure.

8. A chip characterized by including an enhanced HEMT device according to any one of claims 1 to 7.

9. An electronic device characterized by including the chip described in claim 8.

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