Local layout memory module

Abstract

This invention provides a memory module with a localized layout that allows for the placement of fewer memory chips while maintaining the existing circuit board design, and that can maintain normal operation under different operating mechanisms in different platform environments. [Solution] The local layout memory module 100 comprises a circuit board 1 having a multi-subchannel 11 and a plurality of chip mounting areas 12, a plurality of memory chips 2 provided in the first part 12a of the chip mounting area and not provided in the second part 12b of the chip mounting area, and a serial presence detector 3 that stores an mounting location identification code. The mounting location identification code is used to indicate the first part of the chip mounting area on which the memory chips are provided, is read by the host side to recognize the subchannel corresponding to the first part as an active subchannel, and avoids the execution of memory mapping to the subchannel corresponding to the second part. As a result, the local layout memory module can arrange fewer memory chips while maintaining the existing circuit board design, and can maintain normal operation under different operating mechanisms in different platform environments.

Description

Technical Field

[0001] The present invention relates to a memory module, and more particularly to a memory module with a local layout.

Background Art

[0002] As the demand for memory bandwidth and capacity in high-performance computing platforms and server systems continues to increase, DDR5 memory modules have become one of the current mainstream standards. In the DDR5 architecture, the memory module adopts a dual subchannel design, that is, by arranging two independent subchannels on a single module, it enables data splitting, parallel access, and training processing by the host-side memory controller.

[0003] In the current DDR5 memory market, it is the mainstream standard to adopt 8-bit wide memory chips. As a general configuration of the memory module, 8 8-bit wide memory chips are used, and each subchannel corresponds to 4 8-bit wide memory chips. On the other hand, without changing the standard of the DDR5 memory module, with the technological progress of the memory chips, it is possible to achieve the same capacity with a configuration of fewer chips. For example, it is possible to form the target capacity using 4 high-density 8-bit wide memory chips.

[0004] However, developing a dedicated circuit board to support memory chips with fewer chips and high density requires additional product development costs and introduction barriers. Therefore, a method of arranging memory chips with fewer chips while maintaining the existing circuit board design and maintaining normal operation under different operating mechanisms in different platform environments has become an important issue to be solved in the technical field.

Summary of the Invention

[0005] Therefore, the objective of this invention is to provide a memory module with a local layout that allows for the placement of fewer memory chips while maintaining the existing circuit board design, and that can maintain normal operation under different operating mechanisms in different platform environments.

[0006] The present invention provides a local layout memory module that includes: a circuit board having multiple subchannels and multiple chip mounting areas, wherein the multiple subchannels of the multiple subchannels correspond one-to-one with the multiple chip mounting areas; a plurality of memory chips provided in a first portion of the plurality of chip mounting areas but not in a second portion of the plurality of chip mounting areas, and the first portion and the second portion do not overlap with each other; and a serial presence detector provided on the circuit board that indicates the first portion of the plurality of chip mounting areas on which the plurality of memory chips are provided, is read by the host, recognizes at least one of the subchannels corresponding to the first portion of the plurality of chip mounting areas as an active subchannel, and stores an implementation location identification code that avoids performing memory mapping for at least one of the subchannels corresponding to the second portion of the plurality of chip mounting areas.

[0007] In one embodiment of the present invention, the multi-subchannel is a dual-subchannel having two subchannels, and the plurality of memory chips are provided in one of the chip mounting areas, while the other chip mounting area does not have memory chips, thus providing a memory module with a local layout.

[0008] In one embodiment of the present invention, the multi-subchannel has at least three subchannels, and at least one of the first portion and the second portion corresponds to at least two of the subchannels, providing a memory module with a local layout.

[0009] In one embodiment of the present invention, the implementation location identification code provides a memory module with a local layout characterized by causing the host side to disable the subchannel interleaved access function.

[0010] In one embodiment of the present invention, the implementation location identification code provides a locally laid-out memory module characterized in that the host side dynamically loads corresponding asymmetric signal training parameters based on the chip implementation area where the plurality of memory chips are provided.

[0011] In one embodiment of the present invention, the plurality of memory chips are four memory chips, and each memory chip has a bit width of 8 bits, providing a memory module with a local layout.

[0012] In one embodiment of the present invention, the serial presence detector provides a memory module with a local layout characterized by causing the host side to read a memory reference code corresponding to the implementation location identification code, and causing the host side to perform dynamic signal compensation for the plurality of subchannels when performing memory training. [Effects of the Invention]

[0013] According to the technical means employed in the local layout memory module of this invention, the present invention can realize a memory module configuration with fewer chips by utilizing existing standard circuit boards for arranging eight memory chips without developing a new dedicated circuit board, thereby contributing to a reduction in product development costs and implementation barriers. Furthermore, for platforms that read configuration information within a serial presence detector, the present invention enables the host to accurately recognize the active subchannels using the mounting location identification code within the serial presence detector. On the other hand, for platforms that perform hardware detection by bypassing the firmware settings of the serial presence detector, the present invention enables the host to accurately recognize the active subchannels by not providing the memory chips in the chip mounting area of ​​the second part. This avoids the execution of memory mapping or interleaved access to the unmounted side, improving system initialization compatibility. In addition, the present invention can load corresponding signal training parameters and memory reference codes according to asymmetric mounting configurations, improving signal integrity (SI), operational stability, and high-frequency operating margins. [Brief explanation of the drawing]

[0014] [Figure 1] This is a front view of a memory module with a local layout according to the first embodiment of the present invention. [Figure 2] This is a block diagram of a memory module with a local layout according to the first embodiment of the present invention. [Figure 3] This is a front view of a memory module with a local layout according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0015] The following describes embodiments for implementing the present invention with reference to Figures 1 to 3. This description is merely an example of one embodiment of the present invention and does not limit the embodiments of the present invention.

[0016] As shown in Figures 1 and 2, the local layout memory module 100 according to the first embodiment of the present invention comprises a circuit board 1, a plurality of memory chips 2, and a serial presence detector 3.

[0017] As shown in Figure 1, in the memory module 100 with a local layout according to the first embodiment of the present invention, the circuit board 1 has a multi-subchannel 11 and a plurality of chip mounting areas 12. The plurality of subchannels 11a and 11b of the multi-subchannel 11 correspond one-to-one with the plurality of chip mounting areas 12. Each chip mounting area 12 is provided with a plurality of chip pads (not shown).

[0018] In this embodiment, the multi-subchannel 11 is a dual subchannel, meaning it has two independent subchannels 11a and 11b, and is compatible with the current DDR5 architecture. Subchannel 11a corresponds to the left chip mounting area 12, and subchannel 11b corresponds to the right chip mounting area 12. In other embodiments, the number of subchannels in the multi-subchannel 11 may be at least three. For example, in the second embodiment shown in Figure 3, the circuit board 1 of the locally laid-out memory module 100a has four subchannels 11a, 11b, 11c, and 11d.

[0019] Multiple memory chips 2 are provided in the first portion 12a of the multiple chip mounting areas 12. No memory chips are provided in the second portion 12b of the multiple chip mounting areas 12. The first portion and the second portion do not overlap with each other. In this embodiment, as shown in Figure 1, the memory chips 2 are provided in one chip mounting area 12 (i.e., the first portion 12a), and no memory chips 2 are provided in the other chip mounting area 12 (i.e., the second portion 12b). In other words, it is an asymmetrical layout using half the number of memory chips 2 of the standard configuration. Specifically, there are four memory chips 2, and the bit width of each memory chip 2 is 8 bits, forming a 32-bit width in a single subchannel, satisfying the single subchannel data bus width requirement of the DDR5 standard.

[0020] The serial presence detect (SPD) device 3 is provided on the circuit board 1. The serial presence detect device 3 may be a serial presence detect chip or a serial presence detect hub (SPD hub) including a temperature sensor. A mounting location identification code is stored in a custom area of ​​the serial presence detect device 3. The mounting location identification code is used to indicate the first portion 12a of the chip mounting area 12 where the multiple memory chips 2 are provided. For example, by setting the mounting location identification code for the left side to (0x00) and the mounting location identification code for the right side to (0x01), it is clearly indicated which chip mounting area 12 is populated. Of course, the format and content of the mounting location identification code are not limited to this. As shown in Figure 2, the serial presence detect device 3 is signal-connected to the host side H. As a result, the serial presence detector 3 is read by the memory controller M of the host H, which recognizes at least one of the subchannels corresponding to the first portion of the plurality of chip mounting areas as an active subchannel, and avoids the execution of memory mapping to at least one of the subchannels corresponding to the second portion of the plurality of chip mounting areas.

[0021] In the DDR5 architecture, the default subchannel interleaving access improves the bandwidth by transferring data alternately between dual subchannels. However, when only a single subchannel is valid, the host H can disable the interleaving access function based on the implementation position identification code and operate the memory controller in single-channel mode, thereby avoiding a system crash caused by attempting interleaving access to an invalid subchannel.

[0022] Also, the implementation position identification code is used for the host side to dynamically load corresponding asymmetric signal training parameters based on the chip implementation area 12 where a plurality of the memory chips 2 are provided. Since the wiring on the unimplemented side is physically in an empty pad state, reflections, noise, or impedance mismatches may occur, which may affect the signal quality on the implemented side. The host side can load a set of training parameters optimized for an asymmetric configuration based on the identification code and compensate for the electrical characteristic deviations caused by unimplementation on one side, thereby greatly improving the signal integrity of the host side H. Thereby, the memory module 100 with the local layout of the present invention has excellent overclocking performance.

[0023] Furthermore, the serial presence detect device 3 causes the host side H to read a memory reference code (MRC) corresponding to the implementation position identification code, and when the host side H executes memory training, dynamic signal compensation is performed on the multi-subchannel 11.

[0024] As shown in FIG. 3, the memory module 100a with a local layout according to the second embodiment of the present invention is mainly different from the memory module 100 with a local layout according to the first embodiment in the following points. That is, the multi-subchannel 11 of the circuit board 1 has four subchannels 11a, 11b, 11c, and 11d, which respectively correspond to four chip mounting areas 12. In this configuration, the first part 12a is the two chip mounting areas 12 on both the left and right sides, and for example, two memory chips 2 are provided in each (determined by the bit width of the chip and the data bus width of the subchannel). The second part 12b is the two chip mounting areas 12 in the center and does not have memory chips 2. The mounting position identification code stored in the serial presence detect device 3 indicates the first part 12a of the chip mounting area 12 as the effective mounting position. Based on this, the host side recognizes the subchannels 11a and 11d as effective subchannels and invalidates the memory mapping for the subchannels 11b and 11c.

[0025] In this embodiment, the memory chips 2 are provided in two chip mounting areas 12, and half of the memory chips 2 in the standard configuration are arranged. However, in other embodiments, the memory chips 2 may be provided in one or three chip mounting areas 12.

[0026] In this embodiment, since the two subchannels 11a and 11d are effective, the host side H does not need to invalidate the interleaved access function based on the mounting position identification code. Instead, the interleaved access function is applied to the two specified subchannels 11a and 11d.

[0027] According to the configuration described above, the local layout memory module of this invention can achieve a memory module configuration with fewer chips by utilizing existing standard circuit boards 1 for arranging eight memory chips without developing a new dedicated circuit board, thereby contributing to a reduction in product development costs and implementation barriers. Furthermore, for platforms that read declaration information in the serial presence detector 3, this invention enables the host side H to accurately recognize the active subchannels using the mounting location identification code in the serial presence detector 3. On the other hand, for platforms that perform hardware detection by bypassing the firmware settings of the serial presence detector 3, this invention enables accurate recognition of the active subchannels even in this type of host side H by configuring the second portion 12b of the chip mounting area 12 without memory chips 2. This avoids the execution of memory mapping or interleaved access to the unmounted side, improving system initialization compatibility. In addition, this invention can load corresponding signal training parameters and memory reference codes according to asymmetric mounting configurations, improving signal integrity, operational stability, and high-frequency operating margins.

[0028] The above description merely describes preferred embodiments of the present invention. Further modifications can be made to this technology based on the claims and the above description, but these modifications are considered original to the present invention and are therefore included within the scope of its rights. [Explanation of Symbols]

[0029] 100 Local Layout Memory Modules 100a Local layout memory module 1 Circuit board 11 Multi-subchannel 11a subchannel 11b subchannel 11c subchannel 11d subchannel 12 Chip mounting area 12a Part 1 12b Part 2 2 memory chips 3. Serial presence detector H Host side M Memory Controller

Claims

1. A circuit board having multiple subchannels and multiple chip mounting areas, wherein multiple subchannels of the multiple subchannels correspond one-to-one with the multiple chip mounting areas, Multiple memory chips provided in the first portion of the plurality of chip mounting areas, not provided in the second portion of the plurality of chip mounting areas, and the first portion and the second portion do not overlap with each other. A serial presence detector provided on the circuit board, which indicates a first portion of the plurality of chip mounting areas on which the plurality of memory chips are provided, which is read by the host, recognizes at least one of the subchannels corresponding to the first portion of the plurality of chip mounting areas as an active subchannel, and stores an mounting location identification code that avoids performing memory mapping on at least one of the subchannels corresponding to the second portion of the plurality of chip mounting areas, A memory module with a local layout, characterized by comprising the following features.

2. The memory module with a local layout according to claim 1, wherein the multi-subchannel is a dual subchannel having two subchannels, and the plurality of memory chips are provided in one of the chip mounting areas, and no memory chips are provided in the other chip mounting area.

3. The local layout memory module according to claim 1, characterized in that the multi-subchannel has at least three subchannels, and at least one of the first portion and the second portion corresponds to at least two of the subchannels.

4. The local layout memory module according to claim 1, characterized in that the implementation location identification code causes the host side to disable the subchannel interleaved access function.

5. The local layout memory module according to claim 1, characterized in that the host dynamically loads corresponding asymmetric signal training parameters based on the chip mounting area where the plurality of memory chips are provided, using the aforementioned mounting location identification code.

6. The memory module with a local layout according to claim 2, characterized in that the plurality of memory chips are four memory chips, and each memory chip has a bit width of 8 bits.

7. The local layout memory module according to claim 1, characterized in that the serial presence detector causes the host to read a memory reference code corresponding to the implementation location identification code, and causes the host to perform dynamic signal compensation for the plurality of subchannels when performing memory training.

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