Imaging device and control method

Abstract

This image capturing device 100 comprises: a photoelectric conversion unit 1 which converts light into signal charges; a plurality of pixels 110 which each have a charge storage unit FD for accumulating signal charges and are arranged in a matrix; and a control circuit. Before receiving a trigger signal instructing the start of exposure, the control circuit performs a reset operation, which is for initializing the potential of the charge storage unit FD, on pixels belonging to at least one row among the plurality of pixels 110 in units of a row or in units of a plurality of rows in order. After receiving the trigger signal, the control circuit does not perform the reset operation on the pixels 110 belonging to at least one row among the plurality of pixels 110, and performs an exposure operation, for accumulating signal charges in the charge storage unit FD, on the plurality of pixels 110 at the same time.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device or the like that includes a photoelectric conversion unit that generates electric charges upon receiving irradiation with light. [Background technology]

[0002] In recent years, digital cameras have been widely used in various fields, such as video cameras, digital still cameras, security cameras, and vehicle-mounted cameras. These digital cameras use CCD (Charge Coupled Device) solid-state imaging elements or CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging elements, among which CMOS solid-state imaging elements have become mainstream. This is because CMOS solid-state imaging elements have many advantages, such as the fact that they can be manufactured using a general-purpose CMOS process, making it possible to use existing facilities and ensure a stable supply, and that peripheral circuits can be mixed on the same chip, allowing signals to be read out at high speed, resulting in higher speeds and higher resolution.

[0003] In CMOS solid-state imaging devices, for example, the CDS (Correlated Double Sampling) technique disclosed in Patent Document 1 is widely used.

[0004] Here, we will provide a detailed description of general CDS technology.

[0005] The pixel circuit shown in Fig. 2 of Patent Document 1 is composed of a PD (Photodetector) section that detects optical signals, an FD (Floating Diffusion) section that converts the charge generated in the PD section into a voltage signal and temporarily holds it, a TX transistor that transfers the charge signal from the PD section to the FD section, a RES transistor that resets the voltage of the FD section, an AMP transistor that amplifies the voltage signal of the FD section, and a SEL transistor that outputs the amplified signal. In general, the PD section is composed of a photodiode. The TX transistor is controlled by a control signal φTX, the RES transistor is controlled by a control signal φRST, and the SEL transistor is controlled by a control signal φSEL.

[0006] As shown in FIG. 6 of Patent Document 1, the pixel is driven as follows: first, φRST is set to high level to turn on the RES transistor, and the charge accumulated in the FD section is reset. Next, φRST is set to low level to turn off the RES transistor, and then φSEL is set to high level to turn on the SEL transistor, thereby outputting the reset voltage. At this time, the reset voltage contains reset noise called kTC noise, which causes temporal fluctuations. Then, φTX is set to high level to turn on the TX transistor, thereby transferring the signal charge accumulated in the PD section to the FD section. Then, φTX is set to low level to turn off the TX transistor, and the signal voltage is output. Since the signal voltage is a signal that has changed by the voltage corresponding to the signal charge accumulated in the reset voltage, the difference between the reset voltage (in other words, the reset charge) and the signal voltage (in other words, the reset charge + the signal charge) is taken in the subsequent circuit, and it is possible to cancel the kTC noise and detect only the voltage corresponding to the accumulated signal charge.

[0007] The above is CDS technology, which has the effect of significantly suppressing the reset noise (kTC noise) that occurs when resetting the pixel section. The suppression of reset noise by CDS technology is one of the factors that has led to CMOS-type solid-state imaging elements becoming mainstream. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2010-129705 A [Patent Document 2] JP 2008-28516 A [Patent Document 3] JP 2014-78870 A [Patent Document 4] JP 2001-177084 A [Patent Document 5] JP2010-258682 Public Relations Summary of the Invention [Problem to be solved by the invention]

[0009] In the field of imaging devices, there is a demand for an imaging device that can reduce the time lag from a trigger signal that instructs the start of exposure to the start of exposure while reducing noise. The present disclosure aims to provide an imaging device or the like that can reduce the time lag from a trigger signal that instructs the start of exposure to the start of exposure while reducing noise. [Means for solving the problem]

[0010] An imaging device according to one embodiment of the present disclosure includes a plurality of pixels arranged in a matrix, each of which includes a photoelectric conversion unit that converts light into a signal charge and a charge accumulation unit that accumulates the signal charge, and a control circuit, wherein the control circuit causes pixels belonging to at least one row of the plurality of pixels to perform a reset operation that initializes the potential of the charge accumulation unit in sequence, row by row or in units of multiple rows, before receiving a trigger signal that instructs the start of exposure, and after receiving the trigger signal, causes the plurality of pixels to simultaneously perform an exposure operation that accumulates the signal charge in the charge accumulation unit, without causing the pixels belonging to at least one row of the plurality of pixels to perform the reset operation.

[0011] A control method according to one embodiment of the present disclosure is a control method for an imaging device having a plurality of pixels arranged in a matrix, each of which includes a photoelectric conversion unit that converts light into a signal charge and a charge accumulation unit that accumulates the signal charge, wherein before a trigger signal instructing the start of exposure is received, a reset operation that initializes the potential of the charge accumulation unit is performed on pixels belonging to at least one row of the plurality of pixels in sequence, row by row or in units of multiple rows, and after receiving the trigger signal, an exposure operation that accumulates the signal charge in the charge accumulation unit is performed simultaneously on the plurality of pixels without performing the reset operation on pixels belonging to at least one row of the plurality of pixels. Effect of the Invention

[0012] According to an image capturing apparatus according to an aspect of the present disclosure, it is possible to reduce the time lag from a trigger signal instructing the start of exposure to the start of exposure while reducing noise. [Brief description of the drawings]

[0013] [Figure 1A] FIG. 1A is a diagram illustrating an exemplary circuit configuration of an imaging device according to the first embodiment. [Figure 1B] FIG. 1B is a diagram illustrating an exemplary circuit configuration of a pixel of the imaging device according to the first embodiment. [Figure 1C] FIG. 1C is a diagram illustrating another exemplary circuit configuration of a pixel of the imaging device according to the first embodiment. In FIG. [Diagram 2] FIG. 2 is a cross-sectional view illustrating a schematic device structure of a pixel of the imaging device according to the first embodiment. [Diagram 3] FIG. 3 is a diagram illustrating another exemplary circuit configuration of a pixel of the imaging device according to the first embodiment. In FIG. [Figure 4] FIG. 4 is a diagram showing an example of the photoelectric conversion characteristic of the organic photoelectric conversion film. [Figure 5A] FIG. 5A is a timing chart for explaining an example of the operation of an imaging device according to a comparative example. [Figure 5B]FIG. 5B is a flowchart showing an example of the operation of the imaging device according to the comparative example. [Figure 5C] FIG. 5C is a flowchart showing another example of the operation of the imaging device according to the comparative example. [Figure 6A] FIG. 6A is a timing chart for explaining an example of the operation of the imaging device according to the first embodiment. [Figure 6B] FIG. 6B is a flowchart showing an example of the operation of the imaging device according to the first embodiment. [Figure 6C] FIG. 6C is a timing chart for explaining another example of the operation of the imaging device according to the first embodiment. [Figure 6D] FIG. 6D is a flowchart showing another example of the operation of the imaging device according to the first embodiment. [Figure 7] FIG. 7 is a flowchart showing yet another example of the operation of the imaging device according to the first embodiment. [Figure 8] FIG. 8 is a schematic diagram illustrating an example of a configuration of an imaging device according to the second embodiment. [Figure 9] FIG. 9 is a block diagram showing an example of a configuration of a camera system according to the third embodiment. As shown in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] (Foundational knowledge that led to this disclosure) The CDS technology mentioned above is premised on perfect transfer when transferring the signal charge generated in the PD section that detects the optical signal to the FD section that converts it into a voltage signal. Achieving perfect transfer poses challenges such as the complexity of the process and increased manufacturing costs.

[0015] Furthermore, as disclosed in Patent Document 2, for example, a solid-state imaging element having pixels with a structure that realizes a global shutter has been proposed recently as a solid-state imaging element that captures images of objects moving at high speed without distortion.

[0016] In the solid-state imaging device disclosed in Patent Document 2, the charges of the PD section of all pixels are transferred to the FD section all at once, and then read out row by row in sequence, so that the CDS technique of reading out the reset voltage before reading out the signal voltage of the FD section cannot be applied. Therefore, after reading out the signal voltage of the FD section, the FD section is reset, the reset voltage is read out, and the difference between the signal voltage and the reset voltage is taken. However, since there is no correlation between the reset noise contained in the signal voltage and the reset noise contained in the reset voltage, the reset noise cannot be removed, and there is a problem that the random noise becomes larger compared to the readout using the above-mentioned CDS technique.

[0017] In addition, in recent years, the area per pixel has been reduced due to an increase in the number of pixels, and as a solid-state imaging element that solves the problem of reduced sensitivity caused by a reduction in the area of ​​the PD section, an organic CMOS sensor using an organic photoelectric conversion film in the PD section has been proposed, as disclosed in Patent Document 3. This organic CMOS sensor provides an organic photoelectric conversion film, which is the light receiving section, above the readout circuit, so that even if the pixel size is reduced, the area of ​​the light receiving section can be made large, thereby achieving high sensitivity.

[0018] On the other hand, sensors using photoelectric conversion films such as organic CMOS sensors have a structure in which the PD section and the semiconductor layer are electrically connected by metal wiring, so the signal charge cannot be completely transferred. Therefore, in general, the PD section and the FD section are electrically connected to read out the signal charge of the PD section, preventing the occurrence of incomplete transfer noise and residual images.

[0019] Therefore, the signal voltage of the FD section is read out while the voltage changed due to the charge accumulated during exposure is detected by the FD section, and then the reset voltage is read out while the FD section is reset, to obtain the difference between the signal voltage and the reset voltage. However, since there is no correlation between the reset noise contained in the signal voltage and the reset noise contained in the reset voltage, the reset noise cannot be removed, and there is an issue that the random noise is larger than when reading using the CDS technology mentioned above.

[0020] Thus, although CDS technology is effective in suppressing reset noise, it increases manufacturing costs due to the complexity of the process, and furthermore has issues such as being unable to be applied to CMOS-type solid-state imaging elements, which have a structure that is effective in terms of functionality and performance.

[0021] Furthermore, for example, a technique for removing reset noise for each row without using the CDS technique, as disclosed in Patent Document 4, has also been proposed.

[0022] However, when using a method of removing reset noise row by row, particularly in the specifications of industrial cameras, professional broadcasting cameras, medical cameras, etc., when an exposure start command signal is received from an external trigger signal, particularly a command signal to start simultaneous exposure of at least two pixels or to start full-surface exposure, it takes time to remove the reset noise of each pixel row by row before exposure. As a result, a time delay of several milliseconds to several tens of milliseconds occurs between the issuance of the trigger signal and the start of exposure, which causes problems such as not being able to capture what is to be captured and not being able to perform high-speed inspection. The trigger signal is, for example, a signal issued in accordance with the operation of another machine, or a signal issued when a shutter button or the like is pressed by a person.

[0023] The solid-state imaging device disclosed in Patent Document 5 is configured to enable high-speed exposure start by providing two trigger signals in advance, but this complicates signal control.

[0024] In view of the above circumstances, an object of the present disclosure is to provide an imaging apparatus including a solid-state imaging element that can appropriately remove reset noise and can start exposure quickly in response to an external trigger signal.

[0025] An outline of one aspect of the present disclosure is as follows.

[0026] An imaging device according to one embodiment of the present disclosure includes a plurality of pixels arranged in a matrix, each of which includes a photoelectric conversion unit that converts light into a signal charge and a charge accumulation unit that accumulates the signal charge, and a control circuit, wherein the control circuit causes pixels belonging to at least one row of the plurality of pixels to perform a reset operation that initializes the potential of the charge accumulation unit in sequence, row by row or in units of multiple rows, before receiving a trigger signal that instructs the start of exposure, and after receiving the trigger signal, causes the plurality of pixels to simultaneously perform an exposure operation that accumulates the signal charge in the charge accumulation unit, without causing the pixels belonging to at least one row of the plurality of pixels to perform the reset operation.

[0027] As a result, after receiving the trigger signal, the control circuit causes the pixels belonging to at least one row to perform the exposure operation without performing the reset operation. Therefore, the time from receiving the trigger signal to the exposure operation is shortened compared to the case where the reset operation is performed on all pixels after receiving the trigger signal. Furthermore, since the reset operation is performed on the pixels belonging to at least one row before receiving the trigger signal, the potential is initialized before the accumulation of the signal charge, and especially when the reset operation is performed together with the suppression of the reset noise, the noise in the signal charge of the pixels belonging to at least one row is reduced. Therefore, the imaging device according to this embodiment can reduce the time lag from the trigger signal instructing the start of exposure to the start of exposure in a state where noise is reduced.

[0028] Furthermore, for example, the control circuit may cause all pixels of the plurality of pixels to perform the reset operation in sequence, row by row or in units of multiple rows, before receiving the trigger signal.

[0029] As a result, a reset operation is performed on multiple pixels belonging to all rows before the trigger signal is received, so that the potential is initialized before the accumulation of signal charge, and noise in the signal charge of all multiple pixels is reduced, particularly when the reset operation is performed in conjunction with suppressing reset noise.

[0030] Furthermore, for example, the control circuit may cause pixels belonging to at least one row among the plurality of pixels to perform the reset operation a plurality of times before receiving the trigger signal.

[0031] As a result, the pixels belonging to at least one row are reset multiple times before the control circuit receives a trigger signal. Therefore, in a pixel that is reset multiple times, after the reset operation is performed once, the charge accumulated in the charge storage section due to dark current or the like is initialized again by the reset operation. Therefore, since the noise caused by the charge accumulated due to dark current or the like is reduced, the imaging device according to this embodiment can further reduce noise.

[0032] Furthermore, for example, the control circuit may repeatedly perform the reset operation on the plurality of pixels in sequence on a row basis or on a group of multiple rows basis until the trigger signal is received.

[0033] As a result, the reset operation is repeatedly performed on the multiple pixels until the control circuit receives a trigger signal. Therefore, after the reset operation is performed, the charge accumulated in the charge storage section due to dark current or the like is repeatedly initialized by the reset operation. Therefore, noise caused by the charge accumulated due to dark current or the like is reduced, so that the imaging device according to this embodiment can further reduce noise.

[0034] Furthermore, for example, after the exposure operation, the control circuit may cause the multiple pixels to perform a read operation of outputting a signal corresponding to the signal charge accumulated in the charge accumulation section, in sequence, row by row or in units of multiple rows, starting from the row in which the reset operation is started.

[0035] This allows the reset operation and the read operation to start on a common row, which makes it possible to suppress the complexity of the control circuit. Also, since the read data is read out continuously in time from the upper row to the lower row or from the lower row to the upper row, the continuity of the obtained image is maintained.

[0036] Also, for example, the control circuit may cause the plurality of pixels to perform the reset operation in sequence, row by row or in multiple row units, up to a row different from the row on which the reset operation was started, and after the exposure operation, cause the plurality of pixels to perform a read operation, in sequence, row by row or in multiple row units, starting from the row next in order to the row on which the reset operation was completed, to output a signal corresponding to the signal charge accumulated in the charge accumulation section.

[0037] This makes the time from the reset operation to the read operation for each row approximately the same, so that the difference between the amount of charge accumulated in the charge storage section due to dark current or the like after the reset operation between each row is small, thereby reducing the difference in noise between multiple pixels.

[0038] Furthermore, for example, each of the plurality of pixels may include a feedback circuit that negatively feeds back the potential of the charge storage portion in the reset operation.

[0039] This reduces reset noise that occurs during the reset operation, and therefore the imaging device according to this aspect can further reduce noise.

[0040] Furthermore, for example, each of the plurality of pixels may include a circuit that suppresses reset noise that occurs in the reset operation.

[0041] This reduces reset noise that occurs during the reset operation, and therefore the imaging device according to this aspect can further reduce noise.

[0042] Also, for example, the device may further include a voltage supply circuit, and the photoelectric conversion unit may include a counter electrode electrically connected to the voltage supply circuit, a pixel electrode electrically connected to the charge storage unit, and a photoelectric conversion layer located between the counter electrode and the pixel electrode, and the control circuit may cause the voltage supply circuit to apply a voltage to the counter electrode to form an electric field in the photoelectric conversion layer, thereby causing the multiple pixels to perform the exposure operation.

[0043] This makes it possible to reduce the time lag from the trigger signal instructing the start of exposure to the start of exposure in a stacked imaging device in which a reset operation is effective for each row or for each set of rows, while reducing noise. In addition, since the exposure operation is performed by applying a voltage to the opposing electrodes, the circuitry can be made less complicated.

[0044] Furthermore, a control method according to one aspect of the present disclosure is a control method for an imaging device having a plurality of pixels arranged in a matrix, each of which includes a photoelectric conversion unit that converts light into a signal charge and a charge accumulation unit that accumulates the signal charge, wherein before a trigger signal instructing the start of exposure is received, a reset operation that initializes the potential of the charge accumulation unit is performed on pixels belonging to at least one row of the plurality of pixels in sequence, row by row or in units of multiple rows, and after receiving the trigger signal, an exposure operation that accumulates the signal charge in the charge accumulation unit is performed simultaneously on the plurality of pixels without performing the reset operation on pixels belonging to at least one row of the plurality of pixels.

[0045] As a result, after receiving the trigger signal, the exposure operation is performed on a plurality of pixels belonging to at least one row without performing a reset operation. Therefore, the time from receiving the trigger signal to the exposure operation is shortened compared to the case where the reset operation is performed on all pixels after receiving the trigger signal. In addition, since the reset operation is performed on a plurality of pixels belonging to all rows before receiving the trigger signal, the potential is initialized before the accumulation of the signal charge, and noise in the signal charge is reduced, especially when the reset operation is performed together with the suppression of the reset noise. Therefore, the control method according to this embodiment can reduce the time lag from the trigger signal instructing the start of exposure to the start of exposure while reducing noise.

[0046] Hereinafter, an embodiment of an imaging device and the like according to the present disclosure will be described with reference to the drawings. Note that the present disclosure will be described with reference to the following embodiments and the accompanying drawings, but these are for illustrative purposes only and are not intended to limit the present disclosure to these embodiments.

[0047] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, the arrangement and connection of the components, steps, and the order of steps shown in the following embodiments are merely examples and are not intended to limit the present disclosure.

[0048] In addition, in this specification, elements that are essential for the operation of an imaging device or are effective in improving characteristics, but are unnecessary for the explanation of the present disclosure, are omitted. Furthermore, each drawing is merely a diagram showing a concept, and scale, shape, etc. are not taken into consideration at all. Therefore, for example, the scale, etc., of each drawing does not necessarily match. Furthermore, in each drawing, substantially the same configuration is given the same reference numeral, and duplicate explanations are omitted or simplified.

[0049] Furthermore, in this specification, terms indicating relationships between elements, such as "equal," terms indicating the shapes of elements, such as "square" or "circle," and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0050] In this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. In addition, the terms "above" and "below" are applied not only to the case where two components are arranged with a gap between them and another component exists between the two components, but also to the case where two components are arranged closely together and are in contact with each other.

[0051] (Embodiment 1) First, the structure of an imaging device 100 according to the present embodiment will be described with reference to FIGS. 1A to 3. FIG.

[0052] [Structure of imaging device] 1A is a diagram illustrating an exemplary circuit configuration of an imaging device 100 according to the present embodiment. As an example, the imaging device 100 is a stacked type imaging element, and has a photoelectric conversion layer stacked on a semiconductor substrate. The imaging device 100 includes a plurality of pixels 110 and a peripheral circuit. The peripheral circuit includes a control circuit that controls the operation of the plurality of pixels 110. The control circuit receives a trigger signal from an external device, and causes the plurality of pixels 110 to perform an exposure operation.

[0053] The pixels 110 are arranged two-dimensionally to form a photosensitive region, or a pixel region. The pixels 110 may be arranged one-dimensionally. In this case, the imaging device 100 is a line sensor.

[0054] In the illustrated example, the pixels 110 are arranged in a row direction and a column direction. In this specification, the row direction and the column direction refer to the directions in which the rows and columns extend, respectively. That is, the vertical direction is the column direction, and the horizontal direction is the row direction.

[0055] Each of the pixels 110 is connected to a power supply line 120. A predetermined power supply voltage is supplied to each pixel 110 via the power supply line 120. As shown in the figure, the imaging device 100 has an accumulation control line 130 that applies the same constant voltage to all photoelectric conversion layers that photoelectrically convert incident light. However, when performing separate control such as suppressing fluctuations, the voltage may be divided and applied to several parts.

[0056] The peripheral circuits include a voltage supply circuit 140, a vertical scanning circuit 141, a column signal processing circuit 142, a horizontal signal readout circuit 143, and a constant current source 144. The vertical scanning circuit 141 is also called a "row scanning circuit," and the horizontal signal readout circuit 143 is also called a "column scanning circuit." The column signal processing circuit 142 and the constant current source 144 may be arranged for each column of the pixels 110 arranged two-dimensionally.

[0057] An example of the configuration of the peripheral circuit will be described below.

[0058] The voltage supply circuit 140 is connected to the accumulation control line 130. When the imaging device 100 is in operation, the voltage supply circuit 140 applies a predetermined bias voltage to the counter electrode 1b (described in detail later) of the pixel 110 via the accumulation control line 130. The operation of the voltage supply circuit 140 is controlled by a control circuit.

[0059] The vertical scanning circuit 141 is connected to a selection control signal line CON7 and an amplification control signal line CON3. The amplification control signal line CON3 is also called a "band control signal line", and the selection control signal line CON7 is also called an "address signal line". The vertical scanning circuit 141 is a part of a control circuit that controls the operation of the multiple pixels 110. The vertical scanning circuit 141 applies a predetermined voltage to the selection control signal line CON7 to select the multiple pixels 110 arranged in each row on a row-by-row basis. This causes the signal voltage of the selected pixel 110 to be read out and the pixel electrode to be reset, which will be described later.

[0060] The pixels 110 arranged in each column are electrically connected to a column signal processing circuit 142 via a signal readout signal line 170 corresponding to each column. The signal readout signal line 170 is also called a "vertical signal line." The column signal processing circuit 142 performs noise suppression signal processing represented by correlated double sampling and analog-to-digital conversion (AD conversion), etc. A horizontal signal readout circuit 143 is electrically connected to the multiple column signal processing circuits 142 provided corresponding to the columns of the pixels 110A. The horizontal signal readout circuit 143 sequentially reads out signals from the multiple column signal processing circuits 142 to a horizontal common signal line 180.

[0061] Next, an example of the circuit configuration of the pixel 110 will be described.

[0062] 1B is a diagram illustrating a schematic diagram of an exemplary circuit configuration of a pixel 110 of an imaging device 100 according to the present embodiment. The pixel 110 includes a photoelectric conversion unit 1, an amplifier 2, a band control unit 3, a charge accumulation unit FD, and an output selection unit 5. The photoelectric conversion unit 1 detects light and converts the light into a signal charge. The charge accumulation unit FD accumulates the signal charge generated by the photoelectric conversion unit 1. The amplifier 2, the band control unit 3, the charge accumulation unit FD, and the output selection unit 5 form a readout circuit 50.

[0063] The photoelectric conversion unit 1 converts light into a signal charge. The readout circuit 50 reads out the signal charge generated by the photoelectric conversion unit 1. The photoelectric conversion unit 1 includes, for example, a pixel electrode 1a, a counter electrode 1b, and a photoelectric conversion layer 1c sandwiched between the pixel electrode 1a and the counter electrode 1b. The pixel electrode 1a is electrically connected to the charge storage unit FD. The counter electrode 1b is connected to an accumulation control line 130 shown in FIG. 1A, and is electrically connected to a voltage supply circuit 140 via the accumulation control line 130. For example, by applying a reference voltage Vp to the counter electrode 1b and connecting one end of a node forming the charge storage unit FD to the pixel electrode 1a, the signal charge generated by the photoelectric conversion layer 1c of the photoelectric conversion unit 1 can be accumulated in the charge storage unit FD.

[0064] The charge accumulation unit FD is connected to the photoelectric conversion unit 1 by a wiring layer. The charge accumulation unit FD accumulates signal charges generated by the photoelectric conversion unit 1. The charge accumulation unit FD is further connected to an input of the amplifier 2. The amplifier 2 amplifies a signal corresponding to the signal charges accumulated in the charge accumulation unit FD, and outputs the amplified signal to the band control unit 3 and the output selection unit 5.

[0065] The amplifier 2 and the band control section 3 form a feedback circuit 30 via the charge storage section FD. The band control section 3 includes a band control circuit 13. At least three different voltages are supplied to the band control circuit 13 from the voltage control circuit. By being supplied with such voltages, the band control circuit 13 has a band control function. The voltage control circuit is, for example, a part of the vertical scanning circuit 141. The band control circuit 13 applies band limitation to the output signal of the amplifier 2 and outputs it to the charge storage section FD. In the feedback circuit 30, the signal read out from the charge storage section FD is amplified by the amplifier 2, applied band limitation by the band control circuit 13, and fed back to the charge storage section FD.

[0066] The feedback circuit 30 negatively feeds back the signal of the photoelectric conversion unit 1 to the charge accumulation unit FD via the amplification transistor 42. In other words, the feedback circuit 30 is a circuit that negatively feeds back the potential of the charge accumulation unit FD in a reset operation described later.

[0067] The amplifier 2 has an amplifying transistor 42 and a switching circuit 20 including a first switch element 11 and a second switch element 12. The transistor in the readout circuit 50 is, for example, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The electrical connection relationship of the readout circuit 50 will be described below. Note that the amplifier 2 of the pixel 110 may not have the switching circuit 20, and the switching circuit 20 may be included in the peripheral circuit.

[0068] The charge accumulation unit FD is connected to the gate of the amplifying transistor 42. The band control unit 3 includes a band control transistor 46. The output selection unit 5 includes a selection transistor 44. One of the source and drain of the amplifying transistor 42 is connected to one of the source and drain of the band control transistor 46 and one of the source and drain of the selection transistor 44. The other of the source and drain of the band control transistor 46 is connected to the charge accumulation unit FD. An RC filter circuit is formed by the band control transistor 46 and a capacitance component parasitic to the charge accumulation unit FD.

[0069] An amplification control signal line CON3 is connected to the gate of the band control transistor 46. The state of the band control transistor 46 is determined by the voltage of the amplification control signal line CON3. For example, when the voltage of the amplification control signal line CON3 is at a high level, the band control transistor 46 is turned on. As a result, a feedback path is formed by the charge storage unit FD, the amplification transistor 42, and the band control transistor 46.

[0070] When the voltage of the amplification control signal line CON3 becomes lower, the resistance component of the band control transistor 46 becomes larger. Therefore, the band of the band control transistor 46 becomes narrower, and the frequency range of the feedback signal becomes narrower. When the voltage of the amplification control signal line CON3 becomes even lower, that is, low level, the band control transistor 46 turns off. As a result, no feedback path is formed.

[0071] The other of the source and drain of the selection transistor 44 is connected to a signal readout signal line 170. The gate of the selection transistor 44 is controlled by a selection control signal line CON7. The state of the selection transistor 44 is determined by the voltage of the selection control signal line CON7. For example, when the voltage of the selection control signal line CON7 is at a high level, the selection transistor 44 is turned on. As a result, the amplification transistor 42 and the signal readout signal line 170 are electrically connected. When the voltage of the selection control signal line CON7 is at a low level, the selection transistor 44 is turned off. As a result, the amplification transistor 42 and the signal readout signal line 170 are electrically isolated from each other.

[0072] The switching circuit 20 is connected to the other of the source and drain of the amplifying transistor 42. Specifically, the other of the source and drain of the amplifying transistor 42 is connected to a first voltage source VA1 via a first switch element 11. The other of the source and drain of the amplifying transistor 42 is also connected to a second voltage source VA2 via a second switch element 12. By controlling the switching circuit 20 with control signals V1 and V2, the voltage applied to the other of the source and drain of the amplifying transistor 42 is switched to a voltage Va1 or a voltage Va2. The voltage Va1 of the first voltage source VA1 is, for example, a ground voltage GND. The voltage Va2 of the second voltage source VA2 is, for example, a power supply voltage VDD. The switching circuit 20 may be provided for each pixel, or may be shared by a plurality of pixels in order to reduce the number of elements per pixel.

[0073] The output selection unit 5 is connected to a signal readout signal line 170. The signal readout signal line 170 is shared by at least two pixels. The signal amplified by the amplifier 2 is output to the signal readout signal line 170 via the output selection unit 5.

[0074] A constant current source 144 is connected to the signal readout signal line 170. When the selection transistor 44 is on, a source follower circuit is formed by the selection transistor 44, the amplification transistor 42, and the constant current source 144. A signal corresponding to the signal charge accumulated in the charge accumulation unit FD is output to the signal readout signal line 170 and read out to the outside. The constant current source 144 may be provided for each pixel, or may be shared by multiple pixels in order to reduce the number of elements per pixel.

[0075] The photoelectric conversion unit 1 is not limited to such a configuration, and may be an element having other photoelectric conversion functions, such as a photodiode. FIG. 1C is a diagram showing an exemplary circuit configuration of a pixel 115 of an imaging device according to the present embodiment. The pixel 115 shown in FIG. 1C is different from the pixel 110 described above in that it includes a photoelectric conversion unit 1d instead of the photoelectric conversion unit 1. The configuration of the pixel 115 other than the photoelectric conversion unit 1d is the same as that of the pixel 110. As shown in FIG. 1C, the pixel 115 includes a photoelectric conversion unit 1d configured by a photodiode. For example, a reference voltage Vp is applied to one end of the photoelectric conversion unit 1d, and one end of a node forming the charge storage unit FD is connected to the other end of the photoelectric conversion unit 1d, so that the signal charge generated by the photoelectric conversion unit 1d can be stored in the charge storage unit FD.

[0076] Next, the pixel structure of the imaging device 100 according to the present embodiment will be described.

[0077] FIG. 2 is a cross-sectional view that shows a schematic device structure of a pixel 110 of an imaging device 100 according to the present embodiment. In the configuration shown in FIG. 2, the pixel 110 includes a semiconductor substrate 62 that supports a photoelectric conversion unit 1. The semiconductor substrate 62 is, for example, a silicon substrate. As shown in FIG. 2, the photoelectric conversion unit 1 is disposed above the semiconductor substrate 62. In this example, interlayer insulating layers 63A, 63B, and 63C are laminated on the semiconductor substrate 62, and a laminate of a pixel electrode 1a, a photoelectric conversion layer 1c, and a counter electrode 1b is disposed on the interlayer insulating layer 63C. The pixel electrodes 1a are partitioned for each pixel, and the pixel electrodes 1a are formed between two adjacent pixels 110 in a spatially separated manner, so that the two adjacent pixel electrodes 1a are electrically separated. The photoelectric conversion layer 1c and the counter electrode 1b may be formed to span a plurality of pixels 110. The signal charge generated by the photoelectric conversion unit 1 is accumulated in a charge accumulation node 41 between the gate of the amplification transistor 42 and the photoelectric conversion unit 1. The charge accumulation node 41 is an example of the charge accumulation unit FD described above.

[0078] As shown in FIG. 2, the photoelectric conversion unit 1 includes, for example, a pixel electrode 1a, a counter electrode 1b facing the pixel electrode 1a, and a photoelectric conversion layer 1c located between the pixel electrode 1a and the counter electrode 1b.

[0079] The pixel electrode 1a is an electrode for reading out signal charges generated in the photoelectric conversion unit 1. At least one pixel electrode 1a exists for each pixel 110. The pixel electrode 1a is electrically connected to the gate electrode 42e of the amplification transistor 42 and the impurity region 62d.

[0080] The pixel electrode 1a is formed using a conductive material, such as a metal such as aluminum or copper, a metal nitride, or polysilicon doped with impurities to be made conductive.

[0081] The counter electrode 1b is, for example, a transparent electrode made of a transparent conductive material. The counter electrode 1b is disposed on the light-incident side of the photoelectric conversion unit 1. Therefore, light that has passed through the counter electrode 1b is incident on the photoelectric conversion layer 1c.

[0082] In this specification, "transparent" means that at least a part of the light in the wavelength range to be detected is transmitted, and it is not essential that the light is transmitted over the entire wavelength range of visible light.

[0083] The counter electrode 1b is formed using, for example, a transparent conducting oxide (TCO) such as indium tin oxide (ITO).

[0084] The photoelectric conversion layer 1c receives incident light and generates hole-electron pairs. The material of the photoelectric conversion layer 1c is, for example, a semiconducting inorganic material or a semiconducting organic material. The photoelectric conversion layer 1c is, for example, an organic photoelectric conversion film.

[0085] On a semiconductor substrate 62, an amplifier transistor 42, a selection transistor 44, and a band control transistor 46 are formed.

[0086] The amplifier transistor 42 includes impurity regions 62a and 62b formed in a semiconductor substrate 62, a gate insulating layer 42g located on the semiconductor substrate 62, and a gate electrode 42e located on the gate insulating layer 42g. The impurity regions 62a and 62b function as the drain or source of the amplifier transistor 42. The impurity regions 62a and 62b, as well as impurity regions 62c, 62d, and 62e described below, are, for example, n-type impurity regions.

[0087] The selection transistor 44 includes impurity regions 62a and 62c formed in the semiconductor substrate 62, a gate insulating layer 44g located on the semiconductor substrate 62, and a gate electrode 44e located on the gate insulating layer 44g. The impurity regions 62a and 62c function as the drain or source of the selection transistor 44. In this example, the amplification transistor 42 and the selection transistor 44 share the impurity region 62a, so that the source (or drain) of the amplification transistor 42 and the drain (or source) of the selection transistor 44 are electrically connected to each other.

[0088] The band control transistor 46 includes impurity regions 62d and 62e formed in the semiconductor substrate 62, a gate insulating layer 46g located on the semiconductor substrate 62, and a gate electrode 46e located on the gate insulating layer 46g. The impurity regions 62d and 62e function as the drain and source of the band control transistor 46.

[0089] In the semiconductor substrate 62, an element isolation region 62s is provided between adjacent pixels 110 and between the amplification transistor 42 and the band control transistor 46. The element isolation region 62s electrically isolates the adjacent pixels 110. Furthermore, by providing the element isolation region 62s between the adjacent pixels 110, leakage of signal charges accumulated in the charge accumulation node 41 is suppressed.

[0090] In the interlayer insulating layer 63A, a contact plug 65A connected to the impurity region 62d of the band control transistor 46, a contact plug 65B connected to the gate electrode 42e of the amplifying transistor 42, and a wiring 66A connecting the contact plug 65A and the contact plug 65B are formed. As a result, the impurity region 62d (e.g., the drain) of the band control transistor 46 is electrically connected to the gate electrode 42e of the amplifying transistor 42. In the configuration illustrated in FIG. 2, a plug 67A and a wiring 68A are further formed in the interlayer insulating layer 63A. In addition, a plug 67B and a wiring 68B are formed in the interlayer insulating layer 63B, and a plug 67C is formed in the interlayer insulating layer 63C, so that the wiring 66A and the pixel electrode 1a are electrically connected. The contact plug 65A, the contact plug 65B, the wiring 66A, the plug 67A, the wiring 68A, the plug 67B, the wiring 68B, and the plug 67C are typically made of metal.

[0091] 2, a color filter 72 is disposed on the counter electrode 1b. A microlens 74 is disposed on the color filter 72. Although not shown, a protective layer for protecting the photoelectric conversion unit 1 may be disposed between the color filter 72 and the microlens 74. The material of the protective layer is, for example, SiON or AlO.

[0092] The imaging device 100 as described above can be manufactured using a general semiconductor manufacturing process. In particular, when a silicon substrate is used as the semiconductor substrate 62, the imaging device 100 can be manufactured by utilizing various silicon semiconductor processes.

[0093] Here, the photoelectric conversion operation will be described. Light input from the outside is collected by the microlens 74 of each pixel 110, and only light of a desired wavelength is transmitted by the color filter 72, and then enters the photoelectric conversion unit 1. The photoelectric conversion unit 1 converts the light into electric charges. When a voltage is applied between the counter electrode 1b and the pixel electrode 1a, and an electric field is applied, the converted electric charges are collected by the pixel electrode 1a and stored in the charge accumulation node 41, in other words, the charge accumulation unit FD.

[0094] Next, another example of a pixel according to the present embodiment will be described. Fig. 3 is a diagram showing a schematic diagram of an exemplary circuit configuration of a pixel 110A of an imaging device according to the present embodiment. The pixel 110A shown in Fig. 3 is different from the pixel 110 described above in that it includes a band control unit 3A instead of the band control unit 3. The following description will focus on the differences with the pixel 110, and the description of the commonalities will be omitted or simplified.

[0095] In the pixel 110A, the amplifier 2, the band control section 3A, the charge storage section FD, and the output selection section 5 form a readout circuit 50A.

[0096] The feedback circuit 30A negatively feeds back the signal from the photoelectric conversion unit 1 to the charge accumulation unit FD via the amplification transistor 42. In other words, the feedback circuit 30A is a circuit that negatively feeds back the potential of the charge accumulation unit FD in a reset operation described later.

[0097] The band control unit 3A includes a band control circuit 13A and a reset circuit 14A.

[0098] The band control circuit 13A is a circuit that suppresses reset noise generated in a reset operation described later. The band control circuit 13A includes a band control transistor 46A, a first capacitance element 9, and a second capacitance element 10. In this specification, the "capacitive element" means a structure in which a dielectric such as an insulating film is sandwiched between electrodes. In addition, the "electrode" is not limited to an electrode made of metal, but is interpreted to broadly include a polysilicon layer and the like. The electrode may be a part of a semiconductor substrate. The first capacitance element 9 and the second capacitance element 10 may be, for example, a MIM (Metal Insulator Metal) capacitance or a MIS (Metal Insulator Semiconductor) capacitance. The reset circuit 14A includes a reset transistor 48.

[0099] The electrical connections of the read circuit 50A will be described below.

[0100] The gate of the amplifying transistor 42 is connected to the charge storage unit FD. One of the source and drain of the amplifying transistor 42 is connected to one of the source and drain of the band control transistor 46A. One of the source and drain of the amplifying transistor 42 is also connected to one of the source and drain of the selection transistor 44. The other of the source and drain of the band control transistor 46A is connected to one end of the first capacitance element 9. A reference voltage VR1 is applied to the other end of the first capacitance element 9. As a result, the band control transistor 46A and the first capacitance element 9 form an RC filter circuit.

[0101] The other of the source and drain of the band control transistor 46A is also connected to one end of the second capacitive element 10. The other end of the second capacitive element 10 is connected to the charge storage unit FD. In this specification, the node formed between the band control transistor 46A, the first capacitive element 9, and the second capacitive element 10 is referred to as "RD".

[0102] The gate of the band control transistor 46A is connected to the amplification control signal line CON3. The state of the band control transistor 46A is determined by the voltage of the amplification control signal line CON3. For example, when the voltage of the amplification control signal line CON3 is at a high level, the band control transistor 46A is turned on. At this time, the charge storage unit FD, the amplification transistor 42, the band control transistor 46A, and the second capacitive element 10 form a feedback circuit 30A.

[0103] When the voltage of the amplification control signal line CON3 becomes lower, the resistance component of the band control transistor 46A becomes larger, so that the band of the band control transistor 46A becomes narrower, and the frequency range of the feedback signal becomes narrower.

[0104] When the feedback path is formed, the signal output from the band control transistor 46A is attenuated by the attenuation circuit formed by the parasitic capacitance of the second capacitive element 10 and the charge storage unit FD, and is fed back to the charge storage unit FD. If the capacitance of the second capacitive element 10 is Cc and the parasitic capacitance of the charge storage unit FD is Cfd, the attenuation rate is expressed as Cc / (Cc+Cfd).

[0105] When the voltage of the amplification control signal line CON3 further drops to a low level, the band control transistor 46A turns off and no feedback path is formed.

[0106] The charge storage unit FD is further connected to one of the source and drain of a reset transistor 48. The other of the source and drain of the reset transistor 48 is connected to RD. As a result, the voltage of one of the source and drain of the amplifying transistor 42 (the output voltage of the amplifier 2) is applied to the reset transistor 48. The gate of the reset transistor 48 is connected to a reset control signal line CON2, and the state of the reset transistor 48 is determined by the voltage of the reset control signal line CON2. The reset transistor 48 negatively feeds back the signal of the photoelectric conversion unit 1 to the charge storage unit FD via the amplifying transistor 42. With this configuration, it is possible to reduce the change in voltage of the charge storage unit FD before and after turning off the reset transistor 48, enabling faster noise suppression.

[0107] [Pixel behavior] Next, the operation of the multiple pixels 110 of the imaging device 100 will be described. The control circuit of the imaging device 100 causes the multiple pixels 110 to perform an exposure operation for storing signal charges in the charge storage unit FD, a reset operation for initializing the potential of the charge storage unit FD, and a read operation for outputting a signal corresponding to the signal charges stored in the charge storage unit FD. Even when pixel 110A or pixel 115 is used instead of pixel 110, the basic operation is the same.

[0108] First, an exposure operation for storing signal charges in the charge storage unit FD will be described. The control circuit causes the multiple pixels 110 to perform an exposure operation by the following operations.

[0109] 4 is a diagram showing an example of the photoelectric conversion characteristic of the organic photoelectric conversion film as an example of the characteristic of the photoelectric conversion layer 1c. As shown in FIG. 4, the photoelectric conversion characteristic of the organic photoelectric conversion film is ITO For example, when a pixel electrode 1a provided in each pixel 110 is set to a reset voltage VRST and a HIGH voltage is supplied to a counter electrode 1b common to all pixels, a high voltage V HTherefore, the sensitivity of the organic photoelectric conversion film is high and photoelectric conversion is performed. The signal charge generated in the photoelectric conversion layer 1c is collected by the pixel electrode 1a. When a LOW voltage is supplied to the counter electrode 1b, the voltage applied to the counter electrode 1b and the pixel electrode 1a is a low voltage V L , the sensitivity of the organic photoelectric conversion film is lowered, and photoelectric conversion is stopped. That is, in a state in which the pixel electrode 1a provided in each pixel 110 is set to the reset voltage VRST, a HIGH voltage is supplied to the counter electrode 1b common to all pixels to start the exposure operation, and a LOW voltage is supplied to the counter electrode 1b to stop the exposure operation. At this time, the voltage of the amplification control signal line CON3 shown in FIG. 1B is at a low level, and the band control transistor 46 is off. In addition, in the case of the pixel 110A, the voltages of the reset control signal line CON2 and the amplification control signal line CON3 shown in FIG. 2 are at a low level, and the band control transistor 46A and the reset transistor 48 are off. As a result, signal charges are accumulated in the charge accumulation unit FD during the exposure operation. In this way, in the imaging device 100 using the photoelectric conversion layer 1c, the photoelectric conversion characteristics, that is, the sensitivity, can be controlled by controlling the voltage applied to the counter electrode 1b. In the imaging device 100 according to the present embodiment, by using such control of the photoelectric conversion characteristics (that is, the sensitivity characteristics), it becomes possible to perform a global shutter operation in which an exposure operation is performed on at least two or more pixels 110 simultaneously.

[0110] Here, in the case of an imaging device using a photoelectric conversion layer, as described above, the CDS method cannot be used because the charge cannot be completely transferred. Therefore, it is essential to suppress reset noise (e.g., kTC noise) for each pixel before exposure. Before the start of the global shutter exposure described above, a reset operation is also required for the pixels to be exposed.

[0111] Next, a reset operation for initializing the potential of the charge storage unit FD will be described with reference to Fig. 1B and Fig. 2. The control circuit causes the multiple pixels 110 to perform a reset operation by the following operation. The reset operation is performed on a row-by-row basis of the multiple pixels 110. In the reset operation, for example, reset noise is suppressed and the potential of the charge storage unit FD is initialized.

[0112] In the reset operation, the voltage of the selection control signal line CON7 is at a low level. Therefore, the selection transistor 44 is in an off state, and the amplification transistor 42 and the signal readout signal line 170 are electrically separated. Here, the voltage of the amplification control signal line CON3 is set to a high level to turn on the band control transistor 46. At this time, the first switch element 11 of the switching circuit 20 is in an on state, and a voltage Va1 (for example, a ground voltage GND) is applied to the other of the source and drain of the amplification transistor 42. As a result, the voltage of the charge storage unit FD (in other words, the voltage of the pixel electrode 1a) becomes equal to the reset voltage VRST. That is, the potential of the charge storage unit FD is initialized. Furthermore, for example, next, the voltage of the amplification control signal line CON3 is set to a voltage between a high level and a low level, for example, an intermediate voltage. This suppresses the reset noise. In this case, if the voltage is set so that the operating band of the band control transistor 46 is narrower than the operating band of the amplification transistor 42, the reset noise suppression effect is further enhanced. Finally, the voltage of the amplification control signal line CON3 is set to low level to turn off the band control transistor 46. This suppresses reset noise and initializes the potential of the charge storage unit FD.

[0113] In the case of pixel 110A, in addition to setting the voltage of the amplification control signal line CON3 to a high level, the voltage of the reset control signal line CON2 is set to a high level and the reset transistor 48 is turned on, so that the voltage of the charge storage unit FD becomes equal to the reset voltage VRST. Next, the reset transistor 48 is turned off. Furthermore, for example, next, the voltage of the amplification control signal line CON3 is set to a voltage between a high level and a low level, for example an intermediate voltage, thereby obtaining the above-mentioned reset noise suppression effect. Finally, the voltages of the reset control signal line CON2 and the amplification control signal line CON3 are set to a low level, and the band control transistor 46A is turned off.

[0114] Next, a read operation for outputting a signal corresponding to the signal charge accumulated in the charge accumulation unit FD will be described with reference to Fig. 1B and Fig. 2. The control circuit causes the multiple pixels 110 to perform a read operation by the following operation. The read operation is performed on a row-by-row basis for the multiple pixels 110.

[0115] In the read operation, the voltage of the selection control signal line CON7 is set to a high level to turn on the selection transistor 44. Also, the switching circuit 20 is controlled so that the voltage of the other of the source and drain of the amplification transistor 42 becomes Va2 (for example, the power supply voltage VDD). That is, the second switch element 12 is turned on, and the voltage Va2 is applied to the other of the source and drain of the amplification transistor 42. In this state, the amplification transistor 42 and the constant current source 144 form a source follower circuit. Then, the potential of the charge storage unit FD becomes a voltage according to the amount of signal charge stored in the charge storage unit FD. As a result, the voltage of the charge storage unit FD according to the amount of signal charge is amplified by the amplifier 2 with an amplification factor of, for example, about 1, and output to the signal read signal line 170. At this time, the amplification factor of the source follower circuit is, for example, about 1. The voltage of the charge storage unit FD is amplified by the amplifier 2 with an amplification factor of, for example, about 1, and output to the signal read signal line 170.

[0116] This read operation is performed in a state where signal charge from the exposure operation has been accumulated in the charge accumulation unit FD, and in a state where the reset operation for the pixel has been completed and a reset voltage VRST has been set to the pixel electrode. The read operation in a state where signal charge from the exposure operation has been accumulated in the charge accumulation unit FD is referred to as a "signal read operation," and the read operation in a state where the reset voltage VRST has been set to the pixel electrode is referred to as a "reset signal read operation."

[0117] [Operation of imaging device] Next, a description will be given of the operation of the imaging device 100. Specifically, a description will be given of the operation that a control circuit of the imaging device 100 causes a plurality of pixels to perform.

[0118] The following describes operations and problems when an imaging device according to a comparative example is used, as well as operations and effects when imaging device 100 according to the present embodiment is used.

[0119] First, an imaging device according to a comparative example will be described with reference to Figures 5A, 5B, and 5C. The imaging device according to the comparative example has a similar configuration to the imaging device 100 described above, but the operation of each circuit is different from that of the imaging device 100 according to the present embodiment. Below, an example will be described in which a plurality of pixels 110 of the imaging device according to the comparative example configure a pixel array of "rows 0 to n by columns 0 to m."

[0120] Fig. 5A is a timing chart for explaining an example of the operation of an imaging device according to a comparative example, and Fig. 5B is a flowchart showing an example of the operation of an imaging device according to a comparative example.

[0121] FIG. 5A shows the timing of the trigger signal, the timing of the falling edge (or rising edge) of the vertical synchronization signal VD, the temporal change in the magnitude of the voltage applied to the counter electrode 1b of the photoelectric conversion unit 1 (i.e., the bias voltage applied to the photoelectric conversion layer 1c), the driving of the entire plurality of pixels 110, and the reset operation, signal readout operation, and exposure operation in each row of the pixel array of the plurality of pixels 110. The top of FIG. 5A shows the timing of the "trigger signal" that instructs the start of exposure. "VD" in the top graph in FIG. 5A shows the timing of the falling edge (or rising edge) of the vertical synchronization signal VD. "Counter electrode voltage" in the second graph from the top in FIG. 5A shows the temporal change in the voltage applied to the counter electrode 1b from the voltage supply circuit 140 via the accumulation control line 130. Further below, "pixel driving" and "each row operation" show the timing of the driving of the entire plurality of pixels 110 and the operation of each row of the pixel array of the plurality of pixels 110, respectively. The lines of each row operation indicate that the operation is performed sequentially row by row from row 0 to row n. The solid lines of each row operation indicate reset operations, and the dashed lines indicate signal read operations.

[0122] 5A and 5B, first, since it is necessary to perform a reset operation before an exposure operation for all pixels 110, the control circuit of the imaging device according to the comparative example causes a plurality of pixels 110 in all rows from row 0 to row n to perform a reset operation at least for every row during a reset operation period A (S111). When the reset operation is performed, for example, as described above, the reset operation is performed while suppressing reset noise (e.g., kTC noise).

[0123] Next, in a state in which the reset noise of all the pixels 110 is suppressed and the reset voltage VRST is set, the control circuit of the image pickup device according to the comparative example applies a HIGH voltage to the counter electrode 1b during the exposure operation period B, causing the multiple pixels 110 to perform an exposure operation (S112). The exposure operation is performed collectively on at least two or more pixels 110 among the multiple pixels 110.

[0124] Next, after the exposure operation, the control circuit of the imaging device according to the comparative example performs a signal readout operation for at least one row for the pixels 110 belonging to all rows from row 0 to row n during a signal readout operation period C, a reset operation for all the pixels 110 from which signals have been read out again after the signal readout operation, and a reset signal readout operation for all the pixels 110 after the reset operation (S113). In the reset signal readout operation, noise in all the pixels 110 from which signals have been read out is suppressed, and the reset signal readout operation is performed at least for one row with the reset voltage VRST set.

[0125] Thereafter, the control circuit of the imaging device according to the comparative example receives a trigger signal from the outside, determines the exposure start time, and causes the multiple pixels 110 to perform a reset operation, an exposure operation, and a signal readout operation (S114 to S117). In steps S115 to S117, the same operations as in steps S111 to S113 are performed. At this time, after receiving the trigger signal in step S114, a reset operation for all pixels 110 to be exposed is required at least for each row before the exposure operation in step 116, and a long waiting time T1 occurs from receiving the trigger signal from the outside to starting the exposure operation. For example, if 3 microseconds is required for FHD (1000 vertical rows) per row reset operation, a waiting time T1 of 3 milliseconds or more occurs, and it is not possible to shoot what you want to shoot at the timing you want to shoot, or it is not possible to shoot continuously to shoot what you want to shoot at the timing you want to shoot. This causes problems such as not being able to perform continuous inspection of multiple objects at high speed.

[0126] FIG. 5C is a flowchart showing another example of the operation of the imaging device according to the comparative example. In the example shown in FIG. 5C, the control circuit of the imaging device according to the comparative example first receives a trigger signal from the outside and causes the multiple pixels 110 to perform a reset operation, an exposure operation, and a signal readout operation (S121 to S124). In steps S121 to S124, the same operations as those in steps S114 to S117 described above are performed. As shown in FIG. 5B, the imaging device according to the comparative example may determine the exposure operation start time in accordance with the reception of a trigger signal from the outside after performing a first imaging for initialization, or may determine the exposure operation start time in accordance with the reception of a trigger signal from the outside from the beginning, as shown in FIG. 5C. In addition, the imaging device according to the comparative example may repeat control of the exposure operation timing by a trigger signal from the outside and continuous internal scanning.

[0127] Next, the operation of the imaging device 100 according to the present embodiment that solves the above problem will be described with reference to Fig. 6A to Fig. 7. In the following, an example will be described in which a plurality of pixels 110 of the imaging device 100 configure a pixel array of "row 0 to row n x column 0 to column m". Note that the imaging device 100 may include pixel 110A or pixel 115 instead of pixel 110.

[0128] Fig. 6A is a timing chart for explaining an example of the operation of imaging device 100 according to the present embodiment. Fig. 6B is a flowchart showing an example of the operation of imaging device 100 according to the present embodiment. Fig. 6C is a timing chart for explaining another example of the operation of imaging device 100 according to the present embodiment.

[0129] Like Figure 5A, Figures 6A and 6C show the timing of the trigger signal, the timing of the falling (or rising) edge of the vertical synchronization signal VD, the change over time in the magnitude of the voltage applied to the counter electrode 1b of the photoelectric conversion unit 1 (i.e., the bias voltage applied to the photoelectric conversion layer 1c), the driving of the entire multiple pixels 110, and the reset operation, signal readout operation, and exposure operation in each row of the pixel array of the multiple pixels 110.

[0130] As shown in FIG. 6A and FIG. 6B, first, in order to reset the voltage before the exposure operation for all the pixels 110, the control circuit of the imaging device 100 causes the reset operation to be performed for all the pixels 110 in rows 0 to n during the reset operation period A (S11). When the reset operation is performed, for example, as described above, the reset operation is performed at least for each row while suppressing the reset noise (kTC noise). Note that in step S11, the control circuit of the imaging device 100 may cause the pixels 110 belonging to at least one row among the multiple pixels 110 to perform the reset operation in sequence on a row-by-row basis. For example, when imaging is performed in a cut-out mode using some of the pixels 110, the reset operation may be performed for the row of the pixels 110 to be used.

[0131] Next, in a state in which the reset noise of all the pixels 110 is suppressed and the reset voltage VRST is set, the control circuit of the imaging device 100 applies a HIGH voltage to the counter electrode 1b during the exposure operation period B, causing the pixels 110 to perform an exposure operation (S12). The exposure operation is performed simultaneously for at least two or more pixels 110 among the multiple pixels 110. The exposure operation may be performed simultaneously for all the pixels 110.

[0132] The control circuit of the imaging device 100 causes the pixels 110 belonging to all rows from row 0 to row n to perform a signal readout operation of pixel signals accumulated at least for each row during a signal readout operation period C after the exposure operation, a reset operation for all pixels 110 from which signals have been read out again after the readout, and a reset signal readout operation for all pixels 110 after the reset operation (S13). In the reset signal readout operation, noise in all pixels 110 from which signals have been read out is suppressed, and the reset signal readout operation is performed at least for each row in a state in which a reset voltage VRST is set.

[0133] Here, in the imaging device according to the above-mentioned comparative example, after receiving a trigger signal from the outside, a reset operation is required for all pixels 110 that are to be exposed, at least for each row, before the exposure operation, which causes a problem of a long waiting time from receiving the trigger signal from the outside to the start of the exposure operation. Also, a method is conceivable in which a reset operation is performed in advance for all pixels 110 that are to be exposed, at least for each row, regardless of receiving the trigger signal from the outside. However, if the time from the reset operation to receiving the trigger signal from the outside, and thus to the start of the exposure operation, is long, a problem occurs in that accurate signal charge accumulation and signal readout operations cannot be performed due to the influence of minute leaks such as dark current.

[0134] However, in the imaging device 100 according to the present embodiment, even after the reset signal is read out in step S13, a period (pre-reset operation period A2) is provided in which the reset operation is repeated at least for each row, thereby making it possible to shorten the waiting time from receipt of a trigger signal from the outside to the start of an exposure operation. Specifically, the control circuit of the imaging device 100 causes the pixels 110 to perform a reset operation at least for each row in the pre-reset operation period A2 (S14). The reset operation in step S14 is repeated in units of rows 0 to n until the control circuit receives a trigger signal from the outside (S15). In other words, the control circuit of the imaging device 100 causes the pixels 110 to perform the reset operation repeatedly in sequence, row by row, until it receives a trigger signal.

[0135] Furthermore, in step S15, when the control circuit of the imaging device 100 receives a trigger signal from the outside, it performs an interrupt process and stops the process until the end of the process of the pixel 110 in the xth row in which the reset operation is being performed. As a result, the reset operation in step S14 is repeated a times in units of row 0 to row n, and is further performed from row 0 to row x. Here, a is an integer equal to or greater than 0. The xth row is any row between row 0 and row n. In this way, in steps S13 to S15, the control circuit of the imaging device 100 causes all of the pixels 110 to perform a reset operation for initializing the potential of the charge storage unit FD in sequence in row units before receiving a trigger signal instructing the start of exposure. Furthermore, the control circuit of the imaging device 100 causes the pixels 110 belonging to at least one row of the multiple pixels 110 to perform the reset operation multiple times before receiving the trigger signal. As a result, the accumulation of signal charges resulting from dark currents, etc., which cause noise, is suppressed until the control circuit receives a trigger signal from the outside.

[0136] As soon as the reset operation is completed, the control circuit of the imaging device 100 causes at least two or more pixels 110 to perform an exposure operation (S16). Then, the control circuit of the imaging device 100 causes the pixels 110 to perform a signal read operation, a reset operation, and a reset signal read operation (S17). That is, after receiving a trigger signal, the control circuit of the imaging device 100 causes the pixels 110 belonging to at least one row among the pixels 110 to simultaneously perform an exposure operation to accumulate signal charges in the charge accumulation unit FD without causing the pixels 110 belonging to at least one row among the pixels 110 to perform a reset operation. By taking the difference between the output in the signal read operation and the output in the reset read operation thus obtained, a signal corresponding to the amount of charge generated by photoelectric conversion during the exposure operation is obtained. In steps S16 and S17, the same operations as those in steps S12 and S13 described above are performed.

[0137] In step S17, as shown in Fig. 6A, the control circuit of the imaging device 100 may perform a signal read operation on the plurality of pixels 110 in sequence, row by row, starting from row 0 where the reset operation is started in steps S11 and S13, after the exposure operation. With this configuration, the reset operation and the read operation are started on a common row, so that the control circuit can be prevented from becoming complicated. Also, the read data is read out continuously in time from the upper row to the lower row, or from the lower row to the upper row, so that the continuity of the image is maintained.

[0138] The row on which the signal readout operation is started is not particularly limited as long as it is performed on the pixels 110 belonging to all rows in order by row. For example, in step S17, the control circuit of the imaging device 100 may perform the signal readout operation on the pixels 110 in order by row, starting from the row next to the xth row in which the reset operation is completed in step S14, after the exposure operation, as shown in FIG. 6C. By adopting this configuration, the time from the reset operation to the readout operation of each row becomes approximately the same. Therefore, the difference in the amount of charge accumulated in the charge accumulation unit FD by dark current or the like after the reset operation is performed between each row is reduced. Therefore, the difference in noise between the multiple pixels 110 is reduced.

[0139] Then, the operations from step S14 to step S17 are repeated. In this manner, in the imaging device 100 according to the present embodiment, by providing the pre-reset operation period A2, it is possible to shorten the waiting time T2 from receipt of the external trigger signal to the start of the exposure operation by at least the reset operation time for one row, as compared with the waiting time T1 described above.

[0140] Here, in steps S14 and S15, when an external trigger signal is received, the reset operation is stopped until the processing of the row in which the reset operation is being performed is completed, but this is not limited to this. The reset operation only needs to be performed on the pixels 110 belonging to at least one row after receiving the external trigger signal, and for example, the reset operation may be performed on several rows from the row in which the reset operation is being performed, taking into account the stabilization of the peripheral circuits.

[0141] In the example shown in FIG. 6A and FIG. 6B, when the reset operation is repeated in step S14 (pre-reset operation period A2 in FIG. 6A) with rows 0 to n as one unit (i.e., one frame), the reset operation of the next frame is performed from row 0 immediately after the completion of the reset operation of one frame. In other words, when the reset operation is repeated, there is no interval between the completion of the reset operation of one frame and the start of the reset operation of the next frame. Note that in step S14, a period during which the reset operation is not performed may be provided between the completion of the reset operation of one frame and the start of the reset operation of the next frame. The shorter the period during which the reset operation is not performed in step S14, the more noise caused by dark current and the like is suppressed, but it may be set so that the image quality required for the purpose of use is obtained. For example, the period during which the reset operation is not performed in step S14 may be within the length of one frame.

[0142] 6B, if the control circuit of the imaging device 100 receives a trigger signal while steps S11 to S13 are being executed, that is, before the reset operation is performed on all of the pixels 110, the control circuit does not interrupt operations such as the reset operation. In this case, for example, the control circuit of the imaging device 100 may discard the received trigger signal, and may cause the pixels 110 to perform the exposure operation after step S13 without immediately starting the exposure operation. Also, the control circuit of the imaging device 100 may have a circuit configuration that does not receive a trigger signal until the reset operation is performed on all of the pixels 110.

[0143] FIG. 6D is a flowchart showing another example of the operation of the imaging device 100. In the example shown in FIG. 6D, the control circuit of the imaging device 100 first causes the pixels 110 belonging to all rows from row 0 to row n to perform a reset operation (S21). In step S21, the same operation as in step S11 described above is executed. After the reset operation in step S21, the control circuit of the imaging device 100 causes the pixels 110 to perform a reset operation at least for each row (S22). The reset operation in step S22 is repeated in units of rows 0 to n until the control circuit receives a trigger signal from the outside (S23). Upon receiving the trigger signal, the control circuit of the imaging device 100 causes the pixels 110 to simultaneously perform an exposure operation as soon as the reset operation is completed (S24). Then, the control circuit of the imaging device 100 causes the pixels 110 to perform a signal read operation, a reset operation, and a reset signal read operation (S25). Then, the operations from step S22 to step S25 are repeatedly executed. In steps S22 to S25, the same operations as those in steps S14 to S17 described above are executed.

[0144] As shown in Fig. 6B, the imaging device 100 may provide a pre-reset operation period A2 after performing a first imaging for initialization, and determine the exposure operation start time in accordance with reception of an external trigger signal, or may provide a pre-reset operation period A2 from the beginning, and determine the exposure operation start time in accordance with reception of an external trigger signal, as shown in Fig. 6D. Furthermore, the imaging device 100 may repeat control of the exposure operation timing by an external trigger signal and internal continuous scanning.

[0145] FIG. 7 is a flowchart showing another example of the operation in the imaging device 100. In this example, the control circuit of the imaging device 100 causes the pixels 110 to perform the same operations as steps S11 and S12 shown in FIG. 6B as the operations of steps S31 and S32. Next, the control circuit of the imaging device 100 causes the pixels 110 to perform a signal read operation and a reset operation (step S33). That is, in step S33, the reset signal read operation in step S13 shown in FIG. 6B is not performed. Next, the control circuit of the imaging device 100 causes the pixels 110 to perform the same operations as steps S14 to S16 shown in FIG. 6B as the operations of steps S34 to S36. Then, the control circuit of the imaging device 100 causes the pixels 110 to perform a signal read operation and a reset operation (step S37). In step S37, the same operations as step S33 are performed. In this operation example, a signal corresponding to the amount of charge stored in the charge storage unit FD can be obtained by taking the difference between the output during the signal read operation and the output corresponding to the state in which the reset voltage VRST is set.

[0146] (Embodiment 2) Next, a description will be given of embodiment 2. In embodiment 2, an imaging device having a laminated structure of at least two substrate layers will be described.

[0147] 8 is a schematic diagram showing an example of the configuration of an imaging device 101 according to the present embodiment. As shown in FIG. 8, the imaging device 101 includes a first substrate 2000 and a second substrate 2100 laminated on the first substrate 2000.

[0148] The first substrate 2000 is located above the second substrate 2000. The first substrate 2000 has a pixel array 111. The pixel array 111 has a structure in which, for example, the above-mentioned pixels 110, pixels 110A, or pixels 115 are arranged in a matrix.

[0149] The second substrate 2100 has an analog-to-digital conversion circuit (AD conversion circuit) 2200 that receives signal output (specifically, analog signals) from each pixel included in the pixel array 111 and converts them into digital signals, a memory 2400 in which the signals converted into digital signals by the analog-to-digital conversion circuit 2200 are stored, and an arithmetic processing circuit 2300 that performs arithmetic processing on the signals converted into digital signals by the analog-to-digital conversion circuit 2200.

[0150] The first substrate 2000 and the second substrate 2100 are electrically connected by a connection portion 2500 .

[0151] In this stacked structure, for example, the pixel 110, pixel 110A, or pixel 115 for realizing the above-mentioned imaging device 100 is provided on the first substrate 2000, and a circuit for controlling the counter electrode 1b of the photoelectric conversion unit 1 and a circuit for interrupt control logic are provided on the second substrate 2100. By providing the circuit for controlling the counter electrode 1b of the photoelectric conversion unit 1 and the circuit for interrupt control logic on the second substrate 2100, it is possible to freely construct a circuit for control logic without being affected by the pixel area of ​​the pixels included in the pixel array 111. It is not particularly limited as to which of the first substrate 2000 and the second substrate 2100 each circuit is provided on, as long as it is determined according to the purpose. Specifically, for example, the pixel 110, pixel 110A, or pixel 115 is provided on the first substrate 2000, and the vertical operation circuit 141, the voltage supply circuit 140, the column signal processing circuit 142, and the horizontal signal readout circuit 143 are provided on the second substrate 2100. In addition, the pixel 110, the pixel 110A, or the pixel 115 may not include the switching circuit 20, and the switching circuit 20 may be provided on the second substrate 2100. In addition, the constant current source 144 may not be included in the first substrate 1000, and the constant current source 144 may be provided on the second substrate 2100.

[0152] 8, the stacked structure of the imaging device 101 is a structure in which two layers of substrates are stacked, but is not limited thereto, and may be a structure in which three or more layers of substrates are stacked, or a structure in which multiple child substrates are stacked on a single substrate. The connection portion 2500 of the substrate may be provided for each column as shown in FIG. 8, may be provided for each region, or may be provided for each pixel.

[0153] (Embodiment 3) Next, a third embodiment will be described. In the third embodiment, a camera system including the above-mentioned imaging device will be described. Fig. 9 is a block diagram showing an example of the configuration of a camera system 1000 according to the third embodiment.

[0154] The camera system 1000 according to this embodiment includes an image capturing device 102, an optical system 1001 for collecting light such as a lens, a camera signal processing unit 1002 for signal processing data captured by the image capturing device 102 and outputting the data as an image or data, and a system controller 1003 for controlling the image capturing device 102 and the camera signal processing unit 1002.

[0155] The optical system 1001 is a lens or the like for collecting light on an imaging surface of the imaging device 102. Light passing through the optical system 1001 is incident on the photoelectric conversion unit 1 of the imaging device 102, where it is photoelectrically converted to generate a signal charge. For example, the imaging device 100 or 101 according to the above-described embodiment is used as the imaging device 102.

[0156] The camera signal processing unit 1002 functions as a signal processing circuit that processes an output signal from the imaging device 102. The camera signal processing unit 1002 performs processes such as gamma correction, color interpolation processing, spatial interpolation processing, auto white balance, distance measurement calculation, and wavelength information separation. The camera signal processing unit 1002 can be realized by, for example, a DSP (Digital Signal Processor).

[0157] The system controller 1003 controls the entire camera system 1000. The system controller 1003 can be realized by, for example, a microcomputer.

[0158] The camera system 1000 in this embodiment can reduce the delay time from receipt of an external trigger signal to start of exposure operation for the entire light receiving surface by using the imaging device 100 or 101 according to the above embodiment as the imaging device 102. Therefore, it is possible to provide a camera system 1000 with high usability, in which the waiting time until the start of the exposure operation is short, imaging of an object to be imaged can be performed when it is desired, or high-speed inspection is possible.

[0159] (Other embodiments) While the imaging device and camera system according to one or more aspects have been described based on the respective embodiments, the present disclosure is not limited to these embodiments.

[0160] For example, in the above embodiment, the reset operation in step S14 is started immediately after the operation in step S13 is completed, but it may also be started at an interval after the operation in step S13 is completed, as long as the image quality required for the purpose of use is obtained.

[0161] In the above embodiment, in the reset operation, the charge storage unit FD is electrically connected to the switching circuit 20, so that the voltage of the charge storage unit FD becomes equal to the reset voltage VRST, but this is not limited to the above. The reset operation may be performed by applying a reference voltage to the charge storage unit FD from a circuit different from the switching circuit 20.

[0162] In the above embodiment, the photoelectric conversion unit 1 includes the pixel electrode 1a, the counter electrode 1b, and the photoelectric conversion layer 1c, but may further include a charge transport layer or a charge blocking layer between the photoelectric conversion layer 1c and the pixel electrode 1a or between the counter electrode 1b, which further suppresses the generation of dark current and further reduces noise.

[0163] In the above embodiment, the reset operation and the signal read operation are performed on a row-by-row basis. However, a plurality of signal lines may be provided for each column, and the reset operation and the signal read operation may be performed on a row-by-row basis. This can achieve high speed. The configuration in which a plurality of signal lines are provided for each column is described in more detail in U.S. Patent Publication No. 10,225,500, a patent application filed by the applicant. The entire disclosure of these documents is incorporated herein by reference.

[0164] In addition, in a scene where the imaging device of the present disclosure is actually used, it is also assumed that the trigger signal is received during a period other than the pre-reset operation period. For example, when the trigger signal is received before starting the pre-reset operation, the trigger signal may be ignored. Alternatively, after receiving the trigger signal, the exposure operation may be started after performing the reset operation for all rows of pixels. Also, for example, when the trigger signal is received during the exposure period, the trigger signal may be ignored. Alternatively, after the exposure operation is completed, the signal readout operation and the reset operation may be performed, and then the exposure operation may be performed again. Alternatively, after the exposure operation is completed, the reset operation may be performed, and then the exposure operation may be performed again. Alternatively, the exposure operation may be interrupted midway, and the reset operation may be performed before the exposure operation is performed again. Even if the above-mentioned operation is performed when the trigger signal is received during a period other than the pre-reset operation period, it is within the scope of the rights of the present disclosure as long as the operation described in the claims of the present disclosure is performed.

[0165] In addition, as long as they do not deviate from the spirit of this disclosure, various modifications that would occur to a person skilled in the art to this embodiment, and forms constructed by combining components in different embodiments, are also included in the scope of this disclosure. [Industrial Applicability]

[0166] The imaging device according to the present disclosure can be used in various camera systems and sensor systems, such as digital still cameras, medical cameras, surveillance cameras, vehicle-mounted cameras, digital single-lens reflex cameras, and digital mirrorless single-lens cameras. [Explanation of symbols]

[0167] 1, 1d Photoelectric conversion unit 1a Pixel electrode 1b Counter electrode 1c Photoelectric conversion layer 2 Amplifier 3. 3A Bandwidth Control Unit 5 Output selection section 9 First Capacitive Element 10 Second Capacitive Element 11 First switch element 12 Second switch element 13, 13A Bandwidth control circuit 14A Reset Circuit 30, 30A feedback circuit 41 Charge storage node 42 Amplifying transistor 42g, 44g, 46g Gate insulation layer 42e, 44e, 46e Gate electrode 44 Select transistor 46, 46A Bandwidth Control Transistor 48 Reset Transistor 50, 50A readout circuit 62 Semiconductor Substrate 62a, 62b, 62c, 62d, 62e impurity region 62s Element isolation area 63A, 63B, 63C, 63D Interlayer insulation layer 65A, 65B contact plug 66A, 68A, 68B Wiring 67A, 67B, 67C, 67D, 67E plugs 72 Color Filter 74 Micro Lens 100, 101, 102 Imaging device 110, 110A, 115 pixels 111 pixel array 120 Power line 130 Storage control line 141 Vertical scanning circuit 142 Column signal processing circuit 143 Horizontal signal readout circuit 144 Constant current source 170 Signal readout signal line 180 Horizontal common signal line 1000 Camera System 1001 Optical system 1002 Camera signal processing unit 1003 System Controller 2000 First Board 2100 Second board 2200 Analog-to-Digital Conversion Circuit 2300 Calculation Processing Circuit 2400 Memory 2500 Connection CON2 Reset control signal line CON3 Amplification control signal line CON7 Selection control signal line

Claims

1. A plurality of pixels arranged in a matrix, each of which includes a photoelectric conversion unit that converts light into a signal charge and a charge accumulation unit that accumulates the signal charge; Control circuit Equipped with The control circuit includes: a reset operation for initializing a potential of the charge storage unit is performed on pixels belonging to at least one row among the plurality of pixels in sequence on a row-by-row basis or on a multiple-row basis before receiving a trigger signal instructing a start of exposure; after receiving the trigger signal, causing the pixels belonging to at least one row among the plurality of pixels to simultaneously perform an exposure operation for accumulating the signal charge in the charge accumulation portion without causing the pixels belonging to at least one row among the plurality of pixels to perform the reset operation; Imaging device.

2. The control circuit causes all pixels of the plurality of pixels to perform the reset operation in sequence, row by row or in units of multiple rows, before receiving the trigger signal. The imaging device according to claim 1 .

3. The control circuit causes pixels belonging to at least one row among the plurality of pixels to perform the reset operation a plurality of times before receiving the trigger signal.

3. The imaging device according to claim 1.

4. The control circuit causes the pixels to repeatedly perform the reset operation in sequence on a row basis or on a multiple row basis until the trigger signal is received. The imaging device according to claim 1 .

5. the control circuit causes the pixels to perform a readout operation of outputting a signal corresponding to the signal charge stored in the charge storage unit after the exposure operation, in sequence on a row-by-row basis or on a multiple-row basis starting from a row on which the reset operation is started; The imaging device according to claim 1 .

6. The control circuit includes: performing the reset operation on the plurality of pixels in sequence on a row-by-row basis or on a multiple-row basis up to a row different from the row on which the reset operation has been started; After the exposure operation, a readout operation of outputting a signal corresponding to the signal charge stored in the charge storage unit is performed on the plurality of pixels in sequence, starting from the row next to the row on which the reset operation has been completed, on a row-by-row basis or on a multiple-row basis. The imaging device according to claim 1 .

7. Each of the plurality of pixels includes a feedback circuit that negatively feeds back a potential of the charge storage unit in the reset operation. The imaging device according to claim 1 .

8. Each of the plurality of pixels includes a circuit for suppressing reset noise generated in the reset operation. The imaging device according to claim 1 .

9. The imaging device according to claim 1 , wherein the reset operation includes an operation of negatively feeding back a potential of the charge storage section.

10. A voltage supply circuit is further provided, the photoelectric conversion unit includes a counter electrode electrically connected to the voltage supply circuit, a pixel electrode electrically connected to the charge accumulation unit, and a photoelectric conversion layer located between the counter electrode and the pixel electrode; the control circuit causes the voltage supply circuit to apply a voltage to the counter electrode to form an electric field in the photoelectric conversion layer, thereby causing the plurality of pixels to perform the exposure operation; The imaging device according to claim 1 .

11. A method for controlling an imaging device having a plurality of pixels arranged in a matrix, each of which includes a photoelectric conversion unit that converts light into a signal charge and a charge accumulation unit that accumulates the signal charge, comprising: a reset operation for initializing a potential of the charge storage unit is performed on pixels belonging to at least one row among the plurality of pixels in sequence on a row-by-row basis or on a multiple-row basis before receiving a trigger signal instructing a start of exposure; after receiving the trigger signal, performing an exposure operation for accumulating the signal charge in the charge accumulation portion on the plurality of pixels simultaneously without performing the reset operation on pixels belonging to at least one row among the plurality of pixels; Control methods.

12. The control method according to claim 11 , wherein the reset operation includes an operation of negatively feeding back a potential of the charge storage unit.

Images