Configurable PAM level read clock toggle
JP7602698B2Active Publication Date: 2024-12-18ADVANCED MICRO DEVICES INC +1
Patent Information
- Application Number
- JP2024534115
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2022-06-30
- Filing Date
- 2022-11-30
- Publication Date
- 2024-12-18
- Estimated Expiration
- 2042-11-30
Smart Images
Figure 0007602698000004 
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Abstract
The read clock circuit selectively provides a read clock signal from the memory to the memory controller via the memory bus and includes a pulse amplitude modulation (PAM) driver including an input and an output capable of driving at least three levels indicative of respective digital values. The digital control circuit is coupled to the PAM driver and is operable to cause the PAM driver to provide a preamble signal prior to the read clock signal, the preamble signal including an initial toggle state in which the PAM driver toggles between two selected levels at a first rate and a final toggle state in which the PAM driver toggles between the two selected levels at a second rate higher than the first rate, the length of the initial toggle state and the length of the final toggle state being based on the value in the mode register.
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Citation Information
Patent Citations
Low latency multilevel communication interface
JP2004531909A
Semiconductor memory device and data strobe signal generating method thereof
JP2006313616A
Circuit arrangement and a method to transfer data on a 3-level pulse amplitude modulation (PAM-3) channel
US20050220232A1
Advanced memory device having improved performance, reduced power and increased reliability
US20120300563A1