Solid-state imaging element and imaging device

Abstract

A solid-state imaging element according to the present disclosure is provided with a plurality of first photoelectric conversion elements, a plurality of second photoelectric conversion elements, a plurality of current-to-voltage conversion circuits (320, 320A), and a plurality of address event detection circuits (231, 231A). The plurality of first photoelectric conversion elements are arranged side by side in a first region. The plurality of second photoelectric conversion elements are arranged side by side in a second region adjacent to the first region. The plurality of current-to-voltage conversion circuits (320, 320A) respectively convert currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages. The plurality of address event detection circuits (231, 231A) respectively detect a change in the voltages output from the plurality of current-to-voltage conversion circuits (320, 320A). The current-to-voltage conversion circuits (320A) and / or the address event detection circuits (231A) connected to the second photoelectric conversion elements suppress the output a signal based on the currents output from the second photoelectric conversion elements.

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging element and an imaging device. [Background technology]

[0002] In recent years, asynchronous solid-state imaging devices have been proposed in which an address event detection circuit is provided for each pixel, which detects in real time, for each pixel address, that the amount of light at that pixel exceeds a threshold value as an address event (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2016-533140 Summary of the Invention [Problem to be solved by the invention]

[0004] However, with the above-mentioned conventional techniques, it has been difficult to improve the quality of signals output from effective pixels in such a non-synchronous solid-state imaging device.

[0005] In view of this, the present disclosure proposes a solid-state imaging element and an imaging device that can improve the quality of signals output from effective pixels. [Means for solving the problem]

[0006] According to the present disclosure, a solid-state imaging device is provided. The solid-state imaging device includes a plurality of first photoelectric conversion elements, a plurality of second photoelectric conversion elements, a plurality of current-voltage conversion circuits, and a plurality of address event detection circuits. The plurality of first photoelectric conversion elements are arranged side by side in a first region. The plurality of second photoelectric conversion elements are arranged side by side in a second region adjacent to the first region. The plurality of current-voltage conversion circuits convert currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages, respectively. The plurality of address event detection circuits detect changes in voltages output from the plurality of current-voltage conversion circuits, respectively. At least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element suppresses output of a signal based on the current output from the second photoelectric conversion element. [Brief description of the drawings]

[0007] [Figure 1] 1 is a block diagram illustrating an example of a configuration of an imaging device according to an embodiment of the present disclosure. [Diagram 2] 2A to 2C are diagrams for explaining a layered structure of a solid-state imaging element according to an embodiment of the present disclosure. [Diagram 3] 2A and 2B are diagrams for explaining a planar configuration of a light-receiving substrate according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a diagram for explaining a planar configuration of a circuit board according to an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a diagram for explaining a configuration of an effective pixel according to an embodiment of the present disclosure. [Figure 6] FIG. 2 is a diagram showing a circuit configuration of an effective pixel according to an embodiment of the present disclosure. [Figure 7] FIG. 2 is a diagram for explaining a configuration of an effective pixel according to an embodiment of the present disclosure. [Figure 8] 1 is a diagram showing a cross-sectional configuration of a solid-state imaging element according to an embodiment of the present disclosure. [Figure 9] 1 is a diagram showing a planar configuration of a solid-state imaging element according to an embodiment of the present disclosure. [Figure 10]FIG. 2 is a diagram showing a circuit configuration of an effective pixel and a dummy pixel according to an embodiment of the present disclosure. [Figure 11] 1 is a diagram showing a cross-sectional configuration of a solid-state imaging element according to a first modified example of the embodiment of the present disclosure. [Figure 12] 11 is a diagram showing a planar configuration of a solid-state imaging element according to a second modified example of the embodiment of the present disclosure. FIG. [Figure 13] FIG. 11 is a diagram showing a planar configuration of a solid-state imaging element according to a third modified example of the embodiment of the present disclosure. [Figure 14] FIG. 11 is a diagram showing a planar configuration of a solid-state imaging element according to a fourth modified example of the embodiment of the present disclosure. [Figure 15] FIG. 13 is a diagram showing a circuit configuration of an effective pixel according to a fifth modified example of the embodiment of the present disclosure. [Figure 16] FIG. 13 is a block diagram showing a second exemplary configuration of the address event detection unit. [Figure 17] FIG. 11 is a block diagram showing an example of the configuration of an imaging device according to a second configuration example, that is, a scanning type imaging device, which is used as an imaging device in an imaging system to which the technology according to the present disclosure is applied. [Figure 18] FIG. 1 is a schematic diagram illustrating an example of a configuration of a distance measuring system according to an embodiment of the present disclosure. [Figure 19] FIG. 2 is a block diagram showing an example of a circuit configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings. In the following embodiments, the same components are designated by the same reference numerals, and duplicated descriptions will be omitted.

[0009] Conventionally, synchronous solid-state imaging devices that capture image data (frames) in synchronization with a synchronous signal such as a vertical synchronous signal have been used in imaging devices, etc. This general synchronous solid-state imaging device can only capture image data at synchronous signal intervals (e.g., 1 / 60 seconds), making it difficult to meet the demand for faster processing in fields related to traffic, robots, etc.

[0010] In response to this, an asynchronous solid-state imaging device has been proposed in which an address event detection circuit is provided for each pixel, which detects in real time, for each pixel address, the fact that the amount of light at that pixel exceeds a threshold value as an address event. In this solid-state imaging device, a photodiode and multiple transistors for detecting address events are provided for each pixel.

[0011] However, in the above conventional technology, the potential of areas other than the effective pixel area varies, causing fluctuations in the power supply voltage supplied to the effective pixels, which can cause the address event detection circuit to malfunction. In other words, in the above conventional technology, it is difficult to improve the quality of the signal output from the effective pixels.

[0012] Therefore, there is a need for a technology that can overcome the above-mentioned problems and improve the quality of signals output from effective pixels.

[0013] [Configuration of imaging device] First, a configuration of an imaging device 100 according to an embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of a configuration of the imaging device 100 according to an embodiment of the present disclosure.

[0014] The imaging device 100 according to the embodiment includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and a control unit 130. The imaging device 100 is assumed to be a camera mounted on a wearable device, an in-vehicle camera, or the like.

[0015] The imaging lens 110 is an example of an optical system, which takes in incident light from a subject and forms an image on the imaging surface of the solid-state imaging device 200 .

[0016] The solid-state imaging device 200 is also called a DVS (Dynamic Vision Sensor), and detects, as an address event, that the absolute value of the amount of change in luminance of each of a plurality of pixels has exceeded a threshold value. The address event includes, for example, an ON event indicating that the amount of increase in luminance has exceeded an upper threshold value, and an OFF event indicating that the amount of decrease in luminance has fallen below a lower threshold value that is less than the upper threshold value.

[0017] The solid-state imaging device 200 generates a detection signal indicating the detection result of the address event for each pixel. Each detection signal is an on-event detection signal V CH (See Figure 6) and the off-event detection signal V CL (See FIG. 6).

[0018] The solid-state imaging element 200 performs predetermined signal processing, such as image recognition processing, on image data formed from the detection signal, and outputs the processed data to the recording unit 120 via a signal line 209 .

[0019] The recording unit 120 records the data from the solid-state imaging element 200. The control unit 130 controls the solid-state imaging element 200 to cause the solid-state imaging element 200 to capture image data.

[0020] [Structure of solid-state imaging element] Next, the configuration of the solid-state imaging element 200 according to the embodiment will be described with reference to Fig. 2 to Fig. 10. Fig. 2 is a diagram for explaining the layered structure of the solid-state imaging element 200 according to the embodiment of the present disclosure.

[0021] A solid-state imaging element 200 according to the embodiment includes a circuit board 202 and a light receiving board 201 laminated on the circuit board 202. The light receiving board 201 and the circuit board 202 are electrically connected to each other through connecting parts such as vias, Cu-Cu joints, and bumps.

[0022] 3 is a diagram for explaining a planar configuration of the light-receiving substrate 201 according to the embodiment of the present disclosure. As shown in FIG. 3, the light-receiving substrate 201 has a light-receiving portion 210, a via arrangement portion 221, and a via arrangement portion 222.

[0023] In the light receiving section 210, a plurality of light receiving circuits 211 are arranged in a two-dimensional lattice. The light receiving circuits 211 perform photoelectric conversion of incident light to generate a photocurrent, and perform current-voltage conversion of the photocurrent to output a voltage signal. Each of the light receiving circuits 211 is assigned a pixel address consisting of a row address and a column address.

[0024] In the via arrangement portion 221 and the via arrangement portion 222, vias to be connected to the circuit board 202 (see FIG. 4) are arranged.

[0025] 4 is a diagram for explaining a planar configuration of the circuit board 202 according to the embodiment of the present disclosure. As shown in FIG. 4, the circuit board 202 includes an address event detection unit 230, a signal processing circuit 240, a row driving circuit 251, a column driving circuit 252, a via arrangement unit 261, and a via arrangement unit 262.

[0026] A plurality of address event detection circuits 231 are arranged in a two-dimensional lattice in the address event detection section 230. The address event detection circuit 231 quantizes the voltage signal from the light receiving circuit 211, and outputs the quantized voltage signal as a detection signal.

[0027] A pixel address is assigned to each of the address event detection circuits 231, and the address event detection circuits 231 are electrically connected to the light receiving circuits 211 at the same address. In the embodiment, the light receiving circuits 211 and the address event detection circuits 231 at the same address are disposed at the same position in a plan view.

[0028] The signal processing circuit 240 performs a predetermined signal processing on the detection signal from the address event detection unit 230. For example, the signal processing circuit 240 arranges the detection signal as a pixel signal in a two-dimensional lattice shape, and acquires image data having 2 bits of information for each pixel. Then, the signal processing circuit 240 performs signal processing such as image recognition processing on the acquired image data.

[0029] The row driving circuit 251 selects a row address, and outputs a detection signal corresponding to the selected row address to the address event detection unit 230. The column driving circuit 252 selects a column address, and outputs a detection signal corresponding to the selected column address to the address event detection unit 230. In the via arrangement unit 261 and the via arrangement unit 262, vias to be connected to the light receiving substrate 201 (see FIG. 3) are arranged.

[0030] 5 is a diagram for explaining the configuration of an effective pixel 310 according to an embodiment of the present disclosure. As shown in Fig. 5, each effective pixel 310 is composed of a light receiving circuit 211 in a light receiving substrate 201 and an address event detection circuit 231 in a circuit substrate 202, both of which are assigned the same pixel address.

[0031] As described above, a plurality of light receiving circuits 211 and a plurality of address event detection circuits 231 are arranged in a two-dimensional lattice pattern on the light receiving board 201 and the circuit board 202. Furthermore, the light receiving circuits 211 and the address event detection circuits 231 at the same address are disposed at the same position in a plan view.

[0032] That is, in the solid-state imaging element 200 according to the embodiment, effective pixels 310 each including a pair of a light receiving circuit 211 and an address event detection circuit 231 are arranged in a two-dimensional lattice pattern. The pair of the light receiving circuit 211 and the address event detection circuit 231 are electrically connected to each other at the joint 203 through a connection part such as a via, a Cu-Cu joint, or a bump.

[0033] 6 is a diagram showing a circuit configuration of an effective pixel 310 according to an embodiment of the present disclosure. As shown in FIG. 6, the effective pixel 310 includes a photodiode 311, a current-voltage conversion circuit 320, a buffer 330, a subtractor 340, a quantizer 350, and a transfer circuit 360.

[0034] In the embodiment of the present disclosure, among the components of the effective pixel 310, the photodiode 311 and the N-type transistors 321 and 322 of the current-voltage conversion circuit 320 are included in the light receiving circuit 211. Also, among the components of the effective pixel 310, the buffer 330, the subtractor 340, the quantizer 350, and the transfer circuit 360 are included in the address event detection circuit 231.

[0035] That is, in the embodiment of the present disclosure, the effective pixel 310 includes a photodiode 311 , a current-voltage conversion circuit 320 , and an address event detection circuit 231 .

[0036] The photodiode 311 performs photoelectric conversion on the incident light to generate a photocurrent. The photodiode 311 then supplies the generated photocurrent to the current-voltage conversion circuit 320.

[0037] The current-voltage conversion circuit 320 converts the photocurrent from the photodiode 311 into a logarithmic voltage signal. Then, the current-voltage conversion circuit 320 supplies the converted voltage signal to the buffer 330.

[0038] The buffer 330 corrects the voltage signal sent from the current-voltage conversion circuit 320, and outputs the corrected signal to the subtractor 340. In the effective pixel 310 according to the embodiment, the buffer 330 can improve the driving force for driving the subsequent stage, and can ensure isolation of noise associated with the switching operation of the subsequent stage.

[0039] The subtractor 340 performs subtraction processing to determine the amount of change in the correction signal sent from the buffer 330. The subtractor 340 then supplies the determined amount of change to the quantizer 350 as a differential signal.

[0040] The quantizer 350 converts (i.e., quantizes) the analog differential signal into a digital detection signal by comparing the differential signal with a predetermined threshold. The quantizer 350 according to the embodiment compares the differential signal with each of the upper and lower thresholds, and supplies the comparison results to the transfer circuit 360 as a 2-bit detection signal.

[0041] The transfer circuit 360 transfers the detection signal to the signal processing circuit 240 in accordance with the column driving signal from the column driving circuit 252 .

[0042] A specific circuit configuration of each part will be described below. Current-voltage conversion circuit 320 has N-type transistor 321, N-type transistor 322, and P-type transistor 323. N-type transistor 321, N-type transistor 322, and P-type transistor 323 may be, for example, MOS (Metal-Oxide-Semiconductor) transistors.

[0043] The source of N-type transistor 321 is connected to the cathode of photodiode 311, and the drain is connected to the terminal of power supply voltage VDD. The anode of photodiode 311 is connected to the terminal of ground potential. P-type transistor 323 and N-type transistor 322 are connected in series in this order between the terminal of power supply voltage VDD and the terminal of ground potential.

[0044] The connection point between the P-type transistor 323 and the N-type transistor 322 is connected to the gate of the N-type transistor 321 and the input terminal of the buffer 330. The connection point between the N-type transistor 321 and the photodiode 311 is connected to the gate of the N-type transistor 322. A predetermined bias voltage V blog is applied.

[0045] Then, N-type transistor 321 converts the photocurrent generated by photodiode 311 into a voltage between its gate and source, and N-type transistor 322 amplifies the voltage between its gate, which has a potential corresponding to the photocurrent, and its source, which has a ground potential, and outputs it from its drain.

[0046] In addition, the P-type transistor 323 is connected to the bias voltage V blog to N-type transistor 322. With this configuration, current-voltage conversion circuit 320 converts the photocurrent from photodiode 311 into a voltage signal.

[0047] In the solid-state imaging element 200 according to the embodiment, the photodiode 311, the N-type transistor 321, and the N-type transistor 322 are disposed on the light receiving substrate 201, and the P-type transistor 323 and subsequent circuits are disposed on the circuit substrate 202.

[0048] 7 is a diagram for explaining the configuration of an effective pixel 310 according to an embodiment of the present disclosure. As shown in Fig. 7, a photodiode 311 is embedded in a P-well region of a light receiving substrate 201, and a backgate of an N-type transistor 321 and a backgate of an N-type transistor 322 are formed.

[0049] A power supply voltage VDD is supplied to the drain of N-type transistor 321, and the potential of the P-well region (i.e., the anode of photodiode 311) and the potential of the source of N-type transistor 322 are ground potential. Furthermore, the P-well regions of adjacent effective pixels 310 are separated by pixel separation section 410 (see FIG. 8) formed in the portion indicated by the dashed dotted line.

[0050] Returning to the description of Fig. 6, buffer 330 has P-type transistor 331 and P-type transistor 332. P-type transistor 331 and P-type transistor 332 may be, for example, MOS transistors.

[0051] P-type transistor 331 and P-type transistor 332 are connected in series, in this order, between a terminal of a power supply voltage VDD and a terminal of a ground potential. A predetermined bias voltage V bsf The gate of P-type transistor 332 is connected to the output terminal of current-voltage conversion circuit 320.

[0052] With this configuration, buffer 330 outputs the corrected voltage signal from the connection point between P-type transistor 331 and P-type transistor 332 to subtractor 340 .

[0053] Subtractor 340 has a capacitor 341, a P-type transistor 342, a capacitor 343, a P-type transistor 344, and an N-type transistor 345. P-type transistor 342, P-type transistor 344, and N-type transistor 345 are, for example, MOS transistors.

[0054] The P-type transistor 344 and the N-type transistor 345 are connected in series in this order between a terminal of the power supply voltage VDD and a terminal of the reference potential. A predetermined bias voltage V ba is applied.

[0055] P-type transistor 344 and N-type transistor 345 function as an inverter that inverts and outputs an input signal, when the gate of P-type transistor 344 is an input terminal and the connection point between P-type transistor 344 and N-type transistor 345 is an output terminal.

[0056] One end of capacitor 341 is connected to the output terminal of buffer 330, and the other end is connected to the input terminal of the inverter (i.e., the gate of P-type transistor 344). One end of capacitor 343 is connected to the input terminal of the inverter, and the other end is connected to the output terminal of the inverter (i.e., the connection point between P-type transistor 344 and N-type transistor 345).

[0057] The P-type transistor 342 opens and closes the path connecting both ends of the capacitor 343 in accordance with a row drive signal output from the row drive circuit 251 .

[0058] When the P-type transistor 342 is turned on, a voltage signal V init is input, and the opposite side becomes a virtual ground terminal. For convenience, the potential of this virtual ground terminal is set to zero.

[0059] At this time, the charge Q stored in the capacitor 341 init If the capacitance of capacitor 341 is C1, then this is expressed by the following equation (1): On the other hand, both ends of capacitor 343 are short-circuited, so that the stored charge therein is zero. Q init =C1×V init (1)

[0060] Next, P-type transistor 342 is turned off, and the voltage on the buffer 330 side of capacitor 341 changes to V after If we consider the case where the charge Q stored in the capacitor 341 becomes after is expressed by the following equation (2). Q after =C1×V after (2)

[0061] On the other hand, the charge Q2 stored in the capacitor 343 increases the capacitance of the capacitor 343 to C2 and the output voltage to V out Then, it is expressed by the following equation (3). Q2=-C2×V out (3)

[0062] In this case, since the total charge amount of the capacitors 341 and 343 does not change, the following equation (4) holds. Q init =Q after +Q2 ··(4)

[0063] Then, by substituting equations (1) to (3) into the above equation (4) and transforming it, the following equation (5) is obtained. Vout =-(C1 / C2)×(V after -V init ) ··(5)

[0064] The above equation (5) represents the subtraction operation of a voltage signal, and the gain of the subtraction result is C1 / C2. Since it is usually desired to maximize the gain, it is preferable to design the capacitance C1 to be large and the capacitance C2 to be small. On the other hand, if the capacitance C2 is too small, the kTC noise increases and there is a risk of deteriorating noise characteristics, so the reduction in the capacitance C2 is limited to a range where noise can be tolerated.

[0065] Furthermore, since the subtractor 340 is mounted for each effective pixel 310, there are area restrictions on the capacitance C1 and capacitance C2. Taking these into consideration, for example, the capacitance C1 is set to a value of 20 to 200 femtofarads (fF), and the capacitance C2 is set to a value of 1 to 20 femtofarads (fF).

[0066] Quantizer 350 has a P-type transistor 351, an N-type transistor 352, a P-type transistor 353, and an N-type transistor 354. P-type transistor 351, N-type transistor 352, P-type transistor 353, and N-type transistor 354 are, for example, MOS transistors.

[0067] P-type transistor 351 and N-type transistor 352 are connected in series in this order between a terminal of power supply voltage VDD and a terminal of ground potential. P-type transistor 353 and N-type transistor 354 are connected in series in this order between a terminal of power supply voltage VDD and a terminal of reference potential.

[0068] The gates of P-type transistors 351 and 353 are connected to the output terminal of subtractor 340. A bias voltage V bon is applied to the gate of the N-type transistor 354, and a bias voltage V boff is applied.

[0069] The connection point of the P-type transistor 351 and the N-type transistor 352 is connected to the transfer circuit 360. In the quantizer 350, the voltage at this connection point is converted into the on-event detection signal V CH to the transfer circuit 360.

[0070] The connection point of the P-type transistor 353 and the N-type transistor 354 is connected to the transfer circuit 360. In the quantizer 350, the voltage at this connection point is converted into the off-event detection signal V CL will be output as:

[0071] With this configuration, the quantizer 350 outputs a high-level on-event detection signal V CH When the differential signal falls below the lower threshold, a low-level off-event detection signal V CL That is, the solid-state imaging device 200 according to the embodiment can simultaneously detect the presence or absence of both an ON event and an OFF event.

[0072] Fig. 8 is a diagram showing a cross-sectional configuration of a solid-state imaging element 200 according to an embodiment of the present disclosure, and mainly shows the cross-sectional structure of the peripheral portion of the solid-state imaging element 200. As shown in Fig. 8, the solid-state imaging element 200 has an effective pixel region R1, a dummy pixel region R2, a power supply region R3, and a pad region R4. The effective pixel region R1 is an example of a first region, and the dummy pixel region R2 is an example of a second region.

[0073] The effective pixel region R1 is a region in which the laminated light receiving section 210 and address event detection section 230 are provided. In the effective pixel region R1, a plurality of effective pixels 310 are arranged in a two-dimensional lattice pattern.

[0074] As shown in Fig. 9, the dummy pixel region R2 is a region provided so as to surround the effective pixel region R1 on all four sides. Fig. 9 is a diagram showing a planar configuration of a solid-state imaging element 200 according to an embodiment of the present disclosure.

[0075] 8, a plurality of dummy pixels 310A are arranged in the dummy pixel region R2. The dummy pixels 310A have the same basic configuration as the effective pixels 310, but do not output a signal to the outside. The dummy pixels 310A will be described in detail later.

[0076] In the solid-state imaging device 200 according to the embodiment, the dummy pixel region R2 is formed so as to surround the four sides of the effective pixel region R1, thereby ensuring the regularity of the process from the center to the edge of the effective pixel region R1. Therefore, according to the embodiment, the manufacturing yield of the solid-state imaging device 200 can be improved.

[0077] 9, the power supply region R3 is a region provided so as to surround the dummy pixel region R2 on all four sides. The power supply region R3 includes a ground wiring 421 to which a ground potential is applied from the outside, a power wiring 422 to which a power supply voltage VDD is applied from the outside, and a substrate voltage V SUB and a power supply wiring 423 to which a voltage is applied. The ground wiring 421 and the power supply wirings 422, 423 are formed, for example, in a ring shape around the dummy pixel region R2.

[0078] The ground wiring 421 supplies a ground potential to the effective pixels 310, etc. The power supply wiring 422 supplies a power supply voltage VDD to the effective pixels 310, etc. The power supply wiring 423 supplies a substrate voltage V, which has the same potential as the power supply voltage VDD, to the portions of the solid-state imaging device 200 other than the effective pixel region R1 and the dummy pixel region R2. SUB supplies.

[0079] In the solid-state imaging device 200 according to the embodiment, a power supply wiring 423 is provided in addition to the power supply wiring 422, so that even if the power supply voltage VDD fluctuates when the effective pixels 310 are in operation, a stable substrate voltage V SUB can be supplied to the peripheral portion of the solid-state imaging element 200. Therefore, according to the embodiment, the solid-state imaging element 200 can be operated stably.

[0080] Returning to the explanation of Fig. 8, the pad region R4 is a region provided around the power supply region R3, and has a contact hole 424 and a bonding pad 425. The contact hole 424 is formed along the thickness direction of the light receiving substrate 201 and the circuit substrate 202 from the light incident side surface of the light receiving substrate 201 to the middle of the circuit substrate 202.

[0081] The bonding pad 425 is provided at the bottom of the contact hole 424. In the embodiment, a bonding wire or the like is joined to the bonding pad 425 through the contact hole 424, thereby electrically connecting the recording unit 120 (see FIG. 1) or the control unit 130 (see FIG. 1) to each unit of the solid-state imaging element 200.

[0082] The configuration of the effective pixels 310 arranged in the effective pixel region R1 will be further described with reference to Fig. 8. The solid-state imaging element 200 is configured by laminating a light receiving substrate 201 and a circuit substrate 202, and a bonding portion 203 is provided at the interface between the light receiving substrate 201 and the circuit substrate 202.

[0083] The light receiving substrate 201 has a semiconductor layer 201a and an insulating layer 201b. The semiconductor layer 201a is made of a semiconductor material such as silicon. In the semiconductor layer 201a, a photodiode 311, an N-type transistor 321 (see FIG. 7), an N-type transistor 322 (see FIG. 7), and the like are formed for each of the effective pixels 310 and the dummy pixels 310A.

[0084] Furthermore, in the semiconductor layer 201a, a pixel separator 410 is formed so as to separate adjacent effective pixels 310 and dummy pixels 310A from each other. The pixel separator 410 electrically and optically separates adjacent effective pixels 310 and dummy pixels 310A from each other.

[0085] The pixel separation sections 410 are formed, for example, so as to surround the effective pixels 310 and the dummy pixels 310A individually and to penetrate the semiconductor layer 201a.

[0086] A planarization film 411 is formed on the light incident surface of the semiconductor layer 201a, and an on-chip lens 412 is formed on the light incident surface of the planarization film 411. The planarization film 411 planarizes the surface on which the on-chip lens 412 is mounted.

[0087] The on-chip lenses 412 are provided, for example, individually for the effective pixels 310 and the dummy pixels 310A, and collect incident light and guide it to the effective pixels 310 and the dummy pixels 310A.

[0088] The insulating layer 201b is made of silicon oxide (SiO x The insulating layer 202 is made of an insulating material such as silicon nitride (SiN) or silicon oxynitride (SiON), and is provided on the surface of the semiconductor layer 201a opposite to the light incident side.

[0089] Further, in the insulating layer 201b, a wiring section 401 composed of a wiring layer, vias, etc. The wiring section 401 is electrically connected to the photodiode 311, the N-type transistor 321, and the N-type transistor 322 provided in the semiconductor layer 201a by the wiring configuration shown in FIG.

[0090] The wiring portion 401 is electrically connected to the first pad 403 through the via 402. The first pad 403 is exposed on the surface of the light receiving substrate 201 opposite to the light incident surface (i.e., the interface with the circuit substrate 202), and is made of copper or a copper alloy.

[0091] The circuit board 202 has an insulating layer 202a on the interface side with the light-receiving board 201. The insulating layer 202a is made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0092] Furthermore, insulating layer 202a has second pad 404. Second pad 404 is provided exposed on the light incident surface of circuit board 202 (that is, the interface with light receiving board 201), and is made of copper or a copper alloy.

[0093] The second pad 404 is electrically connected to the wiring portion 406 through the via 405. The wiring portion 406 is electrically connected to the gate of the P-type transistor 332 (see FIG. 6) and the source of the P-type transistor 323 (see FIG. 6). In the embodiment, the first pad 403 and the second pad 404 are directly bonded by Cu-Cu bonding.

[0094] FIG. 10 is a diagram showing a circuit configuration of the effective pixel 310 and the dummy pixel 310A according to an embodiment of the present disclosure.

[0095] As described above, in the effective pixel 310 arranged in the effective pixel region R1, the photocurrent generated in the photodiode 311 is converted into a voltage signal by the current-voltage conversion circuit 320, and the voltage signal is output to the address event detection circuit 231. The photodiode 311 arranged in the effective pixel region R1 is an example of a first photoelectric conversion element.

[0096] On the other hand, in the dummy pixel 310A arranged in the dummy pixel region R2, an address event detection signal (ON event detection signal V CH and off-event detection signal V CL ) is suppressed. The photodiode 311A ​​disposed in the dummy pixel region R2 is an example of a second photoelectric conversion element.

[0097] For example, as shown in FIG. 10, in a current-voltage conversion circuit 320A belonging to a dummy pixel 310A, the terminals of an N-type transistor 321A and an N-type transistor 322A are all shorted, and the potentials of these terminals are fixed to the power supply voltage VDD.

[0098] Here, N-type transistor 321A of current-voltage conversion circuit 320A is a transistor corresponding to N-type transistor 321 of current-voltage conversion circuit 320. Also, N-type transistor 322A of current-voltage conversion circuit 320A is a transistor corresponding to N-type transistor 322 of current-voltage conversion circuit 320.

[0099] Furthermore, the terminals of N-type transistor 321A and N-type transistor 322A are short-circuited by a first layer metal wiring formed on insulating layer 201b, for example, as shown in FIG.

[0100] In this way, since the potentials of the terminals of the N-type transistors 321A, 322A are fixed, the current-voltage conversion circuit 320A belonging to the dummy pixel 310A can suppress the output of an address event detection signal based on the photocurrent from the photodiode 311A.

[0101] In the embodiment, the output of the address event detection signal from the dummy pixel 310A is suppressed, so that it is possible to suppress fluctuations in the power supply voltage VDD caused by the operation of the dummy pixel 310A.

[0102] This suppresses fluctuations in the power supply voltage VDD supplied to the quantizer 350 (see FIG. 6) of the effective pixel 310, thereby preventing the quantizer 350 from malfunctioning due to fluctuations in the power supply voltage VDD and outputting an erroneous address event detection signal.

[0103] Therefore, according to the embodiment, the quality of the address event detection signal output from the effective pixel 310 can be improved.

[0104] In the embodiment, the means for fixing the potential of the current-voltage conversion circuit 320A belonging to the dummy pixel 310A is not limited to supplying the power supply voltage VDD to each terminal of the N-type transistors 321A and 322A.

[0105] For example, a predetermined voltage may be supplied from an external power supply (not shown) to each terminal of N-type transistors 321A and 322A to fix the potential of current-voltage conversion circuit 320A.

[0106] This also suppresses fluctuations in the power supply voltage VDD supplied to the quantizer 350 of the effective pixel 310, thereby preventing the quantizer 350 from malfunctioning due to fluctuations in the power supply voltage VDD and outputting an erroneous address event detection signal.

[0107] Therefore, according to the embodiment, the quality of the address event detection signal output from the effective pixel 310 can be improved.

[0108] In the embodiment, the means for suppressing the output of the address event detection signal based on the photocurrent from the photodiode 311A ​​is not limited to fixing the potential of the current-voltage conversion circuit 320A.

[0109] For example, the potential of the address event detection circuit 231A belonging to the dummy pixel 310A may be fixed to suppress the output of the address event detection signal based on the photocurrent from the photodiode 311A.

[0110] This also suppresses fluctuations in the power supply voltage VDD supplied to the quantizer 350 of the effective pixel 310, thereby preventing the quantizer 350 from malfunctioning due to fluctuations in the power supply voltage VDD and outputting an erroneous address event detection signal.

[0111] Therefore, according to the embodiment, the quality of the address event detection signal output from the effective pixel 310 can be improved.

[0112] In addition, in the embodiment, the potential of the current-voltage conversion circuit 320A and the potential of the address event detection circuit 231A may both be fixed to suppress the output of the address event detection signal based on the photocurrent from the photodiode 311A.

[0113] In addition, in the embodiment, the output of the address event detection signal based on the photocurrent from the photodiode 311A ​​may be suppressed by a means other than fixing the potential of the current-voltage conversion circuit 320A or the address event detection circuit 231A.

[0114] In the embodiment, the potential of the power supply region R3 may be fixed. For example, in the embodiment, as shown in FIG. 8, the potential of the power supply region R3 can be fixed by electrically connecting the semiconductor layer 201a located in the power supply region R3 to the ground wiring 421.

[0115] In the embodiment, by fixing the potential of the power supply domain R3, it is possible to suppress fluctuations in the potential of the power supply wiring 422 located in the power supply domain R3 (that is, the power supply voltage VDD).

[0116] This suppresses fluctuations in the power supply voltage VDD supplied to the quantizer 350 of the effective pixel 310, thereby preventing the quantizer 350 from malfunctioning due to fluctuations in the power supply voltage VDD and outputting an erroneous address event detection signal.

[0117] Therefore, according to the embodiment, it is possible to improve the quality of the address event detection signal output from the effective pixel 310. Note that the potential of the power supply domain R3 is not limited to being fixed to the ground potential, and may be fixed by a power supply voltage, an external power supply, or the like.

[0118] In addition, in the embodiment, it is preferable that the inside of the power supply region R3 is not separated by the pixel separation portion 410. That is, in the embodiment, it is preferable that the power supply region R3 is configured as an electrically integrated region.

[0119] This makes it possible to easily fix the potential of the entire power supply region R3. Therefore, according to the embodiment, it is possible to easily prevent the potential of the power supply wiring 422 located in the power supply region R3 from fluctuating.

[0120] [Various variations] Next, various modified examples of the embodiment will be described with reference to Fig. 11 to Fig. 15. Fig. 11 is a diagram showing a cross-sectional configuration of a solid-state imaging element 200 according to Modification 1 of the embodiment of the present disclosure, and corresponds to Fig. 8 of the embodiment.

[0121] As shown in FIG. 11, the terminals of N-type transistor 321A (see FIG. 10) and N-type transistor 322A (see FIG. 10) provided in dummy pixel 310A may be short-circuited by a second layer metal wiring formed in insulating layer 201b.

[0122] Fig. 12 is a diagram showing a planar configuration of a solid-state imaging element 200 according to Modification 2 of the embodiment of the present disclosure, and corresponds to Fig. 9 of the embodiment. As shown in Fig. 12, in Modification 2, a dummy pixel region R2 is provided so as to surround all four sides of the effective pixel region R1, and a power supply region R3 is provided so as to surround three sides of the dummy pixel region R2.

[0123] Fig. 13 is a diagram showing a planar configuration of a solid-state imaging element 200 according to Modification 3 of the embodiment of the present disclosure. As shown in Fig. 13, in Modification 3, a dummy pixel region R2 is provided so as to surround all four sides of an effective pixel region R1, and a power supply region R3 is provided along two sides of the dummy pixel region R2.

[0124] Fig. 14 is a diagram showing a planar configuration of a solid-state imaging element 200 according to Modification 4 of the embodiment of the present disclosure. As shown in Fig. 14, in Modification 4, a dummy pixel region R2 is provided so as to surround all four sides of an effective pixel region R1, and a power supply region R3 is provided along one side of the dummy pixel region R2.

[0125] FIG. 15 is a diagram showing a circuit configuration of an effective pixel 310 according to a fifth modification of the embodiment of the present disclosure, and shows a quantizer 350 that detects the presence or absence of a selected on-event or off-event.

[0126] Quantizer 350 according to the fifth modification includes a P-type transistor 351, an N-type transistor 352, and a switch 355. P-type transistor 351 and N-type transistor 352 are connected in series in this order between a terminal for a power supply voltage VDD and a terminal for a ground potential.

[0127] The gate of P-type transistor 351 is connected to the output terminal of subtractor 340. The gate of N-type transistor 352 is connected to switch 355.

[0128] Then, the control unit 130 switches the switch 355 to apply a bias voltage V bon or the bias voltage V that indicates the lower threshold boff A connection point 356 of the P-type transistor 351 and the N-type transistor 352 is connected to a transfer circuit 360.

[0129] A bias voltage V bon is applied, in the quantizer 350 according to the fifth modification, the voltage at the connection point 356 is the on-event detection signal V CH to the transfer circuit 360.

[0130] On the other hand, a bias voltage V boff is applied, in the quantizer 350 according to the fifth modification, the voltage at the connection point 356 is the off-event detection signal V CL to the transfer circuit 360.

[0131] With this configuration, the quantizer 350 according to the fifth modification generates a high-level on-event detection signal V when the differential signal exceeds the upper limit threshold value in a case where an on-event is selected by the control unit 130. CH Output.

[0132] On the other hand, in the quantizer 350 according to the fifth modification, when an off-event is selected by the control unit 130, if the differential signal falls below the lower limit threshold, the quantizer 350 outputs a low-level off-event detection signal V CL Output.

[0133] For example, in the solid-state imaging device 200 according to the fifth modification, when a light source (not shown) is turned on by a command from the control unit 130 or the like, the control unit 130 selects an on-event, and generates an on-event detection signal V CH can be output efficiently.

[0134] In the solid-state imaging device 200 according to the fifth modification, when a light source (not shown) is turned off by a command from the control unit 130 or the like, the control unit 130 selects an off event, so that an off event detection signal V CL can be output efficiently.

[0135] In the fifth modification example described above, the number of transistors constituting the quantizer 350 can be reduced, so that the chip area of ​​the solid-state imaging element 200 can be reduced and the power consumption of the solid-state imaging element 200 can be reduced.

[0136] [effect] The solid-state imaging device 200 according to the embodiment includes a plurality of first photoelectric conversion elements (photodiodes 311), a plurality of second photoelectric conversion elements (photodiodes 311A), a plurality of current-voltage conversion circuits 320, 320A, and a plurality of address event detection circuits 231, 231A. The plurality of first photoelectric conversion elements (photodiodes 311) are arranged side by side in a first region (effective pixel region R1). The plurality of second photoelectric conversion elements (photodiodes 311A) are arranged side by side in a second region (dummy pixel region R2) adjacent to the first region (effective pixel region R1). The plurality of current-voltage conversion circuits 320, 320A convert currents output from the plurality of first photoelectric conversion elements (photodiodes 311) and the plurality of second photoelectric conversion elements (photodiodes 311A) into voltages, respectively. The plurality of address event detection circuits 231, 231A detect changes in voltages output from the plurality of current-voltage conversion circuits 320, 320A, respectively. At least one of the current-voltage conversion circuit 320A and the address event detection circuit 231A connected to the second photoelectric conversion element (photodiode 311A) suppresses the output of a signal based on the current output from the second photoelectric conversion element.

[0137] This makes it possible to improve the quality of the address event detection signal output from the effective pixel 310.

[0138] In the solid-state imaging element 200 according to the embodiment, the second region (dummy pixel region R2) is provided so as to surround the first region (effective pixel region R1).

[0139] This makes it possible to improve the manufacturing yield of the solid-state imaging device 200.

[0140] In the solid-state imaging device 200 according to the embodiment, at least one of the current-voltage conversion circuit 320A and the address event detection circuit 231A connected to the second photoelectric conversion element (photodiode 311A) has a fixed internal potential.

[0141] This makes it possible to suppress the output of the address event detection signal based on the photocurrent output from the photodiode 311A.

[0142] In the solid-state imaging device 200 according to the embodiment, the current-voltage conversion circuit 320A connected to the second photoelectric conversion element (photodiode 311A) has a plurality of transistors (N-type transistors 321A, 322A). The plurality of transistors (N-type transistors 321A, 322A) are short-circuited, so that the potential in the current-voltage conversion circuit 320A connected to the second photoelectric conversion element (photodiode 311A) is fixed.

[0143] This makes it possible to suppress the output of the address event detection signal based on the photocurrent output from the photodiode 311A.

[0144] In the solid-state imaging device 200 according to the embodiment, at least one of the current-voltage conversion circuit 320A and the address event detection circuit 231A connected to the second photoelectric conversion element (photodiode 311A) has an internal potential fixed by an external voltage.

[0145] This makes it possible to suppress the output of the address event detection signal based on the photocurrent output from the photodiode 311A.

[0146] Moreover, the solid-state imaging element 200 according to the embodiment further includes a power supply region R3 that is provided outside the second region (dummy pixel region R2) and in which power supply wirings 422 and 423 and a ground wiring 421 are formed.

[0147] This makes it possible to improve the quality of the address event detection signal output from the effective pixel 310.

[0148] In the solid-state imaging device 200 according to the embodiment, the internal potential of the power supply region R3 is fixed.

[0149] This makes it possible to suppress fluctuations in the potential of the power supply wiring 422 located in the power supply domain R3 (that is, the power supply voltage VDD).

[0150] In the solid-state imaging device 200 according to the embodiment, the power supply region R3 is electrically configured as a single unit.

[0151] This makes it possible to easily prevent fluctuations in the potential of the power supply wiring 422 located in the power supply region R3.

[0152] [Second configuration example of the address event detector] Fig. 16 is a block diagram showing a second configuration example of the address event detection section 1000. As shown in Fig. 16, the address event detection section 1000 according to this configuration example has a storage section 1336 and a control section 1337 in addition to a current-voltage conversion section 1331, a buffer 1332, a subtractor 1333, a quantizer 1334, and a transfer section 1335.

[0153] The storage unit 1336 is provided between the quantizer 1334 and the transfer unit 1335, and accumulates the output of the quantizer 1334, i.e., the comparison result of the comparator 1334a, based on a sample signal supplied from the control unit 1337. The storage unit 1336 may be a sampling circuit such as a switch, a plastic, or a capacitor, or may be a digital memory circuit such as a latch or a flip-flop.

[0154] The control unit 1337 supplies a predetermined threshold voltage Vth to the inverting (-) input terminal of the comparator 1334a. The threshold voltage Vth supplied from the control unit 1337 to the comparator 1334a may have different voltage values ​​in a time-division manner. For example, the control unit 1337 supplies a threshold voltage Vth1 corresponding to an ON event indicating that the amount of change in the photocurrent has exceeded an upper threshold, and a threshold voltage Vth2 corresponding to an OFF event indicating that the amount of change has fallen below a lower threshold, at different timings, thereby enabling detection of multiple types of address events with one comparator 1334a.

[0155] For example, the storage unit 1336 may accumulate a comparison result of the comparator 1334a using the threshold voltage Vth1 corresponding to an ON event during a period in which the threshold voltage Vth2 corresponding to an OFF event is supplied from the control unit 1337 to the inverting (-) input terminal of the comparator 1334a. The storage unit 1336 may be located inside the pixel 2030 (see FIG. 17) or outside the pixel 2030. The storage unit 1336 is not an essential component of the address event detection unit 1000. That is, the storage unit 1336 may be omitted.

[0156] [Imaging device according to the second configuration example (scanning method)] The imaging device 100 according to the first configuration example described above is an asynchronous imaging device that reads out events by an asynchronous readout method. However, the event readout method is not limited to the asynchronous readout method, and may be a synchronous readout method. An imaging device to which the synchronous readout method is applied is a scanning imaging device, the same as a normal imaging device that captures images at a predetermined frame rate.

[0157] FIG. 17 is a block diagram showing an example of the configuration of an imaging device according to the second configuration example, that is, a scanning type imaging device, used as the imaging device 2000 in an imaging system to which the technology according to the present disclosure is applied.

[0158] As shown in FIG. 17, an imaging device 2000 according to a second configuration example as an imaging device of the present disclosure includes a pixel array section 2021, a driving section 2022, a signal processing section 2025, a readout area selection section 2027, and a signal generation section 2028.

[0159] The pixel array unit 2021 includes a plurality of pixels 2030. The plurality of pixels 2030 output an output signal in response to a selection signal from the readout region selection unit 2027. Each of the plurality of pixels 2030 may be configured to have a quantizer comparator within the pixel. The plurality of pixels 2030 output an output signal corresponding to the amount of change in light intensity. The plurality of pixels 2030 may be two-dimensionally arranged in a matrix as shown in FIG. 17.

[0160] The driving unit 2022 drives each of the multiple pixels 2030 to output a pixel signal generated in each pixel 2030 to the signal processing unit 2025. The driving unit 2022 and the signal processing unit 2025 are circuit units for acquiring gradation information. Therefore, when only event information is acquired, the driving unit 2022 and the signal processing unit 2025 may not be provided.

[0161] The readout region selection unit 2027 selects a part of the multiple pixels 2030 included in the pixel array unit 2021. Specifically, the readout region selection unit 2027 determines the selection region in response to a request from each pixel 2030 of the pixel array unit 2021. For example, the readout region selection unit 2027 selects any one or more rows among the rows included in the two-dimensional matrix structure corresponding to the pixel array unit 2021. The readout region selection unit 2027 sequentially selects one or more rows according to a preset period. The readout region selection unit 2027 may also determine the selection region in response to a request from each pixel 2030 of the pixel array unit 2021.

[0162] The signal generating unit 2028 generates an event signal corresponding to an active pixel that detects an event among the selected pixels, based on the output signal of the pixel selected by the readout region selecting unit 2027. An event is an event in which the intensity of light changes. An active pixel is a pixel in which the amount of change in the intensity of light corresponding to the output signal exceeds or falls below a preset threshold. For example, the signal generating unit 2028 compares the output signal of the pixel with a reference signal, detects an active pixel that outputs an output signal when the output signal is greater or smaller than the reference signal, and generates an event signal corresponding to the active pixel.

[0163] The signal generation unit 2028 may be configured to include, for example, a column selection circuit that arbitrates signals coming into the signal generation unit 2028. The signal generation unit 2028 may be configured to output not only information about active pixels that detect an event, but also information about inactive pixels that do not detect an event.

[0164] Address information and time stamp information (e.g., (X, Y, T)) of an active pixel in which an event is detected are output from the signal generating unit 2028 through an output line 2015. However, the data output from the signal generating unit 2028 may be not only address information and time stamp information but also frame format information (e.g., (0, 0, 1, 0,...)).

[0165] [Range measurement system] The distance measuring system according to the embodiment of the present disclosure is a system for measuring the distance to a subject using a structured light technique. The distance measuring system according to the embodiment of the present disclosure can also be used as a system for acquiring a three-dimensional (3D) image, and in this case, can be called a three-dimensional image acquisition system. In the structured light method, distance measurement is performed by identifying the coordinates of a point image and the light source (so-called point light source) from which the point image is projected by pattern matching.

[0166] FIG. 18 is a schematic diagram showing an example of the configuration of a distance measuring system according to an embodiment of the present disclosure, and FIG. 19 is a block diagram showing an example of a circuit configuration.

[0167] The distance measuring system 3000 according to this embodiment uses a surface emitting semiconductor laser, for example, a vertical cavity surface emitting laser (VCSEL) 3010 as a light source unit, and an event detection sensor 3020 called a DVS as a light receiving unit. The vertical cavity surface emitting laser (VCSEL) 3010 projects a predetermined pattern of light onto a subject. In addition to the vertical cavity surface emitting laser 3010 and the event detection sensor 3020, the distance measuring system 3000 according to this embodiment includes a system control unit 3030, a light source driving unit 3040, a sensor control unit 3050, a light source side optical system 3060, and a camera side optical system 3070.

[0168] The system control unit 3030 is configured by, for example, a processor (CPU), and drives the vertical cavity surface emitting laser 3010 via the light source driving unit 3040, and drives the event detection sensor 3020 via the sensor control unit 3050. More specifically, the system control unit 3030 controls the vertical cavity surface emitting laser 3010 and the event detection sensor 3020 in synchronization with each other.

[0169] In the distance measuring system 3000 according to the present embodiment having the above configuration, light of a predetermined pattern emitted from the vertical cavity surface emitting laser 3010 is projected onto the subject (measurement target) 3100 through the light source side optical system 3060. This projected light is reflected by the subject 3100. Then, the light reflected by the subject 3100 is incident on the event detection sensor 3020 through the camera side optical system 3070. The event detection sensor 3020 receives the light reflected by the subject 3100, and detects that a luminance change of a pixel exceeds a predetermined threshold as an event. Event information detected by the event detection sensor 3020 is supplied to an application processor 3200 outside the distance measuring system 3000. The application processor 3200 performs a predetermined process on the event information detected by the event detection sensor 3020.

[0170] Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present disclosure. In addition, components of different embodiments and modifications may be appropriately combined.

[0171] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0172] The present technology can also be configured as follows. (1) A plurality of first photoelectric conversion elements arranged side by side in a first region; a plurality of second photoelectric conversion elements arranged side by side in a second region adjacent to the first region; a plurality of current-voltage conversion circuits that convert currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages; a plurality of address event detection circuits each detecting a change in voltage output from the plurality of current-voltage conversion circuits; Equipped with At least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element suppresses output of a signal based on a current output from the second photoelectric conversion element. Solid-state imaging element. (2) The second region is provided so as to surround the first region. The solid-state imaging device according to (1) above. (3) At least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element has an internal potential fixed. The solid-state imaging device according to (1) or (2). (4) the current-voltage conversion circuit connected to the second photoelectric conversion element has a plurality of transistors; By shorting the plurality of transistors, a potential in the current-voltage conversion circuit connected to the second photoelectric conversion element is fixed. The solid-state imaging device according to (3) above. (5) At least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element has an internal potential fixed by an external voltage. The solid-state imaging device according to (3) above. (6) a power supply region provided outside the second region and in which a power supply wiring and a ground wiring are formed The solid-state imaging device according to any one of (1) to (5) above. (7) The power supply area has a fixed internal potential. The solid-state imaging device according to (6) above. (8) The power supply area is electrically integrated. The solid-state imaging device according to (6) or (7) above. (9) A solid-state imaging element; an optical system that captures incident light from a subject and forms an image on an imaging surface of the solid-state imaging device; A control unit that controls the solid-state imaging element, The solid-state imaging device includes: A plurality of first photoelectric conversion elements arranged side by side in a first region; a plurality of second photoelectric conversion elements arranged side by side in a second region adjacent to the first region; a plurality of current-voltage conversion circuits that convert currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages; a plurality of address event detection circuits each detecting a change in voltage output from the plurality of current-voltage conversion circuits; having At least one of the current-voltage conversion circuit and the address event detection circuit suppresses output of a signal based on a current output from the plurality of second photoelectric conversion elements. Imaging device. (10) The second region is provided so as to surround the first region. The imaging device according to (9) above. (11) At least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element has an internal potential fixed. The imaging device according to (9) or (10) above. (12) the current-voltage conversion circuit connected to the second photoelectric conversion element has a plurality of transistors; By shorting the plurality of transistors, a potential in the current-voltage conversion circuit connected to the second photoelectric conversion element is fixed. The imaging device according to (11) above. (13) At least one of the current-voltage conversion circuit and the address event detection circuit connected to the second photoelectric conversion element has an internal potential fixed by an external voltage. The imaging device according to (11) above. (14) a power supply region provided outside the second region and in which a power supply wiring and a ground wiring are formed The imaging device according to any one of (9) to (13) above. (15) The power supply area has a fixed internal potential. The imaging device according to (14) above. (16) The power supply area is electrically integrated. The imaging device according to (14) or (15) above. [Explanation of symbols]

[0173] 100 Imaging device 110 Imaging lens (an example of an optical system) 130 Control section 200 Solid-state image sensor 231, 231A Address event detection circuit 310 effective pixels 310A Dummy pixel 311 Photodiode (an example of a first photoelectric conversion element) 311A Photodiode (an example of a second photoelectric conversion element) 320, 320A Current to voltage conversion circuit 421 Ground wiring 422, 423 power wiring R1: Effective pixel area (an example of the first area) R2 Dummy pixel area (an example of the second area) R3 power supply area

Claims

1. A plurality of first photoelectric conversion elements arranged side by side in a first region; a plurality of second photoelectric conversion elements arranged side by side in a second region adjacent to the first region; a plurality of current-voltage conversion circuits for converting currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages; a plurality of address event detection circuits each detecting a change in voltage output from the plurality of current-voltage conversion circuits; Equipped with the current-voltage conversion circuit connected to the second photoelectric conversion element has a plurality of transistors; a potential in the current-voltage conversion circuit connected to the second photoelectric conversion element is fixed by shorting the plurality of transistors; The current-voltage conversion circuit connected to the second photoelectric conversion element suppresses output of a signal based on a current output from the second photoelectric conversion element. Solid-state imaging element.

2. The second region is provided so as to surround the first region. The solid-state imaging device according to claim 1 .

3. a power supply region provided outside the second region and in which a power supply wiring and a ground wiring are formed 3. The solid-state imaging device according to claim 1.

4. The power supply area has a fixed internal potential. The solid-state imaging device according to claim 3 .

5. The power supply area is electrically integrated. The solid-state imaging device according to claim 3 .

6. A solid-state imaging element; an optical system that captures incident light from a subject and forms an image on an imaging surface of the solid-state imaging device; A control unit that controls the solid-state imaging element, The solid-state imaging device includes: A plurality of first photoelectric conversion elements arranged side by side in a first region; a plurality of second photoelectric conversion elements arranged side by side in a second region adjacent to the first region; a plurality of current-voltage conversion circuits for converting currents output from the plurality of first photoelectric conversion elements and the plurality of second photoelectric conversion elements into voltages; a plurality of address event detection circuits each detecting a change in voltage output from the plurality of current-voltage conversion circuits; having the current-voltage conversion circuit connected to the second photoelectric conversion element has a plurality of transistors; a potential in the current-voltage conversion circuit connected to the second photoelectric conversion element is fixed by shorting the plurality of transistors; The current-voltage conversion circuit connected to the second photoelectric conversion element suppresses output of a signal based on a current output from the second photoelectric conversion element. Imaging device.

Images