Photoelectric conversion device, photoelectric conversion system, mobile object

Abstract

To provide a photoelectric conversion device, a photoelectric conversion system, and a mobile body, where correction processing corresponding to an amplification factor set to an amplifier circuit depending on the magnitude of a pixel signal is preferably performed.SOLUTION: A switch SW6 is turned off in a blanking period, which separates an output line 103 from a pixel 101. A setting circuit 302 outputs, to a voltage output circuit 111, test voltage values V1 and V2 corresponding to combination setting of amplification factors of an amplifier circuit of a row circuit unit 104. The amplifier circuit amplifies the test voltage values V1 and V2 at an amplification factor of four times and one time to output a voltage value V1C4 obtained by amplifying the test voltage value V1 by four times, a voltage value V1C1 obtained by amplifying the test voltage value V1 by one time, a voltage value V2C4 obtained by amplifying the test voltage value V2 by four times, and a voltage value V2C1 obtained by amplifying the test voltage value V2 by one time. The test voltage values V1, V2 are set so that a reference voltage value VREF to be used for signal determination is located at a signal level between the test voltage values V1C4 and V2C4.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device, a photoelectric conversion system, and a moving body. [Background technology]

[0002] Patent Document 1, which describes an imaging device that is an example of a photoelectric conversion device, describes setting the amplification factor of an amplifier circuit according to the magnitude of a pixel signal. Patent Document 1 also describes that in order to correct an amplification factor error, a correction value is obtained from an output signal obtained by inputting a test voltage into the amplifier circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2017-079464 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the amplification factor set in the amplifier circuit and the signal level of the correction value are not considered. Therefore, depending on the amplification factor set in the amplifier circuit, the output of the amplifier circuit may deviate from the processable range of the downstream circuit, resulting in a decrease in accuracy of obtaining the correction value. [Means for solving the problem]

[0005] An example of the present disclosure includes: a pixel that outputs a pixel signal corresponding to an amount of incident light; and an amplifier circuit that amplifies the pixel signal by an amplification factor corresponding to a signal level of the pixel signal; When acquiring a correction condition for correcting a signal based on the pixel signal, A predetermined signal is output to the amplifier circuit. Out A power circuit; When acquiring a correction condition for correcting a signal based on the pixel signal, a setting circuit for setting a signal level of the predetermined signal; 、 of moreover Preparation, When the amplification factor used in the amplifier circuit is a first amplification factor, the setting circuit sets the signal level of the predetermined signal to a first level and a second level smaller than the first level, and when the amplification factor used in the amplifier circuit is a second amplification factor larger than the first amplification factor, the setting circuit sets the signal level of the predetermined signal to a third level and a fourth level smaller than the third level, and a ratio of the first level to the second level is larger than a ratio of the third level to the fourth level. The photoelectric conversion device is characterized in that Also, another example of the present disclosure is a pixel that outputs a pixel signal corresponding to an amount of incident light, and an amplifier circuit that amplifies the pixel signal by an amplification factor corresponding to a signal level of the pixel signal; When acquiring a correction condition for correcting a signal based on the pixel signal, A predetermined signal is output to the amplifier circuit. Out A power circuit; When acquiring a correction condition for correcting a signal based on the pixel signal, a setting circuit for setting a signal level of the predetermined signal; 、 of moreover Preparation, Used in the amplifier circuit When the amplification factor is a first amplification factor, the setting circuit sets the signal level of the predetermined signal between a first level and Less than Set each of the second levels, Used in the amplifier circuit The amplification factor is the first amplification factor Greater than In the case of the second amplification factor, the setting circuit sets the signal level of the predetermined signal between a third level and the third level Less than Set for each of the fourth levels and the second level is less than the fourth level. The photoelectric conversion device is characterized in that Effect of the Invention

[0006] It is possible to suitably carry out correction processing corresponding to the amplification factor set in the amplifier circuit according to the magnitude of the pixel signal. [Brief description of the drawings]

[0007] [Figure 1] 1 is a diagram showing a configuration of a photoelectric conversion device; [Diagram 2] A diagram showing the configuration of a pixel [Diagram 3] The diagram shows the configuration of a readout circuit. [Figure 4] 1 is a diagram showing the operation of a photoelectric conversion device; [Diagram 5] A diagram showing the operation of the readout circuit. [Figure 6] Illustrative diagram of resolution correction [Figure 7] FIG. 1 is a diagram showing a correction value acquisition operation and an error correction operation; [Figure 8] A diagram showing the operation of obtaining correction values [Figure 9] A diagram showing the configuration of a photoelectric conversion system. [Figure 10] A diagram showing the configuration and operation of a moving object DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, each embodiment is not limited to an image pickup device, and can be applied to other examples of photoelectric conversion devices. For example, a distance measuring device (a device for measuring distance using focus detection or TOF (Time Of Flight)) or a photometric device (a device for measuring the amount of incident light) may be used.

[0009] (First embodiment

[0010] (Imaging device) FIG. 1 is a block diagram showing the configuration of an imaging device, which is an example of a photoelectric conversion device.

[0011] The pixels 101 arranged two-dimensionally in the pixel array 100 output pixel signals to output lines 103 by photoelectric conversion. Similarly, the pixel array 100 includes a voltage output circuit 111 connected to the output line 103. The voltage output circuit 111 outputs a plurality of predetermined signals with different voltage values.

[0012] The vertical scanning circuit 102 scans the pixel array 100 in the vertical direction. As a result, pixels located in a row selected by the vertical scanning circuit 102 output pixel signals to an output line 103. The read pixel signals are amplified and AD converted in a column circuit 104. The AD conversion is performed by comparing the magnitude of the signal with a ramp signal, the voltage of which changes over time and is output from a reference signal generation circuit 105.

[0013] The counter circuit 106 starts counting clock pulses in response to the start of a change in the voltage value of the ramp signal. This counting operation of the clock pulses causes the counter circuit 106 to generate a count value. The count value is stored in a column memory in the column circuit 104 as an AD conversion value (a digital signal having a value corresponding to the signal level of the pixel signal) based on the time when the ramp signal exceeds the amplified pixel signal. The AD conversion values ​​stored in the column memory are sequentially transferred by the horizontal scanning circuit 108 to a signal processing unit 109 that corrects the AD conversion value. The AD conversion value corrected by the signal processing unit 109 is output to the outside of the imaging device by a signal output unit 110. A timing generator (hereinafter sometimes referred to as TG) 107 controls synchronization of the drive timing of the above-mentioned circuit group.

[0014] In an operation of acquiring a correction value required for correcting an AD conversion value, the pixel 101 is disconnected from the output line 103 by the operation of the switch SW6. The voltage output circuit 111 inputs a test voltage value to the output line 103 based on an instruction from a setting circuit 302 in the column circuit 104. The test voltage value is set according to a combination of gains switched by the amplifier circuit in the column circuit 104.

[0015] Each part will be explained in detail below.

[0016] (pixels) The configuration of the pixel 101 will be described with reference to FIG.

[0017] The pixel 101 has a photodiode 201 (photoelectric conversion unit), a transfer transistor (transfer switch) 202, and a reset transistor (reset switch) 203. The pixel 101 further includes a floating diffusion unit 204, an amplifier transistor (pixel amplifier) ​​205, and a selection transistor (selection switch) 206. Although each switch is shown as a MOS transistor in Fig. 2, it is not limited to this example and may be any element having a switch function, such as a thin film transistor.

[0018] The photodiode 201 generates charges by photoelectrically converting incident light. The transfer switch 202 transfers the charges generated in the photodiode 201 to the floating diffusion unit 204. The floating diffusion unit 204 converts the transferred charges into a voltage value Vfd by charge-voltage conversion. The pixel amplifier unit 205 functions as a source follower, with a gate to which a voltage value Vfd is input, a drain connected to a power supply Vdd, and a source connected to a selection switch 206. When a corresponding row is selected by a signal SEL, the selection switch 206 becomes conductive. As a result, the source of the pixel amplifier unit 205 is connected to the output line 103, and a pixel signal is output to the column circuit unit 104 via the output line 103.

[0019] (Overall description of the readout circuit) The configuration of the column circuit section 104, which is a readout circuit, will be described with reference to Fig. 3. Fig. 3 shows a column circuit section connected to a single pixel column, and it is assumed that the same column circuit is connected to each column. The column circuit section 104 has an amplifier circuit 301, a setting circuit 302, a comparator 304, and a column memory 305.

[0020] The amplifier circuit 301 includes an input capacitance C0, a differential amplifier (hereinafter, may be simply referred to as an amplifier) ​​303, a plurality of feedback capacitances Cf1, Cf2, Cf3, and Cf4, and switches SW1, SW2, SW3, SW4, and SW5.

[0021] The setting circuit 302 controls the switches SW1, SW2, SW3, and SW4 to switch the feedback capacitance connected to the feedback path of the amplifier 303 and change the capacitance ratio with the input capacitance C0. This changes the amplification factor of the amplifier circuit 301. An example of setting the amplification factor will be described below, where the capacitance value of the input capacitance C0 is 8C, and the capacitance values ​​of the feedback capacitances Cf1, Cf2, Cf3, and Cf4 are C, 3C, 2C, and 6C.

[0022] The switch SW1 of the feedback path is turned on and the other switches of the feedback path are turned off. The amplification factor K1 of the amplifier circuit 301 is K1=C0 / Cf1=8 times. Furthermore, the switches SW1 and SW2 of the feedback path are turned on and the other switches of the feedback path are turned off. The amplification factor K2 of the amplifier circuit 301 is K2=C0 / (Cf1+Cf2)=2 times. Furthermore, the switch SW3 of the feedback path is turned on and the other switches of the feedback path are turned off. The amplification factor K3 of the amplifier circuit 301 is K3=C0 / Cf3=4 times. The switches SW3 and SW4 of the feedback path are turned on and the other switches of the feedback path are turned off. The amplification factor K4 of the amplifier circuit 301 is K4=C0 / (Cf3+Cf4)=1 time. The switch SW5 is controlled by the PC0R pulse of the control signal output from the TG107. In the feedback where switch SW5 is on, switches SW1, SW2, SW3, and SW4 are turned on to reset capacitances C0, Cf1, Cf2, Cf3, and Cf4 and amplifier 303. At the node of a switch that is off among switches SW1, SW2, SW3, and SW4, a potential drop occurs during the signal output operation of amplifier 303, and the off state of the switch may be weakened. Even in this case, by resetting amplifier 303 and the feedback capacitance in advance, it is possible to suppress the occurrence of a change in the amplification factor even if the off state of the switch is weakened.

[0023] The setting circuit 302 also controls the test voltage value input from the voltage output circuit 111, but this will be described in detail later in the explanation of correction of the AD converted value.

[0024] The AD conversion circuit 311 has a comparator 304 and a column memory 305. The comparator 304 receives a signal output by the amplifier circuit 301 and a signal from the reference signal generation circuit 105. Hereinafter, the signal output by the amplifier 301 is referred to as an amplified signal. The reference signal generation circuit 105 outputs a signal whose voltage value is a reference voltage VREF (threshold) during a signal determination period, and a ramp signal VRAMP whose voltage value changes according to time during an AD conversion period. During the signal determination period, the comparator 304 compares the reference voltage VREF, which is a reference for the magnitude of luminance, with the amplified signal Vcamp_out, whose signal level is an amplified pixel signal. The signal Vcomp_out at this time is a determination signal indicating the result of the comparison between the amplified signal and the threshold. The determination signal holds information on the magnitude of luminance in its signal polarity, and is input to the column memory 305 and the setting circuit 302. The amplification factor of the amplifier circuit 301 is set based on the signal level of the determination signal. The column memory 305 holds the determination signal Vcomp_out. This determination signal is used to correct the AD output value, which will be described later. On the other hand, during the AD conversion period, the comparator 304 outputs to the column memory 305 an AD conversion signal whose signal level is inverted based on the magnitude relationship between the amplified signal and the ramp signal VRAMP.

[0025] (Amplification setting) Next, an overview of the operation of setting the gain by the amplifier circuit 301, the setting circuit 302, and the comparator 304 will be described. The operation of setting the gain is performed during a signal determination period. Here, there are two combinations of gains to be switched: setting A and setting B.

[0026] First, the operation of switching the amplification factor in the combination of the amplification factors K3=4 and K4=1, which is setting A, will be described. The setting circuit 302 causes the amplification circuit 301 to turn on the switch SW3 to connect the feedback capacitance Cf3 to the feedback path. The amplification factor of the amplification circuit 301 is set to K3=4.

[0027] During the signal judgment period, the comparator 304 compares the output of the amplifier 303 with the reference signal VREF from the reference signal generating circuit 105, and outputs a judgment signal Vcomp_out indicating the result of the comparison. A high-level judgment signal indicates that the amplified signal has a larger amplitude than the reference signal VREF. On the other hand, a low-level judgment signal indicates that the amplified signal has a smaller amplitude than the reference signal VREF. The amplitude of a signal indicates the potential of the signal relative to a reference potential. The judgment signal is output to the setting circuit 302. When the judgment signal Vcomp_out is at a high level, the setting circuit 302 turns on the switch SW4 in addition to the switch SW3. As a result, both of the feedback capacitances Cf3 and Cf4 are connected to the feedback path. In this way, the setting circuit 302 switches the amplification factor of the amplifier circuit 301 to K4=1. On the other hand, when the judgment signal is at a low level, the feedback capacitance Cf4 is not connected to the path during the period, and the feedback capacitance Cf3 continues to be connected to the feedback path. Therefore, the amplification factor remains unchanged and is set to K3=4. The above is the setting operation of the amplification factor of the amplifier circuit 301 in setting A.

[0028] Next, the switching operation of the amplification factor in the combination of the amplification factors K1=8 times and K2=2 times, which is the setting B with a higher amplification factor compared to the setting A, will be described. Typically, the setting B is a setting with a higher ISO sensitivity of the imaging device than the setting A. In the setting B, the setting circuit 302 causes the amplification circuit 301 to turn on the switch SW1 and connect the feedback capacitance Cf1 to the feedback path. As a result, the amplification factor of the amplification circuit 301 is set to K1=8 times. During the signal determination period, when the determination signal is at a High level, the setting circuit 302 turns on the switch SW2 in addition to the switch SW1. As a result, the feedback capacitance Cf1 and the feedback capacitance Cf2 are connected to the feedback path. In this way, the setting circuit 302 switches the amplification factor of the amplification circuit 301 to K2=2 times. On the other hand, when the determination signal Vcomp_out is at a Low level, the feedback capacitance Cf2 is not connected to the feedback path, and the feedback capacitance Cf1 continues to be connected to the feedback path. Therefore, the amplification factor remains unchanged and is set to K1=8 times. The above is the setting operation of the amplification factor of the amplifier circuit 301 in setting B.

[0029] Furthermore, the setting circuit 302 outputs a command signal for a test voltage value to the voltage output circuit 111 during a correction value acquisition operation in accordance with the combination of gains to be switched. Details will be described later.

[0030] (A / D conversion) Next, the AD conversion of the amplified signal by the AD conversion circuit 311 will be described. The column memory 305 receives signals from the comparator 304 and the counter circuit 106. The counter circuit 106 outputs a count signal that counts in synchronization with the time change of the voltage value of the ramp signal. The count signal is input to an N memory 306 that stores the signal level of the reset state of the amplifier circuit 301 and an S memory 307 that stores the pixel signal level in the light incidence state. In the reset state or the light incidence state during the AD conversion period, a signal polarity change of the AD conversion signal from the comparator 304 occurs at the time when the ramp signal VRAMP exceeds the signal from the amplifier 303. This timing is recorded in each memory as an N level AD conversion value or an S level AD conversion value.

[0031] In this manner, the information held in the N memory 306, the S memory 307, and the J memory 308 of the column circuit 104 is output in sequence to the signal processing circuit 109 by the horizontal scanning circuit .

[0032] The signal processing circuit 109 corrects the AD conversion value based on the information from the column memory 305. Details will be described later. The corrected AD conversion output is output from the signal output unit 110.

[0033] This concludes the description of each part of the imaging device.

[0034] (Timing chart) Next, the operation of the imaging device up to AD conversion will be described with reference to the timing chart of Fig. 4. Fig. 4 shows a timing chart in which the combination of amplification factors of the amplifier circuit 301 is set to setting A. The operation repeats an N-level AD conversion period, a signal determination period, and an S-level AD conversion period in this order.

[0035] First, a procedure for obtaining an N-level AD conversion value during the N-level AD conversion period from time t400 to t407 will be described. At this time, the signal TX input to the pixel 101 keeps the transfer switch 202 off, and the charge accumulated in the PD 201 according to the amount of irradiated light is not transferred to the floating diffusion section 204.

[0036] At time t 400 , the selection switch 206 for the row from which readout begins is switched by a signal SEL input to the pixel 101 , and the pixel 101 is connected to the output line 103 .

[0037] From time t401 to time t404, the switch SW5 is connected by the signal PC0R input to the amplifier circuit 301. During this period, the switches SW1, SW2, SW3, and SW4 are turned on. This resets the input capacitance C0, the feedback capacitances Cf1, Cf2, Cf3, and Cf4, and the amplifier 303.

[0038] At time t402, the reset of the floating diffusion unit 204 is released by the signal RES input to the pixel 101. This causes the floating diffusion unit 204 to hold a voltage mainly including noise components caused by the reset operation of the pixel 101. This causes the pixel 101 to output a signal mainly including noise components (referred to as a noise signal).

[0039] At time t403, the switch SW4 is turned off by the signal PFB4 input from the setting circuit 302 to the amplifier circuit 301. The feedback capacitance Cf4 is not connected to the feedback path. The switch SW3 is turned on. When the combination of the amplification factors of the amplifier circuit 301 is setting A, the signals PFB1 and PFB2 are not used and are therefore not shown. However, like the switch SW4, the switches SW1 and SW2 are turned off by the signals at time t403.

[0040] At time t404, SW5 is turned off by a signal PC0R input to the amplifier circuit 301, and the amplifier circuit 301 is released from the reset state. A charge corresponding to the noise signal output by the pixel 101 is held in the input capacitance C0. After the amplifier circuit 301 is released from the reset state, the signal output by the amplifier circuit 301 is a signal that mainly includes an offset component of the amplifier circuit 301. This signal is referred to as an N signal.

[0041] The period from time t416 to time t417 is a reset period of the comparator 304. The ramp signal VRAMP generated by the reference signal generating circuit 105 is raised once to a certain offset voltage, and then the comparator 304 is reset. As a result, a voltage level that is higher than the reset level of the comparator 304 by the offset voltage is set as the initial voltage of the input node of the ramp signal VRAMP. By setting the offset voltage in this manner, AD conversion is performed with the start portion of the change in the ramp signal VRAMP as an invalid region of AD conversion. The start portion of the change in the ramp signal VRMP may have lower linearity than other portions. By making this portion an invalid region of AD conversion, it is possible to improve the accuracy of AD conversion.

[0042] The period from time t405 to t407 is an AD conversion period for the N signal output by the amplifier circuit 301. Hereinafter, this may be referred to as an NAD period. Note that, here, a form will be described in which the N signal of the amplifier circuit 301 is directly input to the comparator 304. As another example, a clamp capacitance may be provided at the input node of the comparator 304, similar to the input capacitance C0 provided at the input node of the amplifier 303. In this case, when the reset of the comparator 304 is released, the N signal is clamped to the clamp capacitance. Therefore, during the NAD period, a reference voltage used for the clamping operation of the clamp capacitance is input.

[0043] The signal Vcamp_out is at the level of the N signal. The ramp signal VRAMP output from the reference signal generating circuit 105 starts to change in potential at time t405.

[0044] At time t406, when the amplitude of the ramp signal VRAMP becomes larger than that of the signal Vcamp_out at the N signal level, the signal level of the signal Vcomp_out changes. The output of the comparator 304 and the counter signal from the counter circuit 106 are input to the column memory 305. In response to the change in the signal Vcomp_out, the N memory 306 stores a count signal. This stored count signal becomes the AD converted value of the N signal. Hereinafter, it may be referred to as a digital N signal.

[0045] Next, the operation during the signal determination period from time T408 to time t411 will be described.

[0046] During the period from time t408 to t409, the vertical scanning circuit 102 sets the signal TX output to the pixel 101 to a High level. This turns on the transfer switch 202. Therefore, the charge corresponding to the incident light accumulated in the photodiode 201 is transferred to the floating diffusion portion 204. At this time, the pixel 101 outputs a signal based on the charge generated by the incident light. This signal is called a photoelectric conversion signal.

[0047] The amplifier circuit 301 amplifies the input photoelectric conversion signal by a 4-fold amplification factor. The signal that the amplifier circuit 301 amplifies and outputs the photoelectric conversion signal is referred to as an S signal. In the following, the amplification factor applied to the photoelectric conversion signal by the amplifier circuit 301 may be referred to as the "S signal (amplification factor)". In other words, the amplified signal when the photoelectric conversion signal is amplified by a 4-fold amplification factor may be referred to as an S signal (4). In addition, when referring to a signal obtained by amplifying the photoelectric conversion signal without being limited to a particular amplification factor, it may be referred to simply as an S signal. The S signal (4) is output from the amplifier circuit 301 to the comparator 304.

[0048] At time t410, the ramp signal VRAMP output from the reference signal generating circuit 105 starts to rise to the threshold voltage VREF, which is the threshold for signal determination.

[0049] Two lines, a solid line and a dashed line, are shown for the signal Vcamp_out at time t411. The solid line shows the case where the photodiode 201 of the pixel 101 has low luminance. That is, at time t411, the signal Vcamp_out (solid line), which is the S signal (4), is smaller than VREF. In this case, the signal VCOMP_OUT (solid line), which is the judgment signal output by the comparator 304, becomes low level. The J memory stores "J=0", which indicates that the judgment signal is low level. Furthermore, the low level judgment signal is input to the setting circuit 302, but the amplification factor of the amplifier circuit 301 continues to be set to 4 times.

[0050] On the other hand, the dashed line of the signal Vcamp_out at time t411 indicates a case where the photodiode 201 of the pixel 101 is at high luminance. That is, at time t411, the signal Vcamp_out (solid line) which is the S signal (4) is greater than VREF. In this case, the signal VCOMP_OUT (dashed line) which is the judgment signal output by the comparator 304 becomes a High level. The J memory stores "J=1" which indicates that the judgment signal is at a High level. Also, at the same time t411, in response to the input of the High level judgment signal, the setting circuit 302 outputs the signal PFB4 to the amplifier circuit 301 and turns on the switch SW4. A capacitance of 4C, which is the total capacitance value of the feedback capacitances Cf3 and Cf4, is connected to the feedback path of the amplifier circuit 301, and the amplification factor of the amplifier circuit 301 is switched from 4 times to 1 time.

[0051] Next, the period from time t412 to time t415, which is the AD conversion period of the S signal (hereinafter, referred to as the SAD period), will be described.

[0052] The comparator 304 compares the signal Vcamp_out, which is the signal level of the S signal amplified by the amplifier 301, with the ramp signal VRAMP, whose voltage increases from time t412 to time t414 and is output from the reference signal generating circuit 105. When the determination signal is at a low level, the amplification factor of the amplifier circuit 301 during the SAD period remains at four times. At time t414, VRAMP>Vcamp_out (solid line) is established. In response to the change in the magnitude relationship between this S signal (4) and the ramp signal VRAMP, the signal Vcomp_out changes to a low level. In response to the change in the signal level of the signal Vcomp_out, the S memory 307 stores a count signal. The stored count signal becomes the AD converted value of the S signal. Hereinafter, this may be referred to as a digital S signal.

[0053] Also, when the determination signal is at a high level, the amplification factor of the amplifier circuit 301 during the SAD period is set to 1. In the case shown in FIG. 4, at time t413, VRAMP>Vcamp_out (solid line) occurs. In response to the change in the magnitude relationship between this S signal (1) and the ramp signal VRAMP, the signal Vcomp_out changes to a low level. As in the case when the determination signal is at a low level, the S memory 307 stores a count signal in response to the change in the signal level of the signal Vcomp_out. The stored count signal becomes the AD converted value of the S signal. The above is the drive timing of each part related to acquisition of the digital N signal, the determination signal, and the digital S signal when the combination of the amplification factors of the amplifier circuit 301 is set to setting A.

[0054] Fig. 5 is a timing chart when the combination of the amplification factors of the amplifier circuit 301 is setting B. In the case of setting B, the operation is the same as that shown in Fig. 4 except that the setting operation of the feedback capacitance of the amplifier circuit during the signal determination period is different. Here, the operation during the signal determination period in setting B will be mainly described.

[0055] 5, the solid line indicates the case where light of relatively low luminance is incident on the pixel 101. The dashed line indicates the case where light of relatively high luminance is incident on the pixel 101.

[0056] The following describes the operation of the amplifier circuit 301. At time t403', the setting circuit 302 connects the feedback capacitance Cf1 to the feedback path and does not connect the other feedback capacitances to the feedback capacitance. This sets the amplification factor of the amplifier circuit 301 to 8 times.

[0057] If the determination signal is at a low level, the setting circuit 302 keeps the amplification factor of the amplifier circuit 301 at eight times.

[0058] On the other hand, when the determination signal is at a high level, at time t411', the setting circuit 302 outputs the signal PFB2 to the amplifier circuit 301. This turns on the switch SW2, and the feedback capacitance Cf2 is further connected to the feedback path. As a result, the capacitance value connected to the feedback path becomes Cf1+Cf2=4C. This causes the amplification factor of the amplifier circuit 301 to switch from 8 times to 2 times.

[0059] Next, the AD conversion will be described. When the determination signal is at a low level, the amplification factor of the amplifier circuit 301 in the SAD conversion remains at 8 times. In the example shown in FIG. 5, when the solid line (determination signal is at a low level), a digital S signal is obtained which is a count signal corresponding to time t414' when VRAMP>Vcamp_out (solid line). When the determination signal is at a low level, the amplification factor of the amplifier circuit 301 in the SAD conversion is set to 2 times. In the example shown in FIG. 5, when the solid line (determination signal is at a low level), a digital S signal is obtained which is a count signal corresponding to time t413' when VRAMP>Vcamp_out (dashed line).

[0060] (Digital Signal Correction) Next, a correction method for correcting the difference in resolution of AD conversion caused by the difference in the amplification factor in the amplifier circuit 301 in the signal processing circuit 109 will be described with reference to FIG.

[0061] First, a method for acquiring a corrected AD conversion value corresponding to the light incident on the photodiode 201 using the digital N signal, the determination signal, and the digital S signal transferred from the column memory 305 to the signal processing circuit 109 will be described.

[0062] 6, the horizontal axis represents the luminance of the light incident on the photodiode 201, and the vertical axis represents the AD conversion value (corrected digital signal value) output from the signal processing unit 109. The signal processing unit 109 obtains the difference between the digital N signal and the digital S signal through arithmetic processing. This provides a digital (SN) signal with the noise component subtracted from the digital S signal.

[0063] The digital (SN) signal becomes the AD conversion value shown by the thin dashed line in FIG. 6. In the correction for making the resolution of the digital signal uniform (hereinafter, sometimes referred to as digital correction), the digital (SN) signal is multiplied by a value 2Y, which is the ratio of the amplification factor switched by the amplifier circuit 301. The value 2Y is 2Y=4 / 1=8 / 2=4 when the combination of the amplification factors of the amplifier circuit 301 is both set A and set B. At this time, Y is the number of extension bits. The AD conversion value after correction becomes 4×(SN). This AD conversion value after correction is output from the signal processing unit 109. The resolution of the digital signal is in units of 4 LSB (Least Significant Bit), but the dynamic range is extended. On the other hand, when the judgment signal is J=0, the process for obtaining the digital (SN) signal is performed, but the process for correcting the resolution of the digital signal is not performed. As a result, the AD conversion value shown by the solid line in FIG. 6 is obtained by the arithmetic process of the signal processing unit 109, and this AD conversion value is output from the signal processing unit 109.

[0064] In this way, it is possible to realize a dynamic range expansion by a bit expansion method, in which high resolution is achieved on the low luminance side and the dynamic range is expanded on the high luminance side in exchange for a decrease in resolution.

[0065] (Amplification factor error / offset error correction) Due to manufacturing errors in the imaging device, the ratio of the amplification factors of the amplifier circuit 301 may have an error from the design value, and the S signal may contain offset components due to switching noise caused by the operation of a switch on the feedback path. As a result, a difference occurs in the AD conversion value between when J=0 and when J=1 at the boundary between the low brightness output and the high brightness output shown in FIG. 6. This reduces linearity (the relationship of the AD conversion value to the brightness of the incident light). This is a problem in terms of image quality, as the correct brightness is not displayed. A correction process is performed for this difference in the AD conversion values. The error correction method will be described with reference to FIG. 7, taking as an example the combination of the amplification factors of the amplifier circuit 301 set to A.

[0066] The correction value used for error correction is acquired during a blanking period during which no readout operation is performed within an image frame. FIG. 7(a) shows the relationship between the predetermined voltage output by the voltage output circuit 111 to the output line and the correction signal obtained by amplifying the predetermined signal output by the voltage output circuit 111 with the amplifier circuit 301. When the switch SW6 is turned off, the output line 103 is disconnected from the pixel 101. The setting circuit 302 controls the voltage output circuit 111 to output a predetermined signal corresponding to the combination setting A of the amplification factors of the amplifier circuit 301. Specifically, it instructs the voltage output circuit 111 to output test voltage values ​​V1 and V2, which are predetermined signals having different signal levels. The test voltage values ​​V1 and V2 are amplified by the amplifier circuit 301 with amplification factors of 4 and 1, respectively. The output of the test voltage value V1 amplified by the amplifier 303 with an amplification factor of 4 is V1C4, and the output of the test voltage value V1 amplified by the amplifier 303 with an amplification factor of 1 is V1C1. Similarly, the output obtained by amplifying the test voltage value V2 by the amplifier 303 with an amplification factor of 4 is defined as V2C4, and the output obtained by amplifying the test voltage value V2 by the amplifier 303 with an amplification factor of 1 is defined as V2C1. At this time, it is preferable that the signal level between the test voltage values ​​V1C4 and V2C4 includes the reference voltage value VREF used for signal judgment.

[0067] V1C4≦VREF≦V2C4 Formula (1) The test voltage values ​​V1 and V2 are set so as to satisfy this formula (1). This makes it possible to obtain a correction value corresponding to a wider range of the signal range output by the amplifier circuit 301 in an actual imaging operation. The outputs V1C4, V1C1, V2C4, and V2C1 are AD converted by the AD conversion circuit 311 at times t601, t603, t604, and t606. This results in correction signals A1, B1, A2, and B2. In setting A, it is preferable to set the test voltage value amplified by an amplification factor of 4 times so as to fall within the voltage change range of the ramp signal VRAMP. In other words, it is preferable to set the test voltage so as not to deviate from the AD convertible range at a high amplification factor, in a combination of the amplification factors of the switching amplifier circuits. As shown on the vertical axis of FIG. 6, when the AD conversion value by bit expansion is 2X and the number of expansion bits is Y bits, the output saturation is 2 (X-Y) Therefore, the correction signal A2 is 2 (X-Y) Set the test voltage as follows:

[0068] A method for acquiring the correction value will be described with reference to FIG. 7(b). Here, an example will be described in which the signal processing unit 109 is a correction value acquisition unit that performs correction and acquisition. The present invention is not limited to this example, and the correction value acquisition unit may be provided outside the imaging device.

[0069] The signal processing unit 109 determines a correction value α for correcting the error in the amplification factor. The correction value α is determined from the ratio of the slopes of the AD conversion output between the amplification factors being compared. The output slope at an amplification factor of 4 is (A2-A1) (bold solid line), and the slope at an amplification factor of 1 with resolution correction is 4×(B2-B1) (bold dashed line). Therefore, the correction value α is obtained by the following formula (2). α=(A2-A1) / 4×(B2-B1) Equation (2)

[0070] The offset correction value, correction value β, can be calculated from the difference between the two values ​​AD converted between the amplification factors being compared at the same test voltage value and the value corrected using correction value α. This is a comparison between point A1 and point 4×α×B2 in Figure 7(b), or point A2 and point 4×α×B2. In the former example, the correction value β corresponding to the offset correction is calculated from the following formula (3). β=A1-4×α×B1 Equation (3)

[0071] From the above, when the signal judgment value (J=1) indicates high luminance, the signal processing unit 109 corrects the (SN)AD converted value using the correction values ​​α and β as shown in equation (4). DH=4α×(SN)+β(J=1)...Equation (4)

[0072] Furthermore, when the determination signal is J=0, the correction process can be omitted. DL = SN (J = 0) Equation (5)

[0073] This correction allows the AD conversion value at the boundary for switching the amplification factor of the amplifier circuit 301 to have good linearity. The signal processing unit 109 performs correction processing on the digital (SN) signal based on the correction signal updated every time the imaging device captures an image. That is, the signal processing unit 109 of this embodiment is a correction value acquisition unit and also a correction unit that performs correction processing on the digital (SN) signal. When the correction value acquisition unit is provided outside the imaging device, the signal processing unit 109 can be used as the correction unit. Also, both the correction value acquisition unit and the correction unit can be provided outside the imaging device. When the correction value acquisition unit and the correction unit are provided outside the imaging device, the signal processing unit 1007 to which the signal of the imaging device is output, which is described in a second embodiment to be described later, may be used as the correction value acquisition unit and the correction unit.

[0074] This concludes the description of how to obtain and apply the correction values ​​α and β in setting A.

[0075] A method for acquiring the correction value will be described with reference to Fig. 8, taking as an example a state in which the combination of the amplification factors of the amplifier circuit 301 is setting B. Fig. 8 shows the relationship between the test voltage value input from the voltage generating circuit 111 to the output line in setting B and the correction signal amplified by the amplifier circuit.

[0076] In the setting B, the amplification factor of the amplifier circuit 301 is set higher than that of the setting A. Therefore, the test voltage value output from the voltage output circuit 111 is also amplified with a higher amplification factor than that of the setting A. At this time, as described in the example of the setting A, if the test voltage value amplified by the amplifier circuit 301 exceeds the voltage change range of the ramp signal VRAMP compared by the comparator 304 for AD conversion, a correct digital signal cannot be obtained. Therefore, similar to the setting A, the test voltage is set so that the correction signal is 2(XY) or less, taking into consideration the change in the amplification factor. Based on this, the setting circuit 302 instructs the voltage output circuit 111 to output the test voltage values ​​V3 and V4 corresponding to the setting B. At this time, since the amplification factor of the amplifier circuit 301 in the setting B is higher than that of the setting A, the test voltage values ​​V3 and V4 for not deviating from the above-mentioned AD convertible signal range are set to be higher than the test voltage values ​​V1 and V2. End and satisfies the relationship of the following equation (6). (V1 / V2)>(V3 / V4) Equation (6)

[0077] However, V1 may be equal to V3 or V4. That is, V1, which is the first level, may be the same as V3, which is the third level, or V4, which is the fourth level. Also, V1, which is the first level, V2, which is the second level, V3, which is the third level, and V4, which is the fourth level, may be different signal levels.

[0078] The test voltage values ​​V3 and V4 are amplified by the amplifier circuit 301 at an amplification factor of 8 and 2. The output of the test voltage value V3 amplified at an amplification factor of 8 is designated as V3C8, and the output of the test voltage value V3 amplified at an amplification factor of 2 is designated as V3C2. Similarly, the output of the test voltage value V4 amplified at an amplification factor of 8 is designated as V4C8, and the output of the test voltage value V4 amplified at an amplification factor of 2 is designated as V4C2. At this time, the outputs V3C8 and V4C8 of the test voltage values ​​amplified at an amplification factor of 8 by the amplifier circuit 301 and output include the reference voltage value VREF used for signal judgment. V3C8≦VREF≦V4C8 Formula (7)

[0079] As shown in formula (2), the correction value α is calculated from the ratio of the slopes of the AD conversion outputs. Therefore, it is desirable to set the outputs V3C2 and V4C2, which are the test voltage values ​​amplified and output when the amplification factor of the amplifier circuit 301 is 2, so that the slope of the output at the correction value α is large. In this way, even when the amplification factor is higher than that of setting A, such as setting B, a digital signal with reduced amplification factor error can be obtained by correction processing using the correction value α.

[0080] The outputs V3C8, V3C2, V4C8, and V4C2 are AD converted at times t701, t703, t704, and t706 to obtain correction signals A3, A4, B3, and B4.

[0081] The procedure for obtaining the correction values ​​α and β from the correction signal is the same as that for the combination setting A of the amplification factors of the amplifier circuit 301. The formula for obtaining the correction values ​​α and β is given below. α = (A4-A3) / 4 × (B4-B3) Equation (8) β=A3-4×α×B3 Equation (9)

[0082] From the above, when the determination signal is J=1, the signal processing unit 109 corrects the digital (SN) signal using the correction values ​​α and β according to the above-mentioned equations (7) and (8).

[0083] In this way, even if the switching gain of amplifier circuit 301 is set to setting B, which is higher than setting A, good output characteristics similar to setting A can be obtained by appropriately changing the test voltage value set by voltage output circuit 111.

[0084] The embodiment merely describes one specific example of the present invention, and the scope of the present invention is not limited to the configuration of the above embodiment. For example, the voltage output circuit 111 may be a voltage value input means from the outside, or a means for generating a voltage value internally by dividing the voltage of a power supply. The correction of the digital (SN) signal may be a fixed value correction in which a correction signal is output from the signal output unit 110 to the outside of the imaging device, and a calculated correction value is input to the signal processing unit 109. The test voltage value may be set arbitrarily regardless of the signal evaluation voltage value VREF. Even with such a configuration, the same effect as that described in the first embodiment can be obtained.

[0085] In addition, in this embodiment, the AD conversion circuit 311 that converts the output of the amplifier circuit 301 into a digital signal is provided, but the present invention is not limited to this example. The signal output by the amplifier circuit 301 may be output to the outside of the imaging device in analog format. Even in this embodiment, the test voltage values ​​V1, V2, V3, and V4 may be set so that they fall within the range that the circuit downstream of the amplifier circuit can process.

[0086] Second embodiment The photoelectric conversion system according to this embodiment will be described with reference to Fig. 9. Fig. 9 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0087] The photoelectric conversion device (imaging device) described in the first embodiment is applicable to various photoelectric conversion systems. Examples of the applicable photoelectric conversion system include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion system. FIG. 9 illustrates a block diagram of a digital still camera as an example of these.

[0088] 9 includes an image capture device 1004, a lens 1002 that forms an optical image of a subject on the image capture device 1004, an aperture 1003 that varies the amount of light passing through the lens 1002, and a barrier 1001 that protects the lens 1002. The lens 1002 and the aperture 1003 form an optical system that focuses light on the image capture device 1004. The image capture device 1004 is a photoelectric conversion device (image capture device) according to any of the above embodiments, and converts the optical image formed by the lens 1002 into an electrical signal.

[0089] The photoelectric conversion system also has a signal processing unit 1007 which is an image generating unit that generates an image by processing an output signal output from the imaging device 1004. The signal processing unit 1007 performs various corrections and compression as necessary to output image data. The signal processing unit 1007 may be formed on a semiconductor substrate on which the imaging device 1004 is provided, or may be formed on a semiconductor substrate separate from the imaging device 1004. Moreover, the imaging device 1004 and the signal processing unit 1007 may be formed on the same semiconductor substrate.

[0090] The photoelectric conversion system further includes a memory unit 1010 for temporarily storing image data, and an external interface unit (external I / F unit) 1013 for communicating with an external computer or the like. The photoelectric conversion system further includes a recording medium 1012 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading out data on the recording medium 1012. The recording medium 1012 may be built into the photoelectric conversion system, or may be removable.

[0091] The photoelectric conversion system further includes an overall control / calculation unit 1009 that performs various calculations and controls the entire digital still camera, and a timing generation unit 1008 that outputs various timing signals to the image capture device 1004 and the signal processing unit 1007. Here, the timing signals and the like may be input from outside, and the photoelectric conversion system only needs to include at least the image capture device 1004 and the signal processing unit 1007 that processes the output signal output from the image capture device 1004.

[0092] The imaging device 1004 outputs an imaging signal to a signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the imaging signal output from the imaging device 1004, and outputs image data. The signal processing unit 1007 generates an image using the imaging signal.

[0093] In this way, according to this embodiment, it is possible to realize a photoelectric conversion system to which the photoelectric conversion device (imaging device) of any of the above embodiments is applied.

[0094] Third embodiment The photoelectric conversion system and the moving object of this embodiment will be described with reference to Fig. 10. Fig. 10 is a diagram showing the configuration of the photoelectric conversion system and the moving object of this embodiment.

[0095] FIG. 10(a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of collision using any of these distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

[0096] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control unit that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0097] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 10(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0098] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0099] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0100] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also included in the embodiments of the present invention.

[0101] Furthermore, the photoelectric conversion systems shown in the second and third embodiments are examples of photoelectric conversion systems to which the photoelectric conversion device can be applied, and the photoelectric conversion system to which the photoelectric conversion device of the present invention can be applied is not limited to the configurations shown in Figures 9 and 10.

[0102] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0103] 101 pixels 105 Reference signal generation circuit 109 Signal processing unit (correction value acquisition unit, correction unit) 111 Voltage output circuit 301 Amplification circuit 302 Setting circuit 311 AD conversion circuit

Claims

1. a pixel that outputs a pixel signal corresponding to the amount of incident light; an amplifier circuit that amplifies the pixel signal at an amplification factor corresponding to a signal level of the pixel signal, an output circuit that outputs a predetermined signal to the amplifier circuit when acquiring a correction condition for correcting a signal based on the pixel signal; a setting circuit that sets a signal level of the predetermined signal output from the output circuit when acquiring a correction condition for correcting a signal based on the pixel signal, when the amplification factor used in the amplifier circuit is a first amplification factor, the setting circuit sets a signal level of the predetermined signal to a first level and a second level lower than the first level, when the amplification factor used in the amplifier circuit is a second amplification factor that is larger than the first amplification factor, the setting circuit sets the signal level of the predetermined signal to a third level and a fourth level that is smaller than the third level, A photoelectric conversion device, wherein a ratio of the first level to the second level is greater than a ratio of the third level to the fourth level.

2. 2. The photoelectric conversion device according to claim 1, wherein the second level is lower than the fourth level.

3. a pixel that outputs a pixel signal corresponding to the amount of incident light; an amplifier circuit that amplifies the pixel signal at an amplification factor corresponding to a signal level of the pixel signal, an output circuit that outputs a predetermined signal to the amplifier circuit when acquiring a correction condition for correcting a signal based on the pixel signal; a setting circuit that sets a signal level of the predetermined signal output from the output circuit when acquiring a correction condition for correcting a signal based on the pixel signal, when the amplification factor used in the amplifier circuit is a first amplification factor, the setting circuit sets a signal level of the predetermined signal to a first level and a second level lower than the first level, when the amplification factor used in the amplifier circuit is a second amplification factor that is larger than the first amplification factor, the setting circuit sets the signal level of the predetermined signal to a third level and a fourth level that is smaller than the third level, The photoelectric conversion device, wherein the second level is smaller than the fourth level.

4. 4. The photoelectric conversion device according to claim 1, wherein the first level is lower than the third level.

5. 4. The photoelectric conversion device according to claim 1, wherein the first level and the third level are the same.

6. 5. The photoelectric conversion device according to claim 1, wherein the first level, the second level, the third level, and the fourth level are signal levels different from one another.

7. 7. The photoelectric conversion device according to claim 1, wherein the first level is lower than the fourth level.

8. when the amplification factor used in the amplifier circuit is a third amplification factor different from the first amplification factor and the second amplification factor, the setting circuit sets the signal level of the predetermined signal to each of the first level and the second level; A photoelectric conversion device as described in any one of claims 1 to 7, characterized in that when the amplification factor used in the amplifier circuit is a fourth amplification factor different from the first amplification factor and the second amplification factor, the setting circuit sets the signal level of the specified signal to each of the third level and the fourth level.

9. 9. The photoelectric conversion device according to claim 8, wherein the third amplification factor and the fourth amplification factor are smaller than the first amplification factor and the second amplification factor.

10. the output circuit outputs the predetermined signals of the first level and the second level to the amplifier circuit, so that the amplifier circuit outputs a first signal and a second signal; The photoelectric conversion device according to any one of claims 1 to 7, characterized in that the output circuit outputs the specified signals of the third level and the fourth level to the amplifier circuit, thereby causing the amplifier circuit to output a third signal and a fourth signal.

11. A first correction value, which is a correction condition corresponding to the first amplification factor, is calculated using the first signal and the second signal. a second correction value, which is a correction condition corresponding to the second amplification factor, using the third signal and the fourth signal; The photoelectric conversion device according to claim 10 , further comprising a correction value acquisition unit that acquires a correction value.

12. The photoelectric conversion device according to claim 11 , further comprising a correction unit that corrects a signal based on the pixel signal by using the first correction value and the second correction value.

13. an AD conversion circuit for converting a signal output by the amplifier circuit into a signal based on the pixel signal, the pixel signal being a digital signal; 13. The photoelectric conversion device according to claim 11, wherein the first signal, the second signal, the third signal, and the fourth signal all have amplitudes smaller than a signal range that can be AD converted by the AD conversion circuit.

14. A comparison is made between the pixel signal and a threshold value, and the amplification factor is set based on a result of the comparison; The photoelectric conversion device according to any one of claims 10 to 13, characterized in that the threshold value is an amplitude between the first signal and the second signal, and an amplitude between the third signal and the fourth signal.

15. 12. The photoelectric conversion device according to claim 1, further comprising a correction unit that corrects a signal based on the pixel signal.

16. 13. The photoelectric conversion device according to claim 1, further comprising an AD conversion circuit that converts a signal output by the amplifier circuit into a signal based on the pixel signal, which is a digital signal.

17. 17. The photoelectric conversion device according to claim 1, wherein the signal level of the predetermined signal indicates a voltage value.

18. The photoelectric conversion device according to any one of claims 1 to 17, and a signal processing unit that generates an image using a signal output from the photoelectric conversion device.

19. A moving object including the photoelectric conversion device according to any one of claims 1 to 17, A moving body comprising: a control unit that controls the movement of the moving body using a signal output from the photoelectric conversion device.

Images