Imaging device and imaging method

Abstract

A pixel including a photodiode (121) that accumulates charge in response to incident light, the photodiode (121) having an anode connected to a reference potential, a first transistor (125) having an input terminal connected to the cathode of the photodiode (121), and a first capacitor having one end connected to the reference potential and the other end connected to the input terminal of the first transistor (125) through a second transistor (123), and a first gate driver (124) that receives a first output signal output from an output terminal of the first transistor (125) when the second transistor (123) is in an on state, and a first amplifier (141) that amplifies a first output signal output from an output terminal of the first transistor (125) with a second gain lower than the first gain, a converter (142) that converts the signal amplified by the first amplifier (141) into a digital signal, and a control circuit (150) that uses the first digital signal when the first digital signal corresponding to the first output signal is not saturated and selects and outputs a second digital signal corresponding to the second output signal when the first digital signal is saturated.

Description

[Technical field]

[0001] The present disclosure relates to an imaging device and an imaging method. [Background technology]

[0002] In imaging devices using solid-state imaging elements, such as digital cameras, there is a technology called high dynamic range imaging for capturing images of subjects whose input dynamic range within the screen is greater than the range permitted by conventional imaging elements (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2017 / 099423 Summary of the Invention [Problem to be solved by the invention]

[0004] The system described in Patent Document 1 collects and holds the charge overflowing from the photodiode in a capacitor provided in the pixel. In this system, the input dynamic range is determined by the electrostatic capacitance of the photodiode, but since the capacitor can store a signal amount that exceeds the saturation charge of the photodiode, the input dynamic range can be expanded.

[0005] However, in the system described in Patent Document 1, a digital signal is obtained by analog-to-digital conversion of a signal output from a pixel in a state where the pixel conversion gain is high and the pixel conversion gain is not connected to the capacitor, and a signal output from a pixel in a state where the pixel conversion gain is low and the capacitor is connected to the pixel. In this case, the ratio of the quantization width of a signal at a high pixel conversion gain to the quantization width of a signal at a low pixel conversion gain becomes large. As a result, the system has a problem in that contour line-like artifacts occur at the boundary between the two quantization widths due to the large difference in quantization width.

[0006] In view of the above, an object of the present disclosure is to provide an imaging apparatus and a control method thereof that suppresses the occurrence of artifacts. [Means for solving the problem]

[0007] An imaging device according to one embodiment of the present disclosure includes a pixel including: a photodiode that accumulates charge in response to incident light, the photodiode having an anode connected to a reference potential; a first transistor having an input terminal connected to a cathode of the photodiode; and a first capacitor having one end connected to the reference potential and the other end connected to the input terminal of the first transistor via a second transistor; a first amplifier that, when the second transistor is in an on state, amplifies a first output signal output from an output terminal of the first transistor by a first gain and amplifies a second output signal output from the output terminal of the first transistor by a second gain lower than the first gain; a converter that converts the signal amplified by the first amplifier into a digital signal; and a control circuit that selects and outputs the digital signal converted by the converter, the first digital signal being used when a first digital signal corresponding to the first output signal is not saturated and a second digital signal being selected and output when the first digital signal is saturated.

[0008] An imaging method according to one embodiment of the present disclosure is a control method executed by a processor included in an imaging device having a pixel including: a photodiode that accumulates charge in response to incident light, the photodiode having an anode connected to a reference potential; a first transistor having an input terminal connected to the cathode of the photodiode; and a first capacitor having one end connected to the reference potential and the other end connected to the input terminal of the first transistor through a second transistor, the imaging method including: an amplifying step of amplifying a first output signal output from an output terminal of the first transistor with a first gain when the second transistor is in an on state, and amplifying a second output signal output from the output terminal of the first transistor with a second gain lower than the first gain; a converting step of converting the signal amplified in the amplifying step into a digital signal; and a control step of selecting and outputting a second digital signal corresponding to the second output signal when the first digital signal is saturated, the first digital signal being used as the digital signal converted in the converting step, when the first digital signal corresponding to the first output signal is not saturated. Effect of the Invention

[0009] According to the present disclosure, it is possible to provide an imaging apparatus and a control method thereof that suppresses the occurrence of artifacts. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic diagram for explaining a configuration of an imaging device according to a first embodiment. [Diagram 2] FIG. 2 is a block diagram for explaining a situation in which a signal is transferred from a pixel to a digital signal processor. [Diagram 3] 11 is a graph showing characteristics in a state where a capacitor is not connected. [Figure 4] 11 is a graph showing characteristics from a state in which a capacitor is not connected to a state in which a capacitor is connected. [Diagram 5] 11 is a graph showing characteristics of an imaging device according to a comparative example. [Figure 6] 4 is a graph showing characteristics of the imaging device according to the first embodiment. [Figure 7] FIG. 2 is a diagram showing operation timing of the imaging device according to the first embodiment. [Figure 8] FIG. 11 is a schematic diagram for explaining the configuration of a pixel according to a second embodiment. [Figure 9] 10 is a graph showing characteristics from a state in which no capacitor is connected to a state in which two capacitors are connected in the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that each embodiment described below is merely a specific example for implementing the present disclosure, and is not intended to limit the interpretation of the present disclosure. In addition, in order to facilitate understanding of the description, the same reference numerals are used as much as possible for the same components in each drawing, and duplicate descriptions may be omitted. ===First embodiment===

[0012] The configuration of an imaging device 100 will be described with reference to Fig. 1. Fig. 1 is a schematic diagram for explaining the configuration of the imaging device 100 according to the first embodiment. The imaging device of the present disclosure is applied to terminals such as digital cameras, and smartphones, tablets, and personal computers equipped with a camera function.

[0013] As shown in FIG. 1, the imaging device 100 is, for example, a CMOS image sensor, and includes a control circuit 110, pixels 120, signal lines 130, a readout circuit 140, and a digital signal processing unit 150.

[0014] The control circuit 110 is, for example, a circuit that drives the pixels 120. The control circuit 110 outputs data read from the pixels 120 to the outside, for example.

[0015] The pixels 120 accumulate optical signals corresponding to an image on the imaging device 100, for example, based on a control signal output from the control circuit 110. Note that the pixels 120 may generate their own control signals instead of the control signals output from the control circuit 110. The imaging device 100 includes a plurality of pixels 120, which are arranged two-dimensionally.

[0016] The signal lines 130 are, for example, conductors that transmit signals read out from the pixels 120. The signal lines 130 are provided, for example, along the column direction of the multiple pixels 120 (the Y direction in FIG. 1).

[0017] The readout circuit 140 receives analog signals read out from the multiple pixels 120 via the signal line 130. The readout circuit 140 converts the analog signals read out from the multiple pixels 120 into digital signals.

[0018] The digital signal processor 150 processes, for example, the digital signal output from the read circuit 140, and transmits the processed signal to a processor, memory, or the like via a data bus.

[0019] 1, for example, the digital signal processing unit 150 may not be included in the imaging device 100, but may be included in a subsequent processor (not shown). In other words, the position (electrical connection relationship) at which the digital signal processing unit 150 is arranged in the present disclosure is not limited.

[0020] Next, a situation in which a signal is transferred from the pixel 120 to the digital signal processor 150 will be described with reference to Fig. 2. Fig. 2 is a block diagram for explaining a situation in which a signal is transferred from the pixel 120 to the digital signal processor 150.

[0021] First, the pixel 120 will be described. As shown in Fig. 2, the pixel 120 includes, for example, a photodiode 121, transistors 122 to 126, a capacitor 127, and an FD node 128. Note that the pixel 120 includes, for example, an FD (Floating Diffusion) node 128 connected to the gate of the transistor 125. The FD node 128 has, for example, a predetermined capacitance. For convenience, the terminals serving as the source or drain of each transistor are referred to as input terminals or output terminals.

[0022] The photodiode 121 is, for example, a diode that accumulates electric charge in response to incident light. For example, the anode of the photodiode 121 is connected to a reference potential, and the cathode is connected to an FD node 128 through the transistor 122. The transistor 122 is turned on when, for example, a control signal TX is input to the gate.

[0023] The FD node 128 is connected to a power supply Vdd through, for example, a transistor 123 and a transistor 124. The transistor 123 is turned on when, for example, a control signal GS is input to the gate. The transistor 124 is turned on when, for example, a control signal RESET is input to the gate.

[0024] The capacitor 127 is, for example, a capacitor for accumulating charge exceeding the saturation charge of the photodiode 121. By using the capacitor 127, the imaging device 100 can widen the input dynamic range determined by the capacitance of the photodiode 121. For example, one end of the capacitor 127 is connected to a reference potential, and the other end is connected to a node where the transistor 123 and the transistor 124 are connected in series. In other words, the other end of the capacitor 127 is connected to the input terminal of the transistor 123. That is, the capacitor 127 transfers the accumulated charge to the FD node 128 when the transistor 123 is in an on state, for example.

[0025] For example, the transistor 125 has a gate terminal connected to the FD node 128, an input terminal connected to a power supply Vdd, and an output terminal connected to a signal line 130 through the transistor 126. The transistor 126 is turned on when a control signal SEL is input to the gate.

[0026] Next, the read circuit 140 will be described. As shown in Fig. 2, the read circuit 140 includes, for example, an amplifier 141, an analog-to-digital converter 142, and a line memory 143. In Fig. 2, a constant current source 144 is illustrated as a load of the amplifier 141.

[0027] The amplifier 141 is an amplifier that amplifies a signal output from the pixel 120, for example, with a gain according to a predetermined timing. For example, the amplifier 141 may amplify an output signal output from the output terminal of the transistor 125 at a first timing with a first gain, and amplify an output signal output from the output terminal of the transistor 125 at a second timing subsequent to the first timing with a second gain different from the first gain.

[0028] For example, when a full-scale range (hereinafter referred to as "FSR") voltage is V_FSR, the analog-digital converter 142 converts an analog signal of LL (Lower Limit) to LL+V_FSR output from the amplifier 141 into a digital signal. For example, when electrons are accumulated as an analog signal, the analog voltage decreases as the amount of light increases. Therefore, in the following, a case where the value of the digital signal in the analog-digital converter 142 corresponds to LL will be described as "when the digital signal is saturated." Also, for example, when holes are accumulated as an analog signal, the analog voltage increases as the amount of light increases. Therefore, in this case, a case where the value of the digital signal corresponds to LL+FSR will be referred to as "when the digital signal is saturated." In either case, the digital signal of the AD converter generally outputs a maximum value (for example, 1023 in the case of a 10-bit AD converter).

[0029] In the description of this embodiment, the amplifier 141 is described as an independent block, but this is for ease of understanding of this embodiment and is not limited thereto. The amplifier 141 may have the function of an amplifier and the function of an analog-to-digital converter, for example, by combining an amplifier and an analog-to-digital converter in a circuit. Here, the role of the amplifier 141 is to change the ratio of the voltage amplitude of the signal on the signal line 130 output from the pixel 120 to the FSR. That is, the amplifier 141 may be an amplifier having a function of changing the above ratio by increasing or decreasing a reference voltage as is done in many analog-to-digital converters.

[0030] The line memory 143 holds, for example, a digital signal output from the analog-digital converter 142. The line memory 143 is composed of, for example, a latch, a static random access memory (SRAM), a dynamic random access memory (DRAM), etc. The line memory 143 may be composed of, for example, line memories 143a to 143d. The read circuit 140 selects a line memory that holds a digital signal according to a predetermined timing.

[0031] The read circuit 140 transfers a digital signal from the line memory 143 selected according to a predetermined timing to the digital signal processor 150, for example.

[0032] Next, a description will be given of the digital signal processing unit 150. As shown in Fig. 2, the digital signal processing unit 150 includes, for example, a subtractor 151, a digital amplifier 152, and a selector 153.

[0033] The subtractor 151, for example, subtracts each of the multiple digital signals transmitted from the line memory 143. For example, the subtractor 151 includes, for example, a subtractor 151a and a subtractor 151b. For example, the subtractor 151a subtracts the value of the line memory 143a from the value of the line memory 143c. The subtractor 151b subtracts the value of the line memory 143b from the value of the line memory 143d.

[0034] Digital amplifier 152 amplifies, for example, the digital signal subjected to subtraction by subtractor 151 with a predetermined gain. For example, digital amplifier 152 may include digital amplifier 152a and digital amplifier 152b. Digital amplifier 152a receives the digital signal subjected to subtraction by subtractor 151a. Digital amplifier 152b receives the digital signal subjected to subtraction by subtractor 151b.

[0035] The selector 153 selects, for example, one of the digital signals output from the digital amplifier 152a and the digital amplifier 152b. The selector 153 outputs the selected digital signal to the output node 160.

[0036] Specifically, the selector 153 selects one of the two types of digital signals amplified in the digital amplifier 152 so as to, for example, cause the value of the digital signal output from the digital signal processing unit 150 to increase substantially monotonically and continuously with respect to the amount of light incident on the photodiode 121.

[0037] Next, a mechanism capable of suppressing the occurrence of artifacts in the first embodiment will be described with reference to Fig. 3 and Fig. 4. Fig. 3 is a graph showing characteristics in a state where the capacitor 127 is not connected (the transistor 123 is in an off state). Fig. 4 is a graph showing characteristics from a state where the capacitor 127 is not connected to a state where the capacitor 127 is connected (the transistor 123 is in an on state). In Figs. 3 and 4, the horizontal axis indicates the amount of light incident on the pixel 120, and the vertical axis indicates the magnitude of the digital signal output from the digital signal processing unit 150.

[0038] 3, a description will be given of how the characteristics are adjusted to increase substantially monotonically and continuously when the capacitor 127 is not connected. Hereinafter, the state in which the transistor 123 is on and the capacitor 127 is not connected will be referred to as a "state of high pixel conversion gain."

[0039] Here, the term "pixel conversion gain" refers to, for example, the ratio of the voltage at the pixel output (signal line 130) to a given charge generated by the photodiode 121.

[0040] Specifically, when the transistor 123 is in the on state, the charge q0 generated by the photodiode 121 is converted into a voltage at the gate of the transistor 125 with a total capacitance (e.g., 51C) of the capacitance of the FD node 128 (e.g., 1C) when the transistor 123 is in the off state and the capacitance of the capacitor 127 (e.g., 50C) and is output to the signal line 130 (for example, V=q0 / 51C, assuming that the input / output voltage gain of the transistor 125 is 1). The signal amplitude relative to the charge can be reduced by designing the capacitance value of the capacitor 127 to be large. For this reason, the on state of the transistor 123 is referred to as a "state of low pixel conversion gain."

[0041] On the other hand, when the transistor 123 is in the off state, the total capacitance of the FD node 128 is smaller (for example, 1C) than when it is in the on state, and the charge q0 generated by the photodiode 121 produces a larger signal amplitude than when the transistor 123 is in the on state (for example, V=q0 / 1C, assuming that the input / output voltage gain of the transistor 125 is 1). For this reason, the off state of the transistor 123 is called a "state of high pixel conversion gain."

[0042] 3A, for example, a solid line L11 indicates the characteristics when the gain of the amplifier 141 is the gain G11, and a solid line L12 indicates the characteristics when the gain of the amplifier 141 is the gain G12. In the following, as an example, the gain G11 is assumed to be larger than the gain G12.

[0043] 3A, in the light amount range R11, there are two types of output for the same light amount. Furthermore, in the light amount range R12, at the light amount In11 where the gain switches from G11 to G12, the magnitude of the digital signal output from the digital signal processor 150 does not increase substantially monotonically and continuously.

[0044] Therefore, as shown in FIG. 3B, the digital amplifier 152 amplifies the digital signal corresponding to the solid line L12 so that the characteristic increases substantially monotonically and continuously. Here, the substantially monotonically and continuously increasing means, for example, that the magnitude of the continuous digital signal output from the digital signal processor 150 increases substantially proportionally to the increase in the amount of light incident on the pixel 120. Note that the substantially monotonically and continuously increasing also includes, for example, as shown in FIG. 3B, that the magnitude (vertical axis) of the continuous digital signal output from the digital signal processor 150 increases stepwise substantially proportionally to the increase in the amount of light incident on the pixel 120 (horizontal axis). The amplification coefficient of the digital amplifier 152 may be preset according to, for example, the ratio between the gain G1 and the gain G2, or may be finely adjusted by calibration.

[0045] When the digital signal amplified by the lower gain G12 is amplified by the digital amplifier 152, if the maximum value of the amplified digital signal exceeds a permissible value (for example, 1023 in the case of 10 bits), a predetermined attenuation coefficient may be multiplied in the digital amplifier 152. This allows the digital signal output from the digital amplifier 152 to fall within the permissible value.

[0046] Here, for example, when a digital signal amplified with the higher gain G11 is present without being saturated, the selector 153 selects the digital signal. On the other hand, for example, when the digital signal is saturated, the selector 153 selects a digital signal amplified with the lower gain G12. Specifically, for example, when the saturation value is 1024, the selector 153 may select the digital signal amplified with the gain G12 when it exceeds 900 (hereinafter referred to as the "threshold value"). For example, the threshold value may be set in the selector 153 based on a guard band including pixel variations and signal noise.

[0047] Next, a state in which the characteristics are adjusted to increase substantially monotonically and continuously when the capacitor 127 is connected (the transistor 123 is in the ON state) will be described with reference to Fig. 4. As described above, the state in which the transistor 123 is in the ON state and the capacitor 127 is connected is called a "state of low pixel conversion gain".

[0048] 4A, for example, a solid line L21 indicates a characteristic obtained by combining the solid lines L11 and L12 shown in FIG. 3B, a solid line L22 indicates a characteristic when the gain of the amplifier 141 is a gain G21, and a solid line L23 indicates a characteristic when the gain of the amplifier 141 is a gain G22. For example, the gain G21 is larger than the gain G22.

[0049] 4A, in light amount range R21, there are three types of output for the same light amount. Furthermore, in light amount range R22, in light amount In21 where the pixel conversion gain switches from high to low, and in light amount In22 where the gain switches from gain G21 to gain G22, the magnitude of the digital signal output from digital signal processor 150 does not increase substantially monotonically and continuously.

[0050] 4B, the digital signal is amplified so that the characteristic increases substantially monotonically and continuously in the digital amplifier 152. In this case, the amplification coefficient of the digital amplifier 152 may be preset according to, for example, the ratio between the high pixel conversion gain and the low pixel conversion gain, or the ratio between the gain G21 and the gain G22, or may be fine-tuned by calibration.

[0051] Specifically, for a signal with a low pixel conversion gain in the light amount range T22 in Fig. 4(A), the ratio between a high pixel conversion gain and a low pixel conversion gain (hereinafter referred to as the "pixel conversion gain ratio") is multiplied by the digital amplifier 152, so that the solid lines L21 and L23 increase substantially monotonically and continuously. Furthermore, for a digital signal corresponding to the solid line L22, the pixel conversion gain ratio is multiplied by the ratio between the gain G21 and the gain G22 (hereinafter referred to as the "voltage gain ratio"), so that the solid lines L21 to L23 increase substantially monotonically and continuously, as shown in Fig. 4(B).

[0052] Here, when the digital signal corresponding to the solid line L21 is present and not saturated, the selector 153 selects that digital signal. On the other hand, when the digital signal is saturated, for example, the selector 153 selects a digital signal amplified with a higher gain G21 in the low pixel conversion gain. And, when the digital signal amplified with the gain G21 is saturated, for example, the selector 153 selects a digital signal amplified with a lower gain G22.

[0053] Next, the mechanism for suppressing the occurrence of the artifacts shown in FIGS. 3 and 4 will be described in detail using the following equations.

[0054] In the following, the high pixel conversion gain is designated as G_pix_high, the low pixel conversion gain is designated as G_pix_low, the higher gain in amplifier 141 is designated as G_vol_high, the lower gain in amplifier 141 is designated as G_vol_low, the maximum saturation charge number of pixel 120 including capacitor 127 is designated as Q_sat, and the number of quantization steps of analog-to-digital converter 142 is designated as N.

[0055] In the following, an imaging device according to a comparative example will also be briefly described, and it will be explained how artifacts are suppressed in the imaging device 100 according to the first embodiment.

[0056] In the imaging device according to the comparative example, the gain is not switched in the amplifier 141 but is constant (for example, the system of Patent Document 1). First, with reference to FIG. 5, it will be described that artifacts may occur in the imaging device according to the comparative example. FIG. 5 is a graph showing characteristics of the imaging device according to the comparative example. In FIG. 5, the horizontal axis indicates the amount of light incident on a pixel, and the vertical axis indicates the magnitude of the digital signal output from the digital signal processing unit.

[0057] The quantization width on the high pixel conversion gain side in the light amount range R31 shown in FIG. 5, where the state switches from a high pixel conversion gain state to a low pixel conversion gain state, is calculated by equation (1).

[0058] Quantization width (Q11)= Qsat * (G_pix_low / G_pix_high) * (1 / N) ··· (1)

[0059] Moreover, the quantization width on the low pixel conversion gain side in the light amount range R31 shown in FIG. 5 is calculated by the formula (2).

[0060] Quantization width (Q12)= Qsat*(1 / N) ··· (2)

[0061] Therefore, the ratio between the quantization width (Q11) on the high pixel conversion gain side and the quantization width (Q12) on the low pixel conversion gain side is calculated by the formula (3).

[0062] Ratio of quantization width (Q12 / Q11)= G_pix_high / G_pix_low ··· (3)

[0063] According to equation (3), for example, if G_pix_high is set to "1" and G_pix_low is set to "1 / 50" and the dynamic range expansion by the capacitance of capacitor 127 is designed to be 50 times, the ratio of the quantization width will be 50 times, and artifacts will occur.

[0064] Next, an improvement in the quantization width ratio in the imaging device 100 according to the first embodiment compared to an imaging device according to a comparative example will be described with reference to Fig. 6. Fig. 6 is a graph showing characteristics of the imaging device 100 according to the first embodiment. In Fig. 6, the horizontal axis indicates the amount of light incident on a pixel, and the vertical axis indicates the magnitude of the digital signal output from the digital signal processing unit 150.

[0065] The quantization width on the high pixel conversion gain side in the light amount range R41 shown in FIG. 6, where the state switches from a high pixel conversion gain state to a low pixel conversion gain state, is calculated by equation (4).

[0066] Quantization width (Q21) = Qsat * (G_pix_low / G_pix_high) * (1 / N) ··· (4)

[0067] Moreover, the quantization width (Q21) on the low pixel conversion gain side in the light amount range R41 shown in Fig. 6 is obtained by the formula (5). Note that the formula (5) is an equation for obtaining the quantization width (Q22) when the gain of the amplifier 141 on the low pixel conversion gain side is low.

[0068] Quantization width (Q22) = Qsat*(G_read_low / G_read_high) *(1 / N) (5)

[0069] Therefore, the ratio between the quantization width (Q21) on the high pixel conversion gain side and the quantization width (Q22) when the gain of the amplifier 141 on the low pixel conversion gain side is low is calculated by equation (6).

[0070] Quantization width ratio (Q22 / Q21) = (G_pix_high / G_pix_low) / (G_read_high / G_read_low) ··· (6)

[0071] According to equation (6), for example, if the lower gain in amplifier 141 is "G_read_low=1x" and the higher gain is "G_read_high=8x", the quantization width ratio of the imaging device 100 in the first embodiment is 6.25x.

[0072] That is, while the ratio of the quantization width in the image pickup device according to the comparative example is 50, the ratio of the quantization width in the image pickup device 100 according to the first embodiment can be reduced to 6.25. Therefore, artifacts are suppressed in the image pickup device 100.

[0073] In addition, in the imaging device according to the comparative example, when the ratio of the quantization width is reduced from 50 times to 6.25 times, the number of quantization steps in the analog-digital converter 142 must be increased by 8 times (here, 8N). That is, in digital conversion in a state of low pixel conversion gain, it is necessary to separately prepare an analog-digital converter 142 with 3 bits more. This increases the conversion time in the analog-digital converter 142. In particular, in a Time to Digital Converter type analog-digital converter such as a single slope type, the time required for digital conversion increases by 8 times, and such a design is not realistic. In this regard, in the imaging device 100 according to the first embodiment, although the number of digital conversions increases (for example, the number of conversions corresponding to the solid line L22 in FIG. 4 increases), the time per digital conversion can be suppressed. That is, in the imaging device 100, digital conversion can be performed in a shorter time. <<Operation>>

[0074] Next, the operation of the imaging device 100 will be described with reference to Fig. 7. Fig. 7 is a diagram showing the operation timing of the imaging device 100 according to the first embodiment. Fig. 7 shows the operation when, in the imaging device 100, digital conversion is performed in two ways, low gain and high gain, at a high pixel conversion gain, and when digital conversion is performed in two ways, low gain and high gain, at a low pixel conversion gain.

[0075] First, at time t701, the imaging device 100 turns on the transistors 122, 123, and 124, and resets the photodiode 121, the capacitor 127, and the FD node 128. After the resetting, all the transistors are turned off, and signal accumulation begins.

[0076] At time 702 , when a signal is to be read out from the pixel 120 , the transistor 126 is turned on to connect the pixel 120 to the signal line 130 .

[0077] First, when the transistor 123 is in an OFF state (high pixel conversion gain state), the amplifier 141 is set to a high gain, and the potential of the FD node 128 in the reset state is converted into a digital signal by the analog-to-digital converter 142 through the amplifier 141. The converted digital signal is stored in the line memory 143a.

[0078] Next, at time 703, the imaging device 100 sets, for example, the amplifier 141 to a low gain, and converts the potential of the FD node 128 in the reset state into a digital signal by the analog-to-digital converter 142 through the amplifier 141. The converted digital signal is stored in the line memory 143b.

[0079] Next, at time 704 , the imaging device 100 transfers charge from the photodiode 121 to the FD node 128 by turning on the transistor 122 , for example.

[0080] Next, at time 705, the imaging device 100 sets the amplifier 141 to a high gain, for example, and converts the potential of the FD node 128 corresponding to the signal of the photodiode 121 read out in a state of high pixel conversion gain into a digital signal by the analog-to-digital converter 142 via the amplifier 141. The converted digital signal is stored in the line memory 143c.

[0081] Next, at time 706, the imaging device 100 sets the amplifier 141 to a low gain, for example, and converts the potential of the FD node 128 corresponding to the signal of the photodiode 121 read out in a state of high pixel conversion gain into a digital signal by the analog-to-digital converter 142 via the amplifier 141. The converted digital signal is stored in the line memory 143d.

[0082] After time 707, the imaging device 100 processes, for example, signals (four types of signals) sequentially transferred from the line memories 143a to 143d.

[0083] Specifically, the readout circuit 140 subtracts the digital value stored in the line memory 143a from the digital value stored in the line memory 143c for each pixel 120. This allows a digital signal with a high gain of the amplifier 141 at a high pixel conversion gain, from which variations occurring in a reset state have been removed, to be input to the digital amplifier 152a.

[0084] Similarly, the read circuit 140 subtracts the digital value stored in the line memory 143b from the digital value stored in the line memory 143d. This allows a digital signal that is a low gain digital signal of the amplifier 141 at a high pixel conversion gain and from which variations occurring in the reset state have been removed to be input to the digital amplifier 152b.

[0085] Then, the selector 153 of the digital signal processing unit 150 selects either the digital signal output from the digital amplifier 152a or the digital signal output from the digital amplifier 152b, and causes the value of the digital signal output from the digital signal processing unit 150 to increase substantially monotonically and continuously with respect to the amount of light incident on the photodiode 121. This makes it possible to obtain a characteristic that combines the solid lines L11 and L12 in FIG.

[0086] Next, as specifically shown after time 707, the imaging device 100, for example, when the transistor 123 is in the ON state (low pixel conversion gain state), causes the digital signal value output from the digital signal processor 150 to increase substantially monotonically and continuously.

[0087] First, at time 707 , the imaging device 100 transfers charge from the photodiode 121 to the transistor 125 by turning on the transistor 123 , for example.

[0088] At time 708, the imaging device 100 sets the amplifier 141 to a high gain, for example, and converts the potential of the FD node 128 corresponding to the signal of the photodiode 121 read out in a state of low pixel conversion gain into a digital signal by the analog-to-digital converter 142 via the amplifier 141. The converted digital signal is stored in the line memory 143c.

[0089] Next, at time 709, the amplifier 141 is set to a low gain, and the potential of the FD node 128 corresponding to the signal of the photodiode 121 read out in a state of low pixel conversion gain is converted into a digital signal by the analog-to-digital converter 142 via the amplifier 141. The converted digital signal is stored in the line memory 143d.

[0090] Next, at time 710, the transistor 122, the transistor 123, and the transistor 124 are turned on to reset the photodiode 121, the capacitor 127, and the FD node 128. After the reset, all the transistors are turned off to start accumulating signals.

[0091] Next, at time 711, with the transistor 123 in the OFF state (high pixel conversion gain state), the amplifier 141 is set to a high gain, and the potential of the FD node 128 in the reset state is converted into a digital signal by the analog-to-digital converter 142 through the amplifier 141. The converted digital signal is stored in the line memory 143a.

[0092] Next, at time 712, the imaging device 100 sets, for example, the amplifier 141 to a low gain, and converts the potential of the FD node 128 in the reset state into a digital signal by the analog-to-digital converter 142 via the amplifier 141. The converted digital signal is stored in the line memory 143b.

[0093] After time 713, the imaging device 100 processes, for example, signals (four types of signals) sequentially transferred from the line memories 143a to 143d.

[0094] Specifically, the readout circuit 140 subtracts the digital value stored in the line memory 143a from the digital value stored in the line memory 143c for each pixel 120. This allows a digital signal that is a high-gain digital signal of the amplifier 141 at a low pixel conversion gain and from which variations occurring in a reset state have been removed to be input to the digital amplifier 152a.

[0095] Similarly, the read circuit 140 subtracts the digital value stored in the line memory 143b from the digital value stored in the line memory 143d. This allows a digital signal at the low gain of the amplifier 141 at a low pixel conversion gain, from which variations occurring in the reset state have been removed, to be input to the digital amplifier 152b.

[0096] Then, the selector 153 of the digital signal processing unit 150 selects either the digital signal output from the digital amplifier 152a or the digital signal output from the digital amplifier 152b, and causes the value of the digital signal output from the digital signal processing unit 150 to increase substantially monotonically and continuously with respect to the amount of light incident on the photodiode 121. This provides a characteristic that combines the solid lines L22 and L23 in FIG.

[0097] As a result, the imaging device 100 can obtain characteristics that are a combination of the solid lines L21, L22, and L23 shown in FIG. <<First Modification>>

[0098] In the above, the selector 153 has been described as selecting a digital signal amplified with the higher gain G11 when the digital signal is present and not saturated, and selecting a digital signal amplified with the lower gain G12 when the digital signal is saturated, but this is not limited to the above.

[0099] For example, the selector 153 may combine a digital signal amplified with a gain G11 and a digital signal amplified with a gain G12 in the vicinity of saturation of the digital signal amplified with the higher gain G11. Here, the vicinity of saturation of the digital signal may be, for example, 80% (e.g., a digital value of 800) of a digital value corresponding to the number of bits in the digital conversion (e.g., a digital value of 1023 for 10 bits).

[0100] In the first modified example, the selector 153 may have a function of an adder that adds a plurality of signals. Specifically, the selector 153 multiplies each of the digital signal amplified by the gain G11 and the digital signal amplified by the gain G12 by a weighting coefficient (e.g., 0 to 1), and outputs a combined signal.

[0101] For example, the selector 153 may combine the signals by increasing the weight of the digital signal amplified with the gain G12 relative to the digital signal amplified with the gain G11 as the digital signal amplified with the gain G11 approaches saturation.

[0102] According to the first modified example, the change in the quantization width at the timing when the pixel conversion gain state is switched can be further suppressed, so that artifacts can be further suppressed. <<Second Modification>>

[0103] In the above description, the imaging device 100 has been described as having one amplifier 141 and one analog-to-digital converter 142 for each pixel column of the pixels 120, but the present invention is not limited to this.

[0104] For example, the imaging device 100 may have an amplifier and an analog-digital converter of a different system from the amplifier 141 and the analog-digital converter 142 of one system. In this case, a digital signal amplified with a gain G11 may be output from the amplifier 141 and the analog-digital converter 142 of one system at a first timing, and a digital signal amplified with a gain G12 may be output from the amplifier and the analog-digital converter of a different system at the same first timing. That is, instead of storing a digital signal when the amplifier 141 is set to a high gain and a digital signal when the amplifier 141 is set to a low gain in the line memory 143 at different timings (for example, consecutive timings) as shown in FIG. 7, the imaging device 100 can store each digital signal in the line memory 143 at the same timing. Here, the same timing includes timings that are slightly shifted, for example, within a few clocks, in addition to timings that overlap.

[0105] According to the second modification, artifacts can be suppressed in a shorter time. <<Third Modification>>

[0106] Furthermore, the imaging device 100 may output a signal in a high pixel conversion gain state and a signal in a low pixel conversion gain state, which appear at the FD node 128, as a digital signal from the analog-digital converter 142, independently for example for every predetermined number of bits (for example, every 10 bits). Alternatively, the signal in a high pixel conversion gain state and the signal in a low pixel conversion gain state may be synthesized, and the synthesized signal may be output collectively as a signal of a predetermined number of bits (for example, 12 bits to 16 bits) from the analog-digital converter 142. In this case, it is desirable to set the predetermined number of bits so that the quantization width falls within about Qsat*(G_read_low / G_read_high)*(1 / N).

[0107] According to the third modification, artifacts can be suppressed in a shorter time. ===Second embodiment===

[0108] An imaging device 200 according to the second embodiment will be described with reference to Figs. 8 and 9. In the imaging device 200, the pixel 120 in the imaging device 100 has only the capacitor 127 as a capacitor for widening the input dynamic range, but the present invention is not limited to this. The imaging device 200 has, for example, a plurality of capacitors connected in parallel in addition to the capacitor 127 of the imaging device 100. This makes it possible to suppress artifacts more effectively than the imaging device 100. In the following, only components different from the imaging device 100 will be described, and a description of components similar to those of the imaging device 100 will be omitted.

[0109] The configuration of a pixel 220 having a plurality of capacitors in an imaging device 200 will be described with reference to Fig. 8. Fig. 8 is a schematic diagram for explaining the configuration of a pixel 220 according to a second embodiment. Note that Fig. 8 shows, as an example, a configuration in which a capacitor 222 is connected in parallel in addition to the capacitor 127.

[0110] As shown in FIG. 8, the pixel 220 further includes a transistor 221 and a capacitor 222 compared to the pixel 120, for example.

[0111] The capacitor 222 is, for example, a capacitor for accumulating a charge exceeding the saturation charge of the photodiode 121. For example, one end of the capacitor 222 is connected to a reference potential (for example, ground) and the other end is connected to the input terminal of the transistor 125 through the transistor 221. It is desirable that the capacitor 222 has a capacitance smaller than that of the capacitor 127. Here, the capacitor 127 is connected to the input terminal of the transistor 125 through the transistor 123 and the transistor 221.

[0112] Next, a mechanism by which the imaging device 200 can suppress artifacts compared to the imaging device 100 by using the configuration of the pixel 220 will be described with reference to Fig. 9. Fig. 9 is a graph that illustrates the characteristics obtained by amplifying a signal with two types of gain by the amplifier 141 for three types of pixel conversion gain.

[0113] 9, in the imaging device 200, when the transistor 221 is in an off state (high pixel conversion gain state, G_pix_high in FIG. 9), the output signal output from the transistor 125 is amplified by the amplifier 141 (not shown) at a high gain (G_read_high in FIG. 9) and a low gain (G_read_low in FIG. 9). In FIG. 9, the characteristics of the digital signals obtained by converting the analog signals amplified at the respective gains by the analog-digital converter 142 (not shown) are shown as characteristics T11 and T12.

[0114] Furthermore, in the imaging device 200, the output signal output from the transistor 125 when the transistor 221 is in the on state (a state of intermediate pixel conversion gain, G_pix_mid in FIG. 9) is amplified by the amplifier 141 at a high gain (G_read_high in FIG. 9) and a low gain (G_read_low in FIG. 9). In FIG. 9, the characteristics of the digital signals obtained by converting the analog signals amplified by the respective gains in the analog-digital converter 142 are shown as characteristics T21 and T22.

[0115] Furthermore, in the imaging device 200, when the transistor 221 and the transistor 123 are in an on state (a state of low pixel conversion gain, G_pix_low in FIG. 9), the output signal output from the transistor 125 is amplified by the amplifier 141 at a high gain (G_read_high in FIG. 9) and a low gain (G_read_low in FIG. 9). In FIG. 9, the characteristics of the digital signals obtained by converting the analog signals amplified by the respective gains in the analog-digital converter 142 are shown as characteristics T31 and T32.

[0116] In the imaging device 200, a characteristic amplified with different gains in the same pixel conversion gain state is combined with a characteristic amplified with a predetermined gain in a different pixel conversion gain state. Specifically, in the imaging device 200, for example, in the selector 153 (not shown), a digital signal showing the characteristics T11 and T12 in a high pixel conversion gain state is combined with a digital signal showing the characteristics T21 of a high gain in an intermediate pixel conversion gain. In addition, in the imaging device 200, for example, in the selector 153 (not shown), a digital signal showing the characteristics T31 and T32 in a low pixel conversion gain state is combined with a digital signal showing the characteristics T22 of a low gain in an intermediate pixel conversion gain state.

[0117] Furthermore, for example, the selector 153 may combine signals by increasing the weight of the digital signal amplified with a high gain in an intermediate pixel conversion gain state as the characteristics of the digital signal in a high pixel conversion gain state approach saturation (or may combine more digital signals).

[0118] As a result, the imaging device 200 can suppress artifacts more effectively than the imaging device 100. Furthermore, compared to the imaging device 100, for example, when only two pieces of original data can be obtained, the imaging device 200 can suppress artifacts using two pieces of data, whereas the imaging device 100 creates three pieces of data, and therefore can reduce the amount of data to be processed. ===Summary===

[0119] The imaging device 100 according to the first embodiment includes a pixel 120 including a photodiode 121 that accumulates electric charge in response to incident light and has an anode connected to a reference potential, a transistor 125 (first transistor) having an input terminal (e.g., a base) connected to the cathode of the photodiode 121, and a capacitor 127 (first capacitor) having one end connected to the reference potential and the other end connected to an input terminal (e.g., a gate) of the transistor 125 (first transistor) through a transistor 123 (second transistor), and a signal output from an output terminal (e.g., a drain or source) of the transistor 125 (first transistor) when the transistor 123 (second transistor) is in an on state. The digital signal processor 150 includes an amplifier 141 (first amplifier) ​​that amplifies a first output signal by a first gain and amplifies a second output signal output from an output terminal (e.g., a drain or source) of a transistor 125 (first transistor) by a second gain lower than the first gain, an analog-to-digital converter 142 (converter) that converts the signal amplified by the amplifier 141 (first amplifier) ​​into a digital signal, and a digital signal processor 150 (control circuit) that uses the first digital signal when the first digital signal corresponding to the first output signal is not saturated and selects and outputs a second digital signal corresponding to the second output signal when the first digital signal is saturated. This makes it possible to suppress the occurrence of artifacts caused by switching of pixel conversion gain in an imaging device having a capacitor for widening an input dynamic range.

[0120] Moreover, the digital signal processing unit 150 (control circuit) of the imaging device 100 according to the first embodiment includes a digital amplifier 152 (second amplifier) ​​that amplifies the digital signal output from the analog-to-digital converter 142 (converter) so as to substantially monotonically and continuously increase the value of the digital signal output from the digital signal processing unit 150 (control circuit) with respect to the amount of light incident on the photodiode 121. This makes it possible to suppress the occurrence of artifacts caused by switching of pixel conversion gain.

[0121] Furthermore, the digital signal processor 150 (control circuit) of the imaging device 100 according to the first embodiment uses a digital signal (hereinafter referred to as an off digital signal) converted by the analog-to-digital converter 142 (converter) when the transistor 123 (second transistor) is in an off state and the digital signal (off digital signal) is not saturated, and uses and outputs at least one of the first digital signal and the second digital signal when the off digital signal is saturated. This makes it possible to suppress the occurrence of artifacts caused by switching of pixel conversion gain.

[0122] Moreover, the amplifier 141 (first amplifier) ​​of the imaging device 100 according to the first embodiment amplifies the third output signal output from the output terminal (e.g., drain or source) of the transistor 125 (first transistor) with a third gain when the transistor 123 (second transistor) is in an off state, and amplifies the fourth output signal output from the output terminal (e.g., drain or source) of the transistor 125 (first transistor) with a fourth gain higher than the third gain, and the digital signal processing unit 150 (control circuit) uses at least one of the third digital signal corresponding to the third output signal and the fourth digital signal corresponding to the fourth output signal output from the analog-to-digital converter 142 (converter) as the off digital signal. This makes it possible to further suppress the occurrence of artifacts caused by switching of pixel conversion gain.

[0123] The imaging device 200 according to the second embodiment further includes a capacitor 222 (second capacitor) electrically connected in parallel with the capacitor 127 (first capacitor), the capacitor having one end connected to a reference potential and the other end connected to an input terminal (e.g., gate) of the transistor 125 (first transistor) through a transistor 221 (third transistor), and having a capacitance smaller than that of the capacitor 127 (first capacitor), and the capacitor 127 (first capacitor) is connected to the input terminal (e.g., gate) of the transistor 125 (first transistor) through the transistor 123 (second transistor) and the transistor 221 (third transistor). This makes it possible to further suppress the occurrence of artifacts caused by switching of pixel conversion gain with a smaller amount of information processing.

[0124] The above-described embodiments are intended to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. The elements of the embodiments, as well as their arrangements, materials, conditions, shapes, sizes, etc., are not limited to those illustrated and can be changed as appropriate. In addition, configurations shown in different embodiments can be partially substituted or combined with each other. [Explanation of symbols]

[0125] 100, 200...imaging device, 110...control circuit, 120...pixel, 121...photodiode, 122-126...transistor, 127...capacitor, 128...FD node, 130...signal line, 140...readout circuit, 141...amplifier, 142...analog-to-digital converter, 143...line memory, 150...digital signal processing unit, 151...subtractor, 152...digital amplifier, 153...selector.

Claims

1. a pixel including: a photodiode that accumulates charge in response to incident light, the photodiode having an anode connected to a reference potential; a first transistor having a gate terminal connected to a cathode of the photodiode; and a first capacitor having one end connected to the reference potential and the other end connected to the gate terminal of the first transistor through a second transistor; a first amplifier that amplifies a first output signal output from an output terminal of the first transistor by a first gain when the second transistor is in an on-state, and amplifies a second output signal output from the output terminal of the first transistor by a second gain lower than the first gain; a converter that converts the signal amplified by the first amplifier into a digital signal; a control circuit for selecting and outputting a first digital signal, which is a digital signal converted by the converter and corresponds to the first output signal, when the first digital signal is not saturated, and a second digital signal, which corresponds to the second output signal, when the first digital signal is saturated; An imaging device comprising:

2. the control circuit includes a second amplifier that amplifies the digital signal output from the converter so that the value of the digital signal output from the control circuit increases substantially monotonically and continuously with respect to the amount of light incident on the photodiode; The imaging device according to claim 1 .

3. the control circuit uses the off digital signal when the off digital signal converted by the converter is not saturated while the second transistor is in an off state, and uses at least one of the first digital signal and the second digital signal for output when the off digital signal is saturated. The imaging device according to claim 2 .

4. the first amplifier amplifies a third output signal output from an output terminal of the first transistor by a third gain when the second transistor is in an off state, and amplifies a fourth output signal output from an output terminal of the first transistor by a fourth gain higher than the third gain; the control circuit uses at least one of a third digital signal corresponding to the third output signal and a fourth digital signal corresponding to the fourth output signal output from the converter as the off digital signal and outputs the off digital signal. The imaging device according to claim 3 .

5. a second capacitor having one end connected to a reference potential and the other end connected to the gate terminal of the first transistor through a third transistor, the second capacitor having a capacitance smaller than a capacitance of the first capacitor, the second capacitor being electrically connected in parallel with the first capacitor; the first capacitor is connected to a gate terminal of the first transistor through the second transistor and the third transistor; The imaging device according to claim 1 .

6. 1. An imaging method executed by a processor included in an imaging device including a pixel including: a photodiode that accumulates charge in response to incident light, the photodiode having an anode connected to a reference potential; a first transistor having a gate terminal connected to a cathode of the photodiode; and a first capacitor having one end connected to the reference potential and the other end connected to a gate terminal of the first transistor through a second transistor, the method comprising: an amplifying step of amplifying a first output signal output from an output terminal of the first transistor by a first gain while the second transistor is in an on-state, and amplifying a second output signal output from the output terminal of the first transistor by a second gain lower than the first gain; a conversion step of converting the signal amplified in the amplification step into a digital signal; a control step of using a first digital signal converted in the conversion step, the first digital signal corresponding to the first output signal being not saturated, and selecting and outputting a second digital signal corresponding to the second output signal, when the first digital signal is saturated; Imaging method.

7. An imaging device according to any one of claims 1 to 4, Terminal.

Images