Semiconductor Device

Abstract

To provide a highly reliable semiconductor device.SOLUTION: A semiconductor device, in which a cell region and a terminal region are set, includes a first electrode, a semiconductor part provided on the first electrode, an insulating film provided on the semiconductor part in the terminal region, a plurality of second electrodes provided on the insulating film, arranged in a direction from the center to the outer periphery of the semiconductor part when viewed from above, and separated from each other, a first floating electrode provided in the insulating film, overlapping with a gap between a pair of second electrodes that are adjacent among the plurality of second electrodes when viewed from above, and facing one of the pair of second electrodes through the insulating film, and a second floating electrode provided in the insulating film and apart from the first floating electrode, overlapping with the first floating electrode in the gap when viewed from above, having a part thereof that overlaps with the first floating electrode existing below a part of the first floating electrode that overlaps with the gap, and facing the other of the pair of second electrodes through the insulating film.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Conventionally, there has been known a semiconductor device having a cell region in which elements such as diodes or transistors are provided, and a termination region surrounding the cell region. In such a semiconductor device, an attempt has been made to improve the breakdown voltage by providing a structure in the termination region that suppresses the spread of a depletion layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-38937 A Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a highly reliable semiconductor device. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment is a semiconductor device having a cell region and a termination region surrounding the cell region, the semiconductor device including a first electrode, a semiconductor portion provided on the first electrode, an insulating film provided on the semiconductor portion in the termination region, a plurality of second electrodes provided on the insulating film, aligned in a direction from the center of the semiconductor portion toward the periphery as viewed from above and spaced apart from each other, and a gap between a pair of adjacent second electrodes among the plurality of second electrodes provided in the insulating film. In a second direction perpendicular to the first direction a first floating electrode that overlaps with one of the pair of second electrodes via the insulating film; and a second floating electrode that is provided in the insulating film so as to be spaced apart from the first floating electrode and is in contact with the first floating electrode in the gap. In the second directiona second floating electrode that overlaps with the first floating electrode, the portion of the second floating electrode being located below the portion of the first floating electrode that overlaps with the gap, and that faces the other of the pair of second electrodes via the insulating film. [Brief description of the drawings]

[0006] [Figure 1] 1 is a top view showing a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view taken along line AA' in FIG. [Diagram 3] 1 is a top view showing a semiconductor portion of the semiconductor device according to the first embodiment. [Figure 4] 1 is a top view showing a semiconductor portion and an insulating film of a semiconductor device according to a first embodiment. [Diagram 5] 1 is a top view showing a semiconductor portion, an insulating film, an upper electrode, an EQPR electrode, and a plurality of intermediate electrodes of the semiconductor device according to the first embodiment. [Figure 6] 1 is a top view showing a region in which each floating electrode is provided in the semiconductor device according to the first embodiment. [Figure 7] 5A to 5C are schematic views showing the operation of the termination region of the semiconductor device according to the first embodiment. [Figure 8] 1 is a cross-sectional view showing a termination region of a semiconductor device according to a reference example. [Figure 9] FIG. 4 is a cross-sectional view showing a semiconductor device according to a second embodiment. [Figure 10] FIG. 1 is a cross-sectional view showing a semiconductor device according to a reference example. [Figure 11] 13 is a graph showing the simulation results of the relationship between the withstand voltage and charge for the semiconductor device according to the second embodiment and the semiconductor device according to the reference example, with the horizontal axis representing the charge generated on the surface of the protective film and the vertical axis representing the withstand voltage. [Figure 12] 10 is a simulation result showing equipotential lines in a state in which positive and negative charges are generated on the surface of the protective film in the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as the actual ones. Even when the same part is shown, the dimensions and ratios of each part may be different depending on the drawing. Furthermore, in this specification and each drawing, elements similar to those explained with reference to the previous drawings are given the same reference numerals, and detailed explanations are omitted as appropriate.

[0008] For ease of understanding, the following description will use an XYZ Cartesian coordinate system to explain the arrangement and configuration of each part. The X-axis, Y-axis, and Z-axis are mutually perpendicular. The direction in which the X-axis extends is referred to as the "X-direction," the direction in which the Y-axis extends as the "Y-direction," and the direction in which the Z-axis extends as the "Z-direction." For ease of understanding, the direction of the arrow in the Z-direction is referred to as upward and the opposite direction as downward, but these directions are unrelated to the direction of gravity.

[0009] In the following, n + , n - The notation indicates the relative level of impurity concentration in n-type semiconductors. Specifically, a notation with a "+" indicates that the impurity concentration is relatively higher than a notation with a "-". Here, the "impurity concentration" refers to the net impurity concentration after both donor and acceptor impurities are offset in each region.

[0010] <First embodiment> First, the first embodiment will be described. FIG. 1 is a top view showing a semiconductor device according to the present embodiment. FIG. 2 is a cross-sectional view taken along line AA' in FIG. The shape of the semiconductor device 100 is a substantially rectangular parallelepiped in this embodiment, however, the shape of the semiconductor device is not particularly limited to the above shape.

[0011] In the semiconductor device 100, a cell region CE and a termination region EN surrounding the periphery of the cell region CE are defined as shown in Fig. 1. In Fig. 1, the region surrounded by the innermost thick two-dot chain line is the cell region CE, and the entire region outside the cell region CE in the semiconductor device 100 is the termination region EN.

[0012] The cell region CE is provided with one or more types of elements such as diodes or transistors. Examples of the transistors provided in the cell region CE include metal-oxide-semiconductor field-effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBTs). The structure of the termination region EN will be described later.

[0013] 2, the semiconductor device 100 includes a lower electrode 110, a semiconductor portion 120, an insulating film 130, an upper electrode 140, an EQPR (EQuivalent-Potential Ring) electrode 150, intermediate electrodes 161 and 162, a plurality of first floating electrodes 171, 173, and 175, and a plurality of second floating electrodes 172, 174, and 176. In this embodiment, the lower electrode 110 corresponds to the first electrode, and the upper electrode 140, the EQPR electrode 150, and the intermediate electrodes 161 and 162 correspond to the second electrodes. Each portion of the semiconductor device 100 will be described in detail below.

[0014] The lower electrode 110 is provided over substantially the entire area of ​​the lower surface of the semiconductor device 100. That is, the lower electrode 110 is provided over substantially the entire area of ​​the cell region CE and the entire area of ​​the termination region EN. The shape of the lower electrode 110 is flat. In this embodiment, the shape of the lower electrode 110 as viewed from above is substantially rectangular, as shown in FIG. 1. However, the shape of the lower electrode is not limited to the above shape.

[0015] When a diode is provided in the cell region CE, the lower electrode 110 functions as, for example, a cathode electrode of the diode. When a MOSFET is provided in the cell region CE, the lower electrode 110 functions as, for example, a drain electrode of the MOSFET. When an IGBT is provided in the cell region CE, the lower electrode 110 functions as, for example, a collector electrode of the IGBT.

[0016] As shown in FIG. 2, a semiconductor portion 120 is provided on the lower electrode 110, spanning from the cell region CE to the termination region EN.

[0017] FIG. 3 is a top view showing a semiconductor portion of the semiconductor device according to this embodiment. In FIG. 3, for ease of understanding, only the n-type semiconductor portion 120 in the upper surface of the termination region EN is shown. + The region where the stopper region 121c having a dot shape is provided and the region where the p-type semiconductor layer 122 is provided are indicated by mutually different dot patterns.

[0018] The semiconductor part 120 includes, for example, silicon (Si). In this embodiment, the shape of the semiconductor part 120 is a substantially rectangular parallelepiped shape. In this specification, when the component A is located closer to the center C of the semiconductor part than the component B when viewed from above, it is said that "the component A is located inside the component B". Similarly, when the component A is located closer to the outer periphery 120e of the semiconductor part than the component B when viewed from above, it is said that "the component A is located outside the component B". In this embodiment, the center C is located at the intersection of the diagonals of the outer periphery 120e. However, the shape of the semiconductor part is not limited to the above shape.

[0019] 2, the semiconductor section 120 has an n-type semiconductor layer 121 and a p-type semiconductor layer 122. In this embodiment, the n-type semiconductor layer 121 corresponds to a first semiconductor layer, and the p-type semiconductor layer 122 corresponds to a second semiconductor layer.

[0020] The n-type semiconductor layer 121 is + Shape Area 121a, n -Shaped areas 121b and n + In this embodiment, the stopper region 121c has a shape of n + The n-shaped region 121a corresponds to the first semiconductor region. - The n-shaped region 121b corresponds to the second semiconductor region. + The stopper region 121c having a groove shape corresponds to the third semiconductor region.

[0021] n + The region 121a is provided from the cell region CE to the termination region EN. + The n-shaped region 121a is provided on the lower electrode 110 in the termination region EN and is in contact with the lower electrode 110. + The shaped region 121 a is electrically connected to the lower electrode 110 .

[0022] When a diode is provided in the cell region CE, in the portion of the cell region CE where the diode is provided, n + The n-type region 121a is provided on the lower electrode 110 and is in contact with the lower electrode 110. When a MOSFET is provided in the cell region CE, the n-type region 121a is in contact with the lower electrode 110. + The region 121a is provided on the lower electrode 110 and is in contact with the lower electrode 110. When an IGBT is provided in the cell region CE, a p-type semiconductor layer is provided on the lower electrode 110 in the portion of the cell region CE where the IGBT is provided, and an n-type semiconductor layer is provided on the lower electrode 110. + At least a portion of the p-type region 121a is provided on the p-type semiconductor layer.

[0023] n - The region 121b has a shape similar to that of the cell region CE to the termination region EN. + The area 121a is provided with a shape similar to that of the oval shape. - The impurity concentration of the region 121b is n + The impurity concentration of the region 121a is lower than that of the region 121b.

[0024] n + The stopper region 121c has a shape of n in the end region EN.- The upper layer of the region 121b is provided on the outer periphery of the region 121b. + The impurity concentration of the stopper region 121c is n - The impurity concentration of the n-shaped region 121b is higher than that of the n-shaped region 121b. + The stopper region 121c has a substantially rectangular ring shape as shown in FIG.

[0025] As shown in FIG. 2, the p-type semiconductor layer 122 is an upper layer of the n-type semiconductor layer 121, more specifically, - The p-type semiconductor layer 122 is provided in an upper layer portion of the n-type region 121b. The p-type semiconductor layer 122 is provided from the termination region EN to the cell region CE. + It is located inside the stopper region 121c of the n + The p-type semiconductor layer 122 is spaced from the stopper region 121c having a rounded corner as shown in FIG.

[0026] When a diode is provided in the cell region CE, the p-type semiconductor layer 122 may function as a p-type semiconductor layer connected to the anode electrode of the diode in the cell region CE. When a MOSFET or an IGBT is provided in the cell region CE, the p-type semiconductor layer 122 may function as a p-type semiconductor layer adjacent to the gate electrode of the MOSFET or IGBT in the cell region CE via an insulating film.

[0027] As shown in FIG. 2, in the termination region EN, an insulating film 130 is provided on the semiconductor portion 120.

[0028] FIG. 4 is a top view showing a semiconductor portion and an insulating film of the semiconductor device according to this embodiment. In FIG. 4, for ease of understanding, the region in the termination region EN where the insulating film 130 is provided is shown by a dot pattern.

[0029] The insulating film 130 is made of an insulating material, such as, but not limited to, an oxide such as a silicon oxide film, or a nitride such as a silicon nitride. In this embodiment, the shape of the insulating film 130 seen from above is a substantially rectangular ring shape with rounded corners. However, the shape of the insulating film is not limited to the above shape.

[0030] In this embodiment, the inner periphery 130e1 of the insulating film 130 is located inside the outer periphery 122e of the p-type semiconductor layer 122 when viewed from above. + The insulating film 130 is located outside the inner periphery 121ce of the stopper region 121c having a shape similar to that of the insulating film 130. Therefore, in this embodiment, the insulating film 130 overlaps with the outer periphery of the p-type semiconductor layer 122 when viewed from above, and also partially overlaps with a portion of the n-type semiconductor layer 121 located outside the p-type semiconductor layer 122.

[0031] As shown in FIG. 2, on the insulating film 130, an upper electrode 140, an EQPR electrode 150, and a plurality of intermediate electrodes 161 and 162 are provided.

[0032] FIG. 5 is a top view showing a semiconductor portion, an insulating film, an upper electrode, an EQPR electrode, and a plurality of intermediate electrodes of the semiconductor device according to this embodiment. 5, in the termination region EN, the regions in which the upper electrode 140, the EQPR electrode 150, and the multiple intermediate electrodes 161 and 162 are provided are shown by different dot patterns. The upper electrode 140, the EQPR electrode 150, and the multiple intermediate electrodes 161 and 162 will be described below.

[0033] First, the upper electrode 140 will be described. The upper electrode 140 is made of a metal material such as, but not limited to, aluminum (Al). As shown in Fig. 2, the upper electrode 140 is provided across the cell region CE to the termination region EN. Specifically, the upper electrode 140 covers a part of the upper surface of the p-type semiconductor layer 122, the inner peripheral surface of the insulating film 130, and an inner region of the upper surface of the insulating film 130. The upper electrode 140 is in contact with the p-type semiconductor layer 122, and is thereby electrically connected to the p-type semiconductor layer 122.

[0034] When a diode is provided in the cell region CE, the upper electrode 140 may function as an anode electrode of the diode in the cell region CE. When a MOSFET is provided in the cell region CE, the upper electrode 140 may function as a source electrode of the MOSFET in the cell region CE. When an IGBT is provided in the cell region CE, the upper electrode 140 may function as an emitter electrode of the IGBT in the cell region CE.

[0035] In this embodiment, the shape of the outer periphery 140e of the upper electrode 140 viewed from above is a substantially rectangular shape with rounded corners as shown in Fig. 5. The outer periphery 140e of the upper electrode 140 is located outside the inner periphery 130e1 of the insulating film 130 and the outer periphery 122e of the p-type semiconductor layer 122 when viewed from above.

[0036] Next, the EQPR electrode 150 will be described. The EQPR electrode 150 is made of a metal material such as, but not limited to, aluminum (Al). When viewed from above, the EQPR electrode 150 is provided outside the upper electrode 140 and is separated from the upper electrode 140. As shown in FIG. 2, the EQPR electrode 150 is provided on the outer region of the upper surface of the insulating film 130, the outer peripheral surface of the insulating film 130, the n + The EQPR electrode 150 covers the area of ​​the upper surface of the stopper region 121c that is exposed from the insulating film 130. + The stopper region 121c is in contact with the n + The stopper region 121c is electrically connected to the stopper region 121c.

[0037] 5, the shape of the EQPR electrode 150 seen from above is a substantially rectangular ring shape in this embodiment. The outer periphery of the EQPR electrode 150 seen from above roughly coincides with the outer periphery 120e of the semiconductor portion 120. The inner periphery 150e of the EQPR electrode 150 seen from above is substantially the same as the outer periphery 130e2 of the insulating film 130 and the inner periphery 130e3 of the insulating film 130. + The stopper region 121c is located inside the inner circumference 121ce of the stopper region 121c.

[0038] Each of the intermediate electrodes 161, 162 is made of a metal material such as, but not limited to, aluminum (Al). The intermediate electrodes 161, 162 are provided on the insulating film 130. The intermediate electrodes 161, 162 are located between the upper electrode 140 and the EQPR electrode 150. Specifically, the intermediate electrode 161 is provided outside the upper electrode 140 when viewed from above, and is separated from the upper electrode 140. The intermediate electrode 162 is provided outside the intermediate electrode 161 and inside the EQPR electrode 150 when viewed from above, and is separated from the intermediate electrode 161 and the EQPR electrode 150.

[0039] In this manner, the upper electrode 140, the multiple intermediate electrodes 161, 162, and the EQPR electrode 150 are aligned in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e when viewed from above, and are spaced apart from each other. In this embodiment, the upper electrode 140 and the intermediate electrode 161 correspond to a pair of adjacent second electrodes. Similarly, in this embodiment, the intermediate electrode 161 and the intermediate electrode 162 also correspond to a pair of adjacent second electrodes. Similarly, in this embodiment, the intermediate electrode 162 and the EQPR electrode 150 also correspond to a pair of adjacent second electrodes.

[0040] In this embodiment, the shape of each of the intermediate electrodes 161, 162 viewed from above is a substantially rectangular ring shape with rounded corners. In this embodiment, the semiconductor device 100 is provided with two intermediate electrodes 161, 162, but the number of intermediate electrodes provided in the semiconductor device may be one, or three or more. Also, the semiconductor device may not be provided with an intermediate electrode. In this case, the upper electrode and the EQPR electrode correspond to a pair of adjacent second electrodes.

[0041] 2 and 5, in this embodiment, an annular gap S1 is provided between the upper electrode 140 and the intermediate electrode 161. In addition, an annular gap S2 is provided between the two intermediate electrodes 161 and 162. In addition, an annular gap S3 is provided between the intermediate electrode 162 and the EQPR electrode 150.

[0042] As shown in FIG. 2, a plurality of first floating electrodes 171, 173, and 175 and a plurality of second floating electrodes 172, 174, and 176 are provided in the insulating film .

[0043] FIG. 6 is a top view showing a region in which each floating electrode is provided in the semiconductor device according to this embodiment. In FIG. 6, in the termination region EN, the region where the first floating electrodes 171, 173, and 175 are provided and the region where the second floating electrodes 172, 174, and 176 are provided are indicated by different diagonal line patterns.

[0044] Each of the floating electrodes 171-176 is made of a conductive material such as, but not limited to, polysilicon or a metal material containing impurities. When viewed from above, each of the floating electrodes 171-176 has a substantially rectangular ring shape with rounded corners. The multiple floating electrodes 171-176 are spaced apart from each other, as shown in FIG. 2. Each of the floating electrodes 171-176 is entirely covered with the insulating film 130.

[0045] The positions of the floating electrodes 171 to 176 will be described in detail below. First, the position of the first floating electrode 171 will be described. 2 and 6, the first floating electrode 171 overlaps with the gap S1 and the upper electrode 140 when viewed from above. The first floating electrode 171 faces the upper electrode 140 via the insulating film 130. In this specification, "A and B overlap when viewed from above" means that at least a part of A and at least a part of B overlap when A and B are viewed from above in an appropriate transparent manner.

[0046] 6, the inner periphery 171e1 of the first floating electrode 171 is located outside the inner periphery 130e1 of the insulating film 130 and inside the outer periphery 122e of the p-type semiconductor layer 122. In this embodiment, the outer periphery 171e2 of the first floating electrode 171 is located within the gap S1 when viewed from above.

[0047] Next, the position of the second floating electrode 172 will be described. 2 and 6, the second floating electrode 172 overlaps with the first floating electrode 171 in the gap S1 when viewed from above. The second floating electrode 172 also overlaps with the intermediate electrode 161 when viewed from above. The second floating electrode 172 faces the intermediate electrode 161 with the insulating film 130 interposed therebetween.

[0048] 6, the inner periphery 172e1 of the second floating electrode 172 is located inside the outer periphery 140e of the upper electrode 140 when viewed from above. The outer periphery 172e2 of the second floating electrode 172 is located outside the inner periphery 161e1 of the intermediate electrode 161 when viewed from above.

[0049] Next, the position of the first floating electrode 173 will be described. The first floating electrode 173 is located outside the floating electrodes 171 and 172 when viewed from above. The first floating electrode 173 overlaps the gap S2 and the intermediate electrode 161 when viewed from above, as shown in Figures 2 and 6. The first floating electrode 173 faces the intermediate electrode 161 with the insulating film 130 interposed therebetween.

[0050] 6, the inner periphery 173e1 of the first floating electrode 173 is located outside the outer periphery 172e2 of the second floating electrode 172 and inside the outer periphery 161e2 of the intermediate electrode 161. In this embodiment, the outer periphery 173e2 of the first floating electrode 173 is located within the gap S2 when viewed from above.

[0051] Next, the position of the second floating electrode 174 will be described. 2 and 6, the second floating electrode 174 overlaps with the first floating electrode 173 in the gap S2 when viewed from above. The second floating electrode 174 also overlaps with the intermediate electrode 162 when viewed from above. The second floating electrode 174 faces the intermediate electrode 162 with the insulating film 130 interposed therebetween.

[0052] 6, the inner periphery 174e1 of the second floating electrode 174 is located inside the outer periphery 161e2 of the intermediate electrode 161 when viewed from above. The outer periphery 174e2 of the second floating electrode 174 is located outside the inner periphery 162e1 of the intermediate electrode 162 when viewed from above.

[0053] Next, the position of the first floating electrode 175 will be described. 2 and 6, the first floating electrode 175 is located outside the floating electrodes 173 and 174 when viewed from above. The first floating electrode 175 overlaps the gap S3 and the intermediate electrode 162 when viewed from above. The first floating electrode 175 faces the intermediate electrode 162 with the insulating film 130 interposed therebetween.

[0054] When viewed from above, the inner periphery 175e1 of the first floating electrode 175 is located outside the outer periphery 174e2 of the second floating electrode 174 and inside the outer periphery 162e2 of the intermediate electrode 162. In this embodiment, the outer periphery 175e2 of the first floating electrode 175 is located within the gap S3 when viewed from above.

[0055] Next, the position of the second floating electrode 176 will be described. 2 and 6, the second floating electrode 176 overlaps with the floating electrode 175 in the gap S3 when viewed from above. The second floating electrode 176 also overlaps with the EQPR electrode 150 when viewed from above. The second floating electrode 176 faces the EQPR electrode 150 with the insulating film 130 interposed therebetween.

[0056] 6, the inner periphery 176e1 of the second floating electrode 176 is located inside the outer periphery 162e2 of the intermediate electrode 162 when viewed from above. The outer periphery 176e2 of the second floating electrode 176 is located outside the inner periphery 150e of the EQPR electrode 150 and inside the inner periphery 121ce of the n+ type stopper region 121c when viewed from above.

[0057] Although the positions of the outer periphery and inner periphery of each of the floating electrodes 171 to 176 have been described above, the positions of the outer periphery and inner periphery of each of the floating electrodes 171 to 176 are not limited to the above positions.

[0058] Next, the specific shapes of the floating electrodes 171 to 176 will be described. In this embodiment, as shown in FIG. 2, the first floating electrode 171 has a first portion P1 that is located inside the second floating electrode 172 and adjacent to the second floating electrode 172 in the direction from the center C of the semiconductor portion 120 toward the outer periphery 120e, a second portion P2 that is located above the second floating electrode 172, and a third portion P3 that is located between the first portion P1 and the second portion P2 and is continuous with the first portion P1 and the second portion P2.

[0059] In this embodiment, the first portion P1 and the second portion P2 each extend in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e. In this embodiment, the third portion P3 extends in the Z direction from the outer end of the first portion P1 toward the inner end of the second portion P2. A part of the second portion P2 overlaps with the gap S1 when viewed from above. The first portion P1, another part of the second portion P2, and the third portion P3 overlap with the upper electrode 140 when viewed from above. The other first floating electrodes 173 and 175 each have the first portion P1, the second portion P2, and the third portion P3, similar to the first floating electrode 171.

[0060] In this embodiment, the second floating electrodes 172, 174, 176 each have a flat plate shape extending in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e. However, the shapes of the floating electrodes 171, 172, 173, 174, 175, and 176 are not limited to the above shapes.

[0061] Next, the operation of termination region EN of semiconductor device 100 will be described. FIG. 7 is a schematic diagram showing the operation of the termination region of the semiconductor device according to this embodiment.

[0062] In the termination region EN, when a voltage that makes the potential of the lower electrode 110 higher than that of the upper electrode 140, i.e., a reverse bias voltage, is applied between the lower electrode 110 and the upper electrode 140, a depletion layer spreads from the p-type semiconductor layer 122 toward the outer circumferential surface of the semiconductor section 120. When the outer circumferential surface of the semiconductor section 120 is formed by cutting such as dicing, defects exist on the outer circumferential surface. Therefore, the vicinity of the outer circumferential surface of the semiconductor section 120 may not be able to withstand the strong electric field generated by the depletion layer. In this embodiment, between the EQPR electrode 150 and the lower electrode 110, a depletion layer spreads from the p-type semiconductor layer 122 toward the outer circumferential surface of the semiconductor section 120. + Shape Area 121a, n - Shaped areas 122b and n + The EQPR electrode 150 and the lower electrode 110 are electrically connected to each other through the stopper region 121c having a substantially equal potential. This makes it possible to prevent the depletion layer from reaching the outer peripheral surface of the semiconductor portion 120.

[0063] In addition, a depletion layer extending from the p-type semiconductor layer 122 toward the outer peripheral surface of the semiconductor portion 120 causes a depletion layer between the p-type semiconductor layer 122 and the n-type semiconductor layer 122. + An electric field is generated between the p-type semiconductor layer 122 and the n-type stopper region 121c. + If there is a location where the potential changes suddenly between the stopper region 121c having the same shape, that is, if there is a location where equipotential lines are concentrated, avalanche breakdown may occur at that location.

[0064] FIG. 8 is a cross-sectional view showing a termination region of a semiconductor device according to a reference example. The semiconductor device 800 according to the reference example differs from the semiconductor device 100 according to the present embodiment in that the floating electrodes 171 to 176 and the intermediate electrodes 161 and 162 are not provided, and a semi-insulating film 890 is provided in the gap between the upper electrode 140 and the EQPR electrode 150. The semi-insulating film 890 is, for example, a silicon nitride film to which hydrogen is added.

[0065] In the semiconductor device 800 according to the reference example, a semi-insulating film 890 having uniform characteristics such as electrical resistance is provided, and it is expected that the potential will gradually change from the upper electrode 140 to the EQPR electrode 150 by the semi-insulating film 890. This makes it possible to prevent the occurrence of a location where the potential changes suddenly in a portion of the semiconductor section 120 located between the upper electrode 140 and the EQPR electrode 150. However, in reality, the characteristics such as electrical resistance of the semi-insulating film 890 may not be uniform, and the above-mentioned effect may not be sufficiently obtained. Furthermore, if a semi-insulating film is not provided in the cell region CE, a new dedicated device may be required to form the semi-insulating film 890 in the termination region EN.

[0066] In contrast, in this embodiment, as shown in FIG. 7, the upper electrode 140 and the first floating electrode 171 are capacitively coupled, the first floating electrode 171 and the second floating electrode 172 are capacitively coupled, and the second floating electrode 172 and the intermediate electrode 161 are capacitively coupled. In FIG. 7, for ease of explanation, the capacitive coupling of the two electrodes is shown by connecting the two electrodes with a circuit symbol of a capacitor. Here, "electrode A and electrode B are capacitively coupled" means that electrode A and electrode B face each other via an insulator, and the electrodes A, B, and the insulator therebetween function as a capacitor. In this way, a plurality of capacitors are interposed between the upper electrode 140 and the intermediate electrode 161. Therefore, the potential can be changed stepwise between the upper electrode 140 and the intermediate electrode 161.

[0067] Similarly, in this embodiment, the intermediate electrode 161 and the first floating electrode 173 are capacitively coupled, the first floating electrode 173 and the second floating electrode 174 are capacitively coupled, and the second floating electrode 174 and the intermediate electrode 162 are capacitively coupled. Therefore, the potential can be changed stepwise between the intermediate electrode 161 and the intermediate electrode 162.

[0068] Similarly, in this embodiment, the intermediate electrode 162 and the first floating electrode 175 are capacitively coupled, the first floating electrode 175 and the second floating electrode 176 are capacitively coupled, and the second floating electrode 176 and the EQPR electrode 150 are capacitively coupled. Therefore, the potential can be changed stepwise between the intermediate electrode 162 and the EQPR electrode 150.

[0069] Moreover, the intermediate electrodes 161, 162 are floating electrodes that can take any potential between the potential of the upper electrode 140 and the potential of the EQPR electrode 150. Therefore, the potential can be changed stepwise between the upper electrode 140 and the EQPR electrode 150. As a result, it is possible to prevent the occurrence of a location where the potential changes suddenly in a portion of the semiconductor section 120 located between the upper electrode 140 and the EQPR electrode 150. Moreover, the intermediate electrodes 161, 162 and the floating electrodes 171 to 176 are made of a general material used in the cell region CE, so there is no need to prepare a dedicated device for forming them.

[0070] The upper electrode 140 and the intermediate electrode 161, the intermediate electrode 161 and the intermediate electrode 162, and the intermediate electrode 162 and the EQPR electrode 150 may also be capacitively coupled. The first floating electrode 171 and the intermediate electrode 161, the first floating electrode 173 and the intermediate electrode 162, and the first floating electrode 175 and the EQPR electrode 150 may also be capacitively coupled. The p-type semiconductor layer 122 and the first floating electrode 171 may also be capacitively coupled.

[0071] 8, when the semiconductor device 800 according to the reference example is mounted on a lead frame or a substrate and sealed with a sealing member made of a resin material or the like, cations contained in the sealing member may be attracted to the upper electrode 140, generating a positive charge Q1 near the surface of the semi-insulating film 890. Similarly, anions contained in the sealing member may be attracted to the EQPR electrode 150, generating a negative charge Q2 near the surface of the semi-insulating film 890.

[0072] In this way, when charges Q1 and Q2 are generated near the surface of the semi-insulating film 890, it is expected that the semi-insulating film 890 will suppress the generation of negative charges Q3 in the upper layer part of the semiconductor part 120 due to the influence of the positive charges Q1, and the generation of positive charges Q4 in the upper layer part of the semiconductor part 120 due to the influence of the negative charges Q2. However, in reality, the characteristics of the semi-insulating film 890, such as the electrical resistance, are not uniform, and the above-mentioned effects may not be sufficiently obtained.

[0073] 7, in this embodiment, a plurality of intermediate electrodes 161, 162 are provided between the upper electrode 140 and the EQPR electrode 150. In addition, two floating electrodes 171, 172 are provided so as to overlap below the gap S1, two floating electrodes 173, 174 are provided so as to overlap below the gap S2, and two floating electrodes 175, 176 are provided so as to overlap below the gap S3. Therefore, the plurality of intermediate electrodes 161, 162 and the overlapping floating electrodes 171 to 176 function as a shield, and it is possible to suppress the generation of charges Q3, Q4 in the upper layer portion of the semiconductor section 120 due to the influence of the charges Q1, Q2.

[0074] Next, the effects of this embodiment will be described. In the semiconductor device 100 according to this embodiment, an insulating film 130 is provided on the semiconductor portion 120 in the termination region EN. An upper electrode 140, a plurality of intermediate electrodes 161, 162, and an EQPR electrode 150 are provided on the insulating film 130. These electrodes 140, 161, 162, and 150 are aligned in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e when viewed from above, and are spaced apart from each other.

[0075] Further, a first floating electrode 171 and a second floating electrode 172 are provided in the insulating film 130. The first floating electrode 171 overlaps the gap S1 between the pair of adjacent electrodes 140, 161 among these electrodes 140, 161, 162, 150 when viewed from above, and faces one electrode 140 of the pair of adjacent electrodes 140, 161 through the insulating film 130. The second floating electrode 172 is provided in the insulating film 130 so as to be separated from the first floating electrode 171, and overlaps the first floating electrode 171 in the gap S1 when viewed from above. The second floating electrode 172 faces the other electrode 161 of the pair of adjacent electrodes 140, 161 through the insulating film 130. The portion of the second floating electrode 172 that overlaps with the first floating electrode 171 is located below the portion of the first floating electrode 171 that overlaps with the gap S1.

[0076] Therefore, one electrode 140 of the pair of adjacent electrodes 140, 161 is capacitively coupled to the first floating electrode 171, the first floating electrode 171 is capacitively coupled to the second floating electrode 172, and the second floating electrode 172 is capacitively coupled to the other electrode 161 of the pair of adjacent electrodes 140, 161. This allows the potential of the portion located between the pair of adjacent electrodes 140, 161 of the semiconductor part 120 in the termination region EN to be changed stepwise. As a result, it is possible to prevent the occurrence of a location where the potential changes suddenly in the portion located between the pair of adjacent electrodes 140, 161 in the semiconductor part 120. This allows the avalanche breakdown to be suppressed, thereby improving the breakdown voltage of the semiconductor device 100. The other first floating electrodes 173, 175 and the other second floating electrodes 174, 176 can also provide the same effect.

[0077] In addition, the first floating electrode 171 and the second floating electrode 172 overlapping below the gap S1 function as a shield against the charges Q1 and Q2 generated near the surface of the semiconductor device 100, thereby suppressing the generation of charges Q3 and Q4 in the upper layer portion of the semiconductor portion 120. The other first floating electrodes 173 and 175 and the other second floating electrodes 174 and 176 can also provide the same effect. As a result, a highly reliable semiconductor device 100 can be realized.

[0078] In this embodiment, the first floating electrode 171 overlaps with the electrode 140 located on the inner side of the pair of adjacent electrodes 140, 161 when viewed from above. The second floating electrode 172 overlaps with the electrode 161 located on the outer side of the pair of adjacent electrodes 140, 161 when viewed from above. Therefore, it is easy to distribute the equipotential lines in the termination region EN of the semiconductor section 120. The other first floating electrodes 173, 175 and the other second floating electrodes 174, 176 are configured in the same manner, and the same effect can be obtained.

[0079] In this embodiment, the first floating electrode 171 has a first portion P1 located inside the second floating electrode 172 and adjacent to the second floating electrode 172 in the direction from the center C of the semiconductor part 120 toward the outer periphery 120e, a second portion P2 located above the second floating electrode 172, and a third portion P3 located between the first portion P1 and the second portion P2 and connected to the first portion P1 and the second portion P2. Therefore, it is easy to distribute the equipotential lines in the termination region EN of the semiconductor part 120. The other first floating electrodes 173, 175 and the other second floating electrodes 174, 176 are configured in the same way, and the same effect can be obtained.

[0080] In this embodiment, the semiconductor section 120 has an n-type semiconductor layer 121 provided on the lower electrode 110, and a p-type semiconductor layer 122 provided in an upper layer of the n-type semiconductor layer 121 and located inside the outer periphery of the n-type semiconductor layer 121. When viewed from above, the insulating film 130 overlaps with the outer periphery of the p-type semiconductor layer 122 and overlaps with a portion of the n-type semiconductor layer 121 located outside the p-type semiconductor layer 122. Among the multiple electrodes 140, 161, 162, and 150, the electrode 140 located on the innermost side is connected to a portion of the p-type semiconductor layer 122 located inside the insulating film 130. Among the multiple electrodes 140, 161, 162, and 150, the electrode 150 located on the outermost side is connected to a portion of the n-type semiconductor layer 121 located outside the insulating film 130. Therefore, the EQPR electrode 150, the outer periphery of the n-type semiconductor layer 121, and the lower electrode 110 can be made to have approximately the same potential, and the depletion layer can be prevented from reaching the outer periphery of the semiconductor portion 120. As a result, the breakdown voltage of the semiconductor device 100 can be improved.

[0081] In this embodiment, the n-type semiconductor layer 121 is an n-type + Shape area 121a and n + The impurity concentration is n + The impurity concentration of the n-shaped region 121a is lower than that of the n-shaped region 121b. - Shape area 121b and n - The impurity concentration is n - The impurity concentration of the n-shaped region 121b is higher than that of the n-shaped region 121b. + The electrode 150 located on the outermost side is connected to the n+ type stopper region 121c. Therefore, the EQPR electrode 150, the outer periphery of the n-type semiconductor layer 121, and the lower electrode 110 are made to have a substantially equal potential, and it is possible to prevent the depletion layer from reaching the outer periphery of the semiconductor portion 120.

[0082] <Second embodiment> Next, a second embodiment will be described. FIG. 9 is a cross-sectional view showing the semiconductor device according to this embodiment. The structure of the termination region EN of the semiconductor device 200 according to this embodiment differs from the structure of the termination region EN of the semiconductor device 100 according to the first embodiment in the configuration other than the lower electrode 110 and the semiconductor portion 120. In the following description, in principle, only the differences from the first embodiment will be described, and the matters other than those described below are the same as the first embodiment.

[0083] The shape of the insulating film 230 in this embodiment is different from the shape of the insulating film 130 in the first embodiment. In the first embodiment, the upper surface of the insulating film 130 is flat and parallel to the X and Y directions. In contrast, the region on the upper surface of the insulating film 230 in this embodiment where the first floating electrode 271 and the multiple second floating electrodes 272 are provided directly below rises upward.

[0084] Moreover, the shapes of the upper electrode 240 and the EQPR electrode 250 in this embodiment are different from those of the upper electrode 140 and the EQPR electrode 150 in the first embodiment. In the first embodiment, the shapes of the portions of the upper electrode 140 and the EQPR electrode 150 located on the insulating film 130 were flat. In contrast, the upper electrode 240 and the EQPR electrode 250 in this embodiment run on the portion that rises upward on the upper surface of the insulating film 230. Therefore, the outer end of the upper electrode 240 and the inner end of the EQPR electrode 250 are curved along the upper surface of the insulating film 230.

[0085] In the first embodiment, an example was described in which two intermediate electrodes 161, 162 are provided in the semiconductor device 100, but in this embodiment, six intermediate electrodes 260 are provided in the semiconductor device 200. In this way, the number of intermediate electrodes provided in the semiconductor device is not particularly limited. The number of intermediate electrodes provided in the semiconductor device can be set according to, for example, the required withstand voltage of the semiconductor device. It is preferable to increase the number of intermediate electrodes provided in the semiconductor device as the required withstand voltage of the semiconductor device increases.

[0086] The multiple intermediate electrodes 260 are provided on the insulating film 230 between the upper electrode 240 and the EQPR electrode 250. The multiple intermediate electrodes 260 are aligned in a direction from the center C of the semiconductor portion 120 toward the outer periphery 120e when viewed from above, and are spaced apart from each other. Among the multiple intermediate electrodes 260, the intermediate electrode 260 located on the innermost side is spaced apart from the upper electrode 240. Among the multiple intermediate electrodes 260, the intermediate electrode 260 located on the outermost side is spaced apart from the EQPR electrode 250.

[0087] Therefore, a gap S21 is formed between the upper electrode 240 and the innermost intermediate electrode 260. A gap S22 is formed between adjacent intermediate electrodes 260. A gap S23 is formed between the EQPR electrode 250 and the outermost intermediate electrode 260.

[0088] In the first embodiment, the shape of each of the intermediate electrodes 161, 162 is flat, but in this embodiment, the shape of each of the intermediate electrodes 260 is a shape in which the center portion is recessed downward along the upper surface of the insulating film 230. In this manner, the shape of each intermediate electrode is not particularly limited as long as a gap is formed between the upper electrode, another intermediate electrode, or the EQPR electrode.

[0089] In addition, in this embodiment, the first floating electrode 271 and the second floating electrode 272 are provided directly below each of the gaps S21, S22, and S23. In this embodiment, since the total number of the gaps S21, S22, and S23 is seven, the semiconductor device 200 is also provided with seven first floating electrodes 271. Similarly, the semiconductor device 200 is also provided with seven second floating electrodes 172. In this manner, the number of gaps formed on the insulating film in the termination region is not particularly limited as long as it is one or more. It is preferable to provide the first floating electrodes and the second floating electrodes in the termination region in the number corresponding to the number of gaps.

[0090] Each of the floating electrodes 271, 272 is made of a semiconductor material such as polysilicon or a metal material, similar to the first embodiment. The shape of each of the floating electrodes 271, 272 when viewed from above is a substantially rectangular ring shape with rounded corners, similar to the first embodiment. The multiple floating electrodes 271, 272 are spaced apart from each other. Each of the floating electrodes 271, 272 is entirely covered with the insulating film 230.

[0091] Hereinafter, a description will be given of the configuration of the first floating electrode 271 and the second floating electrode 272 provided directly below the gap S21 between the upper electrode 240 and the innermost intermediate electrode 260, among the multiple first floating electrodes 271 and multiple second floating electrodes 272. The other first floating electrodes 271 and other second floating electrodes 272 are configured in the same manner, and therefore description thereof will be omitted.

[0092] The first floating electrode 271 overlaps the gap S21 and the upper electrode 240 when viewed from above. The first floating electrode 271 faces the upper electrode 240 via the insulating film 230. In the first embodiment, the inner circumference 171e1 of the first floating electrode 171 is located inside the outer circumference 122e of the p-type semiconductor layer 122, but in this embodiment, the inner circumference 271e1 of the first floating electrode 271 is located outside the outer circumference 122e of the p-type semiconductor layer 122. In this way, the position of the inner circumference 271e1 is not particularly limited as long as it is outside the inner circumference of the insulating film 230 and inside the outer circumference of the upper electrode 240.

[0093] In this embodiment, the first floating electrode 271 has a first portion P21 located inside the second floating electrode 272 and adjacent to the second floating electrode 272 in the direction from the center C of the semiconductor part 120 toward the outer periphery 120e, a second portion P22 located above the second floating electrode 272, and a third portion P23 located between the first portion P21 and the second portion P22 and continuing to the first portion P21 and the second portion P22. In the first embodiment, the third portion P3 extends in the Z direction, but in this embodiment, the third portion P23 extends in a direction inclined with respect to the Z direction. Thus, the extension direction of the third portion is not particularly limited as long as it can connect the first portion and the second portion.

[0094] The second floating electrode 272 overlaps with the first floating electrode 271 in the gap S21 when viewed from above. The second floating electrode 272 also overlaps with the intermediate electrode 260 when viewed from above. The second floating electrode 272 faces the intermediate electrode 260 with the insulating film 230 interposed therebetween.

[0095] In the first embodiment, the inner periphery 172e1 of the second floating electrode 172 is located inside the outer periphery 140e of the upper electrode 140 when viewed from above, but in this embodiment, the inner periphery 272e1 of the second floating electrode 272 is located outside the outer periphery 240e of the upper electrode 240 when viewed from above. In this way, the position of the inner periphery 272e1 may be any position as long as it is inside the inner periphery of the intermediate electrode 260 and the outer periphery of the first floating electrode 271 when viewed from above.

[0096] In the semiconductor device 200 according to this embodiment, one of a pair of adjacent electrodes among the multiple electrodes 240, 260, 250 is capacitively coupled to the first floating electrode 271. The first floating electrode 271 is capacitively coupled to the second floating electrode 272. The second floating electrode 272 is capacitively coupled to the other of the pair of adjacent electrodes.

[0097] The semiconductor device 200 according to this embodiment also differs from the first embodiment in that a protective film 280 is further provided to cover the upper electrode 240, the EQPR electrode 250, the multiple intermediate electrodes 260, and the insulating film 230, which cover the portions exposed from these electrodes 240, 250, and 260. In this manner, the semiconductor device 200 may be provided with the protective film 280. The protective film 280 is made of an insulating material such as a resin material.

[0098] FIG. 10 is a cross-sectional view showing a semiconductor device according to a reference example. FIG. 11 is a graph showing the results of a simulation of the relationship between the withstand voltage and charge for the semiconductor device according to this embodiment and the semiconductor device according to the reference example, with the charge generated on the surface of the protective film taken on the horizontal axis and the withstand voltage taken on the vertical axis. FIG. 12 shows the results of a simulation showing equipotential lines in a state in which positive and negative charges are generated on the surface of the protective film in the semiconductor device according to this embodiment.

[0099] 10, the semiconductor device 900 according to the reference example includes a lower electrode 110, a semiconductor portion 120, an insulating film 930, an upper electrode 940, an EQPR electrode 950, and a protective film 980, similar to the semiconductor device 200 according to the present embodiment. The semiconductor device 900 according to the reference example is different from the semiconductor device 200 according to the present embodiment in that an intermediate electrode is not provided in the gap between the upper electrode 940 and the EQPR electrode 950 on the insulating film 930, and in that a first floating electrode and a second floating electrode are not provided in the insulating film 930.

[0100] In this embodiment, as described above, one of a pair of adjacent electrodes among the multiple electrodes 240, 260, and 250 is capacitively coupled to the first floating electrode 271, the first floating electrode 271 is capacitively coupled to the second floating electrode 272, and the second floating electrode 272 is capacitively coupled to the other of the pair of adjacent electrodes. Therefore, as shown in FIG. 12, the potential can be changed stepwise between the upper electrode 240 and the EQPR electrode 250. Specifically, as shown in FIG. 12, the equipotential lines in the gap S21 are distributed between the upper electrode 240 and the first floating electrode 271, between the first floating electrode 271 and the second floating electrode 272, and between the second floating electrode 272 and the intermediate electrode 260. In this way, by suppressing the concentration of equipotential lines in the termination region EN of the semiconductor portion 120, that is, by suppressing the occurrence of a location where the potential changes suddenly in the termination region EN of the semiconductor portion 120, it is possible to suppress the occurrence of avalanche breakdown. As a result, it is possible to improve the breakdown voltage of the semiconductor device 200. Therefore, as shown in FIG. 11, the breakdown voltage of the semiconductor device 200 according to this embodiment is higher than the breakdown voltage of the semiconductor device 900 according to the reference example.

[0101] In particular, in this embodiment, as shown in FIG. 12, the first floating electrode 271 has a first portion P21 located inside the second floating electrode 272, a second portion P22 located above the second floating electrode 272, and a third portion P23 connected to the first portion and the second portion. Therefore, the equipotential lines in the gap S21 extend from the gap S21 through the semiconductor portion 120 toward the center C of the semiconductor portion 120 while being dispersed between the upper electrode 240 and the first floating electrode 271, between the first floating electrode 271 and the second floating electrode 272, and between the second floating electrode 272 and the intermediate electrode 260. Therefore, it is easy to disperse the equipotential lines in the semiconductor portion 120. The same is true for the first floating electrode 271 and the second floating electrode 272 directly below the other gaps S22 and S23.

[0102] 10 and 11, in the semiconductor device 200 according to the reference example, the withstand voltage when positive charges Q21 and negative charges Q22 are generated on the surface of the protective film 980 is smaller than the withstand voltage when positive charges Q21 and negative charges Q22 are not generated on the surface of the protective film 980. Moreover, the larger the absolute values ​​of the positive charges Q21 and negative charges Q22 are, the lower the withstand voltage becomes.

[0103] The semiconductor device 200 according to this embodiment also shows a similar tendency. In the semiconductor device 900 according to the reference example, as shown in FIG. 10, no member is provided between the upper electrode 940 and the EQPR electrode 950 to shield the influence of the charges Q21 and Q22 on the semiconductor portion 120. In contrast, as shown in FIG. 12, in the semiconductor device 200 according to this embodiment, a plurality of intermediate electrodes 260 are provided between the upper electrode 940 and the EQPR electrode 950, and the first floating electrode 171 and the second floating electrode 172 overlap each other directly below each of the gaps S21, S22, and S23. Therefore, in the semiconductor device 200 according to this embodiment, the influence of the charges Q21 and Q22 on the semiconductor portion 120 can be shielded. Therefore, as shown in FIG. 11, in the semiconductor device 200 according to this embodiment, the reduction amount ΔV21 of the breakdown voltage when the charge is changed by a predetermined amount ΔQ is smaller than the reduction amount ΔV22 of the breakdown voltage when the charge is changed by a predetermined amount ΔQ in the semiconductor device 900 according to the reference example. That is, in this embodiment, the decrease in the breakdown voltage caused by the charges Q21 and Q22 is smaller than in the reference example.

[0104] As described above, in the semiconductor device 200 according to this embodiment, it is also possible to change in a stepwise manner the potential between one electrode and the other electrode of a pair of adjacent electrodes among the multiple electrodes 240, 260, and 250. This makes it possible to suppress avalanche breakdown, thereby improving the breakdown voltage of the semiconductor device 200.

[0105] Also in this embodiment, the first floating electrode 171 and the second floating electrode 172 overlapping below the gaps S21, S22, and S23 function as a shield against the charges Q21 and Q22 generated on the surface of the semiconductor device 200. Therefore, it is possible to suppress the generation of negative charges Q3 and positive charges Q4 in the upper layer portion of the semiconductor section 120. As a result, a highly reliable semiconductor device 200 can be realized.

[0106] Although several embodiments of the present invention have been described, these embodiments are presented by way of example only. The present invention is not intended to limit the scope of the present invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0107] 100, 200: Semiconductor device 110: Lower electrode (1st electrode) 120: Semiconductor Division 120e: Outer circumference 121: n-type semiconductor layer (first semiconductor layer of first conductivity type) 121a :n + Shaped region (first semiconductor region) 121b :n - Shaped region (second semiconductor region) 121c :n + Shaped stopper region (third semiconductor region) 121ce: Inner circumference 122: p-type semiconductor layer 122b :n - The realm of form 122e: Outer circumference 130, 230: insulating film 130e1: Inner circumference 130e2: Outer circumference 140, 240: Upper electrode (second electrode) 140e: Outer circumference 150, 250: EQPR electrode (second electrode) 150e: Inner circumference 161, 162, 260: Intermediate electrodes 161e1, 162e1: Inner circumference 161e2, 162e2: outer circumference 171, 173, 175, 271: First floating electrode 171e1, 173e1, 175e1, 271e1: Inner circumference 171e2, 173e2, 175e2: outer circumference 172, 174, 176, 272: Second floating electrode 172e1, 174e1, 176e1, 272e1: inner week 172e2, 174e2, 176e2: Periphery 280: Protective film C : Center CE: セル domain EN :Terminal area P1, P21: Part 1 P2, P22: Part 2 P3, P23: Part 3 Q1, Q2: Charge Q3, Q4, Q21, Q22: Charge S1, S2, S3, S21, S22, S23: gap ΔQ: Quantitative charge ΔV21, ΔV22: reduction in pressure resistance

Claims

1. A semiconductor device having a cell region and a termination region surrounding the cell region, A first electrode; A semiconductor portion provided on the first electrode; an insulating film provided on the semiconductor portion in the termination region; a plurality of second electrodes provided on the insulating film, arranged in a first direction from a center of the semiconductor portion toward an outer periphery when viewed from above, and spaced apart from one another; a first floating electrode provided in the insulating film, overlapping a gap between a pair of adjacent second electrodes among the plurality of second electrodes in a second direction perpendicular to the first direction, and facing one of the pair of second electrodes via the insulating film; a second floating electrode provided in the insulating film so as to be spaced apart from the first floating electrode, overlapping with the first floating electrode in the second direction within the gap, a portion of the first floating electrode overlapping with the first floating electrode being located below a portion of the first floating electrode overlapping with the gap, and facing the other of the pair of second electrodes via the insulating film; A semiconductor device comprising:

2. an outer periphery of the first floating electrode overlaps with the gap in the second direction; The semiconductor device according to claim 1 .

3. The first floating electrode is a first portion located inside the second floating electrode and adjacent to the second floating electrode in the first direction; The semiconductor device according to claim 1 .

4. The first floating electrode is a second portion located above the second floating electrode; a third portion located between the first portion and the second portion and connected to the first portion and the second portion; The semiconductor device according to claim 3 , further comprising:

5. The semiconductor portion is a first semiconductor layer of a first conductivity type provided on the first electrode; a second semiconductor layer of a second conductivity type provided in an upper layer portion of the first semiconductor layer and positioned inside an outer periphery of the first semiconductor layer when viewed from above; having the insulating film overlaps with an outer periphery of the second semiconductor layer and a portion of the first semiconductor layer located outside the second semiconductor layer in the second direction; an innermost second electrode among the plurality of second electrodes is connected to a portion of the second semiconductor layer that is located on the inner side of the insulating film; 5. The semiconductor device according to claim 1, wherein an outermost second electrode of the plurality of second electrodes is connected to a portion of the first semiconductor layer that is located outside the insulating film.

6. The first semiconductor layer is a first semiconductor region provided on the first electrode; a second semiconductor region provided on the first semiconductor region and having an impurity concentration lower than an impurity concentration of the first semiconductor region; a third semiconductor region provided in an outer periphery of the upper layer portion of the second semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the second semiconductor region; having The semiconductor device according to claim 5 , wherein the outermost second electrode is connected to the third semiconductor region.

7. The semiconductor device according to claim 1 , wherein the first floating electrode and the second floating electrode include polysilicon.

Images