Semiconductor Device

Abstract

To provide a semiconductor device with higher breakdown tolerance.SOLUTION: A semiconductor device includes a semiconductor substrate, an element electrode provided over the semiconductor substrate, an element electrode pad electrically connected to the element electrode, and a wire connected to the element electrode pad at a plurality of connection places. The semiconductor substrate includes an emitter region with a first conductivity type facing the element electrode on an upper surface of the semiconductor substrate and arranged in an arrangement direction. The density of the emitter region below the connection place of any wire is different from the density of the emitter region below the connection place of another wire.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, there has been known a semiconductor device in which wires are provided on element electrodes and the element electrodes are connected to external electrodes through the wires (for example, Patent Document 1). Patent Document 1: International Publication No. 2018-225571 Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable to improve the breakdown voltage of a semiconductor device. [Means for solving the problem]

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate. The semiconductor device may include an element electrode. The element electrode may be provided above the semiconductor substrate. The semiconductor device may include an element electrode pad. The element electrode pad may be electrically connected to the element electrode. The semiconductor device may include a wire. The wire may be connected to the element electrode pad at a plurality of connection points. The semiconductor substrate may have an emitter region of a first conductivity type. The emitter region may face the element electrode on an upper surface of the semiconductor substrate. The emitter regions may be arranged in an arrangement direction. The density of the emitter region below a connection point of any one of the wires may be different from the density of the emitter region below a connection point of any other one of the wires.

[0005] The wire may have a connection portion, which may be connected to an external electrode, and the greater the distance to the connection portion, the higher the density of the emitter region below the connection point of the wire may be.

[0006] The semiconductor device may include three or more wires. A density of emitter regions below a connection point of a wire sandwiched between other wires may be higher than a density of emitter regions below at least one of the connection points of the other wires.

[0007] The density of the emitter regions may be changed by disposing the emitter regions discretely in the arrangement direction.

[0008] The density of the emitter regions may be changed by disposing the emitter regions discretely in the extension direction perpendicular to the arrangement direction.

[0009] The density of the emitter regions may be varied based on the distance between the wire connection point and the edge of the semiconductor device.

[0010] The semiconductor device may include a plurality of gate electrodes. The plurality of gate electrodes may be provided on an upper surface of a semiconductor substrate, extending in an extension direction perpendicular to an arrangement direction. The semiconductor device may include a contact region of a first conductivity type. The contact region of the first conductivity type may be provided between two gate electrodes. The contact regions may be discretely arranged in the extension direction.

[0011] The contact region may be sandwiched between the emitter regions in the extension direction.

[0012] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view showing an example of a semiconductor device 100. [Diagram 2] FIG. 2 is a diagram showing a connection point 62 of a wire 60. [Diagram 3] 1 is a diagram showing an example of the configuration of a semiconductor device 100 in a region 94-1. [Figure 4]1 is a diagram showing an example of the configuration of the semiconductor device 100 in a region 94-2. [Diagram 5] FIG. 2 is a diagram illustrating an example of the arrangement of emitter regions 12 in a plan view. [Figure 6] 13 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. [Figure 7] 13 is a diagram showing another example of the configuration of the semiconductor device 100 in the region 94-1. FIG. [Figure 8] 13 is a diagram showing another example of the configuration of the semiconductor device 100 in the region 94-2. FIG. [Figure 9] 13 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. [Figure 10] 13 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. [Figure 11] 13 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. [Figure 12] 13 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. [Figure 13] 13 is a diagram showing another example of the configuration of the semiconductor device 100 in the region 94-1. FIG. [Figure 14] 13 is a diagram showing another example of the configuration of the semiconductor device 100 in the region 94-2. FIG. [Figure 15] 13 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. [Figure 16] 13 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. [Figure 17] FIG. 2 is a plan view showing an example of a semiconductor device 200. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0015] FIG. 1 is a plan view showing an example of a semiconductor device 100. The semiconductor device 100 of this example includes a semiconductor element. The semiconductor element may be an IGBT (Insulated Gate Bipolar Transistor). The semiconductor element may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor element of the semiconductor device 100 of this example is an IGBT. In the plan view of FIG. 1, the semiconductor device 100 includes a gate pad 54, an element electrode pad 56, a plurality of wires 60, and a protective film 70. The semiconductor device 100 is provided with a semiconductor substrate 80 (see FIG. 2) having a semiconductor element. The semiconductor substrate 80 may be provided with an emitter region, which will be described later.

[0016] In this specification, the surface of the semiconductor substrate 80 on which the gate pad 54 and the element electrode pad 56 are placed is defined as the xy plane, and the surface perpendicular to the xy plane is defined as the z axis. In this specification, the direction from the semiconductor substrate 80 toward the gate pad 54 and the element electrode pad 56 in the z axis direction is defined as the up direction, and the opposite direction is defined as the down direction, but the up and down directions are not limited to the direction of gravity. In this specification, the upper surface of each member is defined as the upper surface, and the lower surface is defined as the lower surface. The ends of the semiconductor device 100 in the x axis direction are defined as ends 24 (24-1, 24-2). The ends of the semiconductor device 100 in the y axis direction are defined as ends 26 (26-1, 26-2).

[0017] A protective film 70 is provided above the semiconductor substrate 80. The protective film 70 protects the semiconductor substrate 80. The protective film 70 may be an organic material. The protective film 70 is, for example, a polyimide-based polymer material. The protective film 70 has an opening 90. The protective film 70 is not provided inside the opening 90. In the example of FIG. 1, the protective film 70 has an opening 90-1 and an opening 90-2.

[0018] The gate pad 54 is provided above the semiconductor substrate 80. In the example of FIG. 1, the gate pad 54 is provided inside the opening 90-1. The gate pad 54 is electrically connected to the gate electrode of the semiconductor element. The gate pad 54 applies a predetermined voltage to the gate electrode of the semiconductor element. The gate pad 54 may be made of a metal material. The gate pad 54 is, for example, an alloy mainly composed of aluminum.

[0019] The element electrode pad 56 is provided above the semiconductor substrate 80. In the example of FIG. 1, the element electrode pad 56 is provided inside the opening 90-2. The element electrode pad 56 is electrically connected to an element electrode provided on the upper surface of the semiconductor substrate 80. The element electrode is, for example, an emitter electrode. The element electrode pad 56 and the element electrode may be made of a metal material. The element electrode pad 56 may be made of a different metal material from the element electrode so as to make it easier to connect the wire 60. The element electrode pad 56 may be made of the same metal material as the element electrode as long as there is no problem in connecting the wire 60. The element electrode pad 56 and the element electrode are, for example, an alloy mainly composed of aluminum.

[0020] The wire 60 is connected to the element electrode pad 56 at a plurality of connection points 62. In the example of FIG. 1, the wire 60-1 is connected to the element electrode pad 56 at connection points 62-1 and 62-2. The wire 60-1 has an end 64-1 and a connection portion 66-1. The end 64-1 is one end of the wire 60-1, and the connection portion 66-1 is the other end of the wire 60-1. The connection portion 66-1 is connected to the external electrode 92. The connection portion 62-1 is a connection portion on the connection portion 66-1 side on the wire 60-1, and the connection portion 62-2 is a connection portion on the end 64-1 side on the wire 60-1. Here, the connection portion 66-1 side indicates that the distance to the connection portion 66-1 is smaller than that to the end 64-1. The distance is not a spatial linear distance but an electrical path length along the wire 60-1.

[0021] In the example of FIG. 1, the wire 60-2 is connected to the element electrode pad 56 at the connection points 62-3 and 62-4. The wire 60-2 has an end 64-2 and a connection portion 66-2. The end 64-2 is one end of the wire 60-2, and the connection portion 66-2 is the other end of the wire 60-2. The connection portion 66-2 is connected to the external electrode 92. The connection portion 62-3 is a connection portion on the wire 60-2 at the connection portion 66-2 side, and the connection portion 62-4 is a connection portion on the wire 60-2 at the end 64-2 side. Here, the connection portion 66-2 side indicates that the distance to the connection portion 66-2 is smaller than that to the end 64-2. The distance is not a spatial linear distance but an electrical path length along the wire 60-2.

[0022] A predetermined voltage is applied to the element electrode pad 56 from the external electrode 92 via the wire 60-1 and the wire 60-2. In this example, the wire 60-1 is connected to the element electrode pad 56 at the connection points 62-1 and 62-2. The wire 60-1 is also connected to the element electrode pad 56 at the connection points 62-3 and 62-4. This makes it possible to reduce current concentration compared to a case where there is only one connection point. Although two wires 60 are shown in FIG. 1, the semiconductor device 100 may have more wires 60.

[0023] Connection points 62-1 and 62-3 are provided on the connection portion 66 side. Therefore, the current flowing through connection points 62-2 and 62-4 passes through connection points 62-1 and 62-3, respectively, and therefore connection points 62-1 and 62-3 are more likely to have a high temperature due to the current concentration than connection points 62-2 and 62-4. Therefore, connection points 62-1 and 62-3 are more likely to be destroyed due to a rise in temperature.

[0024] In this example, the density of the emitter region below the connection point 62 of any of the wires 60 is different from the density of the emitter region below the connection point 62 of any of the other wires 60. That is, the density of the emitter region below the connection point 62 of the wires 60 is made different for each connection point 62. For example, the density of the emitter region below the connection point 62 where current concentrates is made low. The density of the emitter region will be described later. By making the density of the emitter region different, it is possible to make the density of the emitter region low at connection points 62-1 and 62-3 where current is likely to concentrate. Therefore, it is possible to improve the breakdown resistance caused by temperature rise (for example, FBSOA resistance).

[0025] In the semiconductor device 100, the density of the emitter region below the connection point 62 of the wire 60 may be higher as the distance from the connection portion 66 increases. The distance from the connection portion 66 is not the spatial linear distance from the connection portion 66 but the electrical path length along the wire 60. The density of the emitter region below the connection portion 62-2 may be higher than the density of the emitter region below the connection portion 62-1. Also, the density of the emitter region below the connection portion 62-4 may be higher than the density of the emitter region below the connection portion 62-3. The greater the distance from the connection portion 66, the less likely the current is to concentrate. Therefore, by increasing the density of the emitter region at the connection portion 62 of the wire 60 as the distance from the connection portion 66 increases, the current concentration can be suppressed.

[0026] The density of the emitter region may be changed based on the distance between the connection point 62 of the wire 60 and the end of the semiconductor device 100. The density of the emitter region may be changed based on the distance between the connection point 62 of the wire 60 and the end 24-1 of the semiconductor device 100. The density of the emitter region may be changed based on the distance between the connection point 62 of the wire 60 and the end 24-2 of the semiconductor device 100. The density of the emitter region may be changed based on the distance between the connection point 62 of the wire 60 and the end 26-1 of the semiconductor device 100. The density of the emitter region may be changed based on the distance between the connection point 62 of the wire 60 and the end 26-2 of the semiconductor device 100. The distance between the connection point 62 and the end of the semiconductor device 100 may be the shortest spatial distance between the connection point 62 and the end of the semiconductor device 100. The distance between the connection point 62 and the end of the semiconductor device 100 is the distance in a direction in which no other connection point 62 exists. For example, when the connection point 62-1 and the connection point 62-2 are arranged side by side as shown in FIG. 1, the distance between the connection point 62-1 and the end of the semiconductor device 100 is the distance between the connection point 62-1 and the end 26-2. Similarly, the distance between the connection point 62-2 and the end of the semiconductor device 100 is the distance between the connection point 62-2 and the end 26-1. For example, the density of the emitter region below the connection point 62 of the wire 60 is lowered as the distance between the connection point 62 of the wire 60 and the end of the semiconductor device 100 increases. The greater the distance between the connection point 62 of the wire 60 and the end of the semiconductor device 100, the greater the current flows in from a wider region and the current is more likely to concentrate. Therefore, even if the emitter region is changed based on the distance between the connection point 62 of the wire 60 and the end of the semiconductor device 100, the current concentration can be suppressed.

[0027] FIG. 2 is a diagram showing a connection point 62 of the wire 60. In FIG. 2, a connection point 62-1 and a connection point 62-2 of the wire 60-1 are shown in a schematic manner. In FIG. 2, the element electrode, the gate electrode, and the like arranged between the element electrode pad 56 and the semiconductor substrate 80 are omitted. In addition, the wire 60-1 is provided in an opening 90-2 of the protective film 70. The wire 60 may be joined to the element electrode pad 56 by being pressed against the element electrode pad 56 at the connection point 62. In addition, when joining the wire 60, ultrasonic waves may be applied to the connection point 62, and the connection point 62 may be heated. In addition, the wire 60 may be joined to the element electrode pad 56 by a conductive material such as solder. In this case, the connection point 62 is a portion including a conductive material such as solder. The wire 60 may be a metal material. The wire 60 may be made of an appropriate material according to a joining method to the element electrode pad 56. When joining the wire 60 to the element electrode pad 56, if the element electrode pad 56 is an alloy mainly composed of aluminum and ultrasonic waves are applied to the connection portion 62 to further heat it, the material of the wire 60 may be, for example, aluminum. The diameter of the wire 60 may be appropriately selected according to the current flowing therethrough. The diameter of the wire 60 is, for example, within the range of 300 μm to 700 μm.

[0028] As shown in FIG. 2, the connection point 62 is provided with a width. In the example of FIG. 2, the connection point 62-1 has a width W1. That is, the connection point 62-1 is connected to the element electrode pad 56 with a length of the width W1. The connection point 62-2 has a width W2. That is, the connection point 62-2 is connected to the element electrode pad 56 with a length of the width W2. The region below the connection point 62 is defined as a region 94. In FIG. 2, the region 94 is shown by hatching. The region below the connection point 62-1 is a region 94-1. The region 94-1 also has a width W1. The region below the connection point 62-2 is a region 94-2. The region 94-2 also has a width W2. By making the density of the emitter region arranged in the region 94-1 and the density of the emitter region arranged in the region 94-2 different, it is possible to improve the breakdown resistance caused by a temperature rise.

[0029] Fig. 3 is a diagram showing an example of the configuration of the semiconductor device 100 in the region 94-1. The semiconductor device 100 in Fig. 3 is a planar gate IGBT in which a gate electrode 40 is provided on the upper surface 21 of a semiconductor substrate 80. The semiconductor device 100 may be a trench gate IGBT in which the gate electrode 40 is embedded in a trench. In the example of Fig. 3, the semiconductor device 100 includes a gate electrode 40, an element electrode 52, an element electrode pad 56, a wire 60-1, and a semiconductor substrate 80.

[0030] The semiconductor substrate 80 has an emitter region 12, a base region 14, a drift region 18, and a collector region 20. The base region 14 is selectively formed on an upper surface 21 of the semiconductor substrate 80. The drift region 18 is provided between the base region 14 and a lower surface 23 of the semiconductor substrate 80. In this example, the drift region 18 is of a first conductivity type, and the base region 14 is of a second conductivity type. In this example, the first conductivity type is described as N type, and the second conductivity type is described as P type. However, the first conductivity type may be P type, and the second conductivity type may be N type. The drift region 18 in this example is N - The base region 14 is of the P - It is a type.

[0031] An emitter region 12 of the first conductivity type having a higher impurity concentration than the drift region 18 is formed on the upper surface 21 of the semiconductor substrate 80. The emitter region 12 of this example is N + 3, a plurality of emitter regions 12 are discretely arranged in the arrangement direction (x-axis direction). Note that in the example of FIG. 3, an example is shown in which the arrangement direction of the emitter regions 12 is perpendicular (x-axis direction) to the extension direction (y-axis direction) of the wire 60-1 shown in FIG. 2, but the arrangement direction of the emitter regions 12 is not limited to the x-axis direction. The arrangement direction of the emitter regions 12 may have any angle with respect to the extension direction of the wire. The emitter regions 12 face the element electrode 52 on the upper surface 21 of the semiconductor substrate 80. In addition, a collector region 20 of a second conductivity type having a higher impurity concentration than the base region 14 is formed on the lower surface 23 of the semiconductor substrate 80. The collector region 20 of this example is P +In addition, in the semiconductor device 100, a collector electrode (not shown) facing the collector region 20 is provided on the lower surface 23 of the semiconductor substrate 80.

[0032] The gate electrode 40 is provided on the upper surface 21 of the semiconductor substrate 80. The gate electrode 40 extends in an extension direction perpendicular to the arrangement direction. The gate electrode 40 has an insulating film 42 and a gate conductive portion 44. The insulating film 42 may be formed by oxidizing or nitriding a semiconductor. The gate conductive portion 44 is formed inside the insulating film 42. In other words, the insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 80. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0033] The gate conductive portion 44 includes at least a region facing the base region 14. The gate conductive portion 44 in this example is disposed on the upper surface 21 of the semiconductor substrate 80, facing the base region 14 between the emitter region 12 and the drift region 18. Each gate conductive portion 44 is electrically connected to a gate pad 54. When a predetermined voltage is applied to the gate electrode 40 via the gate pad 54, a channel is formed in a surface layer of the base region 14 facing the gate electrode 40. At least a portion of the emitter region 12 may be provided facing the gate conductive portion 44. In the example of FIG. 3, at least a portion of the emitter region 12 faces the insulating film 42 of the gate electrode 40.

[0034] The element electrode 52 is provided above the semiconductor substrate 80. In the example of Fig. 3, the element electrode 52 is provided on the upper surface 21 of the semiconductor substrate 80. The element electrode 52 may be provided on the upper surface 21 of the semiconductor substrate 80 via a barrier layer. The element electrode 52 faces the emitter region 12 and the base region 14 on the upper surface 21 of the semiconductor substrate 80. The element electrode 52 and the gate conductive portion 44 are insulated from each other by the insulating film 42.

[0035] 3, an element electrode pad 56 and a wire 60 (wire 60-1) are provided above the element electrode 52. The wire 60-1 is connected to the element electrode pad 56 at a connection point 62-1.

[0036] In this example, the density of the emitter regions 12 is changed by disposing the emitter regions 12 discretely in the arrangement direction. In this example, the distance D1 between the emitter regions 12 in the arrangement direction is changed. Also, the width L1 of the base region 14 in the arrangement direction may be changed. The greater the distance D1 between the emitter regions 12 in the arrangement direction, the more the concentration of current can be reduced and the more the temperature rise can be suppressed.

[0037] 4 is a diagram showing an example of the configuration of the semiconductor device 100 in the region 94-2. The region 94-2 differs from the structure shown in FIG. 3 in that the wire 60-1 is connected to the element electrode pad 56 at the connection point 62-2. The region 94-2 also differs from the structure shown in FIG. 3 in that the distance between the emitter regions 12 is D2 and the width of the base region 14 is L2. The other configurations in the region 94-2 may be the same as those in the region 94-1 shown in FIG. 3.

[0038] A distance D2 between the emitter regions 12 in the region 94-2 is different from a distance D1 between the emitter regions 12 in the region 94-1. Therefore, the density of the emitter regions 12 below the connection points 62 of the wire 60 can be made to differ for each connection point 62. In the example of Fig. 3 and Fig. 4, D1>D2. That is, the density of the emitter regions 12 in the region 94-2 is higher than the density of the emitter regions 12 in the region 94-1.

[0039] Fig. 5 is a diagram illustrating an example of the arrangement of the emitter regions 12 in a plan view. Fig. 3 or Fig. 4 is an example of a-a' cross section of Fig. 5. Fig. 5 shows the emitter regions 12, the base region 14, and the drift region 18 on the upper surface 21 of the semiconductor substrate 80. Also, the gate electrode 40 is shown by hatching.

[0040] In this example, the emitter regions 12 are discretely arranged in the arrangement direction and in the extension direction, thereby varying the density of the emitter regions 12. In the example of Fig. 5, the extension direction is the y-axis direction.

[0041] In the example of FIG. 5, the width of the emitter regions 12 in the extension direction is L3, and the distance between the emitter regions 12 in the extension direction is L4. L4 may be larger than L3. As an example, L3:L4=1:3. By adjusting the ratio of L3 to L4, it is possible to reduce current concentration and suppress temperature rise. To reduce the density of the emitter regions 12, the ratio of L3 to L4 should be reduced. To increase the density of the emitter regions 12, the ratio of L3 to L4 should be increased.

[0042] Fig. 6 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. Fig. 3 or Fig. 4 is an example of the b-b' cross section of Fig. 6. Fig. 6 differs from Fig. 5 in that the width of the emitter regions 12 in the extension direction is L5 and the distance between the emitter regions 12 in the extension direction is L6. Other configurations in Fig. 6 may be the same as those in Fig. 5.

[0043] In the example of FIG. 6, L6 may be the same as L5. It may be the same even if there is an error of ±10% or less. In the example of FIG. 6, the ratio of L5 to L6 is larger than in the example of FIG. 5, so the density of the emitter regions 12 is higher than in the example of FIG. 5. As shown in FIG. 5 and FIG. 6, by adjusting the ratio of L5 to L6, it is possible to reduce current concentration and suppress temperature rise. Note that the width of the emitter regions 12 in the stretching direction may be larger than the interval between the emitter regions 12 in the stretching direction.

[0044] 3 or 4 is an example of the cross section of FIG. 5 and FIG. 6, but the ratio of the width and the spacing of the emitter regions 12 may be changed for each connection point 62. For example, in region 94-1, the emitter regions 12 may be arranged with L3:L4=1:3 as shown in FIG. 5, and in region 94-2, the emitter regions 12 may be arranged with L5:L6=1:1 as shown in FIG. 6. In this way, by changing the ratio of the width and the spacing of the emitter regions 12 for each connection point 62, the density of the emitter regions 12 in the extension direction can be changed for each connection point 62.

[0045] Fig. 7 is a diagram showing another example of the configuration of the semiconductor device 100 in the region 94-1. The semiconductor device 100 in Fig. 7 differs from the semiconductor device 100 in Fig. 3 in that it includes a contact region 15 on the upper surface 21 of the semiconductor substrate 80. Other configurations in Fig. 7 may be the same as those in Fig. 3.

[0046] The contact region 15 is provided on the upper surface 21 of the semiconductor substrate 80 between the two gate electrodes 40. The contact region 15 may be provided between the emitter regions 12. That is, in this example, the contact region 15 does not face the gate electrode 40. The contact region 15 is connected to the element electrode 52. The contact region 15 in this example is of the second conductivity type having a higher impurity concentration than the base region 14. The contact region 15 in this example is of the P + Further, the distance D1 between the emitter regions 12 in the arrangement direction is equal to the width of the contact region 15 in the arrangement direction.

[0047] Fig. 8 is a diagram showing another example of the configuration of the semiconductor device 100 in the region 94-2. The semiconductor device 100 in Fig. 8 differs from the semiconductor device 100 in Fig. 4 in that it includes contact regions 15 on the upper surface 21 of the semiconductor substrate 80. Other configurations in Fig. 8 may be the same as those in Fig. 4. Furthermore, the distance D2 between the emitter regions 12 in the arrangement direction is equal to the width of the contact regions 15 in the arrangement direction.

[0048] 3 and 4, the distance D2 between the emitter regions 12 in the region 94-2 is different from the distance D1 between the emitter regions 12 in the region 94-1. Therefore, the density of the emitter regions 12 below the connection points 62 of the wire 60 can be made to differ for each connection point 62. In the examples of FIGS. 8 and 7, D1>D2.

[0049] Fig. 9 is a diagram illustrating another example of the arrangement of emitter regions 12 in a plan view. Fig. 7 or Fig. 8 is an example of a c-c' cross section of Fig. 9. Fig. 9 differs from Fig. 5 in that it includes contact regions 15. Other configurations in Fig. 9 may be the same as Fig. 5. Even when the contact regions 15 are included, current concentration can be reduced and temperature rise can be suppressed by adjusting the ratio of L3 and L4.

[0050] Fig. 10 is a diagram illustrating another example of the arrangement of emitter regions 12 in a plan view. Fig. 7 or Fig. 8 is an example of a d-d' cross section of Fig. 10. Fig. 10 differs from Fig. 6 in that it includes contact regions 15. Other configurations in Fig. 10 may be the same as those in Fig. 6. Even when the contact regions 15 are included, current concentration can be reduced and temperature rise can be suppressed by adjusting the ratio of L5 and L6.

[0051] FIG. 11 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. 7 or FIG. 8 is an example of the e-e' cross section of FIG. 11. FIG. 11 differs from FIG. 9 and FIG. 10 in that the contact regions 15 are provided discretely in the extension direction. Other configurations in FIG. 11 may be the same as FIG. 9 and FIG. 10. The emitter regions 12 are provided between the contact regions 15 in the extension direction. That is, the contact regions 15 are sandwiched between the emitter regions 12 in the extension direction. In the example of FIG. 11, the emitter regions 12 are provided in a ladder shape.

[0052] In the example of FIG. 11, the width of the contact region 15 in the extension direction is L7, and the distance between the contact regions 15 in the extension direction is L8. The ratio of L7 to L8 may be large. As an example, L7:L8=3:1. By adjusting the ratio of L7 to L8, the density of the emitter region 12 can be changed.

[0053] FIG. 12 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. 7 or FIG. 8 is an example of the f-f' cross section of FIG. 12. FIG. 12 differs from FIG. 9 and FIG. 10 in that the contact regions 15 are provided discretely in the extension direction. Other configurations in FIG. 12 may be the same as FIG. 9 and FIG. 10. The emitter regions 12 are provided between the contact regions 15 in the extension direction. In the example of FIG. 12, the emitter regions 12 are provided in a ladder shape.

[0054] In the example of FIG. 12, the width of the contact region 15 in the extension direction is L9, and the distance between the contact regions 15 in the extension direction is L10. The ratio of L9 to L10 may be small. As an example, L9:L10=1:3. The density of the emitter region 12 can be changed by adjusting the ratio of L9 to L10. FIGS. 11 and 12 are effective for miniaturizing the semiconductor device 100 because the width between the gate electrodes 40 can be narrower than in FIGS. 9 and 10.

[0055] Fig. 13 is a diagram showing another example of the configuration of the semiconductor device 100 in the region 94-1. The semiconductor device 100 in Fig. 13 differs from the semiconductor device 100 in Fig. 7 in that the semiconductor device 100 in Fig. 13 includes an emitter region 12 instead of the contact region 15 on the upper surface 21 of the semiconductor substrate 80. Other configurations in Fig. 13 may be the same as those in Fig. 7.

[0056] Fig. 14 is a diagram showing another example of the configuration of the semiconductor device 100 in the region 94-2. The semiconductor device 100 in Fig. 14 differs from the semiconductor device 100 in Fig. 8 in that it has an emitter region 12 instead of the contact region 15 on the upper surface 21 of the semiconductor substrate 80. Other configurations in Fig. 14 may be the same as those in Fig. 8. In Figs. 13 and 14, the emitter region 12 is provided continuously between two gate electrodes 40 on the upper surface 21 of the semiconductor substrate 80.

[0057] FIG. 15 is a diagram illustrating another example of the arrangement of the emitter regions 12 in a plan view. FIG. 13 or FIG. 14 is an example of the g-g' cross section of FIG. 15. FIG. 15 differs from FIG. 9 and FIG. 10 in that the emitter regions 12 are provided continuously between two gate electrodes 40. Other configurations in FIG. 15 may be the same as FIG. 9 and FIG. 10. Even when the emitter regions 12 are provided continuously between two gate electrodes 40, current concentration can be reduced and temperature rise can be suppressed by adjusting the ratio of L11 and L12.

[0058] FIG. 16 is a diagram for explaining another example of the arrangement of the emitter region 12 in a plan view. FIG. 13 or FIG. 14 is an example of the h-h' cross section of FIG. 16. FIG. 16 is different from FIG. 9 and FIG. 10 in that the emitter region 12 is continuously provided between two gate electrodes 40. Other configurations of FIG. 16 may be the same as FIG. 9 and FIG. 10. Even if the emitter region 12 is continuously provided between two gate electrodes 40, the concentration of current can be reduced and the temperature rise can be suppressed by adjusting the ratio of L13 and L14. Also, in FIG. 15 and FIG. 16, the emitter region 12 and the contact region 15 are provided discretely in the extension direction. FIG. 15 and FIG. 16 are effective for miniaturization of the semiconductor device 100 because the width between the gate electrodes 40 can be narrowed compared to FIG. 9 and FIG. 10, as in FIG. 11 and FIG. 12.

[0059] Fig. 17 is a plan view showing an example of a semiconductor device 200. The semiconductor device 200 in Fig. 17 differs from the semiconductor device 100 in Fig. 1 in that the semiconductor device 200 in Fig. 17 includes three or more wires 60. Other configurations of the semiconductor device 200 in Fig. 17 may be the same as those of the semiconductor device 100 in Fig. 1.

[0060] The semiconductor device 200 includes a wire 60-1, a wire 60-2, and a wire 60-3. In the example of FIG. 17, the wire 60-3 is connected to the element electrode pad 56 at a connection point 62-5 and a connection point 62-6. The wire 60-3 has an end 64-3 and a connection portion 66-3. The end 64-3 is one end of the wire 60-3, and the connection portion 66-3 is the other end of the wire 60-3. The connection portion 66-3 is connected to the external electrode 92. The connection point 62-5 is a connection point on the connection portion 66-3 side on the wire 60-3, and the connection point 62-6 is a connection point on the end 64-3 side on the wire 60-3. The wire 60-2 is sandwiched between the wire 60-1 and the wire 60-3 in the arrangement direction.

[0061] The density of the emitter regions 12 below the connection point 62 of the wire 60 sandwiched between the other wires 60 may be higher than the density of the emitter regions 12 below at least one of the connection points 62 of the other wires 60. In other words, the density of the emitter regions 12 below the connection point 62 of the wire 60-2 may be higher than the density of the emitter regions 12 below at least one of the connection points 62 of the wires 60-1 and 60-3. In the example of FIG. 17, the density of the emitter regions 12 below the connection point 62-3 may be higher than the density of the emitter regions 12 below the connection point 62-1. Also, the density of the emitter regions 12 below the connection point 62-3 may be higher than the density of the emitter regions 12 below the connection point 62-5. Current is less likely to concentrate on the wire 60-2 that is sandwiched between the other wires 60-1 and 60-3, so by increasing the density of the emitter region 12, current concentration can be reduced and temperature rise can be suppressed.

[0062] Also, the density of the emitter regions 12 below the connection point 62-4 may be higher than the density of the emitter regions 12 below at least one of the connection points of the wires 60-1 and 60-3. The density of the emitter regions 12 below the connection point 62-4 may be higher than the density of the emitter regions 12 below the connection point 62-2. The density of the emitter regions 12 below the connection point 62-4 may be higher than the density of the emitter regions 12 below the connection point 62-6. The density of the emitter regions 12 below the connection point 62-4 may be higher than the density of the emitter regions 12 below the connection point 62-1. The density of the emitter regions 12 below the connection point 62-4 may be lower than the density of the emitter regions 12 below the connection point 62-1. The density of the emitter regions 12 below the connection point 62-4 may be higher than the density of the emitter regions 12 below the connection point 62-5. The density of the emitter regions 12 below the connection point 62-4 may be lower than the density of the emitter regions 12 below the connection point 62-5.

[0063] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]

[0064] 12 emitter region, 14 base region, 15 contact region, 18 drift region, 20 collector region, 21 upper surface, 23 lower surface, 24 edge, 26 edge, 40 gate electrode, 42 insulating film, 44 gate conductive portion, 52 device electrode, 54 gate pad, 56 device electrode pad, 60 wire, 62 connection portion, 64 edge, 66 connection portion, 70 protective film, 80 semiconductor substrate, 90 opening, 92 external electrode, 94 region, 100 semiconductor device, 200 semiconductor device

Claims

1. A semiconductor substrate; a device electrode provided above the semiconductor substrate; a device electrode pad electrically connected to the device electrode; Three or more wires are connected to the element electrode pads at a plurality of connection points. Equipped with the semiconductor substrate has emitter regions of a first conductivity type arranged in an arrangement direction and facing the element electrodes on an upper surface of the semiconductor substrate; a density of the emitter regions beneath any one of the wire connection points differs from a density of the emitter regions beneath any other of the wire connection points; The density of the emitter regions below the connection points of the wire sandwiched between other wires is higher than the density of the emitter regions below at least one of the connection points of the other wires. Semiconductor device.

2. A semiconductor substrate; a device electrode provided above the semiconductor substrate; a device electrode pad electrically connected to the device electrode; Wires connecting to the element electrode pads at a plurality of connection points; Equipped with the semiconductor substrate has emitter regions of a first conductivity type arranged in an arrangement direction and facing the element electrodes on an upper surface of the semiconductor substrate; a density of the emitter regions beneath any one of the wire connection points differs from a density of the emitter regions beneath any other of the wire connection points; The density of the emitter regions is changed by disposing the emitter regions discretely in the arrangement direction. Semiconductor device.

3. A semiconductor substrate; a device electrode provided above the semiconductor substrate; a device electrode pad electrically connected to the device electrode; Wires connecting to the element electrode pads at a plurality of connection points; Equipped with the semiconductor substrate has emitter regions of a first conductivity type arranged in an arrangement direction and facing the element electrodes on an upper surface of the semiconductor substrate; a density of the emitter regions beneath any one of the wire connection points differs from a density of the emitter regions beneath any other of the wire connection points; The wire has a connection portion for connection to an external electrode, the greater the distance to the connection portion, the higher the density of the emitter region below the connection point of the wire; The emitter region is also provided below the connection point of the wire that is the shortest distance from the connection portion. Semiconductor device.

4. The density of the emitter regions is changed by disposing the emitter regions discretely in an extension direction perpendicular to the arrangement direction. The semiconductor device according to claim 1 .

5. The density of the emitter region is changed based on the distance between the connection point of the wire and the edge of the semiconductor device. The semiconductor device according to claim 1 .

6. a plurality of gate electrodes extending in an extension direction perpendicular to the arrangement direction on the upper surface of the semiconductor substrate; a contact region of a second conductivity type provided between two of the gate electrodes; Equipped with The contact regions are arranged discretely in the extending direction. The semiconductor device according to claim 1 .

7. The contact region is sandwiched between the emitter regions in the extending direction. The semiconductor device according to claim 6.

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