Silicon carbide semiconductor device

Abstract

To provide an SiC semiconductor device that can suppress a decrease in withstanding voltage while suppressing size increase.SOLUTION: A main element and a sense element Se include: a substrate 11 that is formed from silicon carbide; a drift layer 19 that is arranged on the substrate 11; a base layer 21 that is formed on the drift layer 19; a plurality of field relaxation layers 15 that are formed in the drift layer 19, electrically connected to the base layer 21, and arranged so as to extend along one direction in surface directions of the substrate 11; an impurity region 22 that is formed on a surface layer portion of the base layer 21; a gate insulation film 25 that is arranged on a surface of the base layer 21 which is sandwiched between the drift layer 19 and the impurity region 22; a gate electrode 26 that is arranged on the gate insulation film 25; a first electrode 28 that is electrically connected to the impurity region 22 and the base layer 21; and a second electrode 29 that is electrically connected to the substrate 11. In addition, the withstanding voltage of the sense element Se is set so as to be higher than that of the main element.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a silicon carbide (hereinafter also simply referred to as SiC) semiconductor device made of SiC. [Background technology]

[0002] Conventionally, a SiC semiconductor device having a main region in which a main element is formed and a sense region in which a sense element is formed has been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, the same IGBT (short for Insulated Gate Bipolar Transistor) element is formed as the main element and the sense element. In addition, the main element and the sense element (i.e., the main region and the sense region) are formed to have a predetermined area ratio.

[0003] Furthermore, in this SiC semiconductor device, in order to prevent current concentration at specific locations and a decrease in the breakdown voltage, a well layer is provided between the main region and the sense region, and an electrode electrically connected to the well layer is formed on the well layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-167208 A Summary of the Invention [Problem to be solved by the invention]

[0005] However, the above-mentioned SiC semiconductor device is easily increased in size because it has a well layer between the main region and the sense region.

[0006] In view of the above, an object of the present invention is to provide a SiC semiconductor device that can suppress an increase in size and a decrease in breakdown voltage. [Means for solving the problem]

[0007] Claim 1 to achieve the above object 、3、5 a SiC semiconductor device having a main region (Rm) in which a main element (Me) is formed and a sense region (Rs) in which a sense element (Se) is formed, in which a main current flowing through the main element is detected based on a sense current flowing through the sense element, the main element and the sense element being of a first conductivity type or a second conductivity type, the device comprising: a substrate (11) made of SiC; a drift layer (19) of the first conductivity type arranged on the substrate; a base layer (21) of the second conductivity type formed on the drift layer; a plurality of electric field relaxation layers (15) of the second conductivity type formed in the drift layer and electrically connected to the base layer, extending along one direction in the surface direction of the substrate; an impurity region (22) of the first conductivity type formed in a surface layer portion of the base layer; a gate insulating film (25) arranged on the surface of the base layer sandwiched between the drift layer and the impurity region; a gate electrode (26) arranged on the gate insulating film; a first electrode (28) electrically connected to the impurity region and the base layer; and a second electrode (29) electrically connected to the substrate. The sense element has a higher withstand voltage than the main element. Furthermore, in claim 1, the widths (a1, a2) of the electric field relaxation layers are made wider in the sense element than in the main element. In claim 3, the pitch interval (b1, b2) between adjacent electric field buffer layers is narrower in the sense element than in the main element. In claim 5, the depths (c1, c2) of the plurality of electric field relaxation layers are made deeper in the sense element than in the main element.

[0008] According to this, although current concentration is more likely to occur in the sense element than in the main element, the withstand voltage of the sense element is set higher than that of the main element. Therefore, it is possible to suppress a decrease in the withstand voltage of the entire SiC semiconductor device. In addition, since there is no need to form a well layer or the like between the main region and the sense region in this SiC semiconductor device, it is also possible to suppress an increase in size.

[0009] Note that the reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and specific components described in the embodiments described below. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view of a SiC semiconductor device in a first embodiment. [Diagram 2] FIG. [Diagram 3] FIG. 2 is a perspective cross-sectional view of a sense region. [Figure 4] FIG. 2 is a plan view showing a first deep layer in the main region. [Diagram 5] FIG. 2 is a plan view showing a first deep layer in the sense region. [Figure 6] FIG. 11 is a plan view showing a first deep layer in a sense region in a second embodiment. [Figure 7] FIG. 11 is a perspective cross-sectional view of a sense region in a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0012] (First embodiment) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described with reference to the drawings. The SiC semiconductor device of the present embodiment is preferably used mounted on a vehicle such as an automobile.

[0013] The SiC semiconductor device of this embodiment has a main region Rm in which a main element Me is formed, a sense region Rs in which a sense element Se is formed, and an outer peripheral region Rp, as shown in Fig. 1. Hereinafter, the configurations of the main element Me formed in the main region Rm and the sense element Se formed in the sense region Rs will be described with reference to Figs. 2 to 5.

[0014] In addition, the main element Me and the sense element Se of this embodiment are configured by forming MOSFETs (short for Metal Oxide Semiconductor Field Effect Transistor) having the same basic configuration. In addition, the main element Me and the sense element Se are formed to have a predetermined area ratio (for example, 2000:1). In the SiC semiconductor device of this embodiment, the main current flowing through the main element Me is detected (i.e., derived) based on the sense current flowing through the sense element Se and the area ratio. In addition, although detailed description is omitted, the peripheral region Rp has a temperature detection element 1 formed therein, and pads 2 connected to the main element Me, the sense element Se, the temperature detection element 1, etc. formed therein.

[0015] 2 to 5, the following description will be given assuming that one direction in the surface direction of a substrate 11 (described later) is the X-axis direction, a direction intersecting the one direction in the surface direction of the substrate is the Y-axis direction, and a direction perpendicular to the X-axis direction and the Y-axis direction is the Z-axis direction. Note that in this embodiment, the X-axis direction and the Y-axis direction are perpendicular to each other.

[0016] 2 and 3, the SiC semiconductor device is configured using a semiconductor substrate 10, and as described above, the main element Me and the sense element Se have the same basic configuration. + In this embodiment, the substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si surface and an n-type impurity concentration of nitrogen, phosphorus, etc. of 1.0×10 19 / cm 3 The substrate 11 has a thickness of about 300 μm. In this embodiment, the substrate 11 constitutes a drain region.

[0017] On the surface of the substrate 11, a n-type SiC -A type buffer layer 12 is formed on the surface of the substrate 11. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The buffer layer 12 has an n-type impurity concentration between that of the substrate 11 and a low concentration layer 13 described later, and has a thickness of about 1 μm.

[0018] On the surface of the buffer layer 12, for example, an n-type impurity concentration of 5.0 to 10.0×10 15 / cm 3 The thickness of the n-type SiC substrate is about 10 to 15 μm. - A low concentration layer 13 of a mold is formed. The impurity concentration of this low concentration layer 13 may be constant in the Z-axis direction, but it is preferable that the concentration distribution is gradient so that the low concentration layer 13 on the substrate 11 side has a higher concentration than the side away from the substrate 11. For example, the low concentration layer 13 has an impurity concentration of 2.0×10 15 / cm 3 It is preferable that the low concentration layer 13 has a higher internal resistance than the other portions. With this configuration, the internal resistance of the low concentration layer 13 can be reduced, and the on-resistance can be reduced.

[0019] The JFET section 14 and the first deep layer 15 are formed in the surface layer of the low concentration layer 13. In this embodiment, the JFET section 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions arranged alternately and repeatedly in the Y-axis direction. That is, the JFET section 14 and the first deep layer 15 are each formed in a stripe shape extending along the X-axis direction in the normal direction (hereinafter simply referred to as the normal direction) to the surface of the substrate 11, and are arranged alternately along the Y-axis direction. In addition, in the normal direction to the surface of the substrate 11, in other words, it can be said that when viewed from the normal direction to the surface of the substrate 11, or when viewed from the Z-axis direction. In this embodiment, the first deep layer 15 corresponds to an electric field relaxation layer.

[0020] The JFET section 14 is of n-type with a higher impurity concentration than the low concentration layer 13, and has a depth of 0.3 to 1.5 μm. In this embodiment, the JFET section 14 has an n-type impurity concentration of 7.0×10 16 ~5.0×10 17 / cm 3 The first deep layer 15 has a p-type impurity concentration of, for example, boron, etc. of 2.0×10 17 ~2.0×10 18 / cm 3 It is said that.

[0021] Moreover, the first deep layer 15 in this embodiment is formed shallower than the JFET section 14. That is, the first deep layer 15 is formed so that its bottom is located within the JFET section 14. In other words, the first deep layer 15 is formed so that the JFET section 14 is located between the first deep layer 15 and the low concentration layer 13.

[0022] A current spreading layer 17 and a second deep layer 18 are formed on the JFET section 14 and the first deep layer 15. The current spreading layer 17 is made of an n-type impurity layer and has a thickness of 0.5 to 2 μm. The n-type impurity concentration of the current spreading layer 17 is, for example, 1.0×10 16 ~5.0×10 17 / cm 3 Furthermore, the current spreading layer 17 is connected to the JFET section 14. In this embodiment, the low concentration layer 13, the JFET section 14, and the current spreading layer 17 are connected to each other, and form a drift layer 19. In this embodiment, the drift layer 19 is formed in this manner, and therefore the first deep layer 15 is disposed in the drift layer 19.

[0023] The second deep layer 18 has a p-type impurity concentration of, for example, 2.0×10 17 ~2.0×10 18 / cm 3 The thickness of the second deep layer 18 is set to be equal to that of the current spreading layer 17. The second deep layer 18 is formed so as to be connected to the first deep layer 15.

[0024] The current spreading layer 17 and the second deep layer 18 are extended in a direction intersecting the longitudinal direction of the striped portion of the JFET section 14 and the first deep layer 15. In this embodiment, the current spreading layer 17 and the second deep layer 18 are extended in the Y-axis direction as the longitudinal direction, and are arranged in a layout in which a plurality of layers are alternately arranged in the X-axis direction. The formation pitch of the current spreading layer 17 and the second deep layer 18 is set to match the formation pitch of a trench gate structure described later, and the second deep layer 18 is formed to sandwich a trench 24 described later.

[0025] A p-type base layer 21 is formed on the current spreading layer 17 and the second deep layer 18. The first deep layer 15 is electrically connected to the base layer 21 via the second deep layer 18.

[0026] The surface layer of the base layer 21 is + The source region 22 and p + A contact region 23 of a type is formed. The source region 22 is formed so as to contact a side surface of a trench 24 described later, and the contact region 23 is formed on the opposite side of the trench 24 across the source region 22. In this embodiment, the source region 22 corresponds to an impurity region.

[0027] The base layer 21 has a p-type impurity concentration of, for example, 3.0×10 17 / cm 3 The source region 22 has an n-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0×10 21 / cm 3 The contact region 23 has a p-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0×10 21 / cm 3 It is said that.

[0028] In this embodiment, as described above, the semiconductor substrate 10 is formed by stacking the substrate 11, the buffer layer 12, the low concentration layer 13, the JFET section 14, the first deep layer 15, the current spreading layer 17, the second deep layer 18, the base layer 21, the source region 22, the contact region 23, and the like. Hereinafter, the surface of the semiconductor substrate 10 on the substrate 11 side is referred to as the other surface 10b of the semiconductor substrate 10, and the surface on the source region 22 and contact region 23 side is referred to as the one surface 10a of the semiconductor substrate 10. The source region 22 and the contact region 23 are exposed from the one surface 10a of the semiconductor substrate 10.

[0029] A trench 24 is formed in the semiconductor substrate 10 from the one surface 10a side so as to penetrate the base layer 21 etc. to reach the first deep layer 15 and the JFET section 14 and have its bottom surface located within the first deep layer 15 and the JFET section 14.

[0030] 2 and 3, only one trench 24 is shown, but in reality, multiple trenches 24 are formed and arranged at equal intervals. Specifically, multiple trenches 24 are provided so as to extend along the Y-axis direction, and are also formed in stripes arranged at equal intervals in the X-axis direction. That is, in this embodiment, the trenches 24 are formed so that their longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15. Moreover, the trenches 24 are formed so as to be sandwiched between the second deep layers 18 in the normal direction.

[0031] A gate insulating film 25 is formed on the inner wall surface of the trench 24. A gate electrode 26 made of doped poly-Si is formed on the surface of the gate insulating film 25. This forms a trench gate structure. The gate electrode 26 is electrically connected to the pad 2 via a gate wiring (not shown). In this embodiment, the portion of the base layer 21 that contacts the wall surface of the trench 24 corresponds to the surface of the base layer sandwiched between the drift layer and the impurity region.

[0032] An interlayer insulating film 27 is formed on the surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 26, the gate insulating film 25, etc. The interlayer insulating film 27 is made of BPSG (abbreviation of borophosphosilicate glass) or the like.

[0033] The interlayer insulating film 27 has contact holes 27a that expose the source region 22 and the contact region 23. The pattern of the contact holes 27a formed in the interlayer insulating film 27 is arbitrary, and may be, for example, a pattern in which a plurality of squares are arranged, a pattern in which rectangular lines are arranged, or a pattern in which lines are arranged. In this embodiment, the contact holes 27a are linear along the longitudinal direction of the trench 24.

[0034] An upper electrode 28 electrically connected to the source region 22 and the contact region 23 through the contact hole 27a is formed on the interlayer insulating film 27. In this embodiment, the upper electrode 28 corresponds to a first electrode.

[0035] The upper electrode 28 of this embodiment is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 22) is made of a metal that can make ohmic contact with the n-type SiC. At least the portion of the plurality of metals that contacts the p-type SiC (i.e., the contact region 23) is made of a metal that can make ohmic contact with the p-type SiC.

[0036] A lower electrode 29 electrically connected to the substrate 11 is formed on the other surface 10b side of the semiconductor substrate 10. In this embodiment, the lower electrode 29 corresponds to the second electrode. In the SiC semiconductor device of this embodiment, with such a structure, MOSFETs having an n-channel type trench gate structure are formed in the main region Rm and the sense region Rs.

[0037] Here, the present inventors have studied the position where current concentration is likely to occur in the above-mentioned SiC semiconductor device. The present inventors have found that in the above-mentioned SiC semiconductor device, the sense element Se has an area much smaller than that of the main element Me, so that current concentration is likely to occur. The present inventors have also found that the aspect ratio (i.e., the ratio of the length in the x-axis direction to the length in the y-axis direction) in the planar shape of the sense element Se is likely to be unbalanced, so that current concentration is more likely to occur in the sense element Se than in the main element Me. For this reason, in the above-mentioned SiC semiconductor device, the withstand voltage of the sense element Se is likely to decrease, and the decrease in the withstand voltage of the sense element Se reduces the withstand voltage of the entire SiC semiconductor device.

[0038] 2 to 5, the main element Me and the sense element Se are configured such that the sense element Se has a higher breakdown voltage than the main element Me. Specifically, in this embodiment, the width a2 of the first deep layer 15 of the sense element Se is made wider than the width a1 of the first deep layer 15 of the main element Me. However, in this embodiment, the pitch interval b1 in the first deep layer 15 of the main element Me is made equal to the pitch interval b2 in the first deep layer 15 of the sense element Se. In addition, the depth c1 of the first deep layer 15 of the main element Me is made equal to the depth c2 of the first deep layer 15 of the sense element Se.

[0039] In this embodiment, the width of the first deep layer 15 is a direction perpendicular to the longitudinal direction of the first deep layer 15, a length along the surface direction of the semiconductor substrate 10, and a length along the Y-axis direction of the first deep layer 15. In this embodiment, the pitch interval of the first deep layer 15 is a length between an end of one first deep layer 15 in the Y-axis direction and an end of the other first deep layer 15 in the Y-axis direction, which is on the same side as the one first deep layer 15, in two adjacent first deep layers 15. In other words, the pitch interval of the first deep layer 15 is the sum of the width of one first deep layer 15 and the interval between the adjacent first deep layers 15. The depth of the first deep layer 15 is the length in the Z-axis direction of the first deep layer 15, and is the length from the interface between the first deep layer 15 and the current spreading layer 17 or the second deep layer 18.

[0040] The above is the configuration of the SiC semiconductor device in this embodiment. + type, n type, n - The type corresponds to the first conductivity type, and p - type, p type, p + The type corresponds to the second conductivity type. Next, the operation and effects of the above-mentioned SiC semiconductor device will be described.

[0041] In the above-described SiC semiconductor device, in the off state before a gate voltage is applied to the gate electrode 26, no inversion layer is formed in the base layer 21. For this reason, even if a positive voltage, for example, 1600 V, is applied to the lower electrode 29, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device is in the off state where no current flows between the upper electrode 28 and the lower electrode 29.

[0042] Furthermore, when the SiC semiconductor device is in an off state, an electric field is applied between the drain and gate, and electric field concentration may occur at the bottom of the gate insulating film 25. However, in the above-mentioned SiC semiconductor device, the first deep layer 15 and the JFET section 14 are provided at a position deeper than the trench 24. Therefore, the depletion layer formed between the first deep layer 15 and the JFET section 14 suppresses the rise of the equipotential line due to the influence of the drain voltage, making it difficult for a high electric field to penetrate into the gate insulating film 25. Therefore, in this embodiment, it is possible to suppress the gate insulating film 25 from being destroyed when the device is off.

[0043] In this embodiment, the width a2 of the first deep layer 15 of the sense element Se is made wider than the width a1 of the first deep layer 15 of the main element Me. Therefore, the depletion layer in the sense element Se is more likely to extend toward the other surface 10b of the semiconductor substrate 10 than in the main element Me. Therefore, the withstand voltage of the sense element Se becomes higher than the withstand voltage of the main element Me, and a decrease in the withstand voltage of the entire SiC semiconductor device can be suppressed.

[0044] When a predetermined gate voltage, for example, 20 V, is applied to the gate electrode 26, a channel is formed on the surface of the base layer 21 that is in contact with the trench 24. As a result, a current flows between the upper electrode 28 and the lower electrode 29, and the SiC semiconductor device is turned on. In this embodiment, since electrons that have passed through the channel pass through the current spreading layer 17, the JFET section 14, and the low concentration layer 13 and flow to the substrate 11, it can be said that a drift layer 19 having the current spreading layer 17, the JFET section 14, and the low concentration layer 13 is configured.

[0045] According to the present embodiment described above, the breakdown voltage of the sense element Se is set higher than the breakdown voltage of the main element Me. Therefore, it is possible to suppress a decrease in the breakdown voltage of the entire SiC semiconductor device. In addition, in this SiC semiconductor device, it is not necessary to form a well layer or the like between the main region Rm and the sense region Rs, so that it is possible to suppress an increase in size.

[0046] (1) In this embodiment, the width a2 of the first deep layer 15 of the sense element Se is wider than the width a1 of the first deep layer 15 of the main element Me. Therefore, when the SiC semiconductor device is in an off state, the depletion layer caused by the first deep layer 15 of the sense element Se is more likely to extend toward the other surface 10b of the semiconductor substrate 10 than that of the main element Me. Therefore, the withstand voltage of the sense element Se can be made higher than that of the main element Me. Note that such a configuration can be achieved by simply changing the widths a1 and a2 of the first deep layer 15, and therefore the structure can be prevented from becoming complicated.

[0047] Second embodiment A second embodiment will be described. This embodiment is different from the first embodiment in that the pitch intervals b1 and b2 of the first deep layer 15 are changed. As the rest is similar to the first embodiment, a description thereof will be omitted here.

[0048] In the SiC semiconductor device of this embodiment, the configuration of the main element Me is the same as that of the first embodiment, and the first deep layer 15 is formed as shown in Fig. 4. In this embodiment, as shown in Fig. 4 and Fig. 6, the pitch interval b2 of the first deep layer 15 in the sense element Se is narrower than the pitch interval b1 of the first deep layer 15 in the main element Me. In this embodiment, the width a2 of the first deep layer 15 in the sense element Se is equal to the width a1 of the first deep layer 15 in the main element Me.

[0049] According to the present embodiment described above, the pitch interval b2 of the first deep layers 15 in the sense element Se is narrower than the pitch interval b1 of the first deep layers 15 in the main element Me. Therefore, when the SiC semiconductor device is in an off state, the depletion layer caused by the first deep layers 15 in the sense element Se is more likely to extend toward the other surface 10b of the semiconductor substrate 10 than in the main element Me. Therefore, the same effect as in the first embodiment can be obtained. Note that such a configuration can be achieved by simply changing the pitch intervals b1 and b2 of the first deep layers 15, and therefore the structure can be prevented from becoming complicated.

[0050] Third embodiment A third embodiment will be described. This embodiment is different from the first embodiment in that the depths c1 and c2 of the first deep layer 15 are changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0051] In the SiC semiconductor device of this embodiment, the configuration of the main element Me is the same as that of the first embodiment, and the first deep layer 15 is formed as shown in Fig. 2. In this embodiment, as shown in Fig. 2 and Fig. 7, the depth c2 of the first deep layer in the sense element Se is deeper than the depth c1 of the first deep layer 15 in the main element Me. In this embodiment, the width a2 of the first deep layer 15 in the sense element Se is equal to the width a1 of the first deep layer 15 in the main element Me.

[0052] According to the present embodiment described above, the depth c2 of the first deep layer 15 in the sense element Se is deeper than the depth c1 of the first deep layer 15 in the main element Me. Therefore, when the SiC semiconductor device is in an off state, the depletion layer caused by the first deep layer 15 in the sense element Se is more likely to extend toward the other surface 10b of the semiconductor substrate 10 than in the main element Me. Therefore, the same effect as in the first embodiment can be obtained. Note that such a configuration can be achieved by simply changing the depths c1 and c2 of the first deep layer 15, and therefore the structure can be prevented from becoming complicated.

[0053] (Other embodiments) Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure.

[0054] For example, in each of the above embodiments, a SiC semiconductor device has been described in which a MOSFET of an n-channel type trench gate structure in which the first conductivity type is n-type and the second conductivity type is p-type is formed. However, this is merely one example, and the main region Rm and the sense region Rs may have a p-channel type trench gate structure MOSFET in which the conductivity type of each component is inverted from that of the n-channel type. Furthermore, the main region Rm and the sense region Rs may have a configuration in which an IGBT of a similar structure is formed in addition to the MOSFET. In the case of an IGBT, for example, the n-channel type MOSFET in each of the above embodiments may have a p-channel type trench gate structure MOSFET in which the conductivity type of each component is inverted from that of the n-channel type MOSFET. + The drain region (i.e., the substrate 11) is p + Apart from the change to a collector region of the n-type, this MOSFET is similar to the MOSFET described in the first embodiment.

[0055] Furthermore, in each of the above embodiments, the semiconductor device including the main element Me and the sense element Se having a trench gate structure has been described, but the semiconductor device may include the main element Me and the sense element Se having a planar gate structure.

[0056] Furthermore, in each of the above embodiments, the first deep layer 15 is described as extending along the X-axis direction, but the first deep layer 15 may be extended in the Y-axis direction.

[0057] In each of the above embodiments, the trench 24 may be formed so that the bottom surface is located within the current spreading layer 17. In other words, the trench 24 may be formed so as not to reach the first deep layer 15.

[0058] The above-mentioned embodiments may be appropriately combined. For example, the first embodiment may be combined with the second and third embodiments, and the width a2 of the first deep layer 15 of the sense element Se may be made wider than the width a1 of the main element Me. The second embodiment may be combined with the third embodiment, and the pitch interval b2 of the first deep layer 15 of the sense element Se may be made narrower than the pitch interval b1 of the first deep layer 15 of the main element Me. The above-mentioned embodiments may be further combined with each other. [Explanation of symbols]

[0059] 11 Substrate 15 First deep layer (electric field relaxation layer) 19 Drift Layer 21 Base Layer 22 Source region (impurity region) 25 Gate insulating film 26 Gate electrode 28 Upper electrode (1st electrode) 29 Lower electrode (second electrode)

Claims

1. A silicon carbide semiconductor device having a main region (Rm) in which a main element (Me) is formed, and a sense region (Rs) in which a sense element (Se) is formed and has an area smaller than that of the main region, wherein a main current flowing through the main element is detected based on a sense current flowing through the sense element, The main element and the sense element are A substrate (11) having a first conductivity type or a second conductivity type and made of silicon carbide; A drift layer (19) of a first conductivity type disposed on the substrate; A base layer (21) of a second conductivity type formed on the drift layer; a plurality of electric field relaxation layers (15) of a second conductivity type, the electric field relaxation layers (15) being formed in the drift layer and electrically connected to the base layer, and extending along one direction in the surface direction of the substrate; a first conductivity type impurity region (22) formed in a surface layer portion of the base layer; a gate insulating film (25) disposed on a surface of the base layer sandwiched between the drift layer and the impurity region; a gate electrode (26) disposed on the gate insulating film; a first electrode (28) electrically connected to the impurity region and the base layer; a second electrode (29) electrically connected to the substrate; The sense element has a higher withstand voltage than the main element, The width (a1, a2) of the plurality of electric field relaxation layers of the sense element is wider than that of the main element.

2. 2 . The silicon carbide semiconductor device according to claim 1 , wherein a pitch interval (b1, b2) between adjacent said electric field relaxation layers is narrower in said sense element than in said main element.

3. A silicon carbide semiconductor device having a main region (Rm) in which a main element (Me) is formed, and a sense region (Rs) in which a sense element (Se) is formed and has an area smaller than that of the main region, wherein a main current flowing through the main element is detected based on a sense current flowing through the sense element, The main element and the sense element are A substrate (11) having a first conductivity type or a second conductivity type and made of silicon carbide; A drift layer (19) of a first conductivity type disposed on the substrate; A base layer (21) of a second conductivity type formed on the drift layer; a plurality of electric field relaxation layers (15) of a second conductivity type, the electric field relaxation layers (15) being formed in the drift layer and electrically connected to the base layer, and extending along one direction in the surface direction of the substrate; a first conductivity type impurity region (22) formed in a surface layer portion of the base layer; a gate insulating film (25) disposed on a surface of the base layer sandwiched between the drift layer and the impurity region; a gate electrode (26) disposed on the gate insulating film; a first electrode (28) electrically connected to the impurity region and the base layer; a second electrode (29) electrically connected to the substrate; The sense element has a higher withstand voltage than the main element, The silicon carbide semiconductor device, wherein the pitch interval (b1, b2) between adjacent electric field relaxation layers is narrower in the sense element than in the main element.

4. 4 . The silicon carbide semiconductor device according to claim 1 , wherein the depths (c1, c2) of the plurality of electric field relaxation layers are deeper in the sense element than in the main element.

5. A silicon carbide semiconductor device having a main region (Rm) in which a main element (Me) is formed, and a sense region (Rs) in which a sense element (Se) is formed and has an area smaller than that of the main region, wherein a main current flowing through the main element is detected based on a sense current flowing through the sense element, The main element and the sense element are A substrate (11) having a first conductivity type or a second conductivity type and made of silicon carbide; A drift layer (19) of a first conductivity type disposed on the substrate; A base layer (21) of a second conductivity type formed on the drift layer; a plurality of electric field relaxation layers (15) of a second conductivity type, the electric field relaxation layers (15) being formed in the drift layer and electrically connected to the base layer, and extending along one direction in the surface direction of the substrate; a first conductivity type impurity region (22) formed in a surface layer portion of the base layer; a gate insulating film (25) disposed on a surface of the base layer sandwiched between the drift layer and the impurity region; a gate electrode (26) disposed on the gate insulating film; a first electrode (28) electrically connected to the impurity region and the base layer; a second electrode (29) electrically connected to the substrate; The sense element has a higher withstand voltage than the main element, The silicon carbide semiconductor device, wherein the depth (c1, c2) of the plurality of electric field relaxation layers is deeper in the sense element than in the main element.

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