Semiconductor Device

Abstract

To obtain a semiconductor device whose characteristics can be easily adjusted.SOLUTION: A semiconductor device according to the present disclosure includes a substrate having an IGBT region and a diode region, a surface electrode provided on the upper surface of the substrate, and a back surface electrode provided on the back surface opposite to the upper surface of the substrate, and the diode region includes a first portion formed thinner than the IGBT region by recessing the upper surface of the substrate, and a second portion provided on one side of the first portion and thicker than the first portion.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate in which adjacent IGBT and diode regions are defined. A trench is provided in the IGBT surface, and the diode surface of the semiconductor substrate is recessed from the IGBT surface of the semiconductor substrate. The distance between the back surface of the semiconductor substrate opposite the front surface and the bottom end of the trench corresponds to the distance between the back surface of the semiconductor substrate and the diode surface. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-28922 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device of Patent Document 1, the substrate is thin over the entire diode region, which may make it difficult to adjust the characteristics.

[0005] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device whose characteristics can be easily adjusted. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes an IGBT region and A region adjacent to the IGBT region in a direction along the upper surface of the substrate a diode region; The abovea substrate, a surface electrode provided on an upper surface of the substrate, and a back surface electrode provided on a back surface of the substrate opposite to the upper surface, the diode region comprising a first portion formed by recessing the upper surface of the substrate to be thinner than the IGBT region, and a second portion provided on one side of the first portion and thicker than the first portion; a third portion provided on the other side of the first portion and thicker than the first portion; has. The semiconductor device according to the present disclosure comprises a substrate having an IGBT region and a diode region, a surface electrode provided on an upper surface of the substrate, and a back surface electrode provided on a back surface opposite the upper surface of the substrate, the diode region having a first portion formed thinner than the IGBT region by recessing the upper surface of the substrate, and a second portion provided on one side of the first portion and thicker than the first portion, an anode layer of the diode region being provided on an upper surface of the first portion and along a side surface of the substrate connecting the first portion and the second portion, and a portion of the anode layer provided along the upper surface of the first portion and a portion provided along the side surface of the substrate connecting the first portion and the second portion are separated from each other. The semiconductor device according to the present disclosure comprises a substrate having an IGBT region and a diode region, a surface electrode provided on an upper surface of the substrate, and a back surface electrode provided on a back surface opposite the upper surface of the substrate, the diode region having a first portion formed thinner than the IGBT region by recessing the upper surface of the substrate, and a second portion provided on one side of the first portion and thicker than the first portion, the first portion having an anode layer and a Schottky contact layer in an uppermost layer. The semiconductor device according to the present disclosure comprises a substrate having an IGBT region and a diode region, a surface electrode provided on an upper surface of the substrate, and a back surface electrode provided on a back surface opposite the upper surface of the substrate, the diode region having a first portion formed thinner than the IGBT region by recessing the upper surface of the substrate, and a second portion provided on one side of the first portion and thicker than the first portion, the first portion having an anode layer in an uppermost layer, and the second portion having a Schottky contact layer in an uppermost layer. The semiconductor device according to the present disclosure comprises a substrate having an IGBT region and a diode region, a surface electrode provided on an upper surface of the substrate, and a back surface electrode provided on a back surface opposite the upper surface of the substrate, the diode region having a first portion formed thinner than the IGBT region by recessing the upper surface of the substrate, and a second portion provided on one side of the first portion and thicker than the first portion, and a side surface of the substrate connecting the first portion and the second portion is formed from an outwardly convex curved surface. The semiconductor device according to the present disclosure comprises a substrate having an IGBT region and a diode region, a surface electrode provided on an upper surface of the substrate, and a back surface electrode provided on a back surface opposite the upper surface of the substrate, the diode region having a first portion formed thinner than the IGBT region by recessing the upper surface of the substrate, and a second portion provided on one side of the first portion and thicker than the first portion, the diode region having a cathode layer on the back surface side of the substrate, the cathode layer being provided to avoid being directly below an anode layer in the first portion. Effect of the Invention

[0007] In the semiconductor device according to the present disclosure, the diode region has a first portion that is thinner than the IGBT region and a second portion that is thicker than the first portion, which makes it easy to adjust the characteristics. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 11 is a cross-sectional view of a semiconductor device according to a modified example of the first embodiment. [Diagram 3] FIG. 11 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 4] FIG. 11 is a cross-sectional view of a semiconductor device according to a third embodiment. [Diagram 5] FIG. 11 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 6] FIG. 13 is a cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 7] FIG. 13 is a cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 8] FIG. 13 is a cross-sectional view of a semiconductor device according to a seventh embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components are given the same reference numerals, and repeated description may be omitted. In the following description, n and p indicate the conductivity type of the semiconductor. The conductivity types described in each embodiment may be reversed. Furthermore, n- indicates that the impurity concentration is lower than n, and n+ indicates that the impurity concentration is higher than n. Similarly, p- indicates that the impurity concentration is lower than p, and p+ indicates that the impurity concentration is higher than p.

[0010] Embodiment 1 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 includes a substrate having an IGBT region 10 and a diode region 20. The semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region (not shown) is provided around the cell region to maintain the breakdown voltage of the semiconductor device 100.

[0011] An active trench gate 11 and a dummy trench gate 12 are provided in the IGBT region 10. The active trench gate 11 has a gate trench electrode 11a in a trench formed in the substrate via a gate trench insulating film 11b. The dummy trench gate 12 has a dummy trench electrode 12a in a trench formed in the substrate via a dummy trench insulating film 12b. The gate trench electrode 11a is electrically connected to a gate pad (not shown). The dummy trench electrode 12a is electrically connected to a surface electrode 6 provided on the upper surface of the substrate. The surface electrode 6 is an emitter electrode.

[0012] The substrate has an n-type drift layer 1. In the IGBT region 10, the substrate ranges from the n+ type source layer 13 and the p+ type contact layer 14 to the p type collector layer 16. In the IGBT region 10, an n type carrier accumulation layer 2 is provided on the upper surface side of the n- type drift layer 1. Note that the n type carrier accumulation layer 2 does not necessarily have to be provided. The n type carrier accumulation layer 2 and the n- type drift layer 1 may be collectively referred to as the drift layer.

[0013] A p-type base layer 15 is provided on the upper surface side of the n-type carrier accumulation layer 2. The n+ type source layer 13 and the p+ type contact layer 14 form the upper surface of the substrate. The n+ type source layer 13 is provided in contact with the gate trench insulating film 11b. The p+ type contact layer 14 is provided between two adjacent dummy trench gates 12. The p+ type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.

[0014] An n-type buffer layer 3 is provided on the back surface side of the n-type drift layer 1. The n-type buffer layer 3 does not necessarily have to be provided. The n-type buffer layer 3 and the n-type drift layer 1 may be collectively referred to as the drift layer. A p-type collector layer 16 is provided on the back surface side of the n-type buffer layer 3. The p-type collector layer 16 forms the back surface of the substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region.

[0015] An interlayer insulating film 4 is provided on the active trench gate 11. A barrier metal 5 is formed on the interlayer insulating film 4 and on the region of the upper surface of the IGBT region 10 where the interlayer insulating film 4 is not provided. The barrier metal 5 is in ohmic contact with the n+ type source layer 13, the p+ type contact layer 14, and the dummy trench electrode 12a. A front surface electrode 6 is provided on the barrier metal 5. A rear surface electrode 7 is provided on the rear surface opposite to the upper surface of the substrate. The rear surface electrode 7 is a collector electrode. The rear surface electrode 7 is in ohmic contact with the p-type collector layer 16.

[0016] The semiconductor device 100 also has an n-type drift layer 1 in the diode region 20. The n-type drift layer 1 in the diode region 20 and the n-type drift layer 1 in the IGBT region 10 are continuously and integrally configured. In the diode region 20, the substrate ranges from the p+ type contact layer 24 to the n+ type cathode layer 26. A p-type anode layer 25 and a p+ type contact layer 24 are provided on the upper surface side of the n- type drift layer 1. The p+ type contact layer 24 and the p-type anode layer 25 may be collectively referred to as a p-type anode layer.

[0017] In the diode region 20, an n+ type cathode layer 26 is provided on the back surface side of the n-type buffer layer 3. The n+ type cathode layer 26 constitutes the back surface of the substrate. In the diode region 20, the front surface electrode 6 serves as an anode electrode, and the back surface electrode 7 serves as a cathode electrode.

[0018] The diode region 20 has a first portion 20a formed thinner than the IGBT region 10 by recessing the upper surface of the substrate. The diode region 20 further has a second portion 20b provided on one side of the first portion 20a and thicker than the first portion 20a, and a third portion 20c provided on the other side of the first portion 20a and thicker than the first portion 20a. The second portion 20b is adjacent to the IGBT region 10.

[0019] The p-type anode layer 25 has a portion 25a provided along the upper surface of the first portion 20a. The p-type anode layer 25 also has portions 25b and 25c provided along the side surfaces of the substrate connecting the first portion 20a to the second portion 20b and the third portion 20c.

[0020] In this embodiment, there are a plurality of planes in the diode region 20 where the front surface electrode 6 and the p-type anode layer 25 are in contact with each other. The depth of the first portion 20a is arbitrary and selectable. The depth of the first portion 20a can be changed by the mask pattern and etching conditions in the mask process. It is also possible to adjust the depth of the first portion 20a by changing the width of the mask pattern.

[0021] In this embodiment, the diode region 20 has a thin portion and a thick portion. At this time, the p-type anode layer 25 can be distributed widely in the depth direction. This makes it easy to adjust the concentration of each portion of the p-type anode layer 25. By adjusting the depth and concentration of the p-type anode layer 25, the amount of holes injected from the p-type anode layer 25 can be adjusted. This makes it possible to adjust the on-voltage and recovery characteristics during forward operation. Therefore, in this embodiment, it is easy to adjust the characteristics.

[0022] Furthermore, if the silicon thickness is thin over the entire diode region, breakdown may occur more easily in the boundary region between the IGBT region and the diode region or in regions where current concentrates. The current concentrates in the center of the diode region or directly under the wire, for example. Furthermore, chip cracking may occur. Furthermore, a step may form over a wide area between the IGBT region and the diode region, making manufacturing difficult.

[0023] In contrast, in this embodiment, the thin region of the substrate can be limited. This makes it possible to suppress the amount of wafer warpage. Also, it is possible to suppress destruction or chip cracking due to current concentration, thereby improving the yield. Furthermore, by limiting the step portion, it is possible to avoid defocusing during photolithography mask processing, and to reduce residues after etching. This makes it easier to manufacture the semiconductor device 100. As described above, in this embodiment, it is possible to realize easier characteristic adjustment, improved destruction resistance, and easier manufacturing processes.

[0024] 1, the upper surface of the second portion 20b and the upper surface of the IGBT region 10 may form the same plane. If a step exists in the boundary region between the IGBT region 10 and the diode region 20, the electric field may become locally high at the step. In this case, the breakdown voltage may decrease, and breakdown may easily occur during switching operation and recovery operation. If there is no step in the boundary between the IGBT region 10 and the diode region 20, electric field concentration can be suppressed and the withstand capacity during reverse bias can be improved.

[0025] In the example of FIG. 1, an interlayer insulating film 4 is formed on the upper surface of the second portion 20b. The second portion 20b may be in contact with the surface electrode 6. Also, instead of the p+ type contact layer 24, a p-type anode layer 25 may be formed. In this case, a concentration gradient may be provided in the p-type anode layer 25 adjacent to the IGBT region 10. It is preferable that the concentration of the p-type anode layer 25 decreases toward the IGBT region. Also, a trench at the boundary between the IGBT region 10 and the diode region 20 may not be provided.

[0026] Furthermore, the p-type collector layer 16 provided on the back surface side of the substrate in the IGBT region 10 may protrude into the diode region 20. That is, the back surface side of the portion of the diode region 20 adjacent to the IGBT region may be the p-type collector layer 16.

[0027] If the back surface structure of the boundary region adjacent to the IGBT region 10 is an n+ type cathode layer 26, carriers may easily accumulate in the boundary region during forward operation of the diode. This may make it easier for breakdown to occur during recovery operation. In addition, when the IGBT is on, electrons flow into the n+ type cathode layer 26, making it difficult for holes to be injected from the p type collector layer 16, and there is a possibility that a snapback phenomenon will occur in which the IGBT does not turn on. By extending the p type collector layer 16 into the diode region, such interference between carriers of the IGBT and the diode can be suppressed.

[0028] The amount of overflow U1 of the p-type collector layer 16 into the diode region 20 is, for example, the same as the wafer thickness. In general, current flows within an angular range of 45°. Therefore, if the amount of overflow U1 is set to a distance equal to the wafer thickness, current interference can be suppressed. This is not limiting, and the amount of overflow U1 can be set arbitrarily. The p-type collector layer 16 and the p-type anode layer 25 may or may not overlap in a plan view.

[0029] The portions 25a, 25b, and 25c of the p-type anode layer 25 may have different concentrations. The p-type anode layer 25 may have a concentration gradient depending on the depth.

[0030] 2 is a cross-sectional view of a semiconductor device 200 according to a modification of the first embodiment. In the p-type anode layer 25, the portions 25a, 25b, and 25c may be separated from each other. In other words, an anode may be formed for each of a plurality of planes where the front surface electrode 6 and the p-type anode layer 25 are in contact with each other. An anode can be formed for each of the planes by setting a mask pattern in a mask process or by implanting after an etching process.

[0031] In the present embodiment, the height of the diode region 20 is two steps, but the invention is not limited to this and the height of the diode region 20 may be three or more steps.

[0032] In the diode region 20, the first portion 20a may be provided at only one location, or may be provided at multiple locations. Any shape can be adopted as the pattern of the first portion 20a in a plan view. The pattern of the first portion 20a in a plan view may be a stripe type, an island type, or a circle. The shape of the first portion 20a can be appropriately changed by a mask pattern during mask processing. In addition, the diode region 20 only needs to have the first portion 20a and a second portion or a third portion provided on one side of the first portion 20a. In other words, the portion of the diode region 20 that is thicker than the first portion 20a only needs to be provided on at least one side of the first portion 20a.

[0033] 1, the first portion 20a is dug down to a depth equivalent to that of the active trench gate 11. The depth of the first portion 20a is not limited to this. By digging the first portion 20a down to a depth lower than the active trench gate 11, it is possible to further suppress loss. Furthermore, by making the top surface of the first portion 20a equivalent to the bottom of the active trench gate 11, it is possible to suppress an increase in manufacturing costs due to a thin substrate.

[0034] In the semiconductor device 100, the substrate may be made of a wide band gap semiconductor. The wide band gap semiconductor is silicon carbide, a gallium nitride material, or diamond. According to the present embodiment, by appropriately adjusting the characteristics, a high current can be stably passed through the substrate made of the wide band gap semiconductor.

[0035] These modifications can be appropriately applied to the semiconductor device according to the following embodiments. Note that the semiconductor device according to the following embodiments has many points in common with the first embodiment, so the following description will focus on the differences from the first embodiment.

[0036] Embodiment 2 3 is a cross-sectional view of a semiconductor device 300 according to a second embodiment. The semiconductor device 300 differs from the semiconductor device 100 in the structure of the first portion 20a. The other configurations are the same as those of the semiconductor device 100. The first portion 20a of the semiconductor device 300 has a p-type anode layer 25 and a Schottky contact layer 40 in the uppermost layer. The Schottky contact layer 40 may be doped with n-type P (phosphorus).

[0037] In the first portion 20a, the n-type drift layer 1 is thin, so that current tends to concentrate. In the first portion 20a, by forming a part of the p-type anode layer 25 as the Schottky contact layer 40, the amount of holes injected during forward operation can be suppressed. This can reduce loss during recovery. In addition, by changing the patterns of the p-type anode layer 25 and the Schottky contact layer 40, the trade-off between the forward on-voltage and the recovery loss can be adjusted. In addition, the width, concentration, or depth of the p-type anode layer 25 may be adjusted so that the depletion layer during reverse bias extends from the p-type anode layer 25 to cover the Schottky contact layer 40. This can suppress leakage current.

[0038] There is no particular limitation on the area ratio between the p-type anode layer 25 and the Schottky contact layer 40. The pattern of the p-type anode layer 25 and the Schottky contact layer 40 in plan view may be a stripe type, an island type, a honeycomb structure, or a circle.

[0039] Embodiment 3 4 is a cross-sectional view of a semiconductor device 400 according to a third embodiment. The semiconductor device 400 differs from the semiconductor device 100 in the structure of the diode region 20. The other configurations are the same as those of the semiconductor device 100. In the semiconductor device 400, the first portion 20a has a p-type anode layer 25 in the uppermost layer, and the third portion 20c has a Schottky contact layer 40 in the uppermost layer.

[0040] In general, the Schottky contact layer 40 has a large leakage current when reverse biased. 2 As described above, the pattern shape may be restricted in order to block the leakage current with the depletion layer extending from the p-type anode layer 25. In this embodiment, the upper surface of the first portion 20a is the p-type anode layer 25, and the upper surface of the second portion 20b or the third portion 20c is the Schottky contact layer 40, so that the depletion layer easily covers the Schottky contact layer 40 when reverse bias is applied. Therefore, the leakage current can be reduced.

[0041] The area ratio of the p-type anode layer 25 and the Schottky contact layer 40 is arbitrary. The pattern of the p-type anode layer 25 and the Schottky contact layer 40 in a plan view may be a stripe type, an island type, a honeycomb structure, or a circle. In addition, the side surface of the substrate connecting the first portion 20a and the second portion 20b or the third portion 20c may be the p-type anode layer 25 or the Schottky contact layer 40.

[0042] Embodiment 4 5 is a cross-sectional view of a semiconductor device 500 according to embodiment 4. In the semiconductor device 500, the side surfaces of the substrate connecting the first portion 20a to the second portion 20b and the third portion 20c are covered with an oxide film 42. The other structures are the same as those of the semiconductor device 400.

[0043] The oxide film 42 may have any thickness. The oxide film 42 may be formed by, for example, thermal oxidation or C VDThe oxide film 42 is formed by chemical vapor deposition (Chemical Vapor Deposition). After the CVD process, anisotropic etching can be performed to leave the oxide film 42 only on the side of the substrate. The oxide film 42 may have a composite film structure. In the composite film structure, for example, an oxide film, polysilicon, and an oxide film are laminated.

[0044] In this embodiment, the step portion of the substrate is covered with the oxide film 42. Therefore, no current flows through the step portion, and the breakdown resistance during recovery can be improved.

[0045] 5, the entire step is covered with oxide film 42. However, it is not limited thereto, as long as at least a portion of the side surface of the substrate connecting first portion 20a to second portion 20b and third portion 20c is covered with oxide film 42. For example, only the upper corner or lower corner of the side surface of the substrate may be covered with oxide film 42. In this case as well, current concentration at the corner can be suppressed, and breakdown resistance during recovery can be improved.

[0046] Embodiment 5. 6 is a cross-sectional view of a semiconductor device 600 according to a fifth embodiment. In the semiconductor device 600, the side surface of the substrate connecting the first portion 20a and the second portion 20b is formed from an outwardly convex curved surface. The other configurations are the same as those of the semiconductor device 100. The shape of such a step portion can be formed by, for example, isotropic etching. Also, the etching depth can be adjusted by changing the thinness of the mask pattern depending on the position.

[0047] In this embodiment, the thickness of the p-type anode layer 25 can be made more uniform than in the first embodiment. In particular, the p-type anode layer 25 can be prevented from becoming thin at the corners below the steps between the first portion 20a and the second portion 20b and the third portion 20c. This can prevent a decrease in breakdown voltage due to punch-through. In addition, current concentration at the corners during recovery can be prevented, improving the RRSOA (Reverse Recovery Safe Operation Area).

[0048] The curvature of the side surface of the substrate is arbitrary. The larger the curvature of the side surface of the substrate is set, the more the p-type anode layer 25 can be prevented from becoming thin at the corners. A sufficient effect can be obtained if the curvature of the side surface of the substrate is equal to or greater than the curvature of the p-type anode layer 25.

[0049] Embodiment 6 Fig. 7 is a cross-sectional view of a semiconductor device 700 according to a sixth embodiment. The diode region 20 has an n+ type cathode layer 26 on the back surface side of the substrate. In the semiconductor device 700, the n+ type cathode layer 26 is thinned out. Note that, although the structure of the second embodiment is adopted as the structure of the upper surface side of the substrate in Fig. 7, the structure of the other embodiments may be adopted.

[0050] Next, a method for forming such an n+ type cathode layer 26 will be described. First, the entire back surface of the substrate is implanted to form the p-type collector layer 16. Next, the n+ type cathode layer 26 is formed by selectively implanting using a mask pattern. The implantation amount of the n+ type cathode layer 26 is set to be larger than that of the p-type collector layer 16. Furthermore, recrystallization is performed by laser annealing. Due to the difference in concentration, the p-type collector layer 16 is canceled out in the region implanted as the n+ type cathode layer 26. This allows the formation of a pattern of the p-type collector layer 16 and the n+ type cathode layer 26. The pattern in plan view may be a stripe type, an island type, or a circle.

[0051] By thinning out the n+ type cathode layer 26, the injection of electrons from the n+ type cathode layer 26 is suppressed. Therefore, the tail current during recovery can be reduced. In addition, by changing the pattern ratio of the p-type collector layer 16 and the n+ type cathode layer 26, the trade-off between the forward on-state voltage and the recovery loss can be adjusted.

[0052] The n+ type cathode layer 26 may be thinned out more toward the IGBT region 10. In this case, the thinning rate may be inclined toward the IGBT region 10. The n+ type cathode layer 26 may be thinned out largely only in the boundary region with the IGBT region 10. This makes it possible to reduce the carrier concentration on the back surface of the substrate on the IGBT region 10 side. This makes it possible to suppress the recovery current from concentrating at the corners of the steps in the diode region 20. This makes it possible to improve the RRSOA.

[0053] Embodiment 7 8 is a cross-sectional view of a semiconductor device 800 according to the seventh embodiment. In this embodiment, the structure of the n+ type cathode layer 26 is different from that of the sixth embodiment. In the semiconductor device 800, the n+ type cathode layer 26 is provided so as to avoid being located directly below the p-type anode layer 25 of the first portion 20a. Note that, although the structure of the third embodiment is adopted as the structure of the upper surface side of the substrate in FIG. 8, the structure of the other embodiments may be adopted.

[0054] If the n+ type cathode layer 26 is present under the p-type anode layer 25 of the first portion 20a close to the back surface of the substrate, the conductivity modulation effect due to holes injected from the p-type anode layer 25 and electrons injected from the n+ type cathode layer 26 will be large. This may result in large recovery loss. In this embodiment, the n+ type cathode layer 26 is not formed directly under the portion of the p-type anode layer 25 closest to the back surface. This makes it possible to reduce recovery loss.

[0055] In this embodiment, the back-side-most portion of p-type anode layer 25, n-type drift layer 1, and p-type collector layer 16 form a pnp structure. When the voltage rises during recovery operation, this pnp transistor operates to suppress the surge voltage.

[0056] The technical features described in each embodiment may be used in appropriate combination. [Explanation of symbols]

[0057] 1 n-type drift layer, 2 n-type carrier accumulation layer, 3 n-type buffer layer, 4 interlayer insulating film, 5 barrier metal, 6 front electrode, 7 rear electrode, 10 IGBT region, 11 active trench gate, 11a gate trench electrode, 11b gate trench insulating film, 12 dummy trench gate, 12a dummy trench electrode, 12b dummy trench insulating film, 13 n+ Mold source layer, 14 p+ 15 p-type base layer, 16 p-type collector layer, 20 diode region, 20a first portion, 20b second portion, 20c third portion, 24 p+ type contact layer, 25 p-type anode layer, 25a portion, 25b portion, 26 n+ type cathode layer, 40 Schottky contact layer, 42 oxide film, 100, 200, 300, 400, 500, 600, 700, 800 semiconductor device

Claims

1. the substrate having an IGBT region and a diode region adjacent to the IGBT region in a direction along an upper surface of the substrate; a surface electrode provided on an upper surface of the substrate; a back surface electrode provided on a back surface opposite to the top surface of the substrate; Equipped with a diode region having a first portion formed thinner than the IGBT region by recessing an upper surface of the substrate, a second portion provided on one side of the first portion and thicker than the first portion, and a third portion provided on the other side of the first portion and thicker than the first portion.

2. 2 . The semiconductor device according to claim 1 , wherein the anode layer of the diode region is provided along an upper surface of the first portion and a side surface of the substrate connecting the first portion and the second portion.

3. a substrate having an IGBT region and a diode region; a surface electrode provided on an upper surface of the substrate; a back surface electrode provided on a back surface opposite to the top surface of the substrate; Equipped with the diode region has a first portion formed by recessing an upper surface of the substrate so as to be thinner than the IGBT region, and a second portion provided on one side of the first portion and thicker than the first portion, an anode layer of the diode region is provided along an upper surface of the first portion and a side surface of the substrate connecting the first portion and the second portion; a portion of the anode layer provided along a top surface of the first portion and a portion of the anode layer provided along a side surface of the substrate connecting the first portion and the second portion, the portion being separated from the top surface of the anode layer;

4. the second portion is adjacent to the IGBT region, 4. The semiconductor device according to claim 1, wherein an upper surface of the second portion and an upper surface of the IGBT region form the same plane.

5. the IGBT region has a collector layer on the back surface side of the substrate; 5. The semiconductor device according to claim 1, wherein the collector layer protrudes into the diode region.

6. a substrate having an IGBT region and a diode region; a surface electrode provided on an upper surface of the substrate; a back surface electrode provided on a back surface opposite to the top surface of the substrate; Equipped with the diode region has a first portion formed by recessing an upper surface of the substrate so as to be thinner than the IGBT region, and a second portion provided on one side of the first portion and thicker than the first portion, The first portion has an anode layer and a Schottky contact layer on the uppermost layer.

7. a substrate having an IGBT region and a diode region; a surface electrode provided on an upper surface of the substrate; a back surface electrode provided on a back surface opposite to the top surface of the substrate; Equipped with the diode region has a first portion formed by recessing an upper surface of the substrate so as to be thinner than the IGBT region, and a second portion provided on one side of the first portion and thicker than the first portion, The first portion has an anode layer on an uppermost layer, The second portion has a Schottky contact layer on the uppermost layer.

8. 8. The semiconductor device according to claim 1, wherein at least a part of a side surface of the substrate connecting the first portion and the second portion is covered with an oxide film.

9. a substrate having an IGBT region and a diode region; a surface electrode provided on an upper surface of the substrate; a back surface electrode provided on a back surface opposite to the top surface of the substrate; Equipped with the diode region has a first portion formed by recessing an upper surface of the substrate so as to be thinner than the IGBT region, and a second portion provided on one side of the first portion and thicker than the first portion, A semiconductor device, characterized in that a side surface of the substrate connecting the first portion and the second portion is formed as an outwardly convex curved surface.

10. the diode region has a cathode layer on a back surface side of the substrate; 10. The semiconductor device according to claim 1, wherein the cathode layer is thinned out.

11. 11. The semiconductor device according to claim 10, wherein the cathode layer is thinned out more toward the IGBT region side.

12. a substrate having an IGBT region and a diode region; a surface electrode provided on an upper surface of the substrate; a back surface electrode provided on a back surface opposite to the top surface of the substrate; Equipped with the diode region has a first portion formed by recessing an upper surface of the substrate so as to be thinner than the IGBT region, and a second portion provided on one side of the first portion and thicker than the first portion, the diode region has a cathode layer on a back surface side of the substrate; The semiconductor device according to claim 1, wherein the cathode layer is provided so as to avoid being directly below the anode layer of the first portion.

13. 13. The semiconductor device according to claim 1, wherein the substrate is made of a wide band gap semiconductor.

14. 14. The semiconductor device according to claim 13, wherein the wide band gap semiconductor is silicon carbide, a gallium nitride-based material or diamond.

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