Semiconductor Device

Abstract

To improve a performance of a semiconductor device.SOLUTION: A silicon carbide power semiconductor device 10 contains a semiconductor material having a hand gap larger than that of a silicon as a main component. In addition, the silicon carbide power semiconductor device 10 comprises: a plurality of trenches TR1; a plurality of guard regions 21 that covers a bottom part of the plurality of trenches TR1; and a JFET region 16 which is in contact with the plurality of guard regions 21.Then, the silicon carbide power semiconductor device 10 includes a plurality of unit cells CL. At that time, each of the plurality of unit cells CL includes: a plurality of trenches TR1 arranged in an x direction; and a plurality of trenches TR1 arranged in a y direction crossed to the x direction. Then, in a plan view, the plurality of trenches TR1 arranged in the x direction and the plurality of trenches TR1 arranged in the y direction are included in a single guard region 21 of the plurality of guard regions 21.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a technique that is effective when applied to a semiconductor device including a field effect transistor formed on a semiconductor substrate whose main component is a semiconductor material having a band gap larger than that of silicon. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2015-72999 (Patent Document 1) describes a technology related to a semiconductor device having an n-type substrate made of silicon carbide, a drift layer formed on the n-type substrate, a plurality of stripe-shaped trenches formed on the drift layer, a gate electrode formed in each of the plurality of trenches via an insulating film, and an n-type current spreading layer formed on the drift layer and having a higher impurity concentration than the drift layer. In this technology, the bottom of the trench is covered with a p-type bottom layer.

[0003] JP 2021-12934 A (Patent Document 2) describes a structure based on the structure described in the above-mentioned Patent Document 1, in which the channel is oriented vertically to reduce the cell pitch and the bottom of the trench is covered with a p-type bottom layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-72999 A [Patent Document 2] Patent Publication No. 2021-12934 Summary of the Invention [Problem to be solved by the invention]

[0005] Power semiconductor devices are required to have, for example, low on-resistance and low switching loss in addition to high breakdown voltage. Currently, the mainstream of power semiconductor devices is a field effect transistor formed on a semiconductor substrate mainly made of silicon, but this power semiconductor device is approaching its theoretical performance limit.

[0006] In this regard, a semiconductor device including a field effect transistor formed on a semiconductor substrate whose main component is a semiconductor material having a band gap larger than that of silicon (hereinafter referred to as a wide band gap power semiconductor device) has attracted attention.

[0007] This is because a large band gap means that the material has high dielectric breakdown strength, making it easier to achieve high withstand voltage.

[0008] Furthermore, if the semiconductor material itself has a high dielectric breakdown strength, the withstand voltage can be ensured even if the drift layer that maintains the withstand voltage is made thin. Therefore, for example, by making the drift layer thin and increasing the impurity concentration, the on-resistance of the power semiconductor device can be reduced.

[0009] In other words, the wide band gap power semiconductor device is superior in that it can achieve both improved breakdown voltage and reduced on-resistance, which are in a trade-off relationship with each other. For wide band gap power semiconductor elements having such advantages, it is desirable to achieve further performance improvements, and in particular, it is desirable to develop ideas from the viewpoint of reducing the on-resistance.

[0010] The term "main component" refers to the component that is contained in the greatest amount, and is used with the intention of allowing the inclusion of impurities and other components. Examples of semiconductor materials with a band gap larger than that of silicon include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. [Means for solving the problem]

[0011] A semiconductor device according to an embodiment includes, as a main component, a semiconductor material having a band gap larger than that of silicon. The semiconductor device includes a plurality of trenches, a plurality of guard regions covering bottoms of the plurality of trenches, and a JFET region in contact with the plurality of guard regions. Here, the semiconductor device has a plurality of unit cells. At this time, each of the plurality of unit cells includes a plurality of first trenches aligned in a first direction and a plurality of second trenches aligned in a second direction intersecting the first direction. In a plan view, the plurality of first trenches and the plurality of second trenches are contained within a single guard region among the plurality of guard regions. Effect of the Invention

[0012] According to one embodiment, the performance of a semiconductor device can be improved. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a plan view showing a silicon carbide power semiconductor device according to a related art. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Diagram 3] 1 is a plan view showing a silicon carbide power semiconductor device in an embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA in FIG. [Diagram 5] 1A is a schematic diagram showing two stripe-shaped trenches arranged side by side in the related art shown in FIG. 1, and FIG. 1B is a schematic diagram showing a plurality of trenches arranged in a two-dimensional array in the embodiment shown in FIG. 3. [Figure 6] 4(a) is a part of a plan view sliced ​​along line BB in FIG. 2 showing a related art, and FIG. 4(b) is a plan view showing two plan views sliced ​​along line BB in FIG. 4 showing an embodiment, arranged side by side. [Figure 7] 1 is a graph showing the relationship between the length of a JFET region and the resistance value of the JFET region. [Figure 8] FIG. 11 is a plan view showing a silicon carbide power semiconductor device in a first modification. [Figure 9] FIG. 11 is a plan view showing a silicon carbide power semiconductor device in Modification 2. [Figure 10] FIG. 11 is a plan view showing a silicon carbide power semiconductor device in a third modification. [Figure 11] FIG. 13 is a plan view showing a silicon carbide power semiconductor device in a fourth modification. [Figure 12] FIG. 13 is a plan view showing a unit cell in Modification 5. [Figure 13] FIG. 13 is a plan view showing a unit cell in Modification 6. [Figure 14] FIG. 1A is a first configuration diagram for arranging unit cells, and FIG. 1B is a second configuration diagram for arranging unit cells. [Figure 15] 1 is a flowchart illustrating a method for manufacturing a silicon carbide power semiconductor device. [Figure 16] 1A to 1C are cross-sectional views showing a manufacturing process of a silicon carbide power semiconductor device. [Figure 17] 17 is a cross-sectional view showing a manufacturing process of the silicon carbide power semiconductor device continued from FIG. 16. [Figure 18] 18 is a cross-sectional view showing a manufacturing process of the silicon carbide power semiconductor device subsequent to FIG. 17. [Figure 19] 19 is a cross-sectional view showing a manufacturing process of the silicon carbide power semiconductor device subsequent to FIG. 18. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In all the drawings for explaining the embodiments, the same members are generally designated by the same reference numerals, and the repeated explanations thereof will be omitted. In addition, hatching may be applied even to plan views in order to make the drawings easier to understand.

[0015] The technical idea of ​​this embodiment is a technical idea related to a wide bandgap power semiconductor device using a semiconductor material with a bandgap larger than that of silicon. Examples of semiconductor materials with a bandgap larger than that of silicon include compound semiconductors such as silicon carbide (SiC) and gallium nitride (GaN). However, the technical idea of ​​this embodiment is not limited to these, and can be widely applied to wide bandgap power semiconductor devices using semiconductor materials with a bandgap larger than that of silicon.

[0016] In the following, a wide band gap power semiconductor device using silicon carbide will be described as an example of a wide band gap power semiconductor device.

[0017] Silicon carbide has a dielectric breakdown field strength about one order of magnitude greater than that of silicon, so by thinning the drift layer for ensuring the breakdown voltage to about one-tenth the thickness and increasing the impurity concentration by about 100 times, the on-resistance (element resistance) can theoretically be reduced by three orders of magnitude or more. In addition, since the band gap is about three times larger than that of silicon, high-temperature operation is also possible, and wide band gap power semiconductor devices using silicon carbide (hereinafter referred to as silicon carbide power semiconductor devices) are expected to achieve performance that exceeds that of silicon power semiconductor devices.

[0018] Silicon carbide has a larger band gap and a higher dielectric breakdown field strength than silicon, but the electric field strength applied to the insulating film is a problem. Therefore, in the device design of a silicon carbide power semiconductor device, the electric field strength applied to the insulating film must be fully considered. In particular, in a device structure having a gate insulating film such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), if the electric field strength applied to the gate insulating film becomes high, a leakage current occurs in the gate insulating film, which leads to a reduction in the life of the gate insulating film and device malfunction due to dielectric breakdown of the gate insulating film.

[0019] Therefore, technology to improve the breakdown voltage of the gate insulating film by improving the manufacturing process of the gate insulating film and technology to reduce the electric field strength applied to the gate insulating film are becoming important. In particular, in the trench gate structure commonly used in MOSFETs and IGBTs, electric field concentration is likely to occur at the bottom of the trench. In this regard, it is effective to cover the bottom of the trench with a p-type semiconductor layer to reduce the electric field concentration at the bottom of the trench, and the related technology shown below is available.

[0020] <Description of Related Art> The term "related art" as used herein refers to art that is not publicly known, but has problems that the inventors have found, and is a technology that serves as a premise for the present invention.

[0021] FIG. 1 is a plan view showing a silicon carbide power semiconductor device 100 according to the related art.

[0022] As shown in Fig. 1, a silicon carbide power semiconductor device 100 has a plurality of trenches TR. The plurality of trenches TR are arranged in a plurality of rows aligned in the x direction. In each of the plurality of rows, a plurality of stripe-shaped trenches TR extending in the x direction are arranged along the y direction. In each of the plurality of trenches TR, a gate electrode 102 is embedded via a gate insulating film 101.

[0023] FIG. 2 is a cross-sectional view taken along line AA in FIG.

[0024] 2, silicon carbide power semiconductor device 100 has a substrate 103 made of silicon carbide doped with donors (n-type impurities) such as nitrogen (N) or phosphorus (P). A drain electrode 104 made of a metal material such as nickel (Ni) or aluminum (Al) is formed on the back surface of substrate 103. Meanwhile, an epitaxial layer 105 made of silicon carbide doped with n-type impurities is formed on substrate 103. This epitaxial layer 105 is also called a drift layer.

[0025] A source region 106, which is an n-type semiconductor region, is formed on the surface of the epitaxial layer 105, and a body region 107, which is a p-type semiconductor region, is formed in contact with the source region 106. The p-type semiconductor region constituting the body region 107 is formed by introducing aluminum or boron, which is an acceptor (p-type impurity), into silicon carbide. The body region 107 is connected to a guard region 108, which is a p-type semiconductor region.

[0026] Next, a plurality of trenches TR are formed so as to penetrate the source region 106 and the body region 107 and reach the guard region 108. Therefore, the bottom of each of the plurality of trenches TR is covered with the guard region 108 electrically connected to the body region 107. A gate electrode 102 is embedded in each of the plurality of trenches TR via a gate insulating film 101. The gate electrode 102 is formed of, for example, a polysilicon film. Next, an interlayer insulating film 109 made of, for example, a silicon oxide film is formed so as to cover the gate electrode 102, and a source electrode 110 is formed on the interlayer insulating film 109. The source electrode 110 is electrically connected to the source region 106 and also to the body region 107.

[0027] In this manner, the related art silicon carbide power semiconductor device 100 is configured. According to this silicon carbide power semiconductor device 100, the bottom of the trench TR is covered with the guard region 108 electrically connected to the body region 107, and therefore, an advantage is obtained that electric field concentration that becomes apparent at the corners of the trench TR can be suppressed.

[0028] This is because, for example, the body region 107 is electrically connected to the source electrode 110 to which a ground potential (0V) is supplied, and the body region 107 is electrically connected to the guard region 108. Therefore, the ground potential is applied to the guard region 108. This means that a high voltage is not applied to the bottom of the trench TR covered with the guard region 108. As a result, it is possible to suppress the occurrence of electric field concentration due to a high potential at the corners of the bottom of the trench TR. In this way, according to the related technology, the electric field strength applied to the gate insulating film 101 formed on the inner wall of the trench TR can be alleviated, and as a result, device malfunctions due to dielectric breakdown of the gate insulating film 101 can be suppressed.

[0029] Here, further improvements in the performance of silicon carbide power semiconductor device 100 have been studied. Specifically, in Fig. 2, shrinking the trench interval L1 between adjacent trenches TR has been studied to reduce the on-resistance of silicon carbide power semiconductor device 100. However, as shown in Fig. 2, shrinking the trench interval L1 inevitably means that the JFET length L2 is also shortened.

[0030] The shortening of the JFET length L2 means that it becomes difficult for a current to flow through the path of drain electrode 104 → substrate 103 → epitaxial layer 105 → JFET region (region of JFET length L2) → channel (inversion layer formed in body region 107) → source region 106 → source electrode 110. In other words, the shortening of the JFET length L2 means that the on-resistance of silicon carbide power semiconductor device 100 becomes higher.

[0031] That is, in the related art, when the trench interval L1 between the adjacent trenches TR is shrunk in order to reduce the on-resistance of the silicon carbide power semiconductor device 100, the JFET length L2 is also shortened, and as a result, the effect of reducing the on-resistance is limited. Therefore, the related art has room for improvement in terms of sufficiently reducing the on-resistance.

[0032] In the present embodiment, therefore, some improvements have been made to address the room for improvement in the related art. The technical concept of this embodiment that incorporates these improvements will be described below.

[0033] <Configuration of Silicon Carbide Power Semiconductor Device> FIG. 3 is a plan view showing silicon carbide power semiconductor device 10 in the present embodiment.

[0034] In Fig. 3, the silicon carbide power semiconductor device 10 has a plurality of trenches TR1. The plurality of trenches TR1 are arranged in a plurality of rows aligned in the x direction, and in each of the plurality of rows, the plurality of trenches TR1 are arranged to be aligned in each of the x direction and the y direction. That is, in each of the plurality of rows, the plurality of trenches TR1 are arranged in a two-dimensional array (matrix). In other words, in each of the plurality of rows, the plurality of trenches TR1 are arranged in a dot shape. A gate electrode 12 is embedded in each of the plurality of trenches TR1 via a gate insulating film 11.

[0035] For example, as shown in FIG. 3, one trench TR1 among the multiple trenches TR1 aligned in the x direction and one trench TR1 among the multiple trenches TR1 aligned in the y direction can be arranged to be a common trench TR1.

[0036] In the silicon carbide power semiconductor device 10, the four side surfaces of the trench TR1 function as a channel, so that the gate width can be increased, which has the advantage that a channel current can flow with a low on-resistance.

[0037] FIG. 4 is a cross-sectional view taken along line AA in FIG.

[0038] 4, silicon carbide power semiconductor device 10 has a substrate 13 made of silicon carbide doped with donors (n-type impurities) such as nitrogen (N) or phosphorus (P). A drain electrode 14 made of a metal material such as nickel (Ni) or aluminum (Al) is formed on the back surface of substrate 13. Meanwhile, an epitaxial layer 15 made of silicon carbide doped with n-type impurities is formed on substrate 13.

[0039] A source region 18, which is an n-type semiconductor region, is formed on the surface of the epitaxial layer 15, and a body region 19, which is a p-type semiconductor region, is formed so as to be in contact with the source region 18. The p-type semiconductor region constituting the body region 19 is formed by introducing aluminum or boron, which is an acceptor (p-type impurity), into silicon carbide. The body region 19 is connected to a guard region 21, which is a p-type semiconductor region, via a connection region 20, which is a p-type semiconductor region. In addition, a potential fixing region 22, which is electrically connected to the connection region 20, is formed on the connection region 20.

[0040] Next, a current diffusion region 17, which is an n-type semiconductor region, is formed below the body region 19, and a JFET region 16, which is an n-type semiconductor region, is formed in the region sandwiched between this current diffusion region 17 and the epitaxial layer 15 (the region sandwiched between the dotted lines in Figure 2).

[0041] Next, a plurality of trenches TR1 are formed so as to penetrate through the source region 18, the body region 19, and the current diffusion region 17 and reach the guard region 21. Therefore, the bottom of each of the plurality of trenches TR1 is covered with the guard region 21 electrically connected to the body region 19. A gate electrode 12 is embedded in each of the plurality of trenches TR via a gate insulating film 11. The gate electrode 12 is formed of, for example, a polysilicon film. Next, an interlayer insulating film 23 made of, for example, a silicon oxide film is formed so as to cover the gate electrode 12, and a source electrode 24 is formed on the interlayer insulating film 23. The source electrode 24 is electrically connected to the source region 18 and also electrically connected to the potential fixing region 22.

[0042] In this manner, silicon carbide power semiconductor device 10 is constructed.

[0043] The relative impurity concentrations of each semiconductor region will be described below.

[0044] In the following explanation, "n-type" is written as " - "or" + " are used to indicate the relative impurity concentration. For example, in the case of n-type, the order of "n-", "n", "n+" and "n++" indicates the increasing concentration of n-type impurities. The notation for "p-type" is the same as for "n-type". (1) "Epitaxial layer 15" → "n - "Type Semiconductor Region" (2) “JFET area 16” → “n - Type semiconductor region ~n + "Type Semiconductor Region" (3) "Current diffusion region 17" → "n + "Type Semiconductor Region" (4) "Source region 18" → "n ++ "Type Semiconductor Region" (5) "Body region 19" → "p-type semiconductor region" (6) "Connection region 20" → "p-type semiconductor region" (7) "Guard region 21" → "p-type semiconductor region" (8) “Potential fixing region 22” → “p ++ "Type Semiconductor Region" Next, the main function of each semiconductor region will be described.

[0045] The source region 18 is electrically connected to the source electrode 24. The source region 18 and the source electrode 24 are in ohmic contact with each other and the on-resistance is reduced. ++ The body region 19 is a semiconductor region for forming a channel, which is an inversion layer, in a region in contact with the side surface of the trench TR1 when a gate voltage equal to or higher than a threshold voltage is applied to the gate electrode 12 embedded in the trench TR1.

[0046] The connection region 20 is a region that electrically connects the body region 19 and the guard region 21, and this connection region 20 is electrically connected to a potential clamping region 22. Although not shown in FIG. 4, the potential clamping region 22 is electrically connected to a source electrode 24 together with the source region 18. In order to make the contact between the source electrode 24 and the potential clamping region 22 an ohmic contact, the potential clamping region 22 is made of p ++ As a result, the potential fixing region 22, the body region 19, the connection region 20 and the guard region 21 are electrically connected to each other, and a ground potential (0 V) supplied from the source electrode 24 is applied to the potential fixing region 22, the body region 19, the connection region 20 and the guard region 21.

[0047] The current diffusion region 17 is a semiconductor region through which an on-current flows. In order to reduce the on-resistance, the current diffusion region 17 is made of an n +The JFET region 16 is formed in a region sandwiched between a pair of guard regions 21 adjacent to each other, and when the silicon carbide power semiconductor device 10 is turned off, 0V is applied to the guard region 21 while a positive voltage is applied to the JFET region 16, and a reverse bias voltage is applied to the guard region 21 and the JFET region 16. As a result, a depletion layer extends over the entire JFET region 16, and the entire JFET region 16 is depleted, thereby blocking a leak current and ensuring a breakdown voltage. In addition, the epitaxial layer 15 has a function of ensuring a breakdown voltage by extending a depletion layer into the epitaxial layer 15 when the silicon carbide power semiconductor device 10 is turned off.

[0048] <Operation of Silicon Carbide Power Semiconductor Device> Silicon carbide power semiconductor device 10 in the present embodiment is configured as described above, and its operation will be described below.

[0049] First, an on-operation will be described. When the silicon carbide power semiconductor device 10 is turned on, a gate voltage equal to or higher than a threshold voltage is applied to the gate electrode 12 embedded in the trench TR1 while a ground potential (0V) is applied to the source electrode 24 and a positive voltage (several hundred V) is applied to the drain electrode 14. Then, a channel made of an inversion layer is formed in the body region 19 contacting the four side surfaces of the trench TR1. As a result, an on-current flows through the drain electrode 14 → substrate 13 → epitaxial layer 15 → JFET region 16 → current diffusion region 17 → channel → source region 18 → source electrode 24.

[0050] At this time, since the bottom of the trench TR1 is covered with the guard region 21 to which the ground potential is supplied, the occurrence of electric field concentration at the corners at the bottom of the trench TR1 is suppressed, which makes it possible to suppress device malfunctions caused by dielectric breakdown of the gate insulating film 11 formed at the corners of the trench TR1.

[0051] Next, the off operation will be described. When silicon carbide power semiconductor device 10 is turned off, a gate voltage smaller than the threshold voltage is applied to gate electrode 12 embedded in trench TR1 while a ground potential (0V) is applied to source electrode 24 and a positive voltage (several hundred V) is applied to drain electrode 14. Then, the channel made of the inversion layer formed on the four side surfaces of trench TR1 disappears. As a result, the on current is cut off.

[0052] Here, during the off operation, a depletion layer extends across the epitaxial layer 15, the JFET region 16, and the current diffusion region 17, so that a withstand voltage can be ensured. In other words, even if a potential difference between the drain electrode 14 and the source electrode 24 and a surge voltage at the time of off are applied, the silicon carbide power semiconductor device 10 will not be destroyed. Furthermore, since the JFET region 16 sandwiched between a pair of guard regions 21 is completely depleted, the occurrence of a leak current can be effectively suppressed.

[0053] <Features of the embodiment> Next, features of this embodiment will be described.

[0054] The feature of this embodiment is the ingenuity for reducing the on-resistance of silicon carbide power semiconductor device 10, and includes the first and second feature points described below. Specifically, the technical idea underlying the first feature point is the idea of ​​reducing the on-resistance by increasing the gate width of the gate electrode. On the other hand, the technical idea underlying the second feature point is the idea of ​​enhancing the effect of reducing the on-resistance through an ingenuity for suppressing the reduction in the area of ​​the JFET region even if the interval between adjacent trenches is shrunk. This will be specifically described below.

[0055] A first feature of the present embodiment is that, as can be seen by comparing Fig. 1 with Fig. 3, trenches TR1 (see Fig. 3) arranged in a two-dimensional array (dot shape) are adopted instead of the stripe-shaped trenches TR (see Fig. 1). This makes it possible to increase the gate width of the gate electrode when the trench is shrunk, thereby reducing the on-resistance of the silicon carbide power semiconductor device.

[0056] FIG. 5 is a diagram illustrating how the gate width of the gate electrode embedded in the trench TR1 can be increased by employing trenches TR1 arranged in a two-dimensional array.

[0057] Fig. 5(a) is a schematic diagram showing two stripe-shaped trenches TR in the related art shown in Fig. 1 arranged side by side. In Fig. 5(a), the trench width of the trench TR in the x direction is "Lh", the trench width of the trench TR in the y direction is "Lv", and the trench interval between the two trenches TR is "Ls". In this case, considering that the four side surfaces of the trench TR become channels, the gate width W is expressed by the following formula 1. Gate width W=n×2(Lh+Lv) (Formula 1) Here, n is the number of trenches TR.

[0058] Next, Fig. 5(b) is a diagram illustrating a plurality of trenches TR1 arranged in a two-dimensional array in the present embodiment shown in Fig. 3. In Fig. 5(b), taking into consideration that the four side surfaces of the trench TR1 become channels, the gate width W is expressed by the following formula 2. Gate width W=2n×2{(Lh-Ls) / 2+Lv} =n×2(Lh+Lv)+n×2(Lv-Ls) (Formula 2)

[0059] As can be seen from the above-mentioned formulas 1 and 2, when Lv>Ls is satisfied, the gate width W of the trench TR1 in this embodiment is larger than that of the trench TR in the related art. Here, the case where Lv>Ls is satisfied is considered to be satisfied when the trench interval is shrunk in order to reduce the on-resistance. From this, when the trench interval is shrunk, the gate width W can be made larger according to the trench TR1 in this embodiment than that of the trench TR in the related art.

[0060] Therefore, according to the first characteristic point of the present embodiment, it is found that the gate width W can be increased, and as a result, the channel resistance is reduced, and thereby the on-resistance of the silicon carbide power semiconductor device 10 can be reduced.

[0061] Next, a second feature of this embodiment will be described.

[0062] FIG. 6(a) is a partial plan view taken along line BB in FIG. 2, showing the related art.

[0063] As shown in FIG. 6(a), when attempting to reduce the on-resistance of the silicon carbide power semiconductor device 100 by shrinking the spacing between trenches TR arranged in adjacent rows, the JFET length L2 of the dotted JFET region will inevitably become shorter.

[0064] As a result, in the related technology shown in FIG. 6(a), even if the spacing between trenches TR arranged in adjacent rows is shrunk, the JFET length L2 becomes shorter and it becomes difficult for on-current to pass through, so the effect of reducing the on-resistance is limited.

[0065] In contrast, FIG. 6(b) is a plan view showing two plan views, sliced ​​along line BB in FIG. 4, of this embodiment, arranged side by side.

[0066] As shown in FIG. 6(b), in this embodiment, a plurality of unit cells CL are arranged in one column. Specifically, as shown in FIG. 6(b), in the left column, unit cells CL1, CL2, and CL3 are arranged in the y direction. Similarly, in the right column, unit cells CL4, CL5, and CL6 are arranged in the y direction. Here, the "unit cell" in this embodiment refers to a configuration in which, for example, when focusing on unit cell CL1, the unit cell CL1 includes a plurality of trenches TR1 arranged in the x direction and a plurality of trenches TR1 arranged in the y direction, and the plurality of trenches TR1 arranged in the x direction and the plurality of trenches TR1 arranged in the y direction are included in a single guard region 21A among the plurality of guard regions 21 in a plan view, on the premise that the unit cell CL1 includes a plurality of trenches TR1 arranged in the x direction and a plurality of trenches TR1 arranged in the y direction. Similarly, when focusing on unit cell CL2 to unit cell CL3, for example, a "unit cell" refers to a configuration in which, assuming that the unit cell includes a plurality of trenches TR1 lined up in the x direction and a plurality of trenches TR1 lined up in the y direction, in a planar view, the plurality of trenches TR1 lined up in the x direction and the plurality of trenches TR1 lined up in the y direction are contained within a single guard region (21B, 21C) of the plurality of guard regions 21.

[0067] For example, in FIG. 6(b), the unit cell CL1 includes three trenches TR1 aligned in the x direction × three trenches TR1 aligned in the y direction = a total of nine trenches TR1, and these nine trenches TR1 are contained within a single guard region 21A.

[0068] The three unit cells CL1 to CL3 arranged in the left column are connected by a connection region 20. Similarly, the three unit cells CL4 to CL6 arranged in the right column are connected by a connection region 20.

[0069] Here, the unit cells CL (unit cells CL1 to CL6) are configured in a planar shape having at least a first side S1 and a second side S2 that intersect with each other in a planar view, and both the first side S1 and the second side S2 are in contact with the JFET region 16. As a result, in the silicon carbide power semiconductor device 10 shown in Fig. 6(b), the JFET region 16 includes a region RA. That is, in the silicon carbide power semiconductor device 10, for example, the JFET region 16 is formed in the region RA sandwiched between the unit cells CL adjacent to each other.

[0070] Thus, the second feature of this embodiment is that, for example, as shown in FIG. 6(b), a part of the JFET region 16 is also formed in the region RA sandwiched between the unit cells CL adjacent to each other. As a result, even if the JFET length L2 is inevitably shortened as a result of shrinking the interval between the left column and the right column in FIG. 6(b), the shrink does not affect the JFET region 16 formed in the region RA. This suppresses the reduction in the area of ​​the JFET region 16. This means that even if the JFET length L2 is shortened, the resistance in the JFET region 16 can be suppressed from increasing. Therefore, according to the second feature of this embodiment, the effect of reducing the on-resistance of the silicon carbide power semiconductor device 10 can be enhanced.

[0071] FIG. 7 is a graph showing the relationship between the length of the JFET region and the resistance value of the JFET region.

[0072] As shown in FIG. 7, in the related art, as the length of the JFET region becomes shorter, the resistance value of the JFET region increases rapidly, and as a result, the effect of reducing the on-resistance by shrinking the trench spacing in a silicon carbide power semiconductor device is limited.

[0073] In contrast, in this embodiment, even if the length of the JFET region is shortened, a part of the JFET region is formed between the unit cells, and the area of ​​this JFET region is not affected by shortening the length of the JFET region.

[0074] Therefore, according to the present embodiment, even if the length of the JFET region is shortened, a constant area of ​​the JFET region is secured, so that a rapid increase in the resistance value of the JFET region is suppressed. Therefore, according to the present embodiment, it is possible to increase the effect of reducing the on-resistance of the silicon carbide power semiconductor device.

[0075] From the above, according to silicon carbide power semiconductor device 10, the on-resistance can be reduced more than in the related art due to the synergistic effect of the above-mentioned first and second characteristic points. However, in the present embodiment, it is not necessarily necessary to have both the above-mentioned first and second characteristic points, and even if a configuration has either the first or second characteristic point, the effect of reducing the on-resistance of silicon carbide power semiconductor device 10 can be obtained.

[0076] In addition, while FIG. 6(b) shows an example in which the x direction and the y direction are perpendicular to each other, it is sufficient that the x direction and the y direction intersect. In other words, it is sufficient that the angle between the x direction and the y direction is greater than 0 degrees and smaller than 180 degrees. For ease of explanation, the shape of the trench TR1 is rectangular, but it may be, for example, hexagonal or circular. However, a configuration in which the x direction and the y direction are perpendicular to each other and the trench TR1 is rectangular is simple in terms of device design.

[0077] <Variation 1> FIG. 8 is a plan view showing a silicon carbide power semiconductor device 10A in the present first modification.

[0078] 8, each of the unit cells CL has three trenches TR1, two of which are arranged side by side in the x direction and two of which are arranged side by side in the y direction. Also in this first modification, a JFET region 16 is formed between adjacent unit cells CL.

[0079] Silicon carbide power semiconductor device 10A thus configured also embodies the first and second features described above, and as a result, the on-resistance can be reduced.

[0080] <Variation 2> FIG. 9 is a plan view showing a silicon carbide power semiconductor device 10B in the second modification.

[0081] In FIG. 9, each of the unit cells CL has a trench TR2 having a rectangular shape (first planar shape) having a long side in the x direction, and a plurality of trenches TR2 having a square shape (second planar shape) different from the rectangular shape. For example, when focusing on a unit cell CL1 among the unit cells CL, the trench TR1 and the plurality of trenches TR2 are contained in a single guard region 21A among the plurality of guard regions 21 in a plan view. At this time, the plurality of trenches TR2 are arranged side by side in the x direction. Furthermore, in the present modification 2, a JFET region 16 is formed between adjacent unit cells CL. In the silicon carbide power semiconductor device 10B configured in this manner, the first and second features described above are also realized, and as a result, the on-resistance can be reduced.

[0082] <Modification 3> FIG. 10 is a plan view showing a silicon carbide power semiconductor device 10C in the third modification.

[0083] 10, each of the unit cells CL has three trenches TR1 as in the first modification shown in FIG 8, while, for example, the guard region 21A (21B, 21C) shown in FIG 8 is divided into a guard region 21A1 (21B1, 21C1) and a guard region 21A2 (21B2, 21C2). In the third modification, the JFET region 16 is formed not only between the unit cell CL1B and the unit cell CL2A and between the unit cell CL2B and the unit cell CL3A, but also between the guard region 21A1 (21B1, 21C1) and the guard region 21A2 (21B2, 21C2).

[0084] That is, in the present modification 3, it is possible to increase the region where the area is not reduced even if the JFET length L2 is shortened, thereby suppressing a rapid increase in the resistance value of the JFET region 16. Therefore, according to the present modification 3, it is possible to increase the effect of reducing the on-resistance of the silicon carbide power semiconductor device 10C.

[0085] <Variation 4> FIG. 11 is a plan view showing a silicon carbide power semiconductor device 10D in the fourth modification.

[0086] 11, each of the plurality of unit cells CL has "n" trenches TR1 arranged side by side in the x direction×"m" trenches TR1 arranged side by side in the y direction, that is, a total of "n×m" trenches TR1. These trenches TR1 are contained in the guard region 21. In the silicon carbide power semiconductor device 10D in the present fourth modification, the number of unit cells CL connected to the connection region 20 is "k".

[0087] Here, "n", "m" and "k" are natural numbers, and by appropriately determining "n", "m" and "k", it is possible to adjust the number of trenches TR1 included in each unit cell CL and the area of ​​the JFET region 16 sandwiched between adjacent unit cells CL. That is, according to the fourth modification, it is possible to adjust the size of the gate width based on the number of trenches TR1 included in each unit cell CL, and it is possible to adjust the size of the region whose area is not reduced even if the JFET length L2 is shortened based on the number of unit cells CL connected to the connection region 20. In this way, according to the fourth modification, it is possible to balance the effect of reducing the on-resistance due to the first characteristic point described above and the effect of reducing the on-resistance due to the second characteristic point described above by combining (n, m, k).

[0088] <Variation 5> FIG. 12 is a plan view showing a unit cell UCL1 in the fifth modification.

[0089] In FIG. 12, the unit cell UCL1 is configured to have a rectangular shape in a plan view. The unit cell UCL1 has a JFET region 16U that constitutes a part of the JFET region 16, a guard region 21U that constitutes a part of the guard region 21, and a connection region 20U that is electrically connected to the guard region 21U. The unit cell UCL1 further has a potential clamping region 22U that is formed on the connection region 20U and overlaps the connection region 20U in a plan view. In the unit cell UCL1 configured in this manner, as shown in FIG. 12, the JFET region 16U is disposed in the center of the rectangular shape, while the potential clamping region 22U is disposed in the outer periphery surrounding the outer periphery of the rectangular shape. As a result, the configuration of the unit cell UCL1 allows the area of ​​the potential clamping region 22U to be increased, thereby realizing a structure with high potential clamping of the ground potential.

[0090] <Variation 6> FIG. 13 is a plan view showing a unit cell UCL2 in the sixth modification.

[0091] In FIG. 13, the unit cell UCL2 is configured to have a rectangular shape in a plan view. The unit cell UCL2 has a JFET region 16U that constitutes a part of the JFET region 16, a guard region 21U that constitutes a part of the guard region 21, and a connection region 20U that is electrically connected to the guard region 21U. The unit cell UCL2 further has a potential clamping region 22U that is formed on the connection region 20U and overlaps the connection region 20U in a plan view. In the unit cell UCL2 configured in this manner, as shown in FIG. 13, the potential clamping region 22U is disposed in the center of the rectangular shape, while the JFET region 16U is disposed in the outer periphery surrounding the outer periphery of the rectangular shape. As a result, the configuration of the unit cell UCL2 can increase the area of ​​the JFET region 16U, thereby reducing the resistance of the JFET region 16U and improving the freedom of designing the resistance in the JFET region 16U.

[0092] <Variation 7> In the seventh modification, a configuration regarding how a plurality of unit cells UCL2 are arranged will be described.

[0093] FIG. 14(a) is a plan view showing a first configuration in which a plurality of unit cells UCL2 are arranged, and FIG. 14(b) is a plan view showing a second configuration in which a plurality of unit cells UCL2 are arranged.

[0094] 14(a), a plurality of unit cells UCL2 are arranged in a first row and a second row, and a corner of the unit cell UCL2 arranged in the first row coincides with a corner of the unit cell UCL2 arranged in the second row. In the arrangement shown in FIG. 14(a), the electric field strength applied to the JFET region 16U is high in the region R1.

[0095] 14(b), a plurality of unit cells UCL2 are arranged in a first row and a second row, and a corner of the unit cell UCL2 arranged in the first row is offset from a corner of the unit cell UCL2 arranged in the second row in the row direction (y direction). As a result, in the arrangement shown in FIG 14(b), the electric field strength applied to the JFET region 16U in the region R2 can be reduced compared to the arrangement shown in FIG 14(a).

[0096] Therefore, from the viewpoint of reducing the electric field strength applied to the JFET region 16U at the corners of the unit cell UCL2, it is more desirable to adopt the layout configuration shown in FIG. 14(b) than the layout configuration shown in FIG. 14(a).

[0097] <Method for manufacturing silicon carbide power semiconductor device> Next, a method for manufacturing the silicon carbide power semiconductor device in this embodiment will be described.

[0098] FIG. 15 is a flowchart illustrating a method for manufacturing a silicon carbide power semiconductor device.

[0099] <<Semiconductor substrate preparation process (S101)>> First, a substrate made of n-type silicon carbide is prepared. Examples of this substrate include a substrate made by sublimation, a substrate made by solution deposition, and a substrate made by gas growth. Furthermore, a substrate on which an epitaxial layer has already been formed may be used. This substrate may be subjected to chemical mechanical polishing (CMP) before growing an epitaxial layer, which will be described later.

[0100] The concentration of n-type impurities introduced into the substrate is, for example, 1×10 18 / cm 3 More than 1×1021 / cm 3 The crystal type of the substrate may be any of 4H-SiC, 6H, and 3C. The upper surface of the substrate may be a Si surface or a C surface, or may have other surface orientations. Although it is preferable to use a substrate having an off-angle, a just substrate having no off-angle may be used.

[0101] <<Epitaxial layer growth process (S102)>> An epitaxial layer is formed on a substrate by using an epitaxial growth method in which H2 gas is used as a carrier gas and SiH4 gas and C3H8 gas are heated to a temperature of 1500°C or higher. Specifically, Fig. 16 shows an epitaxial layer 15 formed on a substrate 13. Here, the impurity concentration and film thickness of epitaxial layer 15 differ depending on the silicon carbide power semiconductor device to be fabricated, but for example, the impurity concentration is 1 x 10 14 / cm 3 More than 1×10 18 / cm 3 The thickness is often several μm to several tens of μm. A high-concentration buffer layer may be formed before forming the epitaxial layer 15. The impurity concentration of the buffer layer is, for example, 1×10 18 / cm 3 That's about it.

[0102] <<Ion implantation region forming step (S103)>> The polarity of the ion implantation regions described below may be reversed between p-type and n-type. Examples of p-type implantation ions include aluminum and boron, while examples of n-type implantation ions include nitrogen and phosphorus.

[0103] For example, as shown in FIG. 17, the body region 19, potential fixing region 22, connection region 20, and guard region 21, which are p-type semiconductor regions, are formed in the above-mentioned epitaxial layer 15 by ion implantation, and the source region 18, current diffusion region 17, and JFET region 16, which are n-type semiconductor regions, are also formed by ion implantation. At this time, the body region 19 may be formed by a p-type epitaxial growth method.

[0104] 17, the source region 18 and the potential fixing region 22 are formed on the surface of the epitaxial layer 15. The body region 19 is in contact with the source region 18 and is formed at a deeper position than the source region 18. Furthermore, the body region 19 is electrically connected to the potential fixing region 22 and the connection region 20. Moreover, the current spreading region 17 is in contact with the body region 19 and is formed at a deeper position than the body region 19.

[0105] The guard region 21 is in contact with the current diffusion region 17 and is formed at a location deeper than the current diffusion region 17. The guard region 21 is electrically connected to the potential fixing region 22 via the connection region 20. The JFET region 16 is a region that connects the current diffusion region 17 and the epitaxial layer 15, and is a region sandwiched between a pair of adjacent guard regions 21. Ion implantation may be performed on the JFET region 16 to reduce resistance.

[0106] It should be noted that this specification shows the minimum configuration for operating a silicon carbide power semiconductor device, and therefore, for example, a structure may be fabricated that adds a function such as a termination region, or ions such as nitrogen may be implanted into the back surface to increase the conductivity of the back surface contact.

[0107] After the ion implantation process, a carbon film is deposited around the substrate 13 and the epitaxial layer 15 as a cap material for impurity activation annealing. Then, impurity activation annealing is performed at a temperature p of, for example, 1600° C. to 1800° C. After that, the carbon film as the cap material is removed by oxygen plasma ashing. After this process, in order to obtain a cleaner surface, a thermal oxide film may be formed and then removed using a diluted hydrofluoric acid solution.

[0108] <<Trench forming process (S104)>> 18, a trench TR1 is formed so as to penetrate through the source region 18, the body region 19, and the current diffusion region 17 and reach the guard region 21 at its bottom. The trench TR1 can be formed by using, for example, photolithography and etching techniques. At this time, by devising a mask used in patterning to form the trench TR1, the trench TR1 can be formed in a layout as shown in FIG. 3 in plan view. In order to clean the etched surface, a thermal oxide film may be formed and then removed with a diluted hydrofluoric acid solution.

[0109] <<Gate insulating film forming process (S105)>> Next, as shown in FIG. 19, for example, a gate insulating film 11 is formed on the inner wall of the trench TR1 by using a CVD (Chemical Vapor Deposition) method. For example, the gate insulating film 11 is composed of a deposited oxide film having a thickness of 10 nm to 100 nm. The gate insulating film 11 may be formed by thermally oxidizing a substrate made of silicon carbide (SiC). After that, a "POA treatment" or a "PDA treatment" may be performed to modify the interface between the gate insulating film 11 and the substrate.

[0110] <<Gate electrode forming process (S106)>> 19, a gate electrode 12 made of an n-type polycrystalline silicon film having a thickness of 100 nm to 300 nm is formed by using a CVD method. The gate electrode 12 is formed so as to be embedded inside the trench TR1.

[0111] <<Electrode formation process (S107)>> 4, for example, an interlayer insulating film 23 is formed so as to cover the gate electrode 12. Thereafter, in order to make contact between the source region 18 and the potential fixing region 22, a contact hole is formed by etching the interlayer insulating film 23 using a resist film as a mask. Then, after depositing a metal film for silicidation, annealing is performed at a temperature of 700° C. or higher and 1000° C. or lower to perform silicidation, thereby forming a common contact common to the source region 18 and the potential fixing region 22.

[0112] Next, in order to make contact with the gate electrode 12, the interlayer insulating film 23 is etched to form a contact hole for the gate electrode, and then a conductive film is embedded in this contact hole for the gate electrode to form a contact for the gate electrode.

[0113] Next, a source electrode 24 is formed, which is electrically connected to the source region 18 and the potential fixing region 22. Then, a drain electrode 14 is formed on the rear surface of the substrate 13.

[0114] In this manner, silicon carbide power semiconductor device 10 can be manufactured.

[0115] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0116] 16 JFET area 16U JFET area 21 Guard Area 21A Guard Area 21B Guard Area 21C Guard Area 21U Guard Area 22 Potential fixing region 22U potential fixing area CL unit cell CL1 unit cell CL2 unit cell CL3 unit cell CL4 unit cell CL5 unit cell CL6 unit cell S1 First side S2 Second side TR1 Trench TR2 Trench UCL1 unit cell UCL2 unit cell

Claims

1. It contains as its main component a semiconductor material with a larger band gap than silicon, A plurality of trenches; a plurality of guard regions covering bottoms of the plurality of trenches; a JFET region in contact with the plurality of guard regions; A semiconductor device comprising: The semiconductor device includes a plurality of unit cells, Each of the plurality of unit cells comprises: A plurality of first trenches aligned in a first direction; a plurality of second trenches aligned in a second direction intersecting the first direction; Including, In a plan view, the plurality of first trenches and the plurality of second trenches are contained within a single guard region among the plurality of guard regions.

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein one of the plurality of first trenches and one of the plurality of second trenches are a common trench.

3. 2. The semiconductor device according to claim 1, The first direction and the second direction are perpendicular to each other.

4. 2. The semiconductor device according to claim 1, Each of the plurality of unit cells is configured in a planar shape having at least a first side and a second side that intersect with each other in a planar view, the first side and the second side both contact the JFET region.

5. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the plurality of first trenches and the plurality of second trenches are arranged in an array in a plan view.

6. 2. The semiconductor device according to claim 1, Each of the plurality of unit cells is configured to have a rectangular shape in a plan view, Each of the plurality of unit cells comprises: a first JFET region constituting a part of the JFET region; a first guard area constituting a part of the plurality of guard areas; a first potential fixing region electrically connected to the first guard region; 13. A semiconductor device comprising:

7. 7. The semiconductor device according to claim 6, the first JFET region is disposed in a center of the rectangular shape in a plan view, The first potential clamping region is disposed on the outer periphery of the rectangular shape in a plan view.

8. 7. The semiconductor device according to claim 6, the first potential clamping region is disposed in a center of the rectangular shape in a plan view, The first JFET region is disposed on an outer periphery of the rectangular shape in a plan view.

9. 7. The semiconductor device according to claim 6, The plurality of unit cells, in a plan view, a plurality of first unit cells arranged in a first column; a plurality of second unit cells arranged in a second column; Including, a corner of each of the first unit cells and a corner of each of the second unit cells are offset from each other in a column direction.

10. 2. The semiconductor device according to claim 1, The semiconductor device, wherein the semiconductor material is silicon carbide.

11. It contains as its main component a semiconductor material with a larger band gap than silicon, A plurality of trenches; a plurality of guard regions covering bottoms of the plurality of trenches; a JFET region in contact with the plurality of guard regions; A semiconductor device comprising: The semiconductor device includes a plurality of unit cells, Each of the plurality of unit cells comprises: a first trench having a first planar shape; a plurality of second trenches having a second planar shape different from the first planar shape; Including, A semiconductor device, wherein, in a plan view, the first trench and the plurality of second trenches are contained within a single guard region among the plurality of guard regions.

12. 12. The semiconductor device according to claim 11, The first planar shape is a rectangular shape having a long side in a first direction, The second planar shape is a square shape, The semiconductor device, wherein the plurality of second trenches are arranged side by side in the first direction.

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