Hybrid-gate power device

Abstract

The vertical field effect device includes a body, a gate insulating film, and a gate electrode, the gate electrode extending from an upper surface of the body into the body and residing in a trench between a first source region and a second source region. First and second regions vertically overlap the gate electrode. First and second channel regions laterally overlap a bottom of the gate electrode such that each channel formed in the first and second source regions has a horizontal segment in which the first and second channel regions laterally overlap a bottom of the gate electrode. In another embodiment, the first and second channel regions further vertically overlap the gate electrode such that each channel formed in the first and second source regions also has a vertical segment in which the first and second channel regions vertically overlap the gate electrode.

Description

[Technical field]

[0001] The present disclosure relates to vertically oriented power devices. [Background technology]

[0002] A power metal-oxide-semiconductor field effect transistor (MOSFET) is a type of MOSFET suitable for use in high power applications. Generally, power MOSFETs have a vertical structure, with source and gate contacts located on the top surface of the MOSFET's body, and a drain contact located on the bottom surface of the MOSFET's body. These "vertical" MOSFETs are sometimes called vertical diffused MOSFETs (VDMOSFETs) or double-diffused MOSFETs (DMOSFETs). Such power devices, in typical applications, are capable of blocking at least 300 volts in the off state and conducting at least 1 ampere in the on state. Generally, for a given device area, the higher the blocking voltage, the lower the current handling, and vice versa.

[0003] A conventional vertical MOSFET typically includes a substrate and a drift layer formed across the substrate at a lower portion of the body. One or more junction implants extend from an upper surface of the body into the body. Junction-gate field-effect transistor (JFET) regions are formed between the junction implants in the upper portion of the body. Each one of the junction implants is formed by an ion implantation process and may include at least one source region. Each source region is formed shallow below the upper surface of the drift layer. The gate structure typically has one of a planar configuration or a trench configuration. In a planar device, a gate dielectric is formed along the upper surface of the body and extends laterally over at least a portion of each source region. A planar gate electrode is formed over the gate dielectric. In a trench device, the gate dielectric and gate electrode extend to the upper surface of the body and in a trench between the source regions. A source contact is formed over the source region and a drain contact is formed at a bottom surface of the substrate.

[0004] The long-term reliability of vertical MOSFETs is often a function of the integrity of the interface between the JFET region and the gate dielectric. This interface, in turn, defines the gate-drain capacitance of the MOSFET, which directly affects the switching speed, gate leakage current in both the on- and off-states, and blocking voltage in the off-state. Summary of the Invention [Means for solving the problem]

[0005] The present disclosure provides a vertical field effect device having a body, a gate dielectric, and a gate electrode. The body has a first source region and a second source region extending from a top surface of the body into the body. A first channel region laterally overlaps below the first source region. A second channel region laterally overlaps below the second source region. A JFET region is provided between the first channel region and the second channel region. A gate electrode extends from a top surface of the body into the body and is in a trench located between the first source region and the second source region. A gate dielectric is between the gate electrode and the body and separates the gate electrode from the body. The first source region and the second source region vertically overlap the gate electrode. The first channel region and the second channel region laterally overlap a bottom of the gate electrode. Each channel formed in the first and second channel regions between the JFET region and the first and second source regions has a horizontal segment where the first and second channel regions laterally overlap the bottom of the gate electrode.

[0006] In one embodiment, the first and second channel regions do not vertically overlap the gate electrode. The body may also have a first shielding region that laterally overlaps below the first channel region and a second shielding region that laterally overlaps below the second channel region such that the JFET region is further between the first and second shielding regions. The first and second channel regions may be closer to each other than the first and second shielding regions such that a portion of the JFET region between the first and second channel regions is narrower than a portion of the JFET region between the first and second shielding regions.

[0007] In another embodiment, the first and second channel regions vertically overlap the gate electrode such that each channel formed in the first and second channel regions between the JFET region and the first and second source regions has a vertical segment that also vertically overlaps the gate electrode.

[0008] In one variation, no portion of the gate electrode laterally overlaps the first and second source regions. The body may also have a first shielding region that laterally overlaps below the first channel region and a second shielding region that laterally overlaps below the second channel region such that the JFET region is further between the first and second shielding regions. The first and second channel regions may be closer together than the first and second shielding regions such that a portion of the JFET region between the first and second channel regions is narrower than a portion of the JFET region between the first and second shielding regions.

[0009] In any of several embodiments, the first and second source regions may be doped with an N-type material and the first and second channel regions may be doped with a P-type material. The field effect device may be a metal oxide semiconductor field effect device (MOSFET), an insulated gate bipolar transistor (IGBT), or the like.

[0010] In certain embodiments, the trench has a depth, measured from a top surface of the body to a bottom of the trench, of between 0.25 um and 1.0 um, between 0.5 um and 1.25 um, between 0.5 um and 1.5 um, and between 0.75 um and 1.5 um. The body may further include a first shielding region laterally overlapping below the first channel region and a second shielding region laterally overlapping below the second channel region such that the first and second shielding regions are less than 2 micrometers deeper than the bottom of the trench.

[0011] In certain embodiments, the field effect device can block at least 300 volts, 600 volts, 900 volts, 1200 volts, 1700 volts, 2200 volts, 3500 volts, 6500 volts, or 10000 volts in the off state and can conduct at least 1 amp, 5 amps, 10 amps, 20 amps, 50 amps, or 100 amps in the on state.

[0012] Those skilled in the art will appreciate the scope of the present disclosure, and will realize additional aspects of the present disclosure, after reading the following detailed description of the preferred embodiments in conjunction with the accompanying illustrated figures.

[0013] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the disclosure and, together with the above description, serve to explain the principles of the disclosure. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional view of a vertical MOSFET having a planar gate structure according to the related art. [Diagram 2] FIG. 1 is a cross-sectional view of a trench MOSFET having a planar gate structure according to the related art. [Diagram 3] 1 is a cross-sectional view of a hybrid MOSFET according to a first embodiment of the disclosure. [Figure 4]FIG. 2 is a cross-sectional view of a hybrid MOSFET according to a second disclosed embodiment. [Diagram 5] FIG. 11 is a cross-sectional view of a hybrid MOSFET according to a third disclosed embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The following examples represent the necessary information to enable one skilled in the art to practice the above examples and illustrate the best modes of practicing the examples. Upon reading the following description in light of the accompanying illustrated figures, one skilled in the art will understand the concepts disclosed and will clearly understand applications of these concepts not specifically addressed herein. It is to be understood that these concepts and applications are within the scope of this disclosure and the appended claims.

[0016] Although terms such as first, second, etc. may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0017] When an element, such as a layer, region, or substrate, is referred to as being "on" or extending "onto" another element, it will be understood that it may be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Similarly, when an element, such as a layer, region, or substrate, is referred to as being "over" or extending "over" another element, it will be understood that it may be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0018] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0019] The terminology used herein is merely for the purpose of describing particular embodiments and is not intended to limit the disclosure. As used herein, the singular forms "a", "an" and "the" include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including" as used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0020] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that the terms used herein should be interpreted to have a meaning consistent with their meaning in the context of this specification and the relevant art, and cannot be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0021] In general, the present disclosure provides a vertical field effect device having a body, a gate dielectric, and a gate electrode. The body has a first source region and a second source region extending from a top surface of the body into the body. A first channel region laterally overlaps below the first source region. A second channel region laterally overlaps below the second source region. A JFET region is provided between the first channel region and the second channel region. A gate electrode is in a trench extending from a top surface of the body into the body and is located between the first source region and the second source region. A gate dielectric is between the gate electrode and the body and separates the gate electrode from the body.

[0022] The first source region and the second source region vertically overlap the gate electrode. The first channel region and the second channel region laterally overlap a bottom of the gate electrode. Thus, each channel formed in the first and second source regions between the JFET region and the first and second source regions has a horizontal segment where the first and second channel regions laterally overlap a bottom of the gate electrode.

[0023] In one embodiment, the first and second channel regions do not vertically overlap the gate electrode. The body may also have a first shielding region that laterally overlaps below the first channel region and a second shielding region that laterally overlaps below the second channel region such that a JFET region is further between the first and second shielding regions. The first and second channel regions may be closer to each other than the first and second shielding regions such that a portion of the JFET region between the first and second channel regions is narrower than a portion of the JFET region between the first and second shielding regions.

[0024] In another embodiment, the first and second channel regions vertically overlap the gate electrode such that each channel formed in the first and second source regions between the JFET region and the first and second source regions also has a vertical segment in which the first and second channel regions vertically overlap the gate electrode. In one variation, no portion of the gate electrode laterally overlaps the first and second source regions. Prior to exploring the disclosed concepts in detail, an overview of certain related art is provided.

[0025] 1 shows a conventional planar MOSFET 10P. The planar MOSFET 10P has a body B including a substrate 12 and a drift region 14 formed in the substrate 12. One or more junction implants 16 extend into the body B from a top surface thereof, where the top surface is opposite the substrate. Junction gate field effect transistor (JFET) regions 18 are provided between the junction implants 16. Each one of the plurality of junction implants 16 is formed by an ion implantation process and typically includes a shielding region 20, a channel region 22, a source region 24, and a connector region 26.

[0026] The source regions 24 are provided on top of the body B on either side of the JFET region 18. Each channel region 22 is between a corresponding source region 24 and the JFET region 18. Each shielding region 20 has a portion that is below a corresponding channel region 22, source region 24, and connector region 26. Each connector region 26 is outboard or laterally adjacent to a corresponding source region 24 and extends between a top surface of the drift region 14 and the corresponding shielding region 20. In the illustrated example, the shielding region 20 extends upward from the JFET region 18 along a bottom portion of the channel region 22 and the source region 24, and along an outer portion of the source region 24 toward the top surface of the drift region 14. Each channel region 22 is thus bounded by the top surface of the drift region 14, the JFET region 18, the shielding region 20, and the source region 24.

[0027] In a typical configuration, the drift region 14 and the JFET region 18 are approximately 1×10 14 cm -3 and 1×10 18 cm -3 The shielding region 20 is doped to an intermediate concentration (N) with an N-type doping material at a concentration between about 1×10 17 cm -3 and 5×10 19 cm -3 The channel region 22 is heavily doped (P+) with a P-type doping material at a concentration between about 1×1015 cm -3 and 1×10 18 cm -3 The source region 24 is doped to an intermediate concentration (P) with a P-type doping material at a concentration between about 1×10 18 cm -3 and 1×10 21 cm -3 The connector region 26 is heavily doped (N+) with an N-type doping material at a concentration between about 1×10 18 cm -3 and 1×10 21 cm -3 The semiconductor substrate 100 is heavily doped with a P-type doping material at a concentration approximately between 100 and 150 μm. The concentration levels are exemplary only and will vary from embodiment to embodiment depending on the device performance criteria.

[0028] Substrate 12 may be an N-doped, single crystal, SiC substrate 12. Substrate 12 may have various crystal polytypes, such as 2H, 4H, 6H, 3C, etc. In other embodiments, substrate 12 may also be formed from other material systems, such as gallium nitride (GaN), gallium arsenide (GaAs), silicon (Si), germanium (Ge), SiGe, etc. Substrate 12 has a surface area of ​​about 1×10 17 cm -3 and 1×10 19 cm -3 and may have a thickness between about 100 microns and 600 microns, however, the doping concentration and thickness of substrate 12 and other layers may vary based on the desired parameters of MOSFET 10P.

[0029] The drift region 14 may be relatively uniformly doped throughout, or may utilize graded doping throughout all or a portion of the drift region 14. For a uniformly doped drift region 14, the doping concentration is, in one embodiment, about 1×10 14 cm -3 and 2×10 16 cm -3For example, the drift region 14 for a device having a rated voltage of more than 10,000 volts may have a capacitance between 1×10 14 cm -3 A device may have a doping concentration of around 1×10 and may be on the order of 100 microns thick, while a device rated for 650 volts may have a doping concentration of around 1×10 14 cm -3 The doping concentration may be around 100 nm and may be around 6 microns thick.

[0030] If the doping concentration in the drift region 14 is graded, the drift region 14 will have a doping concentration of 1×10 18 cm -3 The drift region 14 may have a maximum doping of 0.1 μm to 100 μm near the top, and may taper off to a level required for device rating near the top. The more heavily doped regions may generally be much thinner than the lightly doped drift region. In other embodiments, the doping concentration may increase in the drift region 14 from the bottom to the top of the drift region 14.

[0031] The drift region 14 may include one or more portions. When multiple portions are provided, the upper portions may represent spreading layers and the lower portions may represent drift layers. In embodiments including one or more upper spreading layers and one or more lower drift layers, the spreading layers are provided immediately above the drift layers to help further reduce the electric field and facilitate spreading of the current as it flows downward toward the drift layers and the drain contact 34. The spreading layers are doped in a manner to reduce the resistance in the current path. The use of spreading layers reduces the ON resistance of the device, where reduced ON resistance can result in a highly efficient device.

[0032] In certain embodiments, the spreading layer is 1×10 16 cm -3 and 4×10 16 cm -3and may be approximately 1 to 3 micrometers thick. The doping concentration in the spreading layer may be uniform or graded, where the relative action doping concentration may increase or decrease from the bottom to the top of the spreading layer depending on the desired characteristics of the device. A uniformly or graded doped drift layer may be paired with a uniform or graded spreading layer. Any of the following embodiments described herein may be configured with the spreading layer and drift layer in drift region 14:

[0033] A gate dielectric 28 is formed along the top surface of the body B and extends laterally between each of the source regions 24 such that portions of the gate electrode 28 extend over at least portions of the channel region 22 and the source regions 24. A gate (G) electrode 30 is formed over the gate dielectric 28. The planar nature of the gate dielectric 28 and gate electrode 30 gives the MOSFET 10P its name: planar.

[0034] Source (S) contacts 32 are formed on the top surface of drift region 14 and over source region 24 such that each one of the source contacts 32 overlaps corresponding portions of both source region 24 and connector region 26 without contacting gate dielectric 28 or gate electrode 30. Drain (D) contacts 34 are located on the bottom surface of substrate 12 opposite drift region 14.

[0035] In operation, when no bias voltage is applied to the gate electrode 30 and the drain contact 34 is positively biased, the PN junction between each shielding region 20 and the drift region 14 is reverse biased, thereby placing the planar MOSFET 10P in an OFF state. In the OFF state of the planar MOSFET 10P, any voltage between the source contact 32 and the drain contact 34 will be maintained by the drift region 14, and only leakage current will flow between these contacts. Due to the vertical structure of the planar MOSFET 10P, large voltages can be applied between the source contact 32 and the drain contact 34 without damaging the device.

[0036] When a positive bias is applied to the gate electrode 30 of the planar MOSFET 10P, a lateral channel is formed in each channel region 22 just below the top surface of the drift region 14 directly beneath the gate electrode 30, thereby placing the planar MOSFET 10P in an ON state. In the ON state, current (indicated by the dashed lines) flows laterally through the lateral channel formed in each channel region 22 from the respective source region 24, through the source contact 32, and to the JFET region 18 of the drift region 14. Notably, the current flows primarily laterally through a portion of the source region 24.

[0037] Once in the JFET region 18, current flows downward through the drift region 14 towards the drain contact 34. The electric field that exists at the PN junction formed between the shielding region 20, the channel region 22, and the drift region 14 tends to force current to flow through the center of the JFET region 18. The center of the JFET region 18 through which the current flows is called the JFET channel. After reaching a certain depth, called the spreading depth, the electric field induced by the junction implant 16 begins to collapse. The collapsing electric field allows the current to spread out as it flows further downward through the drift region 14 towards the drain contact 34.

[0038] For a planar device such as MOSFET 10P, gate electrode 30 is required to be wide and laterally overlap source region 24 so that the channel in channel region 22 is horizontal. The channel length is determined by the lateral gate length (LL) specified in FIG. G ) The gate-source overlap (GOL), which is a measure of how much of the gate electrode 30 overlaps each of the source regions 24, is also horizontal. Thus, the overall gate structure of the MOSFET 10P extends laterally and requires a large area, which generally increases the cost and runs counter to currently occurring desires to make such devices smaller.

[0039] An advantage of a planar device is that the gate dielectric 28 does not have any bends or corners surrounding the gate electrode. Such bends or corners in the gate dielectric 28 are susceptible to degradation over time due to high electric fields generated therein during operation. Such degradation can lead to device performance degradation and failure. Furthermore, there is no need for very deep implants to create the shielding regions 20 because the shielding regions 20 are typically relatively shallow.

[0040] FIG. 2 illustrates another conventional MOSFET configuration called a trench MOSFET 10T. The fundamental difference between the planar MOSFET 10P of FIG. 1 and the trench MOSFET 10T of FIG. 2 is in the configuration of the gate structure. As noted above, the planar MOSFET 10P has a gate insulator 28 and a gate electrode 30, both of which are planar and overlie the top surface of the body B. In contrast, the trench MOSFET 10T has a gate insulator 28 and a gate electrode 30 that are recessed into the body B from the top surface of the body B. In this embodiment, the depth of the trench from the top surface of the body B to the bottom of the trench is typically in the range of 1 um to 2 um.

[0041] The source regions 24 are formed on either side of the gate electrode 30 and are separated from the gate electrode 30 by a gate insulating film 28. A channel region 22 is formed below an inner portion of the source region 24 between a portion of the shielding region 20 and the gate electrode 30. The gate insulating film 28 insulates the gate electrode 30 from the source regions 24, the channel region 22, the shielding region 20, and the JFET region 18.

[0042] In operation, when no bias voltage is applied to the gate electrode 30 and the drain contact 34 is positively biased, the PN junctions between each shielding region 20 and the drift region 14 are reverse biased, thereby placing the trench MOSFET 10T in an OFF state. In the OFF state, all voltages between the source contact 32 and the drain contact 34 are maintained by the drift region 14, and only leakage current will flow between these contacts.

[0043] A positive bias is applied to the gate electrode 30 to place the trench MOSFET 10T in the ON state. In the ON state, a vertical channel is formed in each channel region 22 along the gate dielectric 28 from the corresponding source region 24 to the JFET region 18. Current (indicated by the dashed lines) flows vertically through the vertical channel formed in each channel region 22 from the respective source region 24 through the source contact 32 to the JFET region 18 of the drift region 14. Once in the JFET region 18, the current flows downward through the drift region 14 to the drain contact 34.

[0044] For a typical trench-type layout, the vertical gate length (VL GBoth the channel and the gate-source overlap (GOL), represented by ) are vertical to reduce the width (i.e., pitch) of the gate structure and to increase the current density. In silicon carbide (SiC) devices, the vertically oriented channel results in greater electron mobility and therefore higher current capability. However, for trench devices such as the trench MOSFET 10T, the shielding region 20 is often greater than 1 micrometer below the top surface of the body B, much deeper than many implanters can typically reach. The shielding region 20 is generally made deeper relative to planar devices by the depth of the trench for the gate electrode 30 to keep the shielding of the JFET region 18 commensurate with the performance of the planar device. Another weakness of trench devices such as the trench MOSFET 10T is that the corners of the gate dielectric 28 in the trench are exposed in the JFET region 18 and therefore experience high electric fields when blocking current flows. As noted above, the oxides used to form the gate dielectric 28 are prone to failure when exposed to high electric fields.

[0045] The next embodiment improves upon the planar and trench designs described above by providing a hybrid gate architecture that employs both a recessed gate structure and a channel having at least a horizontal segment. With reference to FIG. 3, a hybrid MOSFET 10H has a gate insulator 28 and a gate electrode 30 that reside in a "trench" recessed into the drift region 14 from a top surface of the drift region 14. Source regions 24 are provided on either side of the gate electrode 30 and are separated from the gate electrode 30 by the gate insulator 28. A channel region 22 is formed below the source region 24 and extends below a portion of the gate electrode 30. A first portion of each channel region 22 laterally overlaps below a portion of the gate electrode 30, and a second portion of each channel region 22 laterally overlaps below at least a portion of the source region 24. For this embodiment, no portion of the channel region 22 vertically overlaps any portion of the gate electrode 30. Again, the gate dielectric 28 insulates the gate electrode 30 from the source region 24, the channel region 22, the shielding region 20, and the JFET region 18. The depth of the trench from the top surface of the body B to the bottom of the trench ranges from 0.2 micrometers to 1.0 micrometers, 0.2 micrometers to 0.5 micrometers, 0.4 micrometers to 0.8 micrometers, 0.5 um to 1.0 um, etc. The depth of the trench is non-limiting.

[0046] In operation, when no bias voltage is applied to gate electrode 30 and drain contact 34 is positively biased, the PN junctions between each shielding region 20 and drift region 14 are reverse biased, thereby placing hybrid MOSFET 10H in the OFF state. In the OFF state, all voltages between source contact 32 and drain contact 34 are maintained by drift region 14, and only leakage current will flow between these contacts.

[0047] A positive bias is applied to the gate electrodes 30 to place the hybrid MOSFET 10H in an ON state. In the ON state, a channel is formed in each channel region 22 for current to flow from the source regions 24 to the JFET region 18. Even though the gate electrodes 30 are recessed into the drift region 14, each channel has a horizontal segment in a portion of the channel region 22 that laterally overlaps a portion of the gate electrode 30. Thus, current (indicated by the dashed lines) flows from the respective source regions 24 through the source contacts 32 to the JFET region 18 of the drift region 14 through the substantially horizontal channels formed in each channel region 22. Once in the JFET region 18, the current flows downward through the drift region 14 through the substrate 12 to the drain contact 34. In general, current only flows through the channel region 22 where the gate electrode 30 is adjacent to the channel region 22.

[0048] The shielding region 20 for this embodiment may laterally overlap all or only a portion of the channel region 22. As shown, the shielding region 20 laterally overlaps all of the channel region 22 and the connector region 26. Notably, the internal vertical boundaries of the channel region 22 and the shielding region 20 are substantially aligned and together define the vertical boundaries of the JFET region 18.

[0049] For the embodiment of FIG. 3, the relatively shallow trench formation between the source regions 24 makes the gate-source overlap (GOL) vertical, thus allowing for a smaller device pitch (i.e., smaller width), and therefore a higher current density. The shielding region 20 only needs to be deeper by the magnitude of the shallow trench depth (e.g., approximately 0.2 to 0.4 micrometers greater than for a planar device) to maintain the same blocking capability. For example, if the trench depth for the gate electrode 30 and gate dielectric 28 ranges from 0.2 um to 0.8 um, the depth of the shielding region 20 would extend 0.5 to 2 um into the body. As a result, the hybrid MOSFET 10H provides a cell pitch that is twice the gate-source overlap (2×GOL) narrower than for a comparable planar device, implying a higher current density for the same layout design rules without the need for an overly deep shielding region 20. For certain manufacturing processes, it is preferable to have the shielding region no more than 1.5 microns from the top surface of the body B. Also, there are no corners in the gate dielectric exposed to high electric fields because any corners that exist are shielded from the electric field in drift region 14 by channel region 22 and shielding region 20 .

[0050] A second embodiment of a hybrid MOSFET 10H' is shown in Figure 4. The hybrid MOSFET 10H' also has a gate insulator 28 and a gate electrode 30 that reside in a "trench" recessed into the drift region 14 from the top surface of the drift region 14. The source regions 24 are provided on either side of the gate electrode 30 and are separated from the gate electrode 30 by the gate insulator 28. The difference between the hybrid MOSFET 10H of Figure 3 and the hybrid MOSFET 10H' of Figure 4 resides primarily in the configuration of the channel region 22 with respect to the gate electrode 30.

[0051] The channel region 22 is formed below the source region 24 and extends below a portion of the gate electrode 30 so that a first portion of each channel region 22 laterally overlaps below a portion of the gate electrode 30; a second portion of each channel region laterally overlaps at least a portion below the source region 24; A second portion of each channel region 22 vertically overlaps a lateral portion of the gate electrode 30 .

[0052] The configuration illustrated in FIG. 4 forms a channel having both vertical and horizontal segments in each of the channel regions 22 when the MOSFET 10H′ is in an ON state. The horizontal segment of each channel is in a first portion of each of the channel regions 22 that laterally overlaps a portion of the gate electrode 30. The vertical segment of each channel is in a second portion of each of the channel regions 22 that vertically overlaps a portion of the gate electrode 30. Thus, current will flow from the source region 24 through the corresponding channel region 22 to the JFET region 18 (indicated by the dashed lines). As it flows through the channel region 22, the current will flow downward from the source region 24 along the vertical segment of the channel in the portion of the channel region 22 that vertically overlaps the gate electrode 30, and then horizontally through the horizontal segment of the channel in the portion of the channel region 22 that laterally overlaps the gate electrode 30. Once in the JFET region 18, the current will flow downward through the drift region 14 through the substrate 12 to the drain contact 34. As shown, current generally only flows through channel region 22 where gate electrode 30 is adjacent to channel region 22 .

[0053] When no bias voltage is applied to gate electrode 30 and drain contact 34 is positively biased, the PN junctions between each shielding region 20 and drift region 14 are reverse biased, thereby placing hybrid MOSFET 10H' in the OFF state. In the OFF state, all voltages between source contact 32 and drain contact 34 are maintained by drift region 14, and only leakage current will flow between these contacts.

[0054] Shielding region 20 may laterally overlap all or only a portion of channel region 22. For the embodiment of FIG. 4, shielding region 20 laterally overlaps most or all of channel region 22. Thus, portions of shielding region 22 overlap portions of gate electrode 30 even though portions of channel region 22 reside between gate electrode 30 and shielding region 20. Notably, the internal vertical boundaries of channel region 22 and shielding region 20 are substantially aligned and together define the vertical boundaries of JFET region 18. The internal boundaries of channel region 22 and shielding region 20 need not be aligned or vertical.

[0055] The embodiment of FIG. 4 provides a slightly deeper trench for the gate electrode 30 and gate dielectric 28. For example, the trench may range from 0.3 to 1.3 micrometers. The slightly deeper trench formation in this area between the source regions 24 compared to the embodiment of FIG. 3 extends the vertical gate-source overlap (GOL). Additionally, the channel has a vertical portion and a horizontal portion, where the channel is below V+LL. G 4. The result is a smaller device pitch and higher current density relative to the hybrid MOSFET 10H′ of FIG. 4. A vertical channel in SiC(0001) would have a higher electron mobility as well. The shielding region 20 needs to be deeper (e.g., approximately 0.3 to 0.6 micrometers larger than for a planar device) by the magnitude of the trench depth to maintain the same blocking capability. The trench depth for the gate electrode 30 and gate dielectric 28 may range from 0.3 to 1.3 micrometers, 0.5 to 1.1 micrometers, 0.7 to 1.0 micrometers, etc. In certain non-limiting examples, the depth of the shielding region 20 may extend from 0.6 to 2 micrometers, 0.9 to 1.7 micrometers, or 1.1 to 1.4 micrometers.

[0056] FIG. 5 illustrates another embodiment of a hybrid MOSFET 10H″. In this embodiment, the interior sidewalls of the shielding regions 20 are recessed back from the interior sidewalls of the channel regions 22, so that the portions of the JFET regions 18 between the channel regions 22 are narrower than the portions of the JFET regions 18 between the shielding regions 20. There is a slight pitch tighter compared to the embodiment of FIG. 4, thereby providing similar or improved shielding and even greater current density. These interior sidewalls of the channel regions 22 and shielding regions 20 may be substantially vertical or angled. The orientation of the sidewalls and the amount of overlap with each other and with the gate electrode 30 may vary based on desired performance characteristics, size, cost, etc. In another embodiment, the shielding regions 20 extend laterally inwardly past the interior sidewalls of the channel regions 22.

[0057] The concepts described herein are particularly useful, but not limited to, other insulated gate devices such as MOSFETs and insulated gate bipolar transistors. In particular, as used herein, the terms source, gate and drain are deemed to include emitter, base and collector, respectively, and thus the appended claims are intended to cover all such insulated gate devices, regardless of how the respective regions or contacts are named.

[0058] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure, and all such improvements and modifications are believed to be within the scope of the concepts disclosed herein and the accompanying claims.

Claims

1. - A body, - first and second source regions extending into the body; a first channel region below and laterally overlapping the first source region and a second channel region below and laterally overlapping the second source region; a first shielding region below and laterally overlapping the first channel region, the first shielding region having a higher doping concentration than the first channel region; a second shielding region below and laterally overlapping the second channel region, the second shielding region having a higher doping concentration than the second channel region; a first connector region and a second connector region, the first connector region laterally adjacent to the first source region and the second connector region laterally adjacent to the second source region, the first connector region and the second connector region having the same conductivity type as the first channel region and the second channel region and a higher doping concentration than the first channel region and the second channel region, the first connector region directly abutting the first shielding region and the second connector region directly abutting the second shielding region; a JFET region between the first channel region and the second channel region; and A body comprising: a gate electrode in a trench extending into the body and positioned between the first source region and the second source region; a gate insulating film between the gate electrode and the body, isolating the gate electrode from the body, the first source region and the second source region vertically overlap the gate electrode; the first channel region and the second channel region laterally overlap a bottom of the gate electrode; The first channel region and the second channel region do not overlap the gate electrode in the vertical direction, The first source region and the second source region are formed with a gate insulating film that does not overlap with a gate electrode along a vertical axis. A vertical field effect device comprising:

2. 2. The vertical field effect device of claim 1 , wherein first and second channels formed in the first and second channel regions between the JFET region and the first and second source regions have horizontal segments, each of the first and second channel regions laterally overlapping the bottom of the gate electrode.

3. 3. The vertical field effect device of claim 2, wherein said first and second channel regions do not vertically overlap said gate electrode.

4. The vertical field effect device of claim 2 , wherein the JFET region is further between the first and second shielding regions.

5. 5. The vertical field effect device of claim 4, wherein the first and second channel regions are closer to each other than the first and second shielding regions such that a portion of the JFET region between the first and second channel regions is narrower than a portion of the JFET region between the first and second shielding regions.

6. 3. The vertical field effect device of claim 2, wherein the first and second channel regions vertically overlap the gate electrode such that the first and second channels formed in the first and second channel regions between the JFET region and the first and second source regions have vertical segments in which the first and second channel regions vertically overlap the gate electrode.

7. 7. The vertical field effect device of claim 6, wherein no portion of said gate electrode laterally overlaps said first and second source regions.

8. 7. The vertical field effect device of claim 6, wherein the body further comprises a first shielding region laterally overlapping below the first channel region and a second shielding region laterally overlapping below the second channel region such that the JFET region is further between the first shielding region and the second shielding region.

9. 9. The vertical field effect device of claim 8, wherein the first and second channel regions are closer to each other than the first and second shielding regions such that a portion of the JFET region between the first and second channel regions is narrower than a portion of the JFET region between the first and second shielding regions.

10. the trench has a depth, measured from a top surface of the body to a bottom of the trench, of between 0.2 um and 0.8 um; 3. The vertical field effect device of claim 2, wherein the body further comprises a first shielding region that laterally overlaps below the first channel region and a second shielding region that laterally overlaps below the second channel region such that the first and second shielding regions are less than 2 micrometers deeper than the bottom of the trench.

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