Semiconductor Device

Abstract

The present invention provides a semiconductor element which is provided with a porous layer that is not susceptible to a strain and is capable of achieving good semiconductor characteristics, while having excellent planarity. A semiconductor element which comprises a semiconductor film and a porous layer that is arranged on a first surface of the semiconductor film or on a second surface that is on the reverse side of the first surface, wherein the porosity of the porous layer is 10% or less.

Description

[Technical field]

[0001] The present invention relates to a semiconductor element useful as a power device or the like. [Background technology]

[0002] Gallium oxide (Ga2O3) is a transparent semiconductor with a wide band gap of 4.8-5.3 eV at room temperature, which absorbs very little visible or ultraviolet light. Therefore, it is a promising material for use in optoelectronic devices and transparent electronics, particularly those operating in the deep ultraviolet region, and in recent years, photodetectors, light-emitting diodes (LEDs), and transistors based on Ga2O3 have been developed (see Non-Patent Document 1).

[0003] Gallium oxide (Ga2O3) has five crystal structures: α, β, γ, σ, and ε, and generally the most stable structure is β-Ga2O3. However, since β-Ga2O3 has a β-gallium structure, it is different from the crystal systems generally used in electronic materials and is not necessarily suitable for use in semiconductor devices. In addition, the growth of a β-Ga2O3 thin film requires a high substrate temperature and a high degree of vacuum, which increases the manufacturing cost. As described in Non-Patent Document 2, in β-Ga2O3, 19 / cm 3 Even a dopant (Si) of 1000 or more ions cannot be used as a donor unless it is annealed at high temperatures of 800°C to 1100°C after ion implantation. On the other hand, α-Ga2O3 has the same crystal structure as the widely used sapphire substrate, making it suitable for use in optical and electronic devices. Furthermore, since it has a wider band gap than β-Ga2O3, it is particularly useful in power devices. For these reasons, semiconductor devices using α-Ga2O3 as a semiconductor are eagerly awaited.

[0004] Patent Documents 1 and 2 describe semiconductor devices that use β-Ga2O3 as a semiconductor and, as electrodes that provide suitable ohmic characteristics, use two layers consisting of a Ti layer and an Au layer, three layers consisting of a Ti layer, an Al layer, and an Au layer, or four layers consisting of a Ti layer, an Al layer, a Ni layer, and an Au layer. Furthermore, Patent Document 3 describes a semiconductor device that uses β-Ga2O3 as a semiconductor and uses either Au, Pt, or a laminate of Ni and Au as an electrode that provides Schottky characteristics compatible with the semiconductor. However, when the electrodes described in Patent Documents 1 to 3 are applied to a semiconductor device using α-Ga2O3 as a semiconductor, there are problems such as the electrodes not functioning as Schottky electrodes or ohmic electrodes, the electrodes not bonding to the film, the semiconductor properties being impaired, etc. Furthermore, the electrode configurations described in Patent Documents 1 to 3 have not been satisfactory for practical use as a semiconductor device, such as leakage current occurring from the electrode end.

[0005] In addition, it is possible to use a conductive adhesive sheet when bonding the components, but this has problems such as poor flatness and a tendency for stress to concentrate, resulting in distortion, making it difficult to apply this to the semiconductor element itself. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2005-260101 A [Patent Document 2] JP 2009-81468 A [Patent Document 3] JP 2013-12760 A [Non-patent literature]

[0007] [Non-Patent Document 1] Jun Liang Zhao et al, “UV and Visible Electroluminescence From a Sn:Ga2O3 / n+-Si Heterojunction by Metal-Organic Chemical Vapor Deposition”, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO.5 MAY 2011 [Non-Patent Document 2] Kohei Sasaki et al, “Si-Ion Implantation Doping in β-Ga2O3 and Its Application to Fabrication of Low-Resistance Ohmic Contacts”, Applied Physics Express 6 (2013) 086502 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to provide a semiconductor element having a porous layer that is excellent in flatness and that can realize good semiconductor characteristics in which stress is relaxed and distortion is resistant. [Means for solving the problem]

[0009] As a result of intensive research to achieve the above-mentioned object, the inventors have discovered that by using a porous layer with a porosity of 10% or less in a semiconductor element, it is possible to obtain a semiconductor element having a porous layer that is excellent in flatness and is resistant to distortion, thereby enabling the realization of good semiconductor characteristics. After obtaining the above findings, the inventors conducted further studies and completed the present invention.

[0010] That is, the present invention relates to the following. [1] A semiconductor element comprising a semiconductor film and a porous layer disposed on a first surface side of the semiconductor film or on a second surface side opposite the first surface side, the porous layer having a porosity of 10% or less. [2] A semiconductor element comprising: a semiconductor film; and a porous layer disposed on a first surface side of the semiconductor film or on a second surface side opposite to the first surface side, the porous layer containing a precious metal. [3] The semiconductor element according to [1] or [2], wherein the semiconductor film is an oxide semiconductor film. [4] The semiconductor element according to any one of [1] to [3] above, wherein the semiconductor film has a corundum structure. [5] The semiconductor element according to any one of [1] to [4] above, wherein a main surface of the semiconductor film is an m-plane. [6] The semiconductor element according to any one of [1] to [5] above, wherein the semiconductor film contains gallium oxide and / or iridium oxide. [7] The semiconductor element according to any one of [1] to [6] above, wherein the semiconductor film contains a dopant. [8] The semiconductor device according to any one of [1] to [7] above, wherein the porous layer is a silver porous layer. [9] The semiconductor device according to any one of [1] to [8] above, further comprising a substrate bonded to the porous layer.

[10] The semiconductor element according to [9], wherein the substrate contains nickel on at least a portion of its surface.

[11] The semiconductor element according to [9], wherein the substrate comprises gold on at least a portion of its surface.

[12] The semiconductor element according to [3], further comprising a dielectric film covering at least a side surface of the oxide semiconductor film.

[13] The semiconductor element according to

[12] , wherein the dielectric film covers the entire side surface of the oxide semiconductor film.

[14] The semiconductor element according to

[12] or

[13] , wherein the dielectric film covers at least a portion of the first surface of the oxide semiconductor film.

[15] The semiconductor element according to any one of

[12] to

[14] above, wherein the oxide semiconductor film has a tapered side surface.

[16] The semiconductor element according to

[15] above, wherein a taper of a side surface of the oxide semiconductor film is inclined so as to widen from a first surface toward a second surface of the oxide semiconductor film.

[17] A semiconductor element having at least a semiconductor film, a first electrode arranged on a first surface side of the semiconductor film, and a second electrode arranged on a second surface side opposite the first surface side, further comprising a porous layer arranged in contact with the second electrode, wherein the porosity of the porous layer is 10% or less.

[18] The semiconductor element according to

[17] , wherein the second electrode includes at least a first metal layer, a second metal layer, and a third metal layer.

[19] The semiconductor element described in

[18] , characterized in that the second metal layer is disposed between the first metal layer and the third metal layer, and the second metal layer is a Pt layer or a Pd layer.

[20] The semiconductor element according to

[18] or

[19] , wherein the first metal layer is a Ti layer or an In layer.

[21] The semiconductor device according to any one of

[18] to

[20] above, wherein the third metal layer is at least one metal layer selected from an Au layer, an Ag layer, and a Cu layer.

[22] The semiconductor device according to any one of

[17] to

[21] , wherein the second electrode is an ohmic electrode.

[23] The semiconductor element according to any one of [1] to

[22] above, which is a vertical device.

[24] The semiconductor element according to any one of [1] to

[23] above, which is a power device.

[25] A semiconductor device comprising at least a semiconductor element bonded to a lead frame, a circuit board, or a heat dissipation board by a bonding member, the semiconductor element being the semiconductor element described in any one of [1] to

[24] .

[26] The semiconductor device according to

[25] , which is a power module, an inverter or a converter.

[27] The semiconductor device according to

[25] or

[26] above, which is a power card.

[28] A semiconductor system comprising a semiconductor element or a semiconductor device, wherein the semiconductor element is a semiconductor element described in any one of [1] to

[24] above, and the semiconductor device is a semiconductor device described in any one of

[25] to

[27] above. Effect of the Invention

[0011] The semiconductor element of the present invention has a porous layer that is excellent in flatness and that can realize good semiconductor characteristics in which stress is relieved and distortion is resistant, and has excellent structural stability. [Brief description of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor element according to a preferred embodiment of the present invention. [Diagram 2] 2A to 2C are diagrams illustrating an embodiment of a preferred method for manufacturing the semiconductor element of FIG. [Diagram 3] 2A to 2C are diagrams illustrating an embodiment of a preferred method for manufacturing the semiconductor element of FIG. [Figure 4] 2A to 2C are diagrams illustrating an embodiment of a preferred method for manufacturing the semiconductor element of FIG. [Diagram 5] 2A to 2C are diagrams illustrating an embodiment of a preferred method for manufacturing the semiconductor element of FIG. [Figure 6] 1 is a cross-sectional view illustrating a semiconductor element according to a preferred embodiment of the present invention. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor element according to a preferred embodiment of the present invention. [Figure 8] FIG. 1 shows cross-sectional SEM images of test examples, where (a) shows a porous layer made of silver formed by normal annealing, and (b) shows a porous layer that has been further subjected to thermocompression bonding to reduce the porosity to 10% or less. [Figure 9] FIG. 1 is a diagram illustrating a preferred example of a power supply system. [Figure 10] FIG. 1 is a diagram illustrating a preferred example of a system device. [Figure 11] FIG. 1 is a diagram illustrating a preferred example of a power supply circuit diagram of a power supply device. [Figure 12] 1A and 1B are diagrams illustrating a preferred example of a semiconductor device. [Figure 13] FIG. 2 is a diagram showing a schematic diagram of a preferred example of a power card. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The semiconductor element of the present invention includes a semiconductor film (hereinafter, also simply referred to as "semiconductor layer") and a porous layer disposed on the first surface side or the second surface side opposite to the first surface side of the semiconductor film, and is characterized in that the porosity of the porous layer is 10% or less. Here, "porosity" refers to the ratio of the volume of the space generated by the voids to the volume of the porous layer (volume including the voids). The porosity of the porous layer can be determined, for example, based on a cross-sectional photograph taken using a scanning electron microscope (SEM). Specifically, cross-sectional photographs (SEM images) of the porous layer are taken at multiple positions. Next, the taken SEM images are binarized using commercially available image analysis software, and the ratio of the parts (e.g., black parts) corresponding to holes (voids) in the SEM images is determined. The ratios of the black parts determined from the SEM images taken at multiple positions are averaged to determine the porosity of the porous layer. The "porous layer" includes not only a porous film-like structure that is a continuous film-like structure, but also a porous aggregate-like structure.

[0014] The porous layer is not particularly limited, but preferably contains a metal, more preferably contains a precious metal such as gold (Au), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), or ruthenium (Ru), and most preferably contains silver (Ag). The porous layer may be a porous substrate coated with a metal film of the precious metal, but in the present invention, it is preferably a porous layer of the metal, more preferably a porous layer of the precious metal, and most preferably a porous layer of silver (Ag). The porous layer may be a single layer or a multilayer. The thickness of the porous layer is not particularly limited as long as it does not impede the object of the present invention, but is preferably about 10 nm to about 1 mm, preferably 10 nm to 200 μm, and more preferably 30 nm to 50 μm.

[0015] The porous layer can be suitably obtained by sintering a metal (preferably a noble metal). The means for making the porosity of the porous layer 10% is not particularly limited and may be a known means. By appropriately setting sintering conditions such as sintering time, pressure, and sintering temperature, the porosity of the porous layer can be easily made 10%. For example, a means for adjusting the porosity to 10% or less by pressure bonding under heating (thermocompression bonding) or the like can be mentioned. More specifically, for example, a sintering time longer than usual under a certain pressure can be mentioned. FIG. 8(a) shows the porosity when a porous layer made of Ag is bonded by normal annealing as a test example. As shown in Figure 8(a), the porosity of the porous layer usually exceeds 10%, but as shown in Figure 8(b), if the layer is heated to, for example, 300°C to 500°C and pressed under a pressure of, for example, 0.2 MPa to 10 MPa for an additional hour, the porosity becomes 10% or less. By using such a porous layer with a porosity of 10% or less in a semiconductor element, it is possible to reduce warping, concentration of thermal stress, and the like, without impairing the semiconductor characteristics.

[0016] The semiconductor element of the present invention includes a semiconductor film and a porous layer disposed on a first surface side of the semiconductor film or a second surface side opposite to the first surface side, and the porous layer contains a precious metal. In this case, it is more preferable that the porosity of the porous layer is 10% or less.

[0017] In the present invention, it is preferable that the semiconductor element has at least a semiconductor film, a first electrode arranged on a first surface side of the semiconductor film, and a second electrode arranged on a second surface side opposite the first surface side, and further includes a porous layer arranged in contact with the second electrode, and the porosity of the porous layer is 10% or less; and it is more preferable that the semiconductor element has at least a semiconductor film, a first electrode arranged on the first surface side of the semiconductor film, and a second electrode arranged on the second surface side opposite the first surface side, and further includes a porous layer arranged in contact with the second electrode and a substrate arranged on the porous layer, the second electrode includes at least a first metal layer, a second metal layer, and a third metal layer, and the porosity of the porous layer is 10% or less.

[0018] The substrate is not particularly limited, but is preferably a conductive substrate. The conductive substrate is not particularly limited as long as it has conductivity and can support a semiconductor layer. The material of the conductive substrate is also not particularly limited as long as it does not impede the object of the present invention. Examples of the material of the conductive substrate include metals (e.g., aluminum, nickel, chromium, nichrome, copper, gold, silver, platinum, rhodium, indium, molybdenum, and tungsten) or conductive metal oxides (e.g., ITO (InSnO compound), FTO (tin oxide doped with fluorine, etc.), zinc oxide, etc.), silicon (Si), and conductive carbon. In the present invention, the conductive substrate preferably contains a transition metal, more preferably contains at least one metal selected from Groups 6 and 11 of the periodic table, and preferably contains a metal of Group 6 of the periodic table. Examples of metals of Group 6 of the periodic table include at least one metal selected from chromium (Cr), molybdenum (Mo), and tungsten (W). In the present invention, the metal in Group 6 of the periodic table preferably includes molybdenum. Examples of the metal in Group 11 of the periodic table include at least one metal selected from copper (Cu), silver (Au) and gold (Au). In the present invention, it is also preferable that the conductive substrate contains two or more kinds of metals, and examples of such combinations of two or more kinds of metals include copper (Cu)-silver (Ag), copper (Cu)-tin (Sn), copper (Cu)-iron (Fe), copper (Cu)-tungsten (W), copper (Cu)-molybdenum (Mo), copper (Cu)-titanium (Ti), molybdenum (Mo)-lanthanum (La), molybdenum (Mo)-yttrium (Y), molybdenum (Mo)-rhenium (Re), molybdenum (Mo)-tungsten (W), molybdenum (Mo)-niobium (Nb), and molybdenum (Mo)-tantalum (Ta). In the present invention, it is preferable that the conductive substrate contains molybdenum as a main component, and more preferably contains molybdenum and copper. Here, the term "main component" means that, for example, when the conductive substrate contains Mo as a main component, Mo is contained in an atomic ratio of preferably 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the conductive substrate, and may be 100%.By using such a preferred conductive substrate material, the preferred conductive adhesive layer, and the preferred semiconductor layer in combination, the semiconductor characteristics of the preferred semiconductor layer can be better expressed in the semiconductor element. In the present invention, the substrate preferably contains nickel on at least a part of the surface of the substrate, and also preferably contains gold on at least a part of the surface of the substrate. The substrate may be attached to the porous layer via one or more other layers, such as an adhesive layer (eg, an adhesive layer made of a conductive adhesive or metal).

[0019] The semiconductor film is not particularly limited as long as it is a film containing a semiconductor, and may be an oxide semiconductor film, preferably contains a crystalline oxide semiconductor, and more preferably contains a crystalline oxide semiconductor as a main component. In the present invention, the crystalline oxide semiconductor preferably contains one or more metals selected from Group 9 (e.g., cobalt, rhodium, or iridium) and Group 13 (e.g., aluminum, gallium, or indium) of the periodic table, more preferably contains at least one metal selected from aluminum, indium, gallium, and iridium, and most preferably contains at least gallium or iridium. The crystal structure of the crystalline oxide semiconductor is also not particularly limited. Examples of the crystal structure of the crystalline oxide semiconductor include a corundum structure, a β-gallium structure, and a hexagonal structure (e.g., an ε-type structure). In the present invention, the crystalline oxide semiconductor preferably has a corundum structure, and more preferably has a corundum structure and further has an m-plane as the main surface. The crystalline oxide semiconductor may have an off-angle. In the present invention, the semiconductor film preferably contains gallium oxide and / or iridium oxide, and more preferably contains α-Ga2O3 and / or α-Ir2O3. The term "main component" means that the crystalline oxide semiconductor is contained in an atomic ratio of preferably 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the semiconductor layer, and may be 100%. The thickness of the semiconductor layer is not particularly limited, and may be 1 μm or less or 1 μm or more, but in the present invention, it is preferably 1 μm or more, and more preferably 10 μm or more. The surface area of ​​the semiconductor film is not particularly limited, but is preferably 1 mm 2 May be more than 1mm 2 May be less than 10mm 2 ~300cm 2 Preferably, 100 mm 2 ~100cm 2It is more preferable that the semiconductor layer is a multilayer film including at least a first semiconductor layer and a second semiconductor layer. When a Schottky electrode is provided on the first semiconductor layer, the semiconductor layer is preferably a multilayer film in which the carrier density of the first semiconductor layer is smaller than the carrier density of the second semiconductor layer. In this case, the second semiconductor layer usually contains a dopant, and the carrier density of the semiconductor layer can be appropriately set by adjusting the doping amount.

[0020] The semiconductor layer preferably contains a dopant. The dopant is not particularly limited and may be a known one. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, or p-type dopants such as magnesium, calcium, or zinc. In the present invention, the n-type dopant is preferably Sn, Ge, or Si. The content of the dopant in the composition of the semiconductor layer is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and most preferably 0.00001 atomic % to 10 atomic %. More specifically, the concentration of the dopant is usually about 1×10 16 / cm 3 ~1×10 22 / cm 3 Alternatively, the concentration of the dopant may be, for example, about 1×10 17 / cm 3 According to one embodiment of the present invention, the dopant may be at a low concentration of about 1×10 20 / cm 3 The concentration of the fixed charges in the semiconductor layer is not particularly limited, but in the present invention, it is preferably 1×10 17 / cm 3 The above-mentioned range is preferable because a depletion layer can be formed satisfactorily in the semiconductor layer.

[0021] The semiconductor layer may be formed by using a known means. Examples of the means for forming the semiconductor layer include a CVD method, an MOCVD method, an MOVPE method, a mist CVD method, a mist epitaxy method, an MBE method, an HVPE method, a pulse growth method, and an ALD method. In the present invention, the means for forming the semiconductor layer is preferably a mist CVD method or a mist epitaxy method. In the mist CVD method or the mist epitaxy method, for example, a raw material solution is atomized (atomization process), the droplets are suspended, and after atomization, the obtained atomized droplets are transported to a substrate by a carrier gas (transportation process), and then the atomized droplets are thermally reacted near the substrate to laminate a semiconductor film containing a crystalline oxide semiconductor as a main component on the substrate (film formation process), thereby forming the semiconductor layer.

[0022] (Atomization process) In the atomization step, the raw solution is atomized. The atomization means for the raw solution is not particularly limited as long as it can atomize the raw solution, and may be a known means, but in the present invention, an atomization means using ultrasonic waves is preferable. The atomized droplets obtained using ultrasonic waves have an initial velocity of zero and are preferably suspended in the air. For example, they are not sprayed like a spray, but are atomized droplets (including mist) that can be suspended in space and transported as a gas, so they are very suitable because they are not damaged by collision energy. The droplet size is not particularly limited, and may be droplets of about several mm, but is preferably 50 μm or less, and more preferably 100 nm to 10 μm.

[0023] (Raw material solution) The raw material solution is not particularly limited as long as it can be atomized or turned into droplets and contains a raw material capable of forming a semiconductor film, and may be an inorganic material or an organic material. In the present invention, the raw material is preferably a metal or a metal compound, and more preferably contains one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt, and iridium.

[0024] In the present invention, the raw material solution can be suitably used in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or salt. Examples of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, and hydride complexes. Examples of the salt include organic metal salts (e.g., metal acetates, metal oxalates, and metal citrates), metal sulfides, metal nitrates, metal phosphates, and metal halides (e.g., metal chlorides, metal bromides, and metal iodides).

[0025] In addition, it is preferable to mix additives such as hydrohalogenated acid and oxidizing agents into the raw material solution. Examples of the hydrohalogenated acid include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Among them, hydrobromic acid and hydroiodic acid are preferable because they can more efficiently suppress the generation of abnormal grains. Examples of the oxidizing agent include peroxides such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), and benzoyl peroxide (C6H5CO)2O2, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.

[0026] The raw material solution may contain a dopant. By adding a dopant to the raw material solution, doping can be performed well. The dopant is not particularly limited as long as it does not impede the object of the present invention. Examples of the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, and p-type dopants such as Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, or P. The content of the dopant is appropriately set by using a calibration curve showing the relationship between the concentration of the dopant in the raw material and the desired carrier density.

[0027] The solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present invention, the solvent preferably contains water, and more preferably is water or a mixed solvent of water and alcohol.

[0028] (Transportation process) In the transport step, the atomized droplets are transported into the film-forming chamber by a carrier gas. The carrier gas is not particularly limited as long as it does not impede the object of the present invention, and suitable examples include inert gases such as oxygen, ozone, nitrogen, and argon, and reducing gases such as hydrogen gas and forming gas. The type of carrier gas may be one type, but may be two or more types, and a dilution gas with a reduced flow rate (for example, a 10-fold dilution gas, etc.) may be further used as a second carrier gas. The number of supply points of the carrier gas may be not only one but also two or more. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 1 to 10 L / min. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 to 2 L / min, and more preferably 0.1 to 1 L / min.

[0029] (Film forming process) In the film-forming step, the mist droplets are thermally reacted in the vicinity of the substrate to form the semiconductor film on the substrate. The thermal reaction may be performed as long as the mist droplets react with heat, and the reaction conditions are not particularly limited as long as the object of the present invention is not hindered. In this step, the thermal reaction is usually performed at a temperature equal to or higher than the evaporation temperature of the solvent, but is preferably not too high (for example, 1000°C) or lower, more preferably 650°C or lower, and most preferably 300°C to 650°C. In addition, the thermal reaction may be performed under any of the following atmospheres: vacuum, non-oxygen atmosphere (for example, inert gas atmosphere, etc.), reducing gas atmosphere, and oxygen atmosphere, as long as the object of the present invention is not hindered. However, it is preferable to perform the thermal reaction under an inert gas atmosphere or oxygen atmosphere. In addition, the thermal reaction may be performed under any of the following conditions: atmospheric pressure, pressurized, and reduced pressure, but in the present invention, it is preferable to perform the thermal reaction under atmospheric pressure. The thickness of the semiconductor film can be set by adjusting the film-forming time.

[0030] (Base) The substrate is not particularly limited as long as it can support the semiconductor film. The material of the substrate is not particularly limited as long as it does not impede the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound. The substrate may have any shape, and is effective for any shape, such as a plate shape such as a flat plate or a disk, a fiber shape, a rod shape, a column shape, a prism shape, a tube shape, a spiral shape, a sphere shape, a ring shape, etc., but in the present invention, a substrate is preferred. The thickness of the substrate is not particularly limited in the present invention.

[0031] The substrate is not particularly limited as long as it is plate-shaped and serves as a support for the semiconductor film. It may be an insulating substrate, a semiconductor substrate, a metal substrate, or a conductive substrate, but the substrate is preferably an insulating substrate, and is also preferably a substrate having a metal film on its surface. Examples of the substrate include a substrate containing a substrate material having a corundum structure as a main component, a substrate containing a substrate material having a β-gallium structure as a main component, and a substrate containing a substrate material having a hexagonal crystal structure as a main component. Here, the term "main component" means that the substrate material having the specific crystal structure is preferably contained in an atomic ratio of 50% or more, more preferably 70% or more, and even more preferably 90% or more of the total components of the substrate material, and may be 100%.

[0032] The substrate material is not particularly limited, and may be any known material, so long as it does not impede the object of the present invention. Suitable examples of the substrate material having the corundum structure include α-Al2O3 (sapphire substrate) or α-Ga2O3, and more suitable examples include a-plane sapphire substrate, m-plane sapphire substrate, r-plane sapphire substrate, c-plane sapphire substrate, and α-type gallium oxide substrate (a-plane, m-plane, or r-plane). Examples of the base substrate mainly made of a substrate material having a β-gallium structure include a β-Ga2O3 substrate, or a mixed crystal substrate containing Ga2O3 and Al2O3, with Al2O3 being more than 0 wt% and 60 wt% or less. Examples of the base substrate mainly made of a substrate material having a hexagonal structure include a SiC substrate, a ZnO substrate, and a GaN substrate.

[0033] In the present invention, an annealing treatment may be performed after the film formation step. The annealing temperature is not particularly limited as long as it does not impede the object of the present invention, and is usually 300°C to 650°C, and preferably 350°C to 550°C. The annealing time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. The annealing may be performed in any atmosphere as long as it does not impede the object of the present invention. It may be a non-oxygen atmosphere or an oxygen atmosphere. Examples of the non-oxygen atmosphere include an inert gas atmosphere (e.g., a nitrogen atmosphere) or a reducing gas atmosphere, and in the present invention, an inert gas atmosphere is preferable, and a nitrogen atmosphere is more preferable.

[0034] In the present invention, the semiconductor film may be provided directly on the substrate, or may be provided via another layer such as a stress relaxation layer (e.g., a buffer layer, an ELO layer, etc.), a peeling sacrificial layer, etc. The means for forming each layer is not particularly limited and may be a known means, but in the present invention, a mist CVD method is preferred.

[0035] In the present invention, the semiconductor film may be used as the semiconductor layer in a semiconductor element after being peeled off from the base or the like by a known means, or may be used as it is in a semiconductor element as the semiconductor layer.

[0036] In the present invention, the second electrode is preferably an ohmic electrode. The ohmic electrode includes at least a first metal layer, a second metal layer, and a third metal layer, the second metal layer being disposed between the first metal layer and the third metal layer, and the second metal layer is preferably a Pt layer or a Pd layer. The first metal layer, the second metal layer, and the third metal layer are usually composed of one or more different metals. In the present invention, the first metal layer of the ohmic electrode is preferably a Ti layer or an In layer. It is also preferable that the third metal layer of the ohmic electrode is at least one metal layer selected from an Au layer, an Ag layer, and a Cu layer. The thickness of each metal layer of the ohmic electrode is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm.

[0037] In the present invention, the first electrode is preferably a Schottky electrode. The Schottky electrode (hereinafter, simply referred to as "electrode layer") is not particularly limited as long as it has conductivity and can be used as a Schottky electrode, as long as it does not impede the object of the present invention. The material of the electrode layer may be a conductive inorganic material or a conductive organic material. In the present invention, the material of the electrode is preferably a metal. The metal is preferably at least one metal selected from Groups 4 to 11 of the periodic table. Examples of metals in Group 4 of the periodic table include titanium (Ti), zirconium (Zr), and hafnium (Hf). Examples of metals in Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta). Examples of metals in Group 6 of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W). Examples of metals in Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re). Examples of metals in Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os). Examples of metals in Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir). Examples of metals in Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt). Examples of metals in Group 11 of the periodic table include copper (Cu), silver (Ag), and gold (Au). In the present invention, it is preferable that the Schottky electrode contains molybdenum and / or cobalt. The thickness of the electrode layer is not particularly limited, but is preferably 0.1 nm to 10 μm, more preferably 5 nm to 500 nm, and most preferably 10 nm to 200 nm. In the present invention, it is preferable that the electrode layer is composed of two or more layers having different compositions. By forming the electrode layer in such a preferred configuration, not only can a semiconductor element having better Schottky characteristics be obtained, but also the effect of suppressing leakage current can be more effectively achieved.

[0038] In the present invention, the Schottky electrode preferably includes at least a first metal layer, a second metal layer, and a third metal layer. The first metal layer of the Schottky electrode is preferably a transition metal layer, more preferably a Mo and / or Co layer, and most preferably a Co layer or a Mo layer. The second metal layer of the Schottky electrode is preferably a Ti layer, and the third metal layer of the Schottky electrode is preferably an Al layer.

[0039] The means for forming the electrode layer is not particularly limited and may be a known means. Specific examples of the means for forming the electrode layer include a dry method and a wet method. Examples of the dry method include sputtering, vacuum deposition, and CVD. Examples of the wet method include screen printing and die coating.

[0040] In one aspect of the present invention, the Schottky electrode preferably has a structure in which the thickness decreases toward the outside of the semiconductor element. In this case, the Schottky electrode may have a tapered region on the side surface, or the Schottky electrode may be composed of two or more layers including a first electrode layer and a second electrode layer, and the outer end of the first electrode layer may be located outside the outer end of the second electrode layer. In one aspect of the present invention, when the Schottky electrode has a tapered region, the taper angle of the tapered region is not particularly limited as long as it does not impede the object of the present invention, but is preferably 80° or less, more preferably 60° or less, and most preferably 40° or less. The lower limit of the taper angle is also not particularly limited, but is preferably 0.2°, and more preferably 1°. In one aspect of the present invention, when the outer end of the first electrode layer of the Schottky electrode is located outside the outer end of the second electrode layer, it is preferable that the distance between the outer end of the first electrode layer and the outer end of the second electrode layer is 1 μm or more, since this can further suppress leakage current. In one aspect of the present invention, it is also preferable that at least a part of the first electrode layer of the Schottky electrode that protrudes outward beyond the outer end of the second electrode layer (hereinafter also referred to as the "protruding part") has a structure in which the film thickness decreases toward the outside of the semiconductor element, since this structure can improve the voltage resistance of the semiconductor element. Moreover, by combining such a preferable electrode configuration with the above-mentioned preferable constituent material of the semiconductor layer, a semiconductor element with better suppression of leakage current and lower loss can be obtained. EXAMPLES

[0041] Preferred embodiments of the present invention will now be described in more detail with reference to the drawings, but the present invention is not limited to these embodiments.

[0042] FIG. 1 shows a main part of a Schottky barrier diode (SBD) as a semiconductor element according to a preferred embodiment of the present invention. The semiconductor element includes at least a semiconductor layer 101 and a porous layer 108 having a porosity of 10% or less, which is disposed on a first surface side of the semiconductor layer 101 or on a second surface side opposite to the first surface side. The SBD in FIG. 1 further includes an ohmic electrode 102, a Schottky electrode 103, and a dielectric film 104. The ohmic electrode 102 includes a metal layer 102a, a metal layer 102b, and a metal layer 102c. The semiconductor layer 101 includes a first semiconductor layer 101a and a second semiconductor layer 101b. The Schottky electrode 103 includes a metal layer 103a, a metal layer 103b, and a metal layer 103c. The first semiconductor layer 101a is, for example, an n-type semiconductor layer, and the second semiconductor layer 101b is, for example, an n+ type semiconductor layer 101b. Moreover, the dielectric film 104 (hereinafter, sometimes referred to as "insulator film") covers the side surfaces of the semiconductor layer 101 (the side surfaces of the first semiconductor layer 101a and the second semiconductor layer 101b) and has an opening located on the upper surface of the semiconductor layer 101 (the first semiconductor layer 101a), and the opening is provided between a part of the first semiconductor layer 101a and the metal layer 103c of the Schottky electrode 103. Moreover, in this embodiment, the side surface of the semiconductor layer 101 has a taper. The dielectric film 104 may be extended so as to cover the taper of the side surface of the semiconductor layer 101 and further cover a part of the upper surface of the semiconductor layer 101 (the first semiconductor layer 101a). The taper of the side surface of the semiconductor layer 101 is inclined so as to widen from the first surface of the semiconductor layer 101 toward the second surface opposite to the first surface. 1, the crystal defects at the edge are improved, a depletion layer is better formed, the electric field relaxation is further improved, and the leakage current can be better suppressed by the dielectric film 104. In this embodiment, the porous layer 108 is disposed on the ohmic electrode 102 (metal layer 102c), and the semiconductor element further has a substrate 109 disposed on the porous layer 108.

[0043] The dielectric film preferably has a taper angle. The means for forming such a taper angle is not particularly limited, and in the present invention, the taper angle can be formed by a known method. A suitable means for forming the taper angle is, for example, a means for forming a thin film having a faster etching rate than the dielectric film on the dielectric film, applying a resist to the thin film, and forming the taper angle by photolithography and etching. Moreover, the taper angle of the dielectric film is preferably 20° or less, and more preferably 10° or less. In the present invention, the lower limit of the taper angle is not particularly limited, but is preferably 0.2°, more preferably 1.0°, and most preferably 2.2°. In the present invention, it is preferable that the dielectric film covers the entire side surface of the oxide semiconductor layer, since this can better suppress the diffusion of oxygen, etc. Also, in the present invention, it is preferable that the dielectric film covers at least a part of the first surface of the oxide semiconductor layer, since this can improve the semiconductor characteristics, such as the breakdown voltage.

[0044] FIG. 6 shows a main part of a Schottky barrier diode (SBD) as a semiconductor element according to a preferred embodiment of the present invention. The SBD in FIG. 6 is different from the SBD in FIG. 1 in that it has a tapered region on the side of the Schottky electrode 103. In the semiconductor element in FIG. 6, the outer end of the metal layer 103b and / or the metal layer 103c as the first metal layer is located outside the outer end of the metal layer 103a as the second metal layer, so that the leakage current can be suppressed more effectively. Furthermore, the part of the metal layer 103b and / or the metal layer 103c that protrudes outward from the outer end of the metal layer 103a has a tapered region in which the film thickness decreases toward the outside of the semiconductor element, so that the semiconductor element has a configuration with better voltage resistance.

[0045] Examples of the material of the metal layer 103a include the metals exemplified above as the material of the second electrode layer. Examples of the material of the metal layer 103b and the metal layer 103c include the metals exemplified above as the material of the first electrode layer. The means for forming each layer in FIG. 1 is not particularly limited as long as it does not impede the object of the present invention, and may be a known means. For example, a means for forming a film by a vacuum deposition method, a CVD method, a sputtering method, or various coating techniques, followed by patterning by a photolithography method, or a means for directly patterning by a printing technique, etc., may be used.

[0046] A preferred manufacturing process for the SBD of FIG. 1 will be described below, but the present invention is not limited to these preferred manufacturing methods. FIG. 2(a) shows a stack in which a first semiconductor layer 101a and a second semiconductor layer 101b are stacked on a crystal growth substrate (sapphire substrate) 110 via a stress relaxation layer by the mist CVD method described above. Metal layers 102a, 102b, and 102c are formed as ohmic electrodes on the second semiconductor layer 101b by the dry method or the wet method, to obtain the stack in FIG. 2(b). The first semiconductor layer 101a is, for example, an n-type semiconductor layer, and the second semiconductor layer 101b is, for example, an n+type semiconductor layer 101b. A substrate 109 is stacked on the stack in FIG. 2(b) via a porous layer 108 made of a noble metal, to obtain a stack (c). Then, as shown in Fig. 3, the crystal growth substrate 110 and the stress relaxation layer 111 of the laminate (c) are peeled off by a known peeling means to obtain a laminate (d). Then, as shown in Fig. 4, the side surface of the semiconductor layer of the laminate (d) is tapered by etching to obtain a laminate (e), and then the insulating film 104 is laminated on the tapered side surface and the upper surface of the semiconductor layer other than the opening, to obtain a laminate (f). Note that during the manufacturing process, the outer end of the insulating film 104 and the outer end of the metal layer 102a are formed so as to have a step with respect to the outer ends of the layers below (metal layer 102b, metal layer 102c, porous layer 108, substrate 109), but the insulating film 104 may be laminated so that these steps are hardly generated as in the laminate (e). Next, as shown in Fig. 5, metal layers 103a, 103b, and 103c are formed as Schottky electrodes at the upper opening of the semiconductor layer of the laminate (f) by the dry method or the wet method to obtain a laminate (g). The semiconductor element obtained in this manner can effectively suppress the diffusion of oxygen and the like in the semiconductor layer, exhibit excellent ohmic characteristics, improve crystal defects at the edge, form a better depletion layer, further improve the electric field relaxation, and can effectively suppress leakage current. When an SBD was fabricated according to the above preferred embodiment, it was confirmed by a microscope that the dielectric film was well laminated on the semiconductor layer, had no particular cracks or irregularities, was excellent in flatness, and was not distorted.The prototype of this embodiment was evaluated for performance in a power cycle test, completing 3000 cycles in 5 minutes, and the evaluation results were good. In addition, when confirmed by SEM-EDS, it was found that the diffusion of oxygen and the like was suppressed. In addition, in this embodiment, as shown in FIG. 8(b), a porous layer with a porosity of 10% or less is used.

[0047] Furthermore, even in the case of an SBD using a semiconductor layer 101 made of an oxide semiconductor and a porous layer 108 made of silver, there are no particular cracks or unevenness, warping is suppressed, and stress relaxation works well, as described above.

[0048] Furthermore, by covering at least the side surfaces of the oxide semiconductor layer with the insulator film (dielectric film) 104, it is possible to suppress the diffusion of oxygen and moisture absorption by the oxide semiconductor, and the inflow of oxygen from the atmosphere, etc., thereby achieving good semiconductor characteristics.

[0049] Fig. 7 shows the main part of a Schottky barrier diode (SBD) as a semiconductor element according to one preferred embodiment of the present invention. (Note that the porous layer 108 and substrate 109 are omitted from the illustration, as they are the same as those in Fig. 6.) The SBD in Fig. 7 differs from the SBD in Fig. 6 in that no tapered region is provided on the side of the Schottky electrode 103 in Fig. 1, and the outer end of the insulating film 104 covering the semiconductor layer 101 and the outer end of the ohmic electrode 102 are flush with each other without any steps. Even with this configuration, the effects of the present invention can be expected.

[0050] The semiconductor element is preferably a vertical device, and is particularly useful as a power device. Examples of the semiconductor element include diodes (e.g., PN diodes, Schottky barrier diodes, junction barrier Schottky diodes, etc.) and transistors (e.g., MOSFETs, MESFETs, etc.), among which diodes are preferred, and Schottky barrier diodes (SBDs) are more preferred.

[0051] In addition to the above, the semiconductor element of the present invention is preferably used as a semiconductor device by bonding to a lead frame, a circuit board, a heat dissipation board, or the like by a bonding member by a known method, and is particularly preferably used as a power module, an inverter, or a converter, and further preferably used in a semiconductor system using, for example, a power supply device. A preferred example of the semiconductor device is shown in FIG. 12. In the semiconductor device of FIG. 12, both sides of a semiconductor element 500 are bonded to a lead frame, a circuit board, or a heat dissipation board 502 by solder 501, respectively. By configuring in this way, a semiconductor device with excellent heat dissipation properties can be obtained. In the present invention, it is preferable that the periphery of the bonding member such as solder is sealed with resin. Such a semiconductor device is also included in the present invention.

[0052] Moreover, the power supply device can be fabricated from the semiconductor device or as the semiconductor device by connecting to a wiring pattern or the like using a known method. FIG. 9 shows a power supply system 170 configured using a plurality of the power supply devices 171, 172 and a control circuit 173. The power supply system can be used in a system device 180 by combining an electronic circuit 181 and a power supply system 182 as shown in FIG. 10. FIG. 11 shows an example of a power supply circuit diagram of a power supply device. FIG. 11 shows a power supply circuit of a power supply device configured of a power circuit and a control circuit, in which a DC voltage is switched at high frequency by an inverter 192 (configured by MOSFETs A to D) and converted to AC, then insulated and transformed by a transformer 193, rectified by a rectifying MOSFET 194 (A to B'), smoothed by a DCL 195 (smoothing coils L1, L2) and a capacitor, and a DC voltage is output. At this time, a voltage comparator 197 compares the output voltage with a reference voltage, and a PWM control circuit 196 controls the inverter 192 and the rectifying MOSFET 194 so as to obtain a desired output voltage.

[0053] In the present invention, the semiconductor device is preferably a power card, and includes a cooler and an insulating member. More preferably, the cooler is provided on both sides of the semiconductor layer via at least the insulating member, and most preferably, a heat dissipation layer is provided on both sides of the semiconductor layer, and the cooler is provided on the outside of the heat dissipation layer via at least the insulating member. FIG. 13 shows a power card according to a preferred embodiment of the present invention. The power card in FIG. 13 is a double-sided cooling type power card 201, and includes a refrigerant tube 202, a spacer 203, an insulating plate (insulating spacer) 208, a sealing resin part 209, a semiconductor chip 301a, a metal heat transfer plate (protruding terminal part) 302b, a heat sink and electrode 303, a metal heat transfer plate (protruding terminal part) 303b, a solder layer 304, a control electrode terminal 305, and a bonding wire 308. The thickness direction cross section of the refrigerant tube 202 has many flow paths 222 partitioned by many partition walls 221 extending in the flow path direction at a predetermined interval from each other. Such a suitable power card can realize higher heat dissipation and can satisfy higher reliability.

[0054] The semiconductor chip 301a is joined to the inner main surface of the metal heat transfer plate 302b with a solder layer 304, and the metal heat transfer plate (protruding terminal portion) 302b is joined to the remaining main surface of the semiconductor chip 301a with a solder layer 304, so that the anode electrode surface and the cathode electrode surface of the flywheel diode are connected in so-called anti-parallel to the collector electrode surface and the emitter electrode surface of the IGBT. Examples of materials for the metal heat transfer plates (protruding terminal portions) 302b and 303b include Mo and W. The metal heat transfer plates (protruding terminal portions) 302b and 303b have a thickness difference that absorbs the thickness difference of the semiconductor chip 301a, and therefore the outer surfaces of the metal heat transfer plates 302b and 303b are flat.

[0055] Resin sealing portion 209 is made of, for example, epoxy resin, and is molded to cover the side surfaces of metal heat transfer plates 302b and 303b, and semiconductor chip 301a is molded with resin sealing portion 209. However, the outer main surfaces, i.e., the contact heat receiving surfaces, of metal heat transfer plates 302b and 303b are completely exposed. Metal heat transfer plates (protruding terminal portions) 302b and 303b protrude from resin sealing portion 209 to the right in Fig. 13, and control electrode terminal 305, which is a so-called lead frame terminal, connects, for example, the gate (control) electrode surface of semiconductor chip 301a on which an IGBT is formed to control electrode terminal 305.

[0056] The insulating plate 208, which is an insulating spacer, is made of, for example, an aluminum nitride film, but may be another insulating film. The insulating plate 208 completely covers and adheres to the metal heat transfer plates 302b and 303b, but the insulating plate 208 and the metal heat transfer plates 302b and 303b may simply be in contact with each other, or may be coated with a good heat transfer material such as silicon grease, or may be joined by various methods. Also, an insulating layer may be formed by ceramic spraying, or the insulating plate 208 may be joined to the metal heat transfer plate, or may be joined or formed on the refrigerant tube.

[0057] The refrigerant tubes 202 are made by cutting a plate material formed by pultrusion or extrusion of an aluminum alloy to a required length. The thickness direction cross section of the refrigerant tubes 202 has many flow paths 222 partitioned by many partition walls 221 extending in the flow path direction at a predetermined interval from each other. The spacer 203 may be, for example, a soft metal plate such as a solder alloy, or may be a film formed by coating or the like on the contact surface of the metal heat transfer plates 302b and 303b. The surface of this soft spacer 203 is easily deformed and fits the minute unevenness and warping of the insulating plate 208 and the minute unevenness and warping of the refrigerant tubes 202 to reduce thermal resistance. Note that a known good thermal conductive grease or the like may be applied to the surface of the spacer 203, or the spacer 203 may be omitted. [Industrial Applicability]

[0058] The semiconductor element of the present invention can be used in a wide variety of fields, including semiconductors (eg, compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic related devices, and industrial materials, but is particularly useful as a power device. [Explanation of symbols]

[0059] 101 Semiconductor layer 101a First semiconductor layer 101b Second semiconductor layer 102 Ohmic electrode 102a metal layer 102b Metal layer 102c metal layer 103 Schottky electrode 103a Metal layer 103b Metal layer 103c metal layer 104 Insulating film (dielectric film) 108 Porous Layer 109 Board 110 Crystal growth substrate 170 Power System 171 Power supply 172 Power supply 173 Control circuit 180 System Unit 181 Electronic circuit 182 Power System 192 Inverter 193 Trans 194 Rectifier MOSFET 195 DCL 196 PWM control circuit 197 Voltage Comparator 201 Double-sided cooled power card 202 Refrigerant tube 203 Spacer 208 Insulating plate (insulating spacer) 209 Sealing resin part 221 Bulkhead 222 Channel 301a Semiconductor chip 302b Metal heat transfer plate (protruding terminal part) 303 Heat sink and electrodes 303b Metal heat transfer plate (protruding terminal part) 304 solder layer 305 Control electrode terminal 308 Bonding Wire 500 Semiconductor elements 501 Solder 502 Lead frames, circuit boards or heat dissipation boards

Claims

1. A semiconductor element comprising a semiconductor film and a porous layer disposed on a first surface side of the semiconductor film or on a second surface side opposite the first surface side, the porous layer having a porosity of 10% or less.

2. A semiconductor element comprising: a semiconductor film; and a porous layer disposed on a first surface side of the semiconductor film or on a second surface side opposite to the first surface side, the porous layer containing a precious metal.

3. 3. The semiconductor device according to claim 1, wherein the semiconductor film is an oxide semiconductor film.

4. 4. The semiconductor device according to claim 1, wherein the semiconductor film has a corundum structure.

5. 5. The semiconductor device according to claim 1, wherein a main surface of the semiconductor film is an m-plane.

6. 6. The semiconductor device according to claim 1, wherein the semiconductor film contains gallium oxide and / or iridium oxide.

7. The semiconductor device according to claim 1 , wherein the semiconductor film contains a dopant.

8. 8. The semiconductor device according to claim 1, wherein the porous layer is a silver porous layer.

9. The semiconductor device according to any one of claims 1 to 8, further comprising a substrate attached to the porous layer.

10. The semiconductor device of claim 9 , wherein the substrate comprises nickel on at least a portion of a surface thereof.

11. The semiconductor device of claim 9 , wherein the substrate comprises gold on at least a portion of a surface thereof.

12. The semiconductor device according to claim 3 , further comprising a dielectric film covering at least a side surface of the oxide semiconductor film.

13. The semiconductor device according to claim 12 , wherein the dielectric film covers the entire side surface of the oxide semiconductor film.

14. The semiconductor device according to claim 12 or 13, wherein the dielectric film covers at least a portion of the first surface of the oxide semiconductor film.

15. The semiconductor element according to claim 12, wherein the side surface of the oxide semiconductor film is tapered.

16. The semiconductor element according to claim 15 , wherein a taper of a side surface of the oxide semiconductor film is inclined so as to widen from a first surface toward a second surface of the oxide semiconductor film.

17. A semiconductor element having at least a semiconductor film, a first electrode arranged on a first surface side of the semiconductor film, and a second electrode arranged on a second surface side opposite the first surface side, further comprising a porous layer arranged in contact with the second electrode, wherein the porosity of the porous layer is 10% or less.

18. 20. The semiconductor device according to claim 17, wherein the second electrode includes at least a first metal layer, a second metal layer, and a third metal layer.

19. 20. The semiconductor device according to claim 18, wherein the second metal layer is disposed between the first metal layer and the third metal layer, and the second metal layer is a Pt layer or a Pd layer.

20. The semiconductor device according to claim 18 or 19, wherein the first metal layer is a Ti layer or an In layer.

21. The semiconductor device according to any one of claims 18 to 20, wherein the third metal layer is at least one metal layer selected from the group consisting of an Au layer, an Ag layer, and a Cu layer.

22. The semiconductor device according to any one of claims 17 to 21, wherein the second electrode is an ohmic electrode.

23. The semiconductor device according to any one of claims 1 to 22, which is a vertical device.

24. The semiconductor element according to any one of claims 1 to 23, which is a power device.

25. A semiconductor device comprising at least a semiconductor element bonded to a lead frame, a circuit board or a heat dissipation board by a bonding member, the semiconductor element being the semiconductor element according to any one of claims 1 to 24.

26. 26. The semiconductor device according to claim 25, which is a power module, an inverter or a converter.

27. 27. The semiconductor device according to claim 25, which is a power card.

28. A semiconductor system comprising a semiconductor element or a semiconductor device, wherein the semiconductor element is a semiconductor element according to any one of claims 1 to 24, and the semiconductor device is a semiconductor device according to any one of claims 25 to 27.

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