Semiconductor light emitting device and method for manufacturing the same

Abstract

To provide a semiconductor light-emitting element capable of enhancing an activation ratio of a p-type impurity contained in a p+layer contained in a p-type layer and a tunnel junction layer, and performing excellent current diffusion and carrier injection, and provide a manufacturing method for the semiconductor light-emitting element.SOLUTION: A semiconductor light-emitting element comprises: a growth substrate (11); a plurality of column-like semiconductor layers (13 and 14) formed on the growth substrate (11); a p-type embedded semiconductor layer (15) coating the plurality of column-like semiconductor layers (13 and 14) so as to be contacted to the side surface of each of the column-like semiconductor layers (13 and 14); a tunnel junction layer (16) formed on the embedded semiconductor layer (15); and an n-type semiconductor layer (17) formed on the tunnel junction layer (16). The embedded semiconductor layer (15), the tunnel junction layer (16), and the n-type semiconductor layer (17) are provided with a mesa structure, and the tunnel junction layer (16) extends to the side surface of the mesa structure.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly to a semiconductor light emitting device having a structure in which a plurality of columnar semiconductor layers are buried with a p-type buried semiconductor layer, and a method for manufacturing the same. [Background technology]

[0002] In recent years, rapid progress has been made in crystal growth methods for nitride-based semiconductors, and high-luminance blue and green light-emitting devices using these materials have been put to practical use. By combining existing red light-emitting devices with these blue and green light-emitting devices, all three primary colors of light are available, making it possible to realize full-color display devices. In other words, by mixing all three primary colors of light, white light can be obtained, which can also be applied to lighting devices.

[0003] It is desirable for semiconductor light-emitting elements used as light sources for lighting applications to achieve high energy conversion efficiency and high optical output in high current density regions, and to have stable light distribution characteristics for the emitted light. To solve these problems, Patent Document 1 proposes a semiconductor light-emitting element in which an n-type nanowire core, an active layer, and a p-type layer are grown on a growth substrate, a tunnel junction layer is formed on the side of the p-type layer, and the layer is embedded with an n-type embedded semiconductor layer.

[0004] In the semiconductor light-emitting device disclosed in Patent Document 1, in which an active layer is formed on the outer periphery of a nanowire core, fewer crystal defects and threading dislocations are obtained and higher quality crystals can be obtained than in the case where an active layer is formed on the entire surface of a growth substrate, and since m-plane growth can be performed, the external quantum efficiency at high current density can be improved. In addition, in the semiconductor light-emitting device using the nanowire core of Patent Document 1, since the active layer can be formed of high quality crystals, it is expected that the In composition of the active layer can be increased to achieve longer wavelengths. In addition, by forming a tunnel junction layer around the nanowire and burying the nanowire with an n-type buried semiconductor layer, current diffusion in the buried semiconductor layer and carrier injection from the tunnel junction layer to the p-type layer can be achieved satisfactorily. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2020-077817 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the conventional technology of Patent Document 1, a p-type layer and a tunnel junction layer are formed as part of a columnar semiconductor including nanowires, and the p+ layer included in the p-type layer and the tunnel junction layer is embedded inside an n-type semiconductor layer. This causes a problem that it is difficult to remove hydrogen atoms that are included inside the p-type layer and the p+ layer during the manufacturing process, activate the p-type impurities, and increase the carrier concentration. If the carrier concentration in the p-type layer and the p+ layer is low, it becomes difficult to inject carriers into the p-type layer, and therefore it becomes difficult to increase the current density of the semiconductor light emitting device and increase the amount of light.

[0007] Therefore, the present invention has been made in consideration of the above-mentioned problems in the conventional technology, and has an object to provide a semiconductor light-emitting device and a method for manufacturing the semiconductor light-emitting device that can increase the activation rate of p-type impurities contained in the p-type layer and the p+ layer contained in the tunnel junction layer, and perform good current diffusion and carrier injection. [Means for solving the problem]

[0008] In order to solve the above problems, the semiconductor light-emitting element of the present invention comprises a growth substrate, a plurality of columnar semiconductor layers formed on the growth substrate, a p-type buried semiconductor layer in contact with side surfaces of the columnar semiconductor layers and covering the plurality of columnar semiconductor layers, a tunnel junction layer formed on the buried semiconductor layer, and an n-type semiconductor layer formed on the tunnel junction layer, wherein a mesa structure is formed in the buried semiconductor layer, the tunnel junction layer, and the n-type semiconductor layer, and the tunnel junction layer is formed by extending to the side surface of the mesa structure.

[0009] In such a semiconductor light-emitting element of the present invention, a tunnel junction layer is formed on the p-type buried semiconductor layer, and the tunnel junction layer is extended to the side surface of the mesa structure. Therefore, in the activation step, hydrogen can be released through the buried semiconductor layer and the tunnel junction layer exposed on the side surface of the mesa structure, which increases the activation rate of the p-type impurities contained in the buried semiconductor layer and the p+ layer of the tunnel junction layer, thereby enabling good current diffusion and carrier injection.

[0010] In one aspect of the present invention, the tunnel junction layer has a laminated structure of an n+ layer and a p+ layer, and a groove is formed that extends from a surface of the mesa structure to at least the p+ layer.

[0011] In one aspect of the present invention, the groove portion is formed to reach the buried semiconductor layer.

[0012] In one aspect of the present invention, the groove portion is formed to reach the growth substrate side from the top surface of the pillar-shaped semiconductor layer.

[0013] In one aspect of the present invention, the groove portion is formed by forming a columnar semiconductor layer It is formed in an area avoiding

[0014] In one aspect of the present invention, the grooves are formed in a dot shape or a linear shape.

[0015] In order to solve the above-mentioned problems, the method for manufacturing a semiconductor light-emitting element of the present invention is characterized by comprising: a first growth step of forming a plurality of columnar semiconductor layers and a p-type buried semiconductor layer on a growth substrate; a second growth step of forming a tunnel junction layer and an n-type semiconductor layer on the buried semiconductor layer; a mesa formation step of forming a mesa structure in the buried semiconductor layer, the tunnel junction layer, and the n-type semiconductor layer to expose the tunnel junction layer from a side surface of the mesa structure; and an activation step of activating a p+ layer included in the tunnel junction layer after the mesa formation step.

[0016] In one aspect of the present invention, the method further comprises, after the second growth step and before the activation step, a groove etching step of forming a groove by etching from a surface of the mesa structure to reach at least the p+ layer.

[0017] In one aspect of the present invention, the second growth step includes a mask forming step on a portion of the buried semiconductor layer, and growing the tunnel junction layer and the n-type semiconductor layer by selective growth using the mask, and a groove mask removal step of removing the mask to form a groove after the second growth step and before the activation step. Effect of the Invention

[0018] The present invention can provide a semiconductor light-emitting device and a method for manufacturing a semiconductor light-emitting device that can increase the activation rate of p-type impurities contained in a p-type layer and a p+ layer contained in a tunnel junction layer, thereby enabling good current diffusion and carrier injection. [Brief description of the drawings]

[0019] [Figure 1] 1 is a schematic diagram showing a semiconductor light emitting device 10 according to a first embodiment. [Diagram 2] 2A and 2B are partial enlarged views showing schematic examples of the structure of a groove portion 19 formed in a semiconductor light-emitting element 10, in which FIG. 2A shows an example in which the p+ layer 16p has been formed, FIG. 2B shows an example in which the buried semiconductor layer 15 has been formed, and FIG. 2C shows an example in which the nanowire layer 13 has been formed. [Diagram 3] 3(a) shows a mask formation step, FIG. 3(b) shows a nanowire growth step, FIG. 3(c) shows an active layer growth step, and FIG. 3(d) shows a buried semiconductor layer growth step in a manufacturing method for a semiconductor light-emitting element 10. [Figure 4] 4A to 4D are schematic diagrams showing a method for manufacturing the semiconductor light-emitting element 10 according to the first embodiment, in which FIG. 4A shows the second growth step, FIG. 4B shows the mesa formation step, FIG. 4C shows the groove etching step and the activation step, and FIG. 4D shows the electrode formation step. [Diagram 5]5(a) and 5(b) are schematic diagrams showing a method for manufacturing a semiconductor light-emitting element 10 according to the second embodiment, in which FIG. 5(a) shows a mask formation step, FIG. 5(b) shows a second growth step, FIG. 5(c) shows a groove mask removal step, FIG. 5(d) shows a mesa formation step and an activation step, and FIG. 5(e) shows an electrode formation step. [Figure 6] 6A to 6D are plan views showing schematic patterns of the formation of groove portions 19 in the third embodiment, in which FIG. 6A shows a circular dot shape, FIG. 6B shows a polygonal dot shape, FIG. 6C shows a low-density linear arrangement, and FIG. 6D shows a high-density linear arrangement. [Figure 7] 7A and 7B are plan views showing schematic diagrams of the formation pattern of grooves 19 and nanowire layers 13 in the fourth embodiment, in which FIG. 7(a) is an example in which circular dot-shaped grooves 19 are arranged between columnar semiconductors, FIG. 7(b) is an example in which linear grooves 19 are arranged along the direction connecting the electrodes, and FIG. 7(c) is an example in which linear grooves 19 are arranged in the direction crossing the electrodes. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] (First embodiment) Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are given the same reference numerals, and duplicated descriptions will be omitted as appropriate. Fig. 1 is a schematic diagram showing a semiconductor light emitting device 10 according to a first embodiment.

[0021] 1, a semiconductor light emitting element 10 includes a growth substrate 11, a mask 12, a nanowire layer 13, an active layer 14, a buried semiconductor layer 15, a tunnel junction layer 16, an n-type semiconductor layer 17, a mesa groove 18, a groove portion 19, a cathode electrode 20, and an anode electrode 21. Here, the nanowire layer 13 and the active layer 14 are selectively grown in a direction perpendicular to the growth substrate 11 to have a columnar shape, and constitute the columnar semiconductor layer of the present invention.

[0022] 1, in a portion of the semiconductor light emitting element 10, the embedded semiconductor layer 15 is removed from the surface to the growth substrate 11 to form a mesa groove 18 (mesa structure), and the surface of the growth substrate 11 is exposed to form a cathode electrode 20. In addition, an anode electrode 21 is formed on the n-type semiconductor layer 17. Here, the mesa structure refers to a structure in which a groove is formed penetrating a plurality of semiconductor layers so as to surround a predetermined region, and a cross section of the laminated structure of each semiconductor layer is exposed from the side.

[0023] The growth substrate 11 is a substantially flat plate-shaped member made of a material that allows crystal growth of a semiconductor material, and a mask 12 is formed on the main surface side. A part of the growth substrate 11 is exposed, and a cathode electrode 20 is formed on the exposed part. When the semiconductor light-emitting element 10 is made of a nitride-based semiconductor, it is preferable to use a GaN substrate as the growth substrate 11, and a c-plane GaN substrate, which is easy to form a resonator facet by cleavage, may be used for laser oscillation. Alternatively, a heterogeneous substrate such as a c-plane sapphire substrate or a Si substrate made of a material different from the semiconductor material grown on the growth substrate 11 may be used, on which multiple semiconductor layers such as a buffer layer and a base layer are grown.

[0024] The buffer layer is a layer formed between the single crystal substrate and the underlayer to reduce the lattice mismatch between them. When a c-plane sapphire substrate is used as the single crystal substrate, it is preferable to use GaN for the buffer layer, but AlN or AlGaN may also be used. The underlayer is a single crystal semiconductor layer formed on the growth substrate 11 or the buffer layer, and is preferably composed of multiple layers, with non-doped GaN formed to a thickness of several μm and an n-type semiconductor layer such as an n-type contact layer formed thereon. The n-type contact layer is a semiconductor layer doped with n-type impurities, for example, Si-doped n-type Al 0.05 Ga 0.95 N is one example.

[0025] The mask 12 is a layer made of a dielectric material formed on the surface of the growth substrate 11 or the underlayer. The material constituting the mask 12 is selected from those from which it is difficult to grow semiconductor crystals, such as SiO2 or SiNx A plurality of openings, which will be described later, are formed in the mask 12, and a semiconductor layer can be grown on the surface of the growth substrate 11 or the underlayer partially exposed through the openings.

[0026] The columnar semiconductor layer is a semiconductor layer grown in an opening in the mask 12, and is formed as a substantially columnar semiconductor layer standing vertically to the main surface of the growth substrate 11. Such a columnar semiconductor layer is obtained by setting appropriate growth conditions according to the semiconductor material to be used and performing selective growth in which a specific crystal plane orientation grows. In the example shown in FIG. 1, a plurality of openings are formed two-dimensionally and periodically in the mask 12, and therefore the columnar semiconductor layer is also formed two-dimensionally and periodically on the growth substrate 11.

[0027] The nanowire layer 13 is a columnar semiconductor layer selectively grown on the growth substrate 11 or the underlayer exposed from the opening of the mask 12, and is composed of, for example, GaN doped with n-type impurities. When GaN is used as the nanowire layer 13, the nanowire layer 13 selectively grown on the growth substrate 11 has a shape of a substantially hexagonal column with six m-planes formed as facets. In FIG. 1, the nanowire layer 13 appears to grow only in the region where the opening is formed, but in reality, crystal growth proceeds on the mask 12 by lateral growth, so that an expanded hexagonal column is formed around the opening. For example, when the opening is formed as a circle with a diameter of about 150 nm, a hexagonal column-shaped nanowire layer 13 with a height of about 1 to 2 μm can be formed, with a hexagon inscribed in a circle with a diameter of about 240 nm as its base.

[0028] In this embodiment, an example is shown in which GaN is used for the nanowire layer 13, but when the In composition of the active layer 14 is increased to lengthen the emission wavelength, GaInN may be used for the nanowire layer 13 to reduce misfit dislocations due to lattice mismatch. Similarly, when shortening the wavelength of the semiconductor light emitting element 10, it is also possible to use AlGaN for the nanowire layer 13, or to change the well layer and barrier layer of the active layer 14 to AlGaN with different compositions.

[0029] The active layer 14 is a semiconductor layer grown on the outer periphery of the nanowire layer 13, and may be, for example, a multi-quantum well active layer in which a GaInN quantum well layer with a thickness of 5 nm and a GaN barrier layer with a thickness of 10 nm are stacked five times. Although a multi-quantum well active layer is mentioned here, a single quantum well structure or a bulk active layer may be used. Since the active layer 14 is formed on the side and upper surface of the nanowire layer 13, the area of ​​the active layer 14 can be secured. The higher the ratio of In incorporated in the active layer, the longer the emission wavelength of the semiconductor light emitting element 10 becomes, and the emission wavelength can be made 480 nm or more by setting the In composition ratio to 0.10 or more. Furthermore, the emission wavelength can be made 500 nm or more by setting the In composition ratio to 0.12 or more. Furthermore, since the side surface of the nanowire layer 13 is composed of an m-plane, the active layer 14 formed on the side surface is also a non-polar plane having an m-plane, and the droop characteristic can be improved.

[0030] The buried semiconductor layer 15 is a semiconductor layer grown on the outer periphery of the active layer 14, and is made of, for example, GaN doped with p-type impurities. The buried semiconductor layer 15 is formed so as to cover the side and upper surface of the active layer 14, and to cover up to the growth substrate 11 or the underlayer. This allows the nanowire layer 13, the active layer 14, and the buried semiconductor layer 15 to form a double heterostructure, which can effectively confine carriers in the active layer 14 and improve the probability of radiative recombination. Although FIG. 1 shows an example in which the buried semiconductor layer 15 is made of a single layer, it may be a multi-layered structure as long as the semiconductor layer is formed so as to be buried from the surface of the growth substrate 11 to the upper surface of the columnar semiconductor layer.

[0031] The tunnel junction layer 16 is a semiconductor layer formed on the buried semiconductor layer 15, and has a two-layer structure in which, for example, a p+ layer 16p (not shown in FIG. 1) that is doped with a high concentration of p-type impurities and is in contact with the buried semiconductor layer 15, and an n+ layer 16n (not shown in FIG. 1) that is doped with a high concentration of n-type impurities and is formed on the p+ layer 16p are grown in this order. The p+ layer 16p is a semiconductor layer doped with a high concentration of p-type impurities, and has, for example, a thickness of 5 nm and a Mg concentration of 2×10 20 cm-3 The n+ layer 16n may be made of GaN having a thickness of, for example, 10 nm and a Si concentration of 2×10 20 cm -3 Since a tunnel junction is formed by the p+ layer and the n+ layer, the two layers of the p+ layer 16p and the n+ layer 16n constitute the tunnel junction layer 16 in the present invention.

[0032] The n-type semiconductor layer 17 is an n-type semiconductor layer formed on the tunnel junction layer 16, and an anode electrode 21 is formed on a part of the surface. The n-type semiconductor layer 17 may be configured as a single layer or a multi-layer laminate structure. The material constituting the n-type semiconductor layer 17 is not limited, and for example, n-type GaN, n-type AlGaN, etc. can be used. Since the anode electrode 21 is formed on the n-type semiconductor layer 17, it is preferable to form a contact layer having a high concentration of n-type impurities on the outermost surface of the n-type semiconductor layer 17.

[0033] The mesa groove 18 is a groove formed penetrating each semiconductor layer from the n-type semiconductor layer 17 to the growth substrate 11 or the underlayer, and divides the light emitting region of the semiconductor light emitting element 10 to form a mesa structure. The outer peripheries of the n-type semiconductor layer 17, the tunnel junction layer 16 (n+ layer 16n, p+ layer 16p), and the embedded semiconductor layer 15 are exposed from the side of the mesa groove 18. Therefore, the tunnel junction layer 16 is formed extending to the side of the mesa structure defined by the mesa groove 18. Here, the exposure of each semiconductor layer to the side of the mesa structure means that the outer periphery of each semiconductor layer extends to the side of the mesa structure when the mesa groove 18 is formed, and includes the case where a passivation film or other structure is formed in the mesa groove 18 in a later process. An element isolation groove is further formed in the mesa groove 18 to individually isolate the semiconductor light emitting elements 10.

[0034] The groove portion 19 is a groove formed so as to reach at least the p+ layer 16p of the tunnel junction layer 16 from the surface of the n-type semiconductor layer 17 of the mesa structure. Fig. 2 is a partially enlarged view showing a schematic example of the structure of the groove portion 19 formed in the semiconductor light emitting element 10, Fig. 2(a) shows an example in which the p+ layer 16p is formed, Fig. 2(b) shows an example in which the buried semiconductor layer 15 is formed, and Fig. 2(c) shows an example in which the nanowire layer 13 is formed.

[0035] 2(a), when groove portion 19 is formed halfway through p+ layer 16p, p+ layer 16p is exposed at the bottom and sides of groove portion 19. In this structure, the exposed area of ​​p+ layer 16p in groove portion 19 is large, so that hydrogen atoms captured in p+ layer 16p can be easily removed from groove portion 19 in an activation step described later.

[0036] 2(b), when groove 19 is formed until it reaches buried semiconductor layer 15, p+ layer 16p is exposed on the side of groove 19, and buried semiconductor layer 15 is exposed on the bottom and side of groove 19. In this structure, since p+ layer 16p is exposed on the side of groove 19, hydrogen atoms that have been captured in p+ layer 16p during the activation process can be released from groove 19. In addition, since buried semiconductor layer 15 is exposed at the bottom and side of groove 19, hydrogen atoms that have been captured in buried semiconductor layer 15 during the activation process can also be released from groove 19.

[0037] 2(c), the grooves 19 may be formed deeper toward the growth substrate 11 than the top surface of the pillar-shaped semiconductor layer, and may reach a part of the nanowire layer 13. Alternatively, the grooves 19 may be formed deeper than the top surface of the nanowire layer 13 at a position that avoids the nanowire layer 13. In these structures, the p+ layer 16p and the embedded semiconductor layer 15 are exposed at the side of the grooves 19, and the hydrogen atoms that were captured during the activation process can be released from the grooves 19.

[0038] The cathode electrode 20 is an electrode formed in an area where the growth substrate 11 or the underlayer is exposed, and is composed of a laminated structure of a metal material that makes ohmic contact with the exposed semiconductor layer and a pad electrode. The anode electrode 21 is an electrode formed on a part of the n-type semiconductor layer 17, and is composed of a laminated structure of a metal material that makes ohmic contact with the top surface of the n-type semiconductor layer 17 and a pad electrode. Although not shown in FIG. 1, a known structure may be applied, such as covering the surface of the semiconductor light emitting element 10 with a passivation film, as necessary. Also, a transparent electrode in which the anode electrode 21 is extended over the entire n-type semiconductor layer 17 may be formed.

[0039] Fig. 3 is a schematic diagram showing a first growth step in a method for manufacturing the semiconductor light-emitting element 10, where Fig. 3(a) shows a mask formation step, Fig. 3(b) shows a nanowire growth step, Fig. 3(c) shows an active layer growth step, and Fig. 3(d) shows a buried semiconductor layer growth step. Fig. 4 is a schematic diagram showing a method for manufacturing the semiconductor light-emitting element 10 according to this embodiment, where Fig. 4(a) shows a second growth step, Fig. 4(b) shows a mesa formation step, Fig. 4(c) shows a groove etching step and an activation step, and Fig. 4(d) shows an electrode formation step.

[0040] First, in the mask formation process shown in FIG. 3(a), a mask 12 made of SiO2 is deposited to a thickness of about 30 nm on a growth substrate 11 made of n-type GaN by a sputtering method, and an opening 12a with a diameter of about 150 nm is formed by using a fine pattern formation method such as nanoimprinting lithography. When a heterogeneous substrate such as sapphire is used as the growth substrate 11, a buffer layer, an underlayer, and an n-type semiconductor layer may be formed on the sapphire substrate, and the surface of the n-type semiconductor layer may be used as the surface of the growth substrate 11. The growth conditions for the buffer layer are, for example, TMA (TriMethylAluminium), TMG (TriMethylGallium), and ammonia as source gases, a growth temperature of 1100° C., a V / III ratio of 1000, and a pressure of 10 hPa with hydrogen as a carrier gas. The growth conditions for the underlayer and the n-type semiconductor layer are, for example, a growth temperature of 1050° C., a V / III ratio of 1000, and a pressure of 500 hPa with hydrogen as a carrier gas.

[0041] 3(b), a nanowire layer 13 made of GaN is grown on the growth substrate 11 exposed from the opening 12a by selective growth using the MOCVD method. The growth conditions for the nanowire layer 13 are, for example, TMG and ammonia as source gases, a growth temperature of 1050°C, a V / III ratio of 10, hydrogen as carrier gas, and a pressure of 100 hPa.

[0042] 3(c), an active layer growth process is performed by using MOCVD to grow an active layer 14, which is made up of five periods of a 5 nm-thick GaInN quantum well layer and a 10 nm-thick GaN barrier layer, on the side and top surfaces of the nanowire layer 13. The growth conditions for the active layer 14 are, for example, a growth temperature of 800°C, a V / III ratio of 3000, a pressure of 1000 hPa with nitrogen as the carrier gas, and TMG, TMI (TriMethylIndium), and ammonia as the source gases.

[0043] Next, in the buried semiconductor layer growth step shown in Fig. 3(d), a buried semiconductor layer 15 made of GaN doped with p-type impurities is grown, and the outer periphery and upper surface of the columnar semiconductor layer made of the nanowire layer 13 and the active layer 14 are buried with the buried semiconductor layer 15. The growth conditions for the buried semiconductor layer 15 are, for example, a growth temperature of 950°C, a V / III ratio of 1000, a pressure of 300 hPa with hydrogen as the carrier gas, and TMG, Cp2Mg (bisCycropentadienylMagnesium) and ammonia as the source gas. In order to thicken the buried semiconductor layer 15, the growth conditions for the buried semiconductor layer 15 are preferably conditions that promote c-plane growth, which is growth in the vertical direction.

[0044] As described above, the buried semiconductor layer 15 needs to be grown on the mask 12 provided between the columnar semiconductor layers, and there is a possibility that voids may occur under the columnar semiconductor layers when the buried semiconductor layer 15 is grown. Therefore, in the growth of the buried semiconductor layer 15, it is preferable to use TMG, silane, and ammonia as source gases, and grow the buried semiconductor layer 15 at a low temperature and a low V / III ratio that promotes the growth of the m-plane, which is lateral growth, in the initial stage. An example of a low temperature and a low V / III ratio is a V / III ratio of 100 or less at 800°C or less, and a pressure of 200 hPa with hydrogen as a carrier gas. After the lateral growth of the buried semiconductor layer 15 fills the lower part of the columnar semiconductor layers on the mask 12 without any gaps, it is preferable to grow the buried semiconductor layer 15 at a high temperature and a high V / III ratio that promotes the growth of the c-plane, which is vertical growth. An example of a high temperature and a high V / III ratio is a V / III ratio of 2000 or more at 1000°C or more, and a pressure of 500 hPa with hydrogen as a carrier gas. The steps from the mask formation step of FIG. 3(a) to the buried semiconductor layer growth step of FIG. 3(d) correspond to the first growth step in the present invention.

[0045] 4(a), the p+ layer 16p and n+ layer 16n of the tunnel junction layer 16 and the n-type semiconductor layer 17 are grown on the buried semiconductor layer 15. The growth conditions for the tunnel junction layer 16 are, for example, a growth temperature of 800° C., a V / III ratio of 3000, and a pressure of 500 hPa with nitrogen as the carrier gas. The p+ layer 16p is 5 nm thick and has a Mg concentration of 2×10 20 cm -3 The n+ layer 16n has a thickness of 10 nm and a Si concentration of 2×10 20 cm -3 Examples of such semiconductors include GaN.

[0046] 4(b), the tunnel junction layer 16 and the buried semiconductor layer 15 are selectively removed from the n-type semiconductor layer 17 by dry etching to expose the upper surface of the growth substrate 11 and form a mesa groove 18. By forming the mesa groove 18 as described above, the region surrounded by the mesa groove 18 is defined as the light emitting region of the semiconductor light emitting element 10.

[0047] Next, in the groove etching step shown in FIG. 4(c), a groove 19 is selectively formed by dry etching, which reaches from the n-type semiconductor layer 17 to at least the p+ layer 16p of the tunnel junction layer 16. After the groove 19 is formed, an activation step is performed to remove hydrogen from the embedded semiconductor layer 15 and the p+ layer 16p that reach the side of the mesa structure and are exposed, and an activation process is performed. At the same time, hydrogen is also removed from the p+ layer 16p exposed in the groove 19, and the activation process is promoted. Here, the method of the activation process is not limited, but one example is a heat treatment (annealing) at 600° C. in an air atmosphere. Here, annealing in an air atmosphere is shown, but it is sufficient that the heat treatment is performed in an atmosphere that does not contain atomic hydrogen that can activate the embedded semiconductor layer 15 and the tunnel junction layer 16.

[0048] 4(d), a cathode electrode 20 is formed on the surface of the growth substrate 11, and an anode electrode 21 is formed on the n-type semiconductor layer 17. Furthermore, as necessary, annealing after electrode formation, formation of a passivation film, and element division are performed to obtain the semiconductor light emitting element 10.

[0049] In the semiconductor light emitting device 10 of this embodiment, when a voltage is applied between the cathode electrode 20 and the anode electrode 21, a current flows through the n-type semiconductor layer 17, the tunnel junction layer 16, the embedded semiconductor layer 15, the active layer 14, the nanowire layer 13, and the growth substrate 11 in that order, and light is generated by radiative recombination in the active layer 14. The light emitted from the active layer 14 is extracted to the outside of the semiconductor light emitting device 10.

[0050] Current injection by tunnel current via the tunnel junction layer 16 has low resistance and can be performed satisfactorily. In addition, since the n-type semiconductor layer 17 easily diffuses current, the current can be diffused over the entire region of the mesa structure and current can be injected from the entire tunnel junction layer 16. This makes it possible to realize a high current density in the semiconductor light emitting device 10 and improve the external quantum efficiency.

[0051] In addition, since the side surface of the nanowire layer 13 is an m-plane formed by selective growth, the active layer 14 and the buried semiconductor layer 15 formed on the outer periphery are also in contact with each other through the m-plane. The m-plane is a non-polar plane and does not cause polarization, so the light emission efficiency of the active layer 14 is high, and since all the side surfaces of the hexagonal prism are m-planes, the light emission efficiency of the semiconductor light emitting element 10 can be improved. Furthermore, since the film thickness of the active layer can be increased, the volume of the active layer 14 can be increased by about 3 to 10 times that of conventional semiconductor light emitting elements, and the injected carrier density can be reduced, thereby significantly reducing efficiency droop.

[0052] As described above, in the semiconductor light emitting device 10 of this embodiment, the tunnel junction layer 16 is formed to extend to the side surface of the mesa structure, and the groove portion 19 is formed at least to the p+ layer 16p. Therefore, in the activation step, hydrogen atoms can be released from the buried semiconductor layer 15 and the tunnel junction layer 16 exposed on the side surface of the mesa structure, and the activation rate of the p-type impurities contained in the buried semiconductor layer 15 and the p+ layer 16p can be increased, making it possible to perform good current diffusion and carrier injection.

[0053] In addition, after the second growth step, a groove etching step is performed to form groove 19 by etching, and groove 19 is formed that reaches at least p+ layer 16p. By performing an activation step thereafter, hydrogen atoms can be removed from p+ layer 16p exposed on the side surface of groove 19 in the activation step, and the activation rate of p-type impurities contained in p+ layer 16p can be increased not only near the periphery of the mesa structure but also in the internal region, making it possible to perform good current diffusion and carrier injection.

[0054] Second embodiment Next, a second embodiment of the present invention will be described with reference to FIG. 5. Descriptions of contents overlapping with the first embodiment will be omitted. FIG. 5 is a schematic diagram showing a method for manufacturing a semiconductor light emitting device 10 according to this embodiment, in which FIG. 5(a) shows a mask formation step, FIG. 5(b) shows a second growth step, FIG. 5(c) shows a groove mask removal step, FIG. 5(d) shows a mesa formation step and an activation step, and FIG. 5(e) shows an electrode formation step. This embodiment is different from the first embodiment in that after the first growth step shown in FIG. 3, the second growth step is carried out by selective growth using a mask.

[0055] 5(a), a mask 22 is formed on a part of the buried semiconductor layer 15 after the buried semiconductor layer growth step shown in FIG. 3(d). As a material for the mask 22, a dielectric material that makes it difficult for the tunnel junction layer 16 to grow crystals from above the mask 22 is selected, such as SiO2 or SiN. x or Al2O3 is suitable. The region where the mask 22 is formed is the region where the grooves 19 are to be formed, and by forming the mask 22 in a desired position and shape, it is possible to form the pattern of the grooves 19 while taking into consideration the positional relationship with the nanowire layer 13, as will be described later.

[0056] 5(b), the p+ layer 16p and the n+ layer 16n of the tunnel junction layer 16 and the n-type semiconductor layer 17 are grown on the buried semiconductor layer 15 by selective growth using a mask 22. At this time, the p+ layer 16p and the n+ layer 16n of the tunnel junction layer 16 are not grown on the mask 22, and the mask 22 remains on the bottom of the groove portion 19.

[0057] 5(c), the mask 22 is removed by etching to form the grooves 19 and expose the surface of the embedded semiconductor layer 15 at the bottom of the grooves 19. At this time, the p+ layer 16p of the tunnel junction layer 16 is exposed at the side of the grooves 19. The mask 22 can be removed by wet etching, which removes only the material of the mask 22 without etching the semiconductor materials constituting the n-type semiconductor layer 17 and the tunnel junction layer 16.

[0058] Next, in the mesa formation step shown in Fig. 5(d), the tunnel junction layer 16 and the buried semiconductor layer 15 are selectively removed from the n-type semiconductor layer 17 by dry etching to expose the upper surface of the growth substrate 11 and form the mesa groove 18. As described above, by forming the mesa groove 18, the area surrounded by the mesa groove 18 is defined as the light emitting area of ​​the semiconductor light emitting element 10. After the groove 19 and the mesa groove 18 are formed, an activation step is performed to remove hydrogen from the buried semiconductor layer 15 and the p+ layer 16p that reach the side surface of the mesa structure and are exposed, thereby performing an activation process. At the same time, hydrogen is also removed from the buried semiconductor layer 15 and the p+ layer 16p that are exposed in the groove 19, accelerating the activation process.

[0059] 5(e), a cathode electrode 20 is formed on the surface of the growth substrate 11, and an anode electrode 21 is formed on the n-type semiconductor layer 17. Furthermore, annealing after electrode formation, formation of a passivation film, and element division are performed as necessary to obtain the semiconductor light emitting element 10.

[0060] In this embodiment, too, grooves 19 are formed in the second growth step by selective growth using mask 22 and the mask removal step, and grooves 19 reaching at least p+ layer 16p are formed. By carrying out an activation step thereafter, hydrogen atoms can be removed from p+ layer 16p exposed on the side surface of grooves 19 in the activation step, and the activation rate of p-type impurities contained in p+ layer 16p can be increased not only near the periphery of the mesa structure but also in the internal region, making it possible to perform good current diffusion and carrier injection.

[0061] Third embodiment Next, a third embodiment of the present invention will be described with reference to Fig. 6. Descriptions of contents overlapping with the first embodiment will be omitted. Fig. 6 is a plan view showing a typical formation pattern of grooves 19 in this embodiment, with Fig. 6(a) showing a circular dot shape, Fig. 6(b) showing a polygonal dot shape, Fig. 6(c) showing a low-density linear arrangement, and Fig. 6(d) showing a high-density linear arrangement.

[0062] 6(a) to 6(d), a rectangular shape of 300 μm×300 μm is assumed as the mesa structure defined by mesa groove 18. The depth to which groove portion 19 is formed may be any of the examples shown in FIGS. 2(a) to 2(c).

[0063] In the example shown in Fig. 6(a), the grooves 19 are formed in the shape of circular dots, with cathode electrodes 20 and anode electrodes 21 formed diagonally in 3 rows and 3 columns at intervals of 100 µm, and grooves 19 are arranged in the remaining 7 places. In this arrangement example, if the diameter of the grooves 19 is 20 µm, the total area of ​​the grooves 19 is about 2200 µm. 2 The area ratio of the grooves 19 to the chip area is about 2.44%. Another example is a pattern in which the cathode electrodes 20 and anode electrodes 21 are formed diagonally in 4 rows and 4 columns at 50 μm intervals, and the grooves 19 are arranged in the remaining 14 places. In this arrangement example, if the diameter of the grooves 19 is 5 μm, the total area of ​​the grooves 19 is about 274 μm. 2 The area ratio of the groove portion 19 to the chip area is about 0.73%.

[0064] In the example shown in Fig. 6(b), the grooves 19 are formed in the shape of square dots, with cathode electrodes 20 and anode electrodes 21 formed at diagonal corners of 3 rows and 3 columns at 100 μm intervals, and grooves 19 are arranged in the remaining 7 places. In this arrangement example, if one side of the grooves 19 is 20 μm, the total area of ​​the grooves 19 is 2800 μm. 2 The area ratio of the grooves 19 to the chip area is about 3.10%. Another example is a pattern in which the cathode electrodes 20 and anode electrodes 21 are formed diagonally in 4 rows and 4 columns at 50 μm intervals, and the grooves 19 are arranged in the remaining 14 places. In this arrangement example, if one side of the grooves 19 is 5 μm, the total area of ​​the grooves 19 is about 350 μm. 2 The area ratio of the groove portion 19 to the chip area is about 0.39%.

[0065] The example shown in Fig. 6(c) is a pattern in which three grooves 19 are formed in a stripe (line) shape at intervals of 100 μm parallel to one side wall of the mesa structure. In this arrangement example, the width of the stripe is 5 μm, the length of the central stripe is 250 μm, and the lengths of the other stripes are 150 μm, so the total area of ​​the grooves 19 is 2750 μm. 2 The area ratio of the groove portion 19 to the chip area is about 3.06%.

[0066] The example shown in Fig. 6(d) is a pattern in which five grooves 19 are formed in a stripe (line) shape at intervals of 50 μm parallel to one side wall of the mesa structure. In this arrangement example, the width of the stripe is 5 μm, the length of the central stripe is 250 μm, and the lengths of the other stripes are 150 μm, so the total area of ​​the grooves 19 is 4250 μm. 2 The area ratio of the groove portion 19 to the chip area is about 4.72%.

[0067] 6(a) to 6(d), the area ratio of the grooves 19 to the chip area is less than 5%, and current is injected from the tunnel junction layer 16 to the embedded semiconductor layer 15 in 95% or more of the area, thereby enabling good and uniform current injection into the semiconductor light emitting device 10. In addition, since the interval between adjacent grooves 19 is set to about 50 to 100 μm, the area of ​​the p+ layer 16p from which hydrogen can be released from the grooves 19 can be secured, and the p+ layer 16p can be activated over the entire surface. In addition, the time required for activation can be shortened.

[0068] (Fourth embodiment) Next, a fourth embodiment of the present invention will be described with reference to Fig. 7. Descriptions of contents overlapping with the first embodiment will be omitted. Fig. 7 is a plan view showing a typical formation pattern of grooves 19 and nanowire layer 13 in this embodiment, Fig. 7(a) is an example in which circular dot-shaped grooves 19 are arranged between columnar semiconductors, Fig. 7(b) is an example in which linear grooves 19 are arranged along the direction connecting the electrodes, and Fig. 7(c) is an example in which linear grooves 19 are arranged in the direction crossing the electrodes.

[0069] In this embodiment, grooves 19 are formed in a region avoiding nanowire layer 13 in plan view. The depth to which grooves 19 are formed may be any of the examples shown in Figures 2(a) to 2(c), and it is preferable to adopt these arrangements in particular when grooves 19 are formed to a position deeper than the top surface of nanowire layer 13 (columnar semiconductor layer) as shown in Figure 2(c) in order not to remove active layer 14 by grooves 19.

[0070] 7(a), grooves 19 are formed in a circular dot shape and are arranged at the centers of nanowire layers 13 (columnar semiconductor layers) arranged in a triangular lattice pattern. In this arrangement, grooves 19 can be formed uniformly over almost the entire surface of the chip region, so that p+ layer 16p can be activated uniformly over almost the entire surface of the chip region.

[0071] 7(b), the grooves 19 are linear and arranged between the nanowire layers 13 in the triangular lattice pattern along the direction connecting the anode electrode 21 and the cathode electrode 20. In this arrangement, the activation rate of the p+ layer 16p can be increased along the path of the current flowing from the anode electrode 21 to the cathode electrode 20, and current injection can be further improved.

[0072] 7(c), the groove 19 is linear and arranged parallel to one side wall of the mesa structure between the nanowire layers 13. In this arrangement, the groove 19 can be formed from one side of the chip region to the opposing other side, so that the activation rate of the p+ layer 16p can be increased over almost the entire surface of the chip region.

[0073] Fifth embodiment Next, a fifth embodiment of the present invention will be described. Descriptions that overlap with those of the first embodiment will be omitted. Although linear grooves 19 are shown in Figs. 6(c)(d) and 7(b)(c), curved grooves may also be used. In particular, when a branch electrode for current diffusion is branched as part of the anode electrode 21, grooves 19 may be formed along the branch electrode.

[0074] The present invention is not limited to the above-described embodiments, and various modifications and variations are possible within the scope of the claims. Modifications are possible, and the technical means disclosed in each of the different embodiments may be appropriately combined. The resulting embodiments are also within the scope of the present invention. [Explanation of symbols]

[0075] 10...Semiconductor light emitting device 11...Growth substrate 12. Mask 12a...Opening 13…Nanowire layer 14…Active layer 15...Buried semiconductor layer 16...Tunnel junction layer 17...n-type semiconductor layer 18…Mesa groove 19…Groove 20…Cathode electrode 21...Anode electrode 22...Mask

Claims

1. A growth substrate; A plurality of pillar-shaped semiconductor layers formed on the growth substrate; a p-type buried semiconductor layer in contact with a side surface of the pillar-shaped semiconductor layer and covering the pillar-shaped semiconductor layer; a tunnel junction layer formed on the buried semiconductor layer; an n-type semiconductor layer formed on the tunnel junction layer; a mesa structure is formed in the buried semiconductor layer, the tunnel junction layer, and the n-type semiconductor layer; The tunnel junction layer is formed so as to extend to a side surface of the mesa structure.

2. The semiconductor light emitting device according to claim 1 , The tunnel junction layer has a stacked structure of an n+ layer and a p+ layer, a groove portion is formed extending from a surface of the mesa structure to at least the p+ layer.

3. The semiconductor light emitting device according to claim 2, The semiconductor light emitting device is characterized in that the groove portion is formed so as to reach the buried semiconductor layer.

4. The semiconductor light emitting device according to claim 3 , The semiconductor light-emitting device, wherein the groove portion is formed so as to reach the growth substrate side from the top surface of the pillar-shaped semiconductor layer.

5. 5. The semiconductor light emitting device according to claim 2, The semiconductor light emitting device, wherein the groove portion is formed in a region that avoids the columnar semiconductor layer in a plan view.

6. The semiconductor light emitting device according to any one of claims 2 to 5, The semiconductor light-emitting element is characterized in that the grooves are formed in a dot shape or a linear shape.

7. a first growth step of forming a plurality of pillar-shaped semiconductor layers and a p-type buried semiconductor layer on a growth substrate; a second growth step of forming a tunnel junction layer and an n-type semiconductor layer on the buried semiconductor layer; a mesa forming step of forming a mesa structure in the buried semiconductor layer, the tunnel junction layer and the n-type semiconductor layer, and exposing the tunnel junction layer from a side surface of the mesa structure; a step of activating a p+ layer included in the tunnel junction layer after the mesa formation step.

8. A method for manufacturing a semiconductor light emitting device according to claim 7, comprising the steps of: a groove etching step of forming a groove extending from a surface of the mesa structure to at least the p+ layer by etching after the second growth step and before the activation step.

9. A method for manufacturing a semiconductor light emitting device according to claim 7, comprising the steps of: In the second growth step, a mask is formed on a portion of the buried semiconductor layer, and the tunnel junction layer and the n-type semiconductor layer are grown by selective growth using the mask; A method for manufacturing a semiconductor light emitting device, comprising the steps of: removing the mask to form a groove after the second growth step and before the activation step.

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