Semiconductor Device

Abstract

To provide a semiconductor device in which the area for an element such as a transistor can be secured.SOLUTION: A semiconductor device includes a semiconductor substrate where a transistor part including a transistor element is provided, a plurality of trench parts with a long side in a first direction in a top view of the semiconductor substrate, an upper surface electrode provided over at least the transistor part, a first wire extending in parallel to a first side and a second side of the semiconductor substrate that face each other in the first direction and including a first metal wiring part provided outside the upper surface electrode in the first direction, and a second wire extending in parallel to the first side and the second side and including a second metal wiring part provided outside the upper surface electrode in the first direction. The trench parts include a first trench part with a conductive part electrically connected to the first metal wiring part, and a second trench part with a conductive part electrically connected to the second metal wiring part. The upper surface electrode, the first metal wiring part, and the second metal wiring part are disposed with a space therebetween in the first direction.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, in a semiconductor device having a gate trench and a dummy trench, a configuration is known in which wiring for screening the dummy trench is provided (see, for example, Patent Documents 1 to 3). [Prior art document] [Patent documents] Patent Document 1: JP 2016-25124 A Patent Document 2: JP 2015-207736 A Patent Document 3: JP 2014-53552 A Patent Document 4: JP 2018-174295 A Summary of the Invention [Problem to be solved by the invention]

[0003] If a screening wiring is provided in an active portion where elements such as transistors are formed, the area in which elements such as transistors can be arranged becomes smaller. [Means for solving the problem]

[0004] In order to solve the above problem, a semiconductor device is provided that includes a semiconductor substrate on which a transistor portion including a transistor element is provided. The semiconductor device may include a plurality of trench portions having a longitudinal direction in a top view of the semiconductor substrate. Any of the above semiconductor devices includes an upper surface electrode provided above at least the transistor portion. Any of the above semiconductor devices may include a first wiring that extends parallel to a first end edge and a second end edge of the semiconductor substrate that face each other in the first direction and includes a first metal wiring portion provided outside the upper surface electrode in the first direction. Any of the above semiconductor devices may include a second wiring that extends parallel to the first end edge and a second end edge and includes a second metal wiring portion provided outside the upper surface electrode in the first direction. In any of the above semiconductor devices, the plurality of trench portions may include a first trench portion having a conductive portion electrically connected to the first metal wiring portion and a second trench portion having a conductive portion electrically connected to the second metal wiring portion. In any of the semiconductor devices described above, the upper electrode, the first metal wiring portion, and the second metal wiring portion may be arranged at intervals in the first direction.

[0005] In any of the above semiconductor devices, the top electrode may overlap, in a top view, with an active portion that is a region through which a main current flows in a depth direction when the transistor portion is controlled to an on state. In any of the above semiconductor devices, the first wiring may include a semiconductor wiring provided below the first metal wiring portion and surrounding the active portion and the second wiring.

[0006] In any of the above semiconductor devices, the first metal wiring portion may constitute a part of a peripheral gate wiring which is a metal wiring. In any of the above semiconductor devices, the second metal wiring portion may constitute a part of a peripheral dummy wiring which is a metal wiring. In any of the above semiconductor devices, the peripheral gate wiring and the peripheral dummy wiring may be arranged so as not to overlap each other in a top view.

[0007] In any of the semiconductor devices described above, the second metal wiring portion may be disposed between the first metal wiring portion and the upper surface electrode.

[0008] In any of the semiconductor devices described above, the second metal wiring portion may be disposed between the first metal wiring portion and the first end side or between the first metal wiring portion and the second end side.

[0009] In any of the above semiconductor devices, the top electrode may include at least two partial electrodes spaced apart from each other when viewed from above. In any of the above semiconductor devices, the second wiring may include an active side metal wiring portion sandwiched between the two partial electrodes.

[0010] In any of the above semiconductor devices, the active side metal wiring portion may extend in a second direction perpendicular to the first direction in a top view. In any of the above semiconductor devices, the active side metal wiring portion may include a terminal portion having a terminated tip. In any of the above semiconductor devices, a bridge portion connecting two of the partial electrodes may be provided adjacent to the terminal portion.

[0011] Any of the above semiconductor devices may include a first pad provided above the semiconductor substrate and to which an external circuit can be connected. In any of the above semiconductor devices, the first wiring may connect the first pad and a conductive portion of the first trench portion.

[0012] Any of the above semiconductor devices may further include a second pad provided above the semiconductor substrate and to which an external circuit can be connected. In any of the above semiconductor devices, the second wiring may connect the second pad and a conductive portion of the second trench portion.

[0013] Any of the above semiconductor devices may include a connection portion that electrically connects the upper electrode and the second wiring.

[0014] In any of the above semiconductor devices, the transistor element may be an IGBT or a MOS transistor.

[0015] In any of the above semiconductor devices, the semiconductor substrate may be a silicon or compound semiconductor substrate.

[0016] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Diagram 2] FIG. 2 is an enlarged view of an area A in FIG. [Diagram 3] FIG. 3 is a diagram showing an example of a cross section bb in FIG. 2. [Figure 4] 2 is a diagram showing an example of element arrangement in an active section 120. FIG. [Diagram 5] FIG. 5 is an enlarged view of region C in FIG. [Figure 6] FIG. 6 is a diagram showing an example of a cross section dd in FIG. [Figure 7] 13A and 13B are diagrams illustrating other examples of the structure of the emitter electrode 52. [Figure 8] 2 is an enlarged view of the vicinity of a bridge portion 53. FIG. [Figure 9] FIG. 9 is a diagram showing an example of the hh cross section in FIG. [Figure 10] FIG. 9 is a diagram showing an example of a cross section ii in FIG. [Figure 11] FIG. 8 is an enlarged view of a region F in FIG. [Figure 12] FIG. 8 is an enlarged view of an area G in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0020] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis. In this specification, the view from the +Z-axis direction may be referred to as a top view.

[0021] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0022] In this specification, the conductivity type of the doped region doped with impurities is described as P type or N type. However, the conductivity type of each doped region may be the opposite polarity. In addition, in this specification, when P+ type or N+ type is described, it means that the doping concentration is higher than P type or N type, and when P- type or N- type is described, it means that the doping concentration is lower than P type or N type.

[0023] In this specification, the doping concentration refers to the concentration of an impurity activated as a donor or an acceptor. In this specification, the difference in concentration between the donor and the acceptor may be referred to as the doping concentration. The difference in concentration can be measured by a voltage-capacitance measurement method (CV method). The carrier concentration measured by a spreading resistance measurement method (SR) may be referred to as the doping concentration. When the doping concentration distribution has a peak, the peak value may be referred to as the doping concentration in the region. When the doping concentration in the region where the donor or the acceptor is present is almost uniform, the average value of the doping concentration may be referred to as the doping concentration in the region. In this specification, the concentration of the dopant refers to the respective concentrations of the donor and the acceptor.

[0024] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0025] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has edges 102 in a top view. When the term "top view" is used in this specification, it means that the semiconductor substrate 10 is viewed from the top surface side. The semiconductor substrate 10 of this example has two pairs of edges 102 that face each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to either of the edges 102. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0026] An active portion 120 is provided on the semiconductor substrate 10. The active portion 120 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in the on state. An emitter electrode 52 is provided above the active portion 120. In FIG. 1, the emitter electrode 52 is hatched with oblique lines.

[0027] In the example of FIG. 1, the emitter electrode 52 has three partial electrodes 52-1, 52-2, and 52-3. Each partial electrode is a part of the emitter electrode 52. The partial electrodes may be separated from each other or may be connected to each other. The active portion 120 may refer to a region that overlaps with the emitter electrode 52 in a top view. In this example, the active portion 120 also includes a region sandwiched between the emitter electrodes 52 in a top view. The active portion 120 in this example may be a rectangular region that circumscribes the emitter electrode 52 in a top view.

[0028] The active section 120 is provided with a transistor section including a transistor element such as an IGBT. The active section 120 may further be provided with a diode section including a diode element such as an FWD. A gate trench section and a dummy trench section are provided on the upper surface of the semiconductor substrate 10 in the active section 120. The gate trench section functions as a gate electrode to which a gate potential is applied in the transistor section. The dummy trench section is provided in the transistor section or the diode section, and an emitter potential is applied to the dummy trench section. The dummy trench section is electrically connected to an emitter electrode.

[0029] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 111, a screening pad 112, an anode pad 113, and a cathode pad 114. In addition, a pad for current detection and the like may be provided. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0030] A gate potential is applied to the gate pad 111. The gate pad 111 is electrically connected to a conductive portion of the gate trench portion of the active portion 120. The semiconductor device 100 includes a gate wiring that connects the gate pad 111 and the gate trench portion. In FIG. 1, the gate wiring is hatched with oblique lines.

[0031] The gate wiring in this example has a peripheral gate wiring 140 and an active side gate wiring 141. The peripheral gate wiring 140 is disposed between the emitter electrode 52 and the edge 102 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 140 in this example surrounds the active portion 120 in a top view. The peripheral gate wiring 140 is also connected to the gate pad 111. The peripheral gate wiring 140 is disposed above the semiconductor substrate 10. The peripheral gate wiring 140 may be a metal wiring.

[0032] The active side gate wiring 141 is disposed between two partial electrodes in top view. That is, the active side gate wiring 141 is provided in the active portion 120. By providing the active side gate wiring 141 in the active portion 120, it is possible to reduce variation in wiring length from the gate pad 111 for each region of the semiconductor substrate 10.

[0033] The active side gate wiring 141 is connected to a gate trench portion of the active section 120. The active side gate wiring 141 is disposed above the semiconductor substrate 10. The active side gate wiring 141 may be a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0034] The active side gate wiring 141 may be connected to the peripheral gate wiring 140. The active side gate wiring 141 of this example is provided extending in the X-axis direction from the peripheral gate wiring 140 to the inside of the active section 120. The active side gate wiring 141 of this example is provided between the partial electrodes 52-1 and 52-2 and between the partial electrodes 52-1 and 52-3. The active side gate wiring 141 may be provided across the active section 120. In the example of FIG. 1, the active side gate wiring 141 is divided by a temperature sensor 117 to be described later. That is, the active side gate wiring 141 is arranged to sandwich the temperature sensor 117.

[0035] A screening potential is applied to the screening pad 112 when the semiconductor device 100 is inspected. The screening pad 112 is electrically connected to the conductive portion of the dummy trench portion of the active portion 120. The dummy trench portion has a conductive portion and an insulating film. The insulating film is provided between the conductive portion and the semiconductor substrate 10. When the semiconductor device 100 is inspected, an emitter potential is applied to the semiconductor substrate 10 to apply a screening potential to the conductive portion of the dummy trench portion. An emitter potential may be applied to the semiconductor substrate 10 from the emitter electrode 52. This allows a predetermined voltage to be applied to the insulating film of the dummy trench portion to inspect the quality of the insulating film. When the semiconductor device 100 is mounted, the screening pad 112 is electrically connected to the emitter electrode 52. This allows an emitter potential to be applied to the dummy trench portion.

[0036] The semiconductor device 100 includes a dummy wiring. The dummy wiring connects the screening pad 112 and the dummy trench portion. The dummy wiring in this example includes a peripheral dummy wiring 130 and an active side dummy wiring 131. The peripheral dummy wiring 130 is disposed between the emitter electrode 52 and the edge 102 of the semiconductor substrate 10 in a top view. The peripheral dummy wiring 130 in this example surrounds the active portion 120 in a top view. The peripheral dummy wiring 130 may be disposed between the active portion 120 and the peripheral gate wiring 140. The peripheral dummy wiring 130 may be disposed between the peripheral gate wiring 140 and the edge 102 of the semiconductor substrate 10. The peripheral dummy wiring 130 is connected to the screening pad 112. The peripheral dummy wiring 130 is disposed above the semiconductor substrate 10. The peripheral dummy wiring 130 may be a metal wiring.

[0037] The active side dummy wiring 131 is disposed between two partial electrodes when viewed from above. That is, the active side dummy wiring 131 is provided in the active section 120. By providing the active side dummy wiring 131 in the active section 120, it is possible to reduce variation in wiring length from the screening pad 112 for each region of the semiconductor substrate 10.

[0038] The active side dummy wiring 131 is connected to the dummy trench portion of the active section 120. The active side dummy wiring 131 is disposed above the semiconductor substrate 10. The active side dummy wiring 131 may be a metal wiring.

[0039] The active side dummy wiring 131 may be connected to the peripheral dummy wiring 130. The active side dummy wiring 131 in this example is provided extending in the X-axis direction from the peripheral dummy wiring 130 to the inside of the active section 120. The active side dummy wiring 131 in this example is provided between the partial electrodes 52-1 and 52-2 and between the partial electrodes 52-1 and 52-3. The active side dummy wiring 131 may be provided across the active section 120. In the example of FIG. 1, the active side dummy wiring 131 is divided by the temperature sensor 117 described later. That is, the active side dummy wiring 131 is arranged to sandwich the temperature sensor 117.

[0040] One of the active side gate wiring 141 and the active side dummy wiring 131 is entirely covered in the first direction by the other of the active side gate wiring 141 and the active side dummy wiring 131. The first direction in this example is the Y-axis direction. In this example, the active side gate wiring 141 is entirely covered in the Y-axis direction by the active side dummy wiring 131. That is, both ends of the active side gate wiring 141 in the Y-axis direction are disposed in a region sandwiched between both ends of the active side dummy wiring 131 in the Y-axis direction. The active side gate wiring 141 may have an area not covered by the active side dummy wiring 131 at any position in the X-axis direction. In the example of FIG. 1, a portion 150 of the active side gate wiring 141 that contacts the peripheral gate wiring 140 is not covered by either the active side dummy wiring 131 or the peripheral dummy wiring 130. The length in the X-axis direction of the portion of the active side gate wiring 141 that is covered by the active side dummy wiring 131 and the peripheral dummy wiring 130 may be five times or more, or may be ten times or more, the length in the X-axis direction of the portion 150 that is not covered by the active side dummy wiring 131 and the peripheral dummy wiring 130. The length in the X-axis direction of the portion 150 corresponds to the distance between the peripheral gate wiring 140 and the peripheral dummy wiring 130.

[0041] By providing the active side gate wiring 141 and the active side dummy wiring 131 so as to overlap, the area occupied by the active side gate wiring 141 and the active side dummy wiring 131 can be reduced. This makes it possible to secure the area for elements such as transistors in the active section 120. One of the active side gate wiring 141 and the active side dummy wiring 131 may be a metal wiring and the other a semiconductor wiring. This makes it easy to overlap the two wirings. The metal wiring may be disposed above the semiconductor wiring. An interlayer insulating film is provided between the two wirings.

[0042] In this example, the active side dummy wiring 131 is a metal wiring, and the active side gate wiring 141 is a semiconductor wiring. In another example, the active side dummy wiring 131 may be a semiconductor wiring, and the active side gate wiring 141 may be a metal wiring. In this case, the peripheral dummy wiring 130 may be disposed between the peripheral gate wiring 140 and the edge 102 of the semiconductor substrate 10.

[0043] The temperature sensing section 117 is a PN junction diode made of polysilicon or the like. The temperature sensing section 117 is disposed above the semiconductor substrate 10. The temperature sensing section 117 may be disposed between the partial electrodes 52-1, 52-2, and 52-3, i.e., approximately at the center of the active section 120. An interlayer insulating film is provided between the temperature sensing section 117 and the semiconductor substrate 10. The anode pad 113 and the cathode pad 114 are connected to the anode region and the cathode region of the temperature sensing section 117 by wirings 118 and 119.

[0044] The semiconductor device 100 of this example includes an edge termination structure 90 between the peripheral gate wiring 140 and the edge 102. The edge termination structure 90 relieves electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has, for example, at least one of a guard ring, a field plate, and a RESURF structure provided in an annular shape surrounding the active portion 120, or a structure that combines a plurality of these structures.

[0045] In this example, the screening pad 112 and the gate pad 111 are disposed near the common edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode 52. The anode pad 113 and the cathode pad 114 may be disposed near the edge 102 on the opposite side to the gate pad 111.

[0046] Fig. 2 is an enlarged view of region A in Fig. 1. Fig. 2 shows partial electrodes 52-1 and 52-2, active side gate wiring 141, active side dummy wiring 131, connection portion 25, gate trench portion 40, and dummy trench portion 30, and omits other members. In Fig. 2, the gate trench portion 40 is marked with the symbol G, and the dummy trench portion 30 is marked with the symbol E.

[0047] The gate trench portion 40 and the dummy trench portion 30 have a longitudinal direction in the Y-axis direction in a top view. That is, the gate trench portion 40 and the dummy trench portion 30 are provided extending in the Y-axis direction. The gate trench portion 40 and the dummy trench portion 30 may have a straight line portion parallel to the Y-axis direction.

[0048] The gate trench portions 40 and the dummy trench portions 30 are arranged at a predetermined interval in the X-axis direction. The arrangement pattern of the gate trench portions 40 and the dummy trench portions 30 is not limited to the example of FIG. 2. A group including one or more gate trench portions 40 and a group including one or more dummy trench portions 30 may be arranged alternately along the X-axis direction. In this specification, a region of the semiconductor substrate 10 sandwiched between two trench portions in the X-axis direction may be referred to as a mesa portion.

[0049] At least one trench portion may have two straight portions connected at their ends by a curved end portion. In the example of FIG. 2, the dummy trench portion 30 has two straight portions 29 and one end portion 31.

[0050] The gate trench portion 40 is connected to the active side gate wiring 141. The gate trench portion 40 may have a region overlapping with the active side gate wiring 141 in a top view. The gate trench portion 40 may be connected to the active side gate wiring 141 in the region overlapping with the active side gate wiring 141. The gate trench portion 40 of this example is provided extending in the Y-axis direction from a position overlapping with the partial electrode 52-1 to a position overlapping with the partial electrode 52-2, and intersects with the active side gate wiring 141 and the active side dummy wiring 131 extending in the X-axis direction. In other words, the gate trench portion 40 crosses the active side gate wiring 141 and the active side dummy wiring 131 in the Y-axis direction.

[0051] The dummy trench portion 30 is connected to the active side dummy wiring 131. The dummy trench portion 30 may have a region overlapping with the active side dummy wiring 131 in a top view. The dummy trench portion 30 may be connected to the active side dummy wiring 131 in a region where the dummy trench portion 30 does not overlap with the active side gate wiring 141 and overlaps with the active side dummy wiring 131 in a top view. An end portion of the dummy trench portion 30 in the Y-axis direction may be disposed in a region where the dummy trench portion 30 does not overlap with the active side gate wiring 141 and overlaps with the active side dummy wiring 131 in a top view. In this example, the tip portion 31 of the dummy trench portion 30 is disposed in that region.

[0052] The dummy trench portion 30 may be arranged so as not to overlap with the active side gate wiring 141. In this example, the active side gate wiring 141 is arranged between the dummy trench portion 30 overlapping with the partial electrode 52-1 and the dummy trench portion 30 overlapping with the partial electrode 52-2. In other words, the active side gate wiring 141 is provided so as to divide the dummy trench portion 30 extending in the Y-axis direction.

[0053] The semiconductor device 100 may have a connection portion 25. The connection portion 25 is formed of polysilicon doped with impurities or the like. The connection portion 25 connects the conductive portion of the dummy trench portion 30 and the active side dummy wiring 131. The connection portion 25 has a width in the X-axis direction greater than that of the dummy trench portion 30. By providing the connection portion 25, the dummy trench portion 30 and the active side dummy wiring 131 can be easily connected.

[0054] Fig. 3 is a diagram showing an example of the bb cross section in Fig. 2. The bb cross section is a YZ cross section passing through the partial electrodes 52-1 and 52-2, the active side gate wiring 141, and the active side dummy wiring 131. In this cross section, the semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, the partial electrodes 52-1 and 52-2, and a collector electrode 24.

[0055] The interlayer insulating film 38 is provided to cover the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be a thermal oxide film, glass such as BPSG, or another insulating film. The interlayer insulating film 38 may also be a film in which a plurality of insulating films are stacked.

[0056] Partial electrodes 52-1, 52-2, 52-3 of the emitter electrode 52 and the active side dummy wiring 131 are provided on the upper surface of the interlayer insulating film 38. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The collector electrode 24, the emitter electrode 52, and the active side dummy wiring 131 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (i.e., the Z-axis direction) is referred to as the depth direction.

[0057] The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 provided in the interlayer insulating film 38. The emitter electrode 52 may contact a P-type base region 14 provided on the upper surface 21 of the semiconductor substrate 10. The base region 14 functions, for example, as an anode region of a diode section. The base region 14 also functions, for example, as a channel region of a transistor section.

[0058] The active side dummy wiring 131 is disposed between the partial electrodes 52-1 and 52-2 in the Y-axis direction. The active side dummy wiring 131 is connected to the connection portion 25 via a contact hole 55 provided in the interlayer insulating film 38. The connection portion 25 connects the active side dummy wiring 131 and the dummy conductive portion 34 of the dummy trench portion 30 (the tip portion 31 in this example).

[0059] The active side gate wiring 141 is disposed between the partial electrodes 52-1 and 52-2 in the Y-axis direction. The active side gate wiring 141 is entirely covered in the Y-axis direction by the active side dummy wiring 131 disposed above the active side gate wiring 141. The active side gate wiring 141 and the active side dummy wiring 131 are insulated by the interlayer insulating film 38. The active side gate wiring 141 and the semiconductor substrate 10 are also insulated by the interlayer insulating film 38. However, the active side gate wiring 141 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film 38 in a cross section different from the cross section shown in FIG. 3.

[0060] The tip portion 31 of the dummy trench portion 30 may be covered with a P+ type well region 11. The well region 11 is a region that has a higher doping concentration than the base region 14, is formed in contact with the upper surface 21 of the semiconductor substrate 10, and is formed to a position deeper than the bottom of the base region 14. By disposing the tip portion 31 inside the well region 11, electric field concentration at the tip portion 31 can be alleviated.

[0061] The well region 11 may be provided in a range in the Y-axis direction that is wider than the active-side gate wiring 141. The well region 11 may be provided continuously from one end portion 31 arranged on either side of the active-side gate wiring 141 in the Y-axis direction to the other end portion 31.

[0062] The active side dummy wiring 131 may be provided in a range overlapping with the well region 11 in the Y-axis direction, or may be provided in a range wider than the well region 11. However, the active side dummy wiring 131 is provided in a range not overlapping with the contact hole 54.

[0063] According to this example, the entire active side gate wiring 141 is arranged to overlap with the active side dummy wiring 131. This makes it possible to reduce the area occupied by the active side gate wiring 141 and the active side dummy wiring 131 in the active section 120. This makes it possible to secure the area for element regions such as transistors in the active section 120.

[0064] A P+ type collector region 22 is provided on the lower surface 23 of the semiconductor substrate 10. The collector region 22 functions as a collector of an IGBT (insulated gate bipolar transistor). An N- type drift region 18 is provided above the collector region 22. An N+ type cathode region that functions as a cathode of a diode may be provided on the lower surface 23 of the semiconductor substrate 10, and an N+ type drain region that functions as a drain of a MOS transistor may be provided.

[0065] 4 is a diagram showing an example of an element arrangement in the active section 120. The active section 120 of this example is provided with a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as an FWD (freewheel diode).

[0066] In FIG. 4, the region in which the transistor section 70 is arranged is marked with the symbol "I", and the region in which the diode section 80 is arranged is marked with the symbol "F". The transistor section 70 and the diode section 80 are arranged side by side along a predetermined arrangement direction (the X-axis direction in FIG. 4). The transistor section 70 and the diode section 80 may be arranged alternately side by side in the X-axis direction. In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of the trench section.

[0067] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A collector region 22 may be provided in a region other than the cathode region on the lower surface of the semiconductor substrate 10. In this specification, an extension region 81 in which the diode section 80 is extended in the Y-axis direction to the gate wiring or the dummy wiring may also be included in the diode section 80. The collector region 22 is provided on the lower surface of the extension region 81.

[0068] Fig. 5 is an enlarged view of region C in Fig. 4. Region C is a region including the transistor section 70, the diode section 80, the active side gate wiring 141, and the active side dummy wiring 131. The semiconductor substrate 10 of this example is provided with a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, which are in contact with the upper surface of the semiconductor substrate 10. The semiconductor substrate 10 of this example is also provided with a cathode region 82 and a collector region 22, which are in contact with the lower surface of the semiconductor substrate 10.

[0069] Moreover, an emitter electrode 52, an active side dummy wiring 131, and an active side gate wiring 141 are provided above the semiconductor substrate 10. An interlayer insulating film is provided between the emitter electrode 52 and the upper surface of the semiconductor substrate 10, but is omitted in Fig. 5. In the interlayer insulating film of this example, a contact hole 56 and a contact hole 54 are provided so as to penetrate the interlayer insulating film.

[0070] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The active side dummy wiring 131 is connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 may be provided between the active side dummy wiring 131 and the dummy conductive portion.

[0071] An insulating film such as a thermal oxide film is provided between the active side gate wiring 141 and the semiconductor substrate 10. The active side gate wiring 141 is connected to a gate conductive portion in the gate trench portion 40 on the upper surface of the semiconductor substrate 10. The active side gate wiring 141 is not connected to a dummy conductive portion in the dummy trench portion 30. The active side gate wiring 141 is connected to a gate conductive portion in the gate trench portion 40 through a contact hole 56 provided in the insulating film. The gate trench portion 40, the dummy trench portion 30, the active side gate wiring 141, and the active side dummy wiring 131 have the same arrangement and configuration as the example shown in FIG. 2.

[0072] The transistor section 70 is provided with a gate trench section 40. The diode section 80 is provided with a dummy trench section 30. The transistor section 70 may also be provided with a dummy trench section 30.

[0073] In the semiconductor substrate 10, the region between the trench portions is called a mesa portion. The transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. The mesa portion is a region of the semiconductor substrate 10 between the trench portions, which is located above the deepest bottom of the trench portions.

[0074] A P-type base region 14 is provided in each mesa portion. The base region 14 is exposed on a part of the upper surface of the mesa portion. A contact region 15 and an emitter region 12 are provided on the upper surface of the base region 14 of the transistor portion 70. The contact region 15 in this example is a P+ type having a higher doping concentration than the base region 14. The emitter region 12 in this example is an N+ type having a higher doping concentration than the drift region 18 shown in FIG. 3.

[0075] The emitter region 12 is provided in contact with the gate trench portion 40 on the upper surface of the semiconductor substrate 10. The emitter region 12 and the contact region 15 of this example are provided from one trench portion to the other trench portion sandwiching the mesa portion 60. On the upper surface of the mesa portion 60 of this example, the contact regions 15 and the emitter region 12 are alternately arranged along the Y-axis direction. Of the contact regions 15 provided in the mesa portion 60, the contact region 15 arranged at the extreme end in the Y-axis direction may be provided at a position overlapping with the end of the contact hole 54 in the Y-axis direction. The emitter region 12 is arranged in the range in which the contact hole 54 is provided in the Y-axis direction.

[0076] In another example, the mesa portion 60 may have the contact region 15 and the emitter region 12 provided in a stripe shape along the Y-axis direction. For example, one emitter region 12 is provided in contact with one of the two trench portions sandwiching the mesa portion 60, while the other emitter region 12 is provided in contact with the other trench portion. The contact region 15 is provided in a region sandwiched between the one emitter region 12 and the other emitter region 12. A base region 14 may be disposed on the upper surface of the mesa portion 60, sandwiching the region in which the contact region 15 and the emitter region 12 are provided in the Y-axis direction.

[0077] The mesa portion 61 of the diode portion 80 may not be provided with the emitter region 12. In this example, a base region 14 is provided on the upper surface of the mesa portion 61. The base region 14 may occupy more than half the area of ​​the upper surface of the mesa portion 61. A contact region 15 may be disposed on the upper surface of the mesa portion 61. The contact region 15 of the mesa portion 61 may be provided at a position overlapping with the end of the contact hole 54 in the Y-axis direction. The base region 14 may be provided on the upper surface of the mesa portion 61, sandwiching the contact region 15 in the Y-axis direction.

[0078] The contact hole 54 provided in the transistor section 70 and the contact hole 54 provided in the diode section 80 may have the same length in the Y-axis direction or may have different lengths. In the transistor section 70, the contact hole 54 is provided above the contact region 15 and the emitter region 12. The contact hole 54 in this example is not provided in the region corresponding to the base region 14 and the well region 11 of the mesa section 60. In the diode section 80, the contact hole 54 is provided above the contact region 15 and the base region 14. However, the contact hole 54 is not provided above the base region 14 sandwiched between the contact region 15 and the well region 11 in the mesa section 61.

[0079] In the diode section 80, an N+ type cathode region 82 is provided in a region in contact with the lower surface of the semiconductor substrate 10. A collector region 22 is provided in a region in contact with the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. In the Y-axis direction, the cathode region 82 is disposed away from the active side dummy wiring 131. At least one of the base region 14 and the contact region 15 may be disposed between the cathode region 82 and the active side dummy wiring 131 in a top view. In this example, the distance in the Y-axis direction between the cathode region 82 and the active side dummy wiring 131 is greater than the distance in the Y-axis direction between the contact hole 54 and the active side dummy wiring 131.

[0080] Fig. 6 is a diagram showing an example of a dd cross section in Fig. 5. The dd cross section is an XZ plane passing through the emitter region 12. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0081] A P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in the cross section. An N+ type emitter region 12 and a P- type base region 14 are provided in this order from the upper surface 21 of the semiconductor substrate 10 in the transistor section 70 in this cross section. An N+ type accumulation region may be provided below the base region 14. In this cross section, a P- type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in the diode section 80.

[0082] In the transistor section 70 and the diode section 80, an N− type drift region 18 is provided below the base region 14. In the transistor section 70 and the diode section 80, an N+ type buffer region 20 is provided below the drift region 18.

[0083] The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0084] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. In the diode section 80, a cathode region 82 is provided below the buffer region 20.

[0085] On the upper surface 21 side of the semiconductor substrate 10, one or more gate trench portions 40 and one or more dummy trench portions 30 are provided. Each trench portion is provided so as to reach the drift region 18 from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14. In a region where at least one of the emitter region 12 and the contact region 15 is provided, each trench portion also penetrates these regions and reaches the drift region 18. The trench portion penetrating the doping region is not limited to a case where the trench portion is formed in the order of forming the doping region and then the trench portion. A case where the trench portion is formed and then the doping region is formed between the trench portions is also included in the case where the trench portion penetrates the doping region.

[0086] The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44 provided on the upper surface 21 side of the semiconductor substrate 10. The gate insulating film 42 is provided to cover the inner wall of the gate trench portion 40. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench portion 40. The gate conductive portion 44 is provided inside the gate insulating film 42 inside the gate trench portion 40. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0087] The gate conductive portion 44 includes a region facing the base region 14 with the gate insulating film 42 interposed therebetween. The gate trench portion 40 in this cross section is covered with the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0088] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 has a dummy trench provided on the upper surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided on the inner side of the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0089] 7 is a diagram showing another structural example of the emitter electrode 52. The emitter electrode 52 of this example has a bridge portion 53 that connects two partial electrodes together. The emitter electrode 52 of this example has a bridge portion 53 that connects partial electrodes 52-1 and 52-2 together, and a bridge portion 53 that connects partial electrodes 52-1 and 52-3 together. The bridge portion 53 may be formed of the same material as the partial electrodes.

[0090] Each of the active side dummy wirings 131 is divided into at least two partial wirings by the bridge portion 53. In the example of Fig. 7, each of the active side dummy wirings 131 is divided into partial wirings 131-1 and 131-2. That is, the bridge portion 53 is provided between the partial wirings 131-1 and 131-2.

[0091] 8 is an enlarged view of region E in FIG. 7. Region E is a region in the vicinity of the bridge portion 53. In FIG. 8, the partial electrodes 52-1, 52-2, the bridge portion 53, the active side gate wiring 141, the active side dummy wiring 131, at least one intersecting dummy wiring 132, and each trench portion are shown, and other members are omitted. In FIG. 8, the active side gate wiring 141 and the intersecting dummy wiring 132 are entirely hatched with oblique lines. Moreover, the partial electrodes 52-1, 52-2, the bridge portion 53, and the active side dummy wiring 131 are hatched with oblique lines only at their ends.

[0092] As described above, the active side dummy wiring 131 is divided into the partial wiring 131-1 and the partial wiring 131-2 by the bridge portion 53. The bridge portion 53 passes between the partial wiring 131-1 and the partial wiring 131-2 and connects the partial electrodes 52-1 and 52-2.

[0093] The intersecting dummy wiring 132 is provided to intersect with the bridge portion 53, and connects the partial wiring 131-1 and the partial wiring 131-2 to each other. In this example, the intersecting dummy wiring 132 is provided to cross the lower part of the bridge portion 53 in the X-axis direction from the partial wiring 131-1 to the partial wiring 131-2. The intersecting dummy wiring 132 may be wiring made of a semiconductor material such as polysilicon doped with impurities. The intersecting dummy wiring 132 is disposed between the semiconductor substrate 10 and the active side dummy wiring 131 and bridge portion 53.

[0094] The intersecting dummy wirings 132 are insulated from the semiconductor substrate 10, the active side dummy wirings 131, and the bridge portion 53 by an interlayer insulating film. The intersecting dummy wirings 132 are connected to the active side dummy wirings 131 at positions where they overlap with each other through contact holes provided in the interlayer insulating film.

[0095] By providing the bridge portion 53, it is possible to reduce variations in the potential in the emitter electrode 52. In addition, by providing the intersecting dummy wiring 132, it is possible to connect the active side dummy wiring 131 that is divided by the bridge portion 53. This makes it possible to transmit the screening potential to the inside of the active portion 120.

[0096] The active side gate wiring 141 is not divided by the bridge portion 53. In this example, the active side gate wiring 141 is provided so as to intersect with the bridge portion 53. That is, the active side gate wiring 141 crosses below the bridge portion 53 in the X-axis direction. This allows the gate potential to be transmitted to the inside of the active portion 120.

[0097] In addition, by using semiconductor wiring for the active side gate wiring 141, it becomes easy to cross the bridge portion 53 and the active side gate wiring 141. Therefore, the gate potential can be transmitted by the single active side gate wiring 141, and attenuation of the gate potential can be suppressed.

[0098] The intersecting dummy wirings 132 may be connected to the dummy trench portions 30. This allows a screening potential to be applied to the dummy trench portions 30 even in the region where the bridge portion 53 is provided. The intersecting dummy wirings 132 may be arranged on either side of the active side gate wiring 141 in the Y-axis direction. This allows the intersecting dummy wirings 132 to be easily connected to the dummy trench portions 30 on the partial electrode 52-1 side and the dummy trench portions 30 on the partial electrode 52-2 side.

[0099] A dummy trench portion 30 may be disposed below the bridge portion 53. A gate trench portion 40 may be disposed below the bridge portion 53. In this example, the dummy trench portion 30 is disposed below the bridge portion 53, and the gate trench portion 40 is not disposed.

[0100] The bridge portion 53 may be provided in the diode portion 80. In this case, the intersecting dummy wiring 132 is connected to the dummy trench portion 30 of the diode portion 80. The dummy trench portion 30 may have a tip portion at a position overlapping with the intersecting dummy wiring 132.

[0101] The dummy trench portion 30 of the transistor portion 70 is connected to the active side dummy wiring 131 (partial wiring 131-1, partial wiring 131-2 in this example). With this configuration, each dummy trench portion 30 can be easily connected to the dummy wiring. Also, since the active side gate wiring 141 is not divided, each gate trench portion 40 can be easily connected to the active side gate wiring 141.

[0102] FIG. 9 is a diagram showing an example of the hh cross section in FIG. 8. The hh cross section is a YZ cross section passing through the two intersecting dummy wirings 132 and the active side gate wiring 141. The two intersecting dummy wirings 132 and the active side gate wiring 141 are provided between the bridge portion 53 and the semiconductor substrate 10. The two intersecting dummy wirings 132 and the active side gate wiring 141 may be provided at the same height position. The two intersecting dummy wirings 132 and the active side gate wiring 141 are insulated from the bridge portion 53 by the interlayer insulating film 38. The two intersecting dummy wirings 132 and the active side gate wiring 141 are also insulated from the semiconductor substrate 10 by the interlayer insulating film 38. However, the intersecting dummy wirings 132 are connected to the dummy conductive portion 34 of the dummy trench portion 30 through a contact hole 56 provided in the interlayer insulating film 38.

[0103] Fig. 10 is a diagram showing an example of a cross section ii in Fig. 8. The cross section ii is an XZ cross section including the partial wiring 131-1, the partial wiring 131-2, and the bridge portion 53. The partial wiring 131-1, the partial wiring 131-2, and the bridge portion 53 are disposed on the interlayer insulating film 38. The partial wirings 131-1, 131-2, and the bridge portion 53 may be provided at the same height position.

[0104] The intersecting dummy wirings 132 are provided between the partial wirings 131-1, 131-2, and bridge portion 53 and the semiconductor substrate 10. The intersecting dummy wirings 132 are insulated from the partial wirings 131-1, 131-2, and bridge portion 53 by the interlayer insulating film 38. However, the intersecting dummy wirings 132 are connected to the partial wirings 131-1 and 131-2 by contact holes 57 provided in the interlayer insulating film 38.

[0105] The intersecting dummy wiring 132 passes under the bridge portion 53 and extends in the X-axis direction from the partial wiring 131-1 to the partial wiring 131-2. This allows the partial wiring 131-1 and the partial wiring 131-2 to be connected to each other.

[0106] Fig. 11 is an enlarged view of region F in Fig. 7. Region F is a region in the vicinity of portion 150 where peripheral gate wiring 140 and active side gate wiring 141 are connected. In Fig. 11, peripheral gate wiring 140, peripheral dummy wiring 130, active side dummy wiring 131, and emitter electrode 52 are hatched with diagonal lines only at their ends. Also, active side gate wiring 141 is hatched with diagonal lines over its entirety.

[0107] The peripheral gate wiring 140 and the peripheral dummy wiring 130 are arranged without overlapping when viewed from above. In this example, the peripheral gate wiring 140 is arranged outside the peripheral dummy wiring 130. Outside refers to the side away from the active section 120. The active side dummy wiring 131 is connected to the peripheral dummy wiring 130. In this example, the active side dummy wiring 131 and the peripheral dummy wiring 130 are both metal wirings.

[0108] The active side gate wiring 141 is provided from below the active side dummy wiring 131, across the peripheral dummy wiring 130, and to below the peripheral gate wiring 140. The active side gate wiring 141 is connected to the peripheral gate wiring 140 at a position where it overlaps with the peripheral gate wiring 140. The active side gate wiring 141 of this example has a portion 150 between the peripheral dummy wiring 130 and the peripheral gate wiring 140 that is not covered by the dummy wiring.

[0109] The gate wiring may have a second peripheral wiring 144 provided along the peripheral gate wiring 140 below the peripheral gate wiring 140. The second peripheral wiring 144 may be made of the same material as the active side gate wiring 141 and may be formed at the same height as the active side gate wiring 141. The second peripheral wiring 144 is connected to the active side gate wiring 141. The second peripheral wiring 144 and the peripheral gate wiring 140 are connected by a contact hole provided in the interlayer insulating film. In FIG. 11, the second peripheral wiring 144 is entirely hatched with oblique lines.

[0110] 12 is an enlarged view of region G in FIG. 7. As described above, the active side gate wiring 141 and the active side dummy wiring 131 are divided by the temperature sensing section 117. Therefore, the active side gate wiring 141 and the active side dummy wiring 131 terminate in the vicinity of the temperature sensing section 117. The active side dummy wiring 131 may be provided closer to the temperature sensing section 117 than the active side gate wiring 141. In other words, the distance between the active side dummy wiring 131 and the temperature sensing section 117 may be smaller than the distance between the active side gate wiring 141 and the temperature sensing section 117. This allows the active side gate wiring 141 to be covered with the active side dummy wiring 131.

[0111] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0112] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0113] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 25 connection portion, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 42 gate insulating film, 44 gate conductive portion, 52 emitter electrode, 52-1, 52-2, 52-3 partial electrodes, 54, 55, 56, 57 contact hole, 60 , 61... mesa portion, 70... transistor portion, 80... diode portion, 81... extension region, 82... cathode region, 90... edge termination structure portion, 100... semiconductor device, 102... edge, 111... gate pad, 112... screening pad, 113... anode pad, 114... cathode pad, 117... temperature sensing portion, 118, 119... wiring, 120... active portion, 130... peripheral dummy wiring, 131... active side dummy wiring, 131-1, 131-2... partial wiring, 132... crossing dummy wiring, 140... peripheral gate wiring, 141... active side gate wiring, 144... second peripheral wiring, 150... portion

Claims

1. A semiconductor substrate provided with a transistor portion including a transistor element; A plurality of trenches each having a longitudinal direction in a first direction in a top view of the semiconductor substrate; an upper surface electrode provided above at least the transistor portion; a first wiring including a first metal wiring portion extending parallel to a first end side and a second end side of the semiconductor substrate opposed to each other in the first direction and provided on the outer side of the upper surface electrode in the first direction; a second wiring including a second metal wiring portion extending parallel to the first end side and the second end side and provided on the outer side of the upper surface electrode in the first direction; Equipped with the plurality of trench portions include a first trench portion having a conductive portion electrically connected to the first metal wiring portion, and a second trench portion having a conductive portion electrically connected to the second metal wiring portion; the upper surface electrode, the first metal wiring portion, and the second metal wiring portion are disposed at intervals in the first direction, the first metal wiring portion constitutes a part of a peripheral gate wiring which is a metal wiring; the second metal wiring portion constitutes a part of a peripheral dummy wiring which is a metal wiring, The second metal wiring portion is disposed on the outer side of the first metal wiring portion in the first direction. Semiconductor device.

2. A semiconductor substrate having a transistor portion including a transistor element; A plurality of trenches each having a longitudinal direction in a first direction in a top view of the semiconductor substrate; an upper surface electrode provided above at least the transistor portion; a first wiring including a first metal wiring portion extending parallel to a first end side and a second end side of the semiconductor substrate opposed to each other in the first direction and provided on the outer side of the upper surface electrode in the first direction; a second wiring including a second metal wiring portion extending parallel to the first end side and the second end side and provided on the outer side of the upper surface electrode in the first direction; a pad provided above the upper surface of the semiconductor substrate and separated from the upper surface electrode; Equipped with the plurality of trench portions include a first trench portion having a conductive portion electrically connected to the first metal wiring portion, and a second trench portion having a conductive portion electrically connected to the second metal wiring portion; the upper surface electrode, the first metal wiring portion, and the second metal wiring portion are disposed at intervals in the first direction, the first metal wiring portion constitutes a part of a peripheral gate wiring which is a metal wiring; the second metal wiring portion constitutes a part of a peripheral dummy wiring which is a metal wiring, The pad is disposed on the inner side of the second wiring in the first direction. Semiconductor device.

3. A semiconductor substrate provided with a transistor portion including a transistor element; A plurality of trenches each having a longitudinal direction in a first direction in a top view of the semiconductor substrate; an upper surface electrode provided above at least the transistor portion; a first wiring including a first metal wiring portion extending parallel to a first end side and a second end side of the semiconductor substrate opposed to each other in the first direction and provided on the outer side of the upper surface electrode in the first direction; a second wiring including a second metal wiring portion extending parallel to the first end side and the second end side and provided on the outer side of the upper surface electrode in the first direction; Equipped with the plurality of trench portions include a first trench portion having a conductive portion electrically connected to the first metal wiring portion, and a second trench portion having a conductive portion electrically connected to the second metal wiring portion; the upper surface electrode, the first metal wiring portion, and the second metal wiring portion are disposed at intervals in the first direction, the upper electrode includes at least two partial electrodes arranged at an interval when viewed from above, the second wiring includes an active side metal wiring portion disposed between the two partial electrodes, the active side metal wiring portion extends in a second direction perpendicular to the first direction in a top view, the active side metal wiring portion includes a terminal end portion, A bridge portion connecting the two partial electrodes is provided adjacent to the end portion. Semiconductor device.

4. the upper surface electrode overlaps, in a top view, an active portion which is a region through which a main current flows in a depth direction when the transistor portion is controlled to be in an on-state, The first wiring is provided below the first metal wiring portion and includes a semiconductor wiring surrounding the active portion and the second wiring.

4. The semiconductor device according to claim 2.

5. The second metal wiring portion is disposed between the first metal wiring portion and the upper surface electrode. The semiconductor device according to claim 2 .

6. a first pad provided above the semiconductor substrate and to which an external circuit can be connected; The first wiring connects the first pad and a conductive portion of the first trench portion. The semiconductor device according to claim 1 .

7. a second pad provided above the semiconductor substrate and to which an external circuit can be connected; The second wiring connects the second pad and a conductive portion of the second trench portion.

7. The semiconductor device according to claim 1, 3 or 6.

8. A connection portion electrically connecting the upper surface electrode and the second wiring is provided. The semiconductor device according to claim 2 .

9. The transistor element is an IGBT or a MOS transistor. The semiconductor device according to claim 1 .

10. The semiconductor substrate is a silicon or compound semiconductor substrate. The semiconductor device according to claim 1 .

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