Semiconductor Device

Abstract

Provided is a semiconductor device provided with a transistor unit, the semiconductor device comprising a first drift region of a first conductivity type provided on a semiconductor substrate, a plurality of trench portions extending from a front surface of the semiconductor substrate to the drift region, an emitter region of the first conductivity type that is provided extending from one trench portion to an adjacent trench portion of the plurality of trench portions in the front surface of the semiconductor substrate and has a higher doping concentration than the drift region, and a trench bottom portion of a second conductivity type provided at a lower end of the trench portions. The transistor unit, as seen in a top view, has an electron transmission region where the trench bottom portion is not provided.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 describes that at least a portion of the IGBT cell includes an electrically floating barrier region of a second conductivity type. [Prior art document] [Patent documents] [Patent Document 1] JP 2019-91892 A Problem to be Solved

[0003] By providing such a barrier region at the bottom of the trench, the avalanche resistance is improved, but there is a problem in that the transient resistance at the time of turn-on increases and the on-resistance deteriorates.

[0004] A first aspect of the present invention provides a semiconductor device, comprising a transistor portion, a drift region of a first conductivity type provided in a semiconductor substrate, a plurality of trench portions extending from a front surface of the semiconductor substrate to the drift region, an emitter region of the first conductivity type extending from one of the trench portions to an adjacent trench portion on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region, and a trench bottom portion of a second conductivity type provided at a lower end of the trench portion, and the transistor portion has an electron passing region in which the trench bottom portion is not provided in a top view.

[0005] The electron passing region may be provided extending from one of the plurality of trench portions to an adjacent trench portion in the trench arrangement direction.

[0006] The electron passing region extends across the plurality of trench portions in the trench arrangement direction.

[0007] The mesa portion of the electron passing region does not need to be provided with an emitter region.

[0008] A trench bottom may be provided below the emitter region.

[0009] The semiconductor device may further include a contact region of a second conductivity type provided on the front surface of the semiconductor substrate, and the electron passing region may be provided such that an end portion in the extension direction of the trench is located within the contact region when viewed from above.

[0010] The electron passing region may be provided with at least an emitter region.

[0011] The transistor portion may have a trench bottom region in which a trench bottom portion is formed in a top view, and the trench bottom region and the electron passing region may be provided alternately in a trench arrangement direction.

[0012] The electron passing region may be provided with at least a gate trench portion to which a gate voltage is applied.

[0013] The bottom of the trench may be electrically floating.

[0014] The doping concentration at the bottom of the trench is 1E12 cm -3 Above, 1E13cm -3 It may be the following:

[0015] The semiconductor device may further include an accumulation region of the first conductivity type provided above the drift region.

[0016] A drift region may be interposed between the accumulation region and the trench bottom.

[0017] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0018] [Figure 1] 1 is a diagram showing an example of the top surface of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2A] 2 is an enlarged view showing an example of the top surface of the semiconductor device 100. FIG. [Figure 2B] FIG. 2B is a diagram showing a cross section taken along line aa' in FIG. 2A. [Figure 2C] FIG. 2B is a diagram showing a cross section taken along the line bb' in FIG. 2A. [Figure 2D] FIG. 2B is a diagram showing a cross section taken along the line cc' in FIG. 2A. [Figure 2E] FIG. 2B is a diagram showing another example of the aa' cross section in FIG. 2A. [Figure 2F] FIG. 2B is a diagram showing another example of the aa' cross section in FIG. 2A. [Figure 3A] 1 is a diagram showing an example of the arrangement of a trench bottom region Rp and an electron passing region Rn. FIG. [Figure 3B] FIG. 3B is a diagram showing a cross section taken along line dd' in FIG. 3A. [Figure 4A] 1 is a diagram showing an example of the arrangement of a trench bottom region Rp and an electron passing region Rn. FIG. [Figure 4B] FIG. 4B is a diagram showing a cross section taken along the line ee' in FIG. 4A. [Figure 5A] 1 is a diagram showing an example of the arrangement of a trench bottom region Rp and an electron passing region Rn. FIG. [Figure 5B] FIG. 5B is a diagram showing the ff' cross section in FIG. 5A. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0020] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as the "top" or "front" and the other side as the "bottom" or "back". Of the two main surfaces of a substrate, layer or other member, one is referred to as the front surface and the other as the back surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0021] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, the +Z-axis and - This means the direction parallel to the Z axis.

[0022] In this specification, the orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Also, the axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Also, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0023] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0024] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0025] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration NA Then, the net doping concentration at any position is N D -N A It becomes.

[0026] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, the VOH defect, which is a combination of vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons.

[0027] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when it is described as P++ type or N++ type, it means that the doping concentration is higher than that of P+ type or N+ type.

[0028] In this specification, the chemical concentration refers to the concentration of an impurity measured regardless of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier concentration measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier concentration measured by CV or SR may be a value in a thermal equilibrium state. In the N-type region, the donor concentration is sufficiently larger than the acceptor concentration, so the carrier concentration in the region may be the donor concentration. Similarly, in the P-type region, the carrier concentration in the region may be the acceptor concentration.

[0029] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. In cases where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.

[0030] The carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0031] The donor or acceptor concentration calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0032] Fig. 1 is a diagram showing an example of the top surface of a semiconductor device 100 according to this embodiment. Fig. 1 shows the positions of each component projected onto the front surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0033] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has edges 102 in a top view. When simply referred to as a top view in this specification, it means a view from the front surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of edges 102 facing each other in a top view. In FIG. 1, the X-axis and the Y-axis are parallel to one of the edges 102. The Z-axis is perpendicular to the front surface of the semiconductor substrate 10.

[0034] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted in FIG.

[0035] The active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of Fig. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface of the semiconductor substrate 10. In another example, the active section 160 may be provided with only the transistor section 70.

[0036] In FIG. 1, the region in which the transistor section 70 is arranged is marked with the symbol "I", and the region in which the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0037] The transistor section 70 has a P+ type collector region in a region in contact with the rear surface of the semiconductor substrate 10. The diode section 80 has an N+ type cathode region in a region in contact with the rear surface of the semiconductor substrate 10. In this specification, the region in which the collector region is provided is referred to as the transistor section 70. In other words, the transistor section 70 is a region that overlaps with the collector region in a top view.

[0038] An N+ type cathode region may be provided on the rear surface of the semiconductor substrate 10 in a region other than the collector region. In this specification, the cathode region is provided on the lower surface of an extension region obtained by extending the transistor section 70 in the Y-axis direction to a gate runner, which will be described later. In this specification, the extension region is included in the diode section 80. In addition, in the transistor section 70, a gate structure having an N-type emitter region, a P-type base region, a gate conductive portion, and a gate insulating film is periodically arranged on the front surface side of the semiconductor substrate 10.

[0039] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. As an example, the semiconductor device 100 shown in FIG. 1 has a gate pad G, but this is merely an example. The semiconductor device 100 may have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0040] A gate potential is applied to the gate pad G. The gate pad G is electrically connected to a conductive portion of the gate trench portion of the active section 160. The semiconductor device 100 includes a gate runner 48 that electrically connects the gate pad G and the gate trench portion.

[0041] The gate runner 48 is disposed between the active portion 160 and the edge 102 of the semiconductor substrate 10 in a top view. The gate runner 48 of this example surrounds the active portion 160 in a top view. The area surrounded by the gate runner 48 in a top view may be the active portion 160.

[0042] The gate runner 48 is disposed above the semiconductor substrate 10. In this example, the gate runner 48 may be formed of polysilicon doped with impurities or the like. The gate runner 48 is electrically connected to a gate conductive portion provided inside the gate trench portion via a gate insulating film.

[0043] The semiconductor device 100 of this example includes a breakdown voltage structure portion 190 provided on the outer periphery of the active portion 160. The breakdown voltage structure portion 190 of this example is disposed between the gate runner 48 and the edge 102. The breakdown voltage structure portion 190 relieves electric field concentration on the front surface side of the semiconductor substrate 10.

[0044] The breakdown voltage structure 190 may include a guard ring 92. The guard ring 92 is a P-type region in contact with the front surface of the semiconductor substrate 10. Although the breakdown voltage structure 190 of this example includes multiple guard rings 92, only one guard ring 92 is shown in FIG. 1 . By providing multiple guard rings 92, the depletion layer on the upper surface side of the active section 160 can be extended outward, improving the breakdown voltage of the semiconductor device 100. The breakdown voltage structure 190 may further include at least one of a field plate and a resurf provided in a ring shape surrounding the active section 160.

[0045] Furthermore, the semiconductor device 100 may include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that operates in a similar manner to a transistor portion provided in the active portion 160.

[0046] Fig. 2A is an enlarged view showing an example of the top surface of the semiconductor device 100. Fig. 2A shows region A shown in Fig. 1, i.e., the vicinity of the boundary between the active section 160 and the voltage withstand structure section 190. The semiconductor device 100 includes a semiconductor substrate having a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD).

[0047] In this example, the transistor sections 70 and the diode sections 80 are alternately arranged along the arrangement direction (the X-axis direction in this example). In top view, the diode sections 80 are provided between the transistor sections 70 adjacent to the voltage withstand structure sections 190 and the voltage withstand structure sections 190. In other words, the diode sections 80 are arranged on the outermost side of the active section 160. In this specification, when simply referring to the "inner side" and the "outer side", the direction toward the center of the semiconductor device 100 refers to the inner side, and the direction away from the center refers to the outer side.

[0048] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, which are provided on the front surface side of a semiconductor substrate. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0049] The semiconductor device 100 of this example also includes a gate metal layer 50 and an emitter electrode 52 provided above the front surface of the semiconductor substrate. The gate metal layer 50 and the emitter electrode 52 are provided separately from each other. The gate metal layer 50 and the emitter electrode 52 are electrically insulated from each other.

[0050] An interlayer insulating film is provided between the emitter electrode 52 and the gate metal layer 50 and the front surface of the semiconductor substrate, but is omitted in Fig. 2A. In this example, contact holes 49, 54, and 56 are provided through the interlayer insulating film. In Fig. 2A, each contact hole is hatched with oblique lines.

[0051] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate through a contact hole 54.

[0052] Moreover, the emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 by a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided on the front surface of the semiconductor substrate via an insulating film such as an interlayer insulating film and a dummy insulating film of the dummy trench portion 30.

[0053] The gate metal layer 50 is electrically connected to the gate runner 48 through a contact hole 49. The gate runner 48 may be formed of polysilicon doped with impurities or the like. The gate runner 48 is connected to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate. The gate runner 48 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 and the emitter electrode 52.

[0054] The gate runner 48 and the emitter electrode 52 are electrically isolated by an insulator such as an interlayer insulating film and an oxide film. The gate runner 48 in this example is provided from below the contact hole 49 to the end of the gate trench portion 40. At the end of the gate trench portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate and is connected to the gate runner 48.

[0055] The emitter electrode 52 and the gate metal layer 50 are made of a conductive material containing a metal. For example, they are made of aluminum or an alloy mainly composed of aluminum (for example, an aluminum-silicon alloy, etc.). Each electrode may have a barrier metal made of titanium, a titanium compound, etc. under the region made of aluminum, etc.

[0056] Each electrode may have a plug formed of tungsten or the like in a contact hole. The plug may have a barrier metal on the side in contact with the semiconductor substrate, tungsten may be embedded so as to be in contact with the barrier metal, and aluminum or the like may be formed on the tungsten.

[0057] The plug is provided in a contact hole in contact with the contact region 15 or the base region 14. A P++ type plug region is formed under the contact hole of the plug, and has a higher doping concentration than the contact region 15. This can improve the contact resistance between the barrier metal and the contact region 15. The depth of the plug region is approximately 0.1 μm or less, and is smaller than the depth of the contact region 15 by 10% or less.

[0058] The plug region has the following features. In the operation of the transistor section 70, the latch-up resistance is improved by improving the contact resistance. On the other hand, in the operation of the diode section 80, if there is no plug region, the contact resistance between the barrier metal and the base region 14 is high, and the conduction loss and switching loss increase. plug By providing the region, increases in conduction loss and switching loss can be suppressed.

[0059] The well region 11 overlaps with the gate runner 48, extends around the periphery of the active portion 160, and is provided in a ring shape in a top view. The well region 11 also extends with a predetermined width into an area where it does not overlap with the gate runner 48, and is provided in a ring shape in a top view. The well region 11 in this example is provided away from the end of the contact hole 54 in the Y-axis direction toward the gate runner 48. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. The gate runner 48 is electrically insulated from the well region 11.

[0060] In this example, the base region 14 is P- type, and the well region 11 is P+ type. The well region 11 is formed from the front surface of the semiconductor substrate to a position deeper than the lower end of the base region 14. The base region 14 is provided in contact with the well region 11 in the transistor portion 70 and the diode portion 80. Therefore, the well region 11 is electrically connected to the emitter electrode 52.

[0061] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the arrangement direction. The transistor section 70 of this example is provided with one or more gate trench sections 40 along the arrangement direction. The diode section 80 of this example is provided with a plurality of dummy trench sections 30 along the arrangement direction. The diode section 80 of this example is not provided with a gate trench section 40.

[0062] The gate trench portion 40 in this example may have two straight portions 39 (portions of the trench that are straight along the extension direction) extending along an extension direction perpendicular to the arrangement direction, and a tip portion 41 connecting the two straight portions 39.

[0063] At least a part of the tip 41 may be curved in top view. The tip 41 connects the ends of the two straight portions 39 in the Y-axis direction to the gate runner 48, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the tip 41 curved, electric field concentration at the end can be alleviated more effectively than if the tip 41 were completed at the straight portion 39.

[0064] In another example, the transistor section 70 may have one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the arrangement direction. In the transistor section 70, the dummy trench sections 30 are provided between the respective straight line portions 39 of the gate trench sections 40. One dummy trench section 30 may be provided between each straight line portion 39, or multiple dummy trench sections 30 may be provided.

[0065] Furthermore, the dummy trench portion 30 does not have to be provided between the respective straight line portions 39, and the gate trench portion 40 may be provided between the respective straight line portions 39. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-voltage.

[0066] The dummy trench portion 30 may have a linear shape extending in the extension direction, and may have a linear portion 29 and a tip portion 31, similar to the gate trench portion 40. In the semiconductor device 100 shown in FIG. 2A, only the dummy trench portions 30 having the tip portions 31 are arranged, but in other examples, the semiconductor device 100 may include linear dummy trench portions 30 that do not have the tip portions 31.

[0067] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottoms of each trench portion in the depth direction are covered by the well region 11. In addition, the trench portion provided at the ends in the X-axis direction may be covered by the well region 11. This can alleviate electric field concentration at the bottoms of each trench portion.

[0068] A mesa portion is provided between each of the trench portions in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate that is sandwiched between the trench portions. As an example, the depth position of the mesa portion is from the front surface of the semiconductor substrate to the bottom end of the trench portion.

[0069] The mesa portion in this example is sandwiched between adjacent trench portions in the X-axis direction, and is provided on the front surface of the semiconductor substrate so as to extend in the extension direction (Y-axis direction) along the trenches. As will be described later with reference to FIG. 2B, in this example, the transistor portion 70 is provided with a mesa portion 60, and the diode portion 80 is provided with a mesa portion 61. In this specification, the term "mesa portion" refers to both the mesa portion 60 and the mesa portion 61.

[0070] Each mesa portion is provided with a base region 14. In each mesa portion, at least one of a first conductive type emitter region 12 and a second conductive type contact region 15 may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate in the depth direction.

[0071] The mesa portion of the transistor section 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate.

[0072] Each of the contact region 15 and the emitter region 12 in the mesa portion is provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact region 15 and the emitter region 12 in the mesa portion are alternately arranged along the extension direction of the trench portion (the Y-axis direction).

[0073] In another example, the contact region 15 and the emitter region 12 of the mesa portion may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0074] The emitter region 12 is not provided in the mesa portion of the diode portion 80. The base region 14 may be provided on the upper surface of the mesa portion of the diode portion 80. The base region 14 may be disposed over the entire mesa portion of the diode portion 80.

[0075] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14 in the extension direction (Y-axis direction). The contact holes 54 in this example are provided above the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 may be arranged in the center in the arrangement direction of the mesa portions (X-axis direction).

[0076] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate. In the back surface of the semiconductor substrate, a P+ type collector region 22 may be provided in a region where the cathode region 82 is not provided. In FIG. 2A, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line. In the voltage withstand structure section 190, an N+ type cathode region 82 may also be provided on the back surface side of the semiconductor substrate.

[0077] Fig. 2B is a diagram showing the a-a' cross section in Fig. 2A. The a-a' cross section is an XZ plane passing through the contact region 15, the base region 14, the gate trench portion 40, and the dummy trench portion 30. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0078] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is an insulating film such as silicate glass doped with impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front surface 21, or another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21. The interlayer insulating film 38 is provided with a contact hole 54 described in FIG. 2A.

[0079] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and on the upper surface of the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the front surface 21 through a contact hole 54 in the interlayer insulating film 38. A plug region 17 of tungsten (W) or the like may be provided inside the contact hole 54. The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a material containing metal or a laminated film thereof.

[0080] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0081] The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a remaining region of the semiconductor substrate 10 in which no other doped regions are provided.

[0082] In the transistor section 70, one or more accumulation regions 16 may be provided in the Z-axis direction above the drift region 18. The accumulation region 16 is a region in which the same dopant as the drift region 18 accumulates at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.

[0083] The accumulation region 16 in this example is of N type. The accumulation region 16 may be provided in the transistor section 70 between the base region 14 and a trench bottom section 75 described later. The accumulation region 16 may be provided only in the transistor section 70, or may be provided in both the transistor section 70 and the diode section 80. By providing the accumulation region 16, it is possible to increase the carrier injection promotion effect (IE effect) and reduce the on-voltage.

[0084] In the transistor section 70, an emitter region 12 is provided above the base region 14 in contact with the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0085] The diode section 80 is provided with a base region 14 exposed on the front surface 21. The base region 14 of the diode section 80 operates as an anode.

[0086] A first conductive type buffer region 20 may be provided below the drift region 18. In this example, the buffer region 20 is N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0087] In the transistor section 70, the collector region 22 is provided below the buffer region 20. The collector region 22 may be provided in contact with the cathode region 82 on the back surface 23.

[0088] In the diode section 80, a cathode region 82 is provided below the buffer region 20. The cathode region 82 may be provided at the same depth as the collector region 22 of the transistor section 70. The diode section 80 may function as a freewheeling diode (FWD) that flows a freewheeling current that conducts in the reverse direction when the transistor section 70 is turned off.

[0089] The semiconductor substrate 10 is provided with a gate trench portion 40 and a dummy trench portion 30. The gate trench portion 40 and the dummy trench portion 30 are provided so as to pass through the front surface 21, the base region 14 and the accumulation region 16, and reach the drift region 18. The trench portion passing through the doped region is not limited to being manufactured in the order of forming the doped region and then the trench portion. The trench portion passing through the doped region also includes a case in which the doped region is formed between the trench portions after the trench portions are formed.

[0090] The gate trench portion 40 has a gate trench provided on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed of an oxide film or a nitride film. The gate conductive portion 44 is provided so as to fill the inside of the gate trench more inward than the gate insulating film 42. The upper surface of the gate conductive portion 44 may be in the same XY plane as the front surface 21. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of polysilicon doped with impurities or the like.

[0091] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0092] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 has a dummy trench provided on the front surface 21, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed of an oxide film or a nitride film. The dummy conductive portion 34 is provided so as to fill the inside of the dummy trench more inward than the dummy insulating film 32. The upper surface of the dummy conductive portion 34 may be in the same XY plane as the front surface 21. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0093] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the front surface 21. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may be curved and convex downward (curved in cross section).

[0094] The transistor portion 70 has a P-type trench bottom portion 75 provided at the lower end of the trench portion. In this example, the trench bottom portion 75 is provided below the accumulation region 16. In the depth direction of the semiconductor substrate 10, the lower end of the trench bottom portion 75 may be located below the bottom of the gate trench portion 40. In other words, the trench bottom portion 75 may cover the bottom of the gate trench portion 40.

[0095] The doping concentration of the trench bottom 75 is higher than the doping concentration of the drift region 18 and lower than the doping concentration of the base region 14. The doping concentration of the trench bottom 75 is 1E12 cm -3 Above, 1E13cm -3 The following is the result.

[0096] In FIG. 2B, the end of trench bottom portion 75 on the positive side in the X-axis direction (diode portion 80 side) coincides with the boundary between cathode region 82 and collector region 22, but may extend further toward diode portion 80 or may recede into transistor portion 70.

[0097] The trench bottom portion 75 may be an electrically floating layer. In this specification, the floating layer refers to a layer that is not electrically connected to any electrode such as the emitter electrode 52. By providing the trench bottom portion 75, the turn-on characteristics of the transistor portion 70 are improved. Furthermore, by providing the trench bottom portion 75, electric field concentration at the bottom of the gate trench portion 40 is alleviated, and the avalanche resistance is improved.

[0098] Fig. 2C is a diagram showing the bb' cross section in Fig. 2A. The bb' cross section is a YZ plane passing through the base region 14 and the contact region 15 provided in the diode section 80 in the vicinity of the Y-axis negative side end of the active section 160.

[0099] In this example, the diode section 80 is provided on the outermost side of the active section 160. In the diode section 80, a contact region 15 is provided on the front surface 21 of the semiconductor substrate 10. In addition, in the diode section 80, the base region 14 is exposed on the front surface 21 of the semiconductor substrate 10 outside the contact region 15 in the Y-axis direction. That is, in the diode section 80, the contact region 15 is sandwiched between the base regions 14 in the Y-axis direction in a top view.

[0100] A well region 11 is provided near the Y-axis negative end of the active section 160. The diffusion depth of the well region 11 is deeper than that of the base region 14. The well region 11 may extend in the Y-axis direction so as to partially cover the bottom of the base region 14.

[0101] 2D is a diagram showing the c-c' cross section in FIG. 2A. The c-c' cross section is a YZ plane passing through the emitter region 12, the base region 14, and the contact region 15 provided in the transistor section 70 in the vicinity of the Y-axis negative end of the active section 160. The c-c' cross section also passes through an extension region obtained by extending the transistor section 70 in the Y-axis direction. A cathode region is provided on the lower surface of the extension region. That is, in a top view, the transistor section 70 is sandwiched between the diode sections 80 in the Y-axis direction.

[0102] In the transistor section 70, the emitter region 12 and the contact region 15 are provided on the front surface 21 of the semiconductor substrate 10. In addition, in the transistor section 70, the base region 14 is exposed on the front surface 21 of the semiconductor substrate 10 outside the contact region 15 in the Y-axis direction. That is, in the transistor section 70, the emitter region 12 and the contact region 15 are sandwiched between the base region 14 in the Y-axis direction in a top view.

[0103] In the transistor section 70, the accumulation region 16 and a trench bottom section 75 are provided above the drift region 18. The trench bottom section 75 is provided below the accumulation region 16. The trench bottom section 75 may be provided in contact with the lower surface of the accumulation region 16. Alternatively, as described below, the trench bottom section 75 may be provided spaced apart from the accumulation region 16, that is, such that the drift region 18 is interposed between the accumulation region 16 and the trench bottom section 75.

[0104] Fig. 2E is a diagram showing another example of the a-a' cross section in Fig. 2A. The a-a' cross section is an XZ plane passing through the contact region 15, the base region 14, the gate trench portion 40, and the dummy trench portion 30, as in Fig. 2B. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross section.

[0105] 2B in that a trench bottom portion 75 provided at the lower end of the trench portion of the transistor portion 70 is thinner than the accumulation region 16 in the depth direction of the semiconductor substrate 10. As shown in FIG.

[0106] In this example, the lower end of the trench bottom portion 75 is located below the bottom of the gate trench portion 40 and covers the bottom of the gate trench portion 40 . The trench bottom 75 is electrically floating. Floating Layer It may be.

[0107] 2E, the end of trench bottom portion 75 on the X-axis direction positive side (diode portion 80 side) coincides with the boundary between cathode region 82 and collector region 22, but it may extend further toward diode portion 80 or may recede into transistor portion 70. This example can obtain the same effect as in FIG. 2B.

[0108] Fig. 2F is a diagram showing another example of the a-a' cross section in Fig. 2A. The a-a' cross section is an XZ plane passing through the contact region 15, the base region 14, the gate trench portion 40, and the dummy trench portion 30, as in Fig. 2B. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross section.

[0109] 2B and 2F in that the trench bottom portion 75 is spaced apart from the accumulation region 16, that is, the drift region 18 is interposed between the accumulation region 16 and the trench bottom portion 75. In FIG.

[0110] The trench bottom portion 75 may have a thickness smaller than that of the accumulation region 16 or the drift region 18 between the accumulation region 16 and the trench bottom portion 75 in the depth direction of the semiconductor substrate 10 .

[0111] 2F, the end of trench bottom portion 75 on the X-axis direction positive side (diode portion 80 side) coincides with the boundary between cathode region 82 and collector region 22, but may extend further toward diode portion 80 or may recede into transistor portion 70. This example can obtain the same effect as in FIG. 2B.

[0112] FIG. 3A is a diagram showing an example of the arrangement of the trench bottom region Rp and the electron passing region Rn. FIG. 3B is a diagram showing a d-d' cross section in FIG. 3A. The trench bottom portion 75 of this example is provided intermittently in the transistor portion 70. The transistor portion 70 has an electron passing portion 77 provided between the trench bottom portions 75 at the same Z-axis position as the trench bottom portions 75. In FIG. 3B, the range of the electron passing portion 77 is shown by hatching, but the electron passing portion 77 is an N-type region the same as the drift region 18, and may be a part of the drift region 18.

[0113] In this specification, the regions corresponding to the trench bottom portion 75 and the electron passing portion 77 in a top view are referred to as a trench bottom region Rp and an electron passing region Rn, respectively. The transistor portion 70 of this example has an electron passing region Rn in which the trench bottom portion 75 is not provided in a top view.

[0114] The electron passing region Rn is provided to extend from a trench portion to an adjacent trench portion in the X-axis direction. That is, as shown in FIG. 3A, the electron passing region Rn is provided to extend across the mesa portion in the X-axis direction. Note that, although only the gate trench portion 40 is shown as the trench portion in FIG. 3A, this is not limiting. The electron passing region Rn is provided to extend across the mesa portion between two adjacent ones of the multiple dummy trench portions 30 and the gate trench portions 40 in the X-axis direction.

[0115] The electron passing region Rn may extend beyond multiple trench portions in the X-axis direction. That is, the electron passing region Rn may extend parallel to the emitter region 12 in a top view.

[0116] In this example, the mesa portion of the electron passing region Rn is not provided with the emitter region 12. That is, as shown in Fig. 3B, the emitter region 12 is not provided above the electron passing portion 77, and a trench bottom portion 75 is provided below the emitter region 12. As shown in Fig. 3A, the electron passing region Rn is provided such that its Y-axis direction end is located within the contact region 15 in top view.

[0117] If the trench bottom region Rp is provided over the entire transistor section 70, the transient resistance increases until the potential of the trench bottom section 75 rises when the transistor section 70 is turned on, which may deteriorate the on-resistance.

[0118] In this example, when the transistor section 70 is turned on, electrons from the emitter region 12 first pass through the electron passing section 77 toward the collector region 22. Then, when holes from the collector region 22 are accumulated in the trench bottom section 75, the electrons also pass through the trench bottom section 75, resulting in conduction. In this way, since the transistor section 70 has the electron passing region Rn, an increase in transient resistance when the transistor section 70 is turned on is suppressed, and the on-resistance is improved.

[0119] In the electron passing portion 77, avalanche is likely to occur due to current concentration. However, in this example, the emitter region 12 is not provided in the mesa portion of the electron passing region Rn, thereby reducing the possibility of latch-up occurring in the electron passing portion 77. In this way, in this example, by providing the trench bottom portion 75 below the emitter region 12, it is possible to improve the turn-on characteristics and the on-resistance at the same time.

[0120] Fig. 4A is a diagram showing an example of the arrangement of the trench bottom region Rp and the electron passing region Rn. Fig. 4B is a diagram showing the e-e' cross section in Fig. 4A. As in Figs. 3A and 3B, the trench bottom portions 75 in this example are provided intermittently in the transistor portion 70, and the transistor portion 70 has an electron passing portion 77 provided between the trench bottom portions 75 at the same Z-axis position as the trench bottom portions 75.

[0121] 3A and 3B, the electron passing region Rn in this example is provided to extend from a trench portion to an adjacent trench portion in the X-axis direction. That is, the electron passing region Rn is provided to extend across the mesa portion in the X-axis direction. The electron passing region Rn may also extend beyond a plurality of trench portions in the X-axis direction. That is, the electron passing region Rn may extend perpendicular to the trench portions in a top view.

[0122] 3A and 3B, the electron passing region Rn in this example is provided with at least an emitter region 12. That is, an electron passing portion 77 is provided below any one of the emitter regions 12. This allows electrons from the emitter region 12 to reliably pass through the electron passing portion 77 when the transistor section 70 is turned on. In this way, by the transistor section 70 having the electron passing region Rn, an increase in transient resistance when the transistor section 70 is turned on is suppressed, and the on-resistance is improved.

[0123] Fig. 5A is a diagram showing an example of the arrangement of trench bottom regions Rp and electron passing regions Rn. Fig. 5B is a diagram showing an f-f' cross section in Fig. 5A. As in Figs. 3A to 4B, trench bottom portions 75 in this example are provided intermittently in transistor portion 70, and transistor portion 70 has electron passing portions 77 provided between trench bottom portions 75 at the same Z-axis position as trench bottom portions 75.

[0124] 3A to 4B, in this example, the trench bottom region Rp and the electron passing region Rn are provided alternately in the X-axis direction. That is, as shown in Fig. 5A, the trench bottom region Rp and the electron passing region Rn are provided alternately and extend parallel to the gate trench portion 40 in a top view.

[0125] At least a gate trench portion 40 may be provided in the electron passing region Rn. That is, an electron passing portion 77 is provided below any of the gate trench portions 40. When a channel is formed in the gate trench portion 40 provided in the electron passing region Rn, electrons from the channel can reliably pass through the lower electron passing portion 77. In this way, by the transistor portion 70 having the electron passing region Rn, an increase in transient resistance when the transistor portion 70 is turned on is suppressed, and the on-resistance is improved.

[0126] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0127] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically indicated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0128] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 plug region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, Reference Signs List 41 tip portion, 42 gate insulating film, 44 gate conductive portion, 48 gate runner, 49 contact hole, 50 gate metal layer, 52 emitter electrode, 54 contact hole, 56 contact hole, 60 mesa portion, 61 mesa portion, 70 transistor portion, 75 trench bottom portion, 77 electron passage portion, 80 diode portion, 82 cathode region, 92 guard ring, 100 semiconductor device, 102 edge, 160 active portion, 190 voltage withstanding structure portion

Claims

1. A semiconductor device including a transistor portion, a drift region of a first conductivity type provided in a semiconductor substrate; a plurality of trenches extending from a front surface of the semiconductor substrate to the drift region; an emitter region of a first conductivity type extending from one of the trench portions to an adjacent trench portion on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second conductivity type trench bottom portion provided at a lower end of the trench portion; Equipped with the transistor portion has an electron passing region in which the trench bottom portion is not provided in a top view, a contact region of a second conductivity type provided on a front surface of the semiconductor substrate; an electron passing portion provided between the trench bottom portions at the same depth direction position as the trench bottom portions; Further equipped with In a trench extension direction, a width of the electron passing portion is smaller than a width of the contact region; The electron passing portion is provided below the contact region. Semiconductor device.

2. A semiconductor device including a transistor portion, a drift region of a first conductivity type provided in a semiconductor substrate; a plurality of trenches extending from a front surface of the semiconductor substrate to the drift region; an emitter region of a first conductivity type extending from one of the trench portions to an adjacent trench portion on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second conductivity type trench bottom portion provided at a lower end of the trench portion; Equipped with the transistor portion has an electron passing region in which the trench bottom portion is not provided in a top view, a contact region of a second conductivity type provided on a front surface of the semiconductor substrate; the emitter regions and the contact regions are alternately provided in a trench extension direction, the transistor portion has a trench bottom region in which the trench bottom portion is formed as seen from above, the trench bottom regions and the electron passing regions are alternately provided in a trench extension direction, The electron passing region is provided with at least the emitter region. Semiconductor device.

3. The electron passing region is provided to extend from one of the trench portions to an adjacent trench portion in a trench arrangement direction.

3. The semiconductor device according to claim 1 or 2.

4. The electron passing region extends beyond a plurality of trench portions in a trench arrangement direction. The semiconductor device according to claim 3 .

5. The emitter region is not provided in the mesa portion of the electron passing region.

5. The semiconductor device according to claim 1, 3 or 4.

6. The trench bottom portion is provided below the emitter region. The semiconductor device according to claim 1 , or any one of claims 3 to 5 .

7. A semiconductor device comprising a transistor portion and a diode portion, a drift region of a first conductivity type provided in a semiconductor substrate; a plurality of trenches extending from a front surface of the semiconductor substrate to the drift region; an emitter region of a first conductivity type extending from one of the trench portions to an adjacent trench portion on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a second conductivity type trench bottom portion provided at a lower end of the trench portion; Equipped with the transistor portion has an electron passing region in which the trench bottom portion is not provided in a top view, the transistor portion has a trench bottom region in which the trench bottom portion is formed as seen from above, The trench bottom regions and the electron passing regions are alternately provided in a trench arrangement direction. The trench bottom portion is provided only in the transistor portion. Semiconductor device.

8. The electron passing region is provided with at least a gate trench portion to which a gate voltage is applied. The semiconductor device according to claim 7.

9. The trench bottom is electrically floating. The semiconductor device according to claim 1 .

10. The doping concentration of the bottom of the trench is 1E12 cm －３ Above, 1E13cm －３ Is less than or equal to The semiconductor device according to claim 1 .

11. The semiconductor device further includes an accumulation region of the first conductivity type provided above the drift region. The semiconductor device according to claim 1 .

12. The drift region is interposed between the accumulation region and the trench bottom. The semiconductor device according to claim 11.

13. The trench bottom portion has a thickness smaller than that of the accumulation region in a depth direction of the semiconductor substrate. The semiconductor device according to claim 11.

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