Solid-state imaging device and imaging device

Abstract

The objective of the present invention is to improve image quality in a solid-state image capturing element which performs exposure simultaneously for all pixels.　A pre-stage circuit block generates each of a prescribed reset level and a plurality of signal levels corresponding to an exposure amount, and holds the same in mutually different capacitive elements. A selecting unit sequentially performs: control to connect the capacitive element holding the reset level, among a prescribed number of the capacitive elements, to a prescribed post-stage node; control to disconnect the prescribed number of the capacitive elements from the post-stage node; and control to connect the capacitive element holding any of the plurality of signal levels, among the prescribed number of capacitive elements, to the post-stage node. A post-stage reset transistor initializes the level of the post-stage node when the prescribed number of capacitive elements have been disconnected from the post-stage node. A post-stage circuit sequentially reads each of the reset level and the plurality of signal levels by way of the post-stage node.

Description

[Technical field]

[0001] The present technology relates to a solid-state imaging element, and more particularly to a solid-state imaging element that performs analog-to-digital (AD) conversion for each column, and an imaging device. [Background technology]

[0002] Conventionally, in solid-state imaging devices, in order to miniaturize pixels, a column ADC (Analog to Digital Converter) method has been used in which an ADC is arranged for each column outside a pixel array section and pixel signals are read out row by row. In this column ADC method, if exposure is performed by a rolling shutter method in which exposure is started row by row, rolling shutter distortion may occur. In order to realize a global shutter method in which exposure is started simultaneously for all pixels, a solid-state imaging device has been proposed in which a pair of capacitors is provided for each pixel and the capacitors hold a reset level and a signal level (see, for example, Non-Patent Document 1). The pair of capacitors is connected in series to a source follower circuit via a node, and the reset level and the signal level are read out in sequence by the source follower circuit. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Jae-kyu Lee, et al., A 2.1e-Temporal Noise and -105dB Parasitic Light Sensitivity Backside-Illuminated 2.3 μm-Pixel Voltage-Domain Global Shutter CMOS Image Sensor Using High-Capacity DRAM Capacitor Technology, ISSCC 2020. Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional technology, a global shutter method is realized in a column ADC method by storing a reset level and a signal level in a pair of capacitances for each pixel. However, when a transistor in a source follower circuit initializes a node connected to a capacitance, kTC noise (in other words, reset noise) occurs at a level corresponding to the capacitance, and the noise causes a problem of degradation of the image quality of the image data.

[0005] The present technology was developed in view of these circumstances, and aims to improve image quality in a solid-state imaging device in which all pixels are exposed simultaneously. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect of the present technology is a solid-state imaging device including a predetermined number of capacitive elements, a front-stage circuit block that generates a predetermined reset level and a plurality of signal levels corresponding to an exposure amount and holds them in the different capacitive elements, a selection unit that sequentially controls connecting the capacitive elements that hold the reset level among the predetermined number of capacitive elements to a predetermined rear-stage node, disconnecting the predetermined number of capacitive elements from the rear-stage node, and connecting the capacitive elements that hold any of the plurality of signal levels among the predetermined number of capacitive elements to the rear-stage node, a rear-stage reset transistor that initializes the level of the rear-stage node when the predetermined number of capacitive elements are disconnected from the rear-stage node, and a rear-stage circuit that sequentially reads out the reset level and the plurality of signal levels via the rear-stage node, thereby reducing kTC noise.

[0007] In addition, in this first aspect, the predetermined number of capacitive elements may include first and second capacitive elements and third and fourth capacitive elements, the pre-stage circuit block may include a first pre-stage circuit that generates a first reset level and a first signal level in sequence and causes the first and second capacitive elements to hold them, and a second pre-stage circuit that generates a second reset level and a second signal level in sequence and causes the third and fourth capacitive elements to hold them, and the selection section may include a first selection circuit that connects either the first or second capacitive elements to the post-stage node, and a second selection circuit that connects either the third or fourth capacitive elements to the post-stage node, thereby providing an effect that the reset levels and signal levels of each of the two pixels are held.

[0008] In addition, in the first aspect, the first front-stage circuit may include a first photoelectric conversion element, a first front-stage transfer transistor for transferring charges from the first photoelectric conversion element to a first floating diffusion layer, a first reset transistor for initializing the first floating diffusion layer, and a first front-stage amplification transistor for amplifying a voltage of the first floating diffusion layer, and the second front-stage circuit may include a second photoelectric conversion element, a second front-stage transfer transistor for transferring charges from the second photoelectric conversion element to the second floating diffusion layer, a second reset transistor for initializing the second floating diffusion layer, and a second front-stage amplification transistor for amplifying a voltage of the second floating diffusion layer, thereby providing an effect of maintaining a level according to the voltage of the floating diffusion layer.

[0009] In addition, in the first aspect, the first front-stage circuit may further include a first current source transistor connected to a first front-stage node, the second front-stage circuit may further include a second current source transistor connected to a second front-stage node, the first front-stage amplification transistor may amplify a voltage of the first floating diffusion layer and output it to the first front-stage node, the second front-stage amplification transistor may amplify a voltage of the second floating diffusion layer and output it to the second front-stage node, one end of each of the first and second capacitance elements may be commonly connected to the first front-stage node and the other end of each of the first and second capacitance elements may be commonly connected to the second front-stage node and the other end of each of the third and fourth ... connected to the second front-stage node and the other end of each of the third and fourth capacitance elements may be commonly connected to the second front-stage node and the other end of each of the third and fourth capacitance elements may be connected to the second front-stage node and the other end of each of the third and fourth capacitance elements may be connected to the second front-stage node and the other end of each of the third and fourth capacitance elements may be connected to the second front-stage node and the other end of each of the third and fourth capacitance elements may be connected to the second front-stage node and the other end of each of the third and fourth capacitance elements may be connected to the second front-stage node and the other end of each of the third and fourth capacitance elements may be connected to the second front-stage node and the other end of each of the third and fourth capacitance elements may be connected to the second front-stage

[0010] In the first aspect, the first and second pre-stage transfer transistors may transfer the charges to the first and second floating diffusion layers at a predetermined exposure start timing, and the first and second reset transistors may initialize the first and second photoelectric conversion elements together with the first and second floating diffusion layers, and the first and second pre-stage transfer transistors may transfer the charges to the first and second floating diffusion layers at a predetermined exposure end timing, thereby providing an effect that all pixels are exposed simultaneously.

[0011] In addition, in this first aspect, the selection unit may sequentially perform control to connect one of the first and second capacitive elements to the subsequent node, control to connect the other of the first and second capacitive elements to the subsequent node, control to connect one of the third and fourth capacitive elements to the subsequent node, and control to connect the other of the third and fourth capacitive elements to the subsequent node, thereby providing an effect that the reset levels and signal levels of each of two pixels are read out in sequence.

[0012] In addition, in the first aspect, the selection unit may sequentially perform control to connect one of the first and second capacitive elements and one of the third and fourth capacitive elements to the subsequent node in a predetermined addition mode, and control to connect the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the subsequent node, thereby providing an effect of reading out a pixel-added signal.

[0013] Also, in this first aspect, the first front-stage circuit may further include a first front-stage selection transistor that outputs a voltage amplified by the first front-stage amplification transistor to a predetermined front-stage node in accordance with a predetermined first selection signal, the second front-stage circuit may further include a second front-stage selection transistor that outputs a voltage amplified by the second front-stage amplification transistor to the front-stage node in accordance with a predetermined second selection signal, and a current source transistor connected to the front-stage node, one end of each of the first and second capacitance elements may be commonly connected to the front-stage node and the other end of each of the first and second capacitance elements may be commonly connected to the front-stage node and the other end of each of the third and fourth capacitance elements may be commonly connected to the front-stage node and the other end of each of the third and fourth capacitance elements may be commonly connected to the front-stage node and the other end of each of the third and fourth capacitance elements may be commonly connected to the front-stage node and the second selection circuit, thereby providing an effect that the current source transistor is shared by two pixels.

[0014] In addition, in the first aspect, the first and second front-stage selection transistors may sequentially transition to a closed state immediately before a predetermined exposure end timing and after the exposure end timing, the first reset transistor initializes the first floating diffusion layer when the first front-stage selection transistor is in the closed state, the second reset transistor initializes the second floating diffusion layer when the second front-stage selection transistor is in the closed state, the first and second front-stage selection transistors sequentially transition to a closed state immediately after the exposure end timing, and the first and second front-stage transfer transistors transfer the charge at a predetermined exposure end timing. This provides an effect that all pixels are exposed simultaneously in a configuration in which a current source transistor is shared by two pixels.

[0015] In addition, in the first aspect, the input / output terminal may further include a short-circuit transistor that opens and closes a path between a first subsequent node and a second subsequent node, the predetermined number of capacitances may include first, second, third, fourth, fifth, sixth, seventh and eighth capacitance elements, and the selection unit may include a first selection circuit that connects one of the first and second capacitance elements to the first subsequent node, a second selection circuit that connects one of the third and fourth capacitance elements to the first subsequent node, a third selection circuit that connects one of the fifth and sixth capacitance elements to the second subsequent node, and a fourth selection circuit that connects one of the seventh and eighth capacitance elements to the second subsequent node. This provides the effect of short-circuiting the first subsequent node and the second subsequent node.

[0016] In addition, in this first aspect, in a predetermined non-addition mode, the short-circuiting transistor is in an open state, and in the non-addition mode, the selection unit may perform a control to sequentially connect each of the first and second capacitive elements to the first subsequent node, a control to sequentially connect each of the third and fourth capacitive elements to the first subsequent node, a control to sequentially connect each of the fifth and sixth capacitive elements to the second subsequent node, and a control to sequentially connect each of the seventh and eighth capacitive elements to the second subsequent node in a predetermined order, thereby achieving an effect that the reset levels and signal levels of each of the four pixels are read out in sequence in the non-addition mode.

[0017] In addition, in this first aspect, in a predetermined addition mode, the short-circuiting transistor is in a closed state, and in the addition mode, the selection unit may sequentially perform control to connect one of the first and second capacitive elements and one of the third and fourth capacitive elements to the first subsequent node while connecting one of the fifth and sixth capacitive elements and one of the seventh and eighth capacitive elements to the second subsequent node, and control to connect the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the first subsequent node while connecting the other of the fifth and sixth capacitive elements and the other of the seventh and eighth capacitive elements to the second subsequent node. This provides an effect that four pixels are added in the pixel addition mode.

[0018] Also, in this first aspect, the predetermined number of capacitive elements include first and second capacitive elements and a third capacitance, and the pre-stage circuit block includes a first photoelectric conversion element, a first pre-stage transfer transistor for transferring charges from the first photoelectric conversion element to a predetermined floating diffusion layer, a second photoelectric conversion element, a second pre-stage transfer transistor for transferring charges from the second photoelectric conversion element to the predetermined floating diffusion layer, a reset transistor for initializing the floating diffusion layer, and a pre-stage amplifying transistor for amplifying a voltage of the floating diffusion layer and outputting it to a predetermined pre-stage node. wherein one end of each of the first and second capacitance elements and the third capacitance element may be commonly connected to the previous node, and the other end of each of the first and second capacitance elements may be connected to the selection unit, thereby providing an effect of holding a reset level and a plurality of signal levels.

[0019] In the first aspect, the first and second pre-stage transfer transistors may transfer the charges to the floating diffusion layer at a predetermined exposure start timing, and the reset transistor may initialize the first and second photoelectric conversion elements together with the floating diffusion layer, and the first and second pre-stage transfer transistors may transfer the charges to the first and second floating diffusion layers in sequence at a predetermined exposure end timing, thereby providing an effect that all pixels are exposed.

[0020] In addition, in the first aspect, the selection unit may sequentially perform control to connect one of the first and second capacitive elements to the subsequent node, control to connect the other of the first and second capacitive elements to the subsequent node, and control to connect the third capacitive element to the subsequent node, thereby providing an effect that a reset level and a plurality of signal levels are read out in sequence.

[0021] In addition, in this first aspect, the preceding circuit block is provided in a first chip, The predetermined number of capacitive elements, the selection section, the post-stage reset transistor, and the post-stage circuit may be provided on a second chip, thereby providing an effect of facilitating miniaturization of pixels.

[0022] In addition, in the first aspect, the display device may further include an analog-to-digital converter that converts the output reset level and the plurality of signal levels into digital signals in sequence, the analog-to-digital converter being provided in the second chip, thereby providing an effect of facilitating miniaturization of pixels.

[0023] In addition, in the first aspect, the display device may further include an analog-to-digital converter that converts the output reset level and the plurality of signal levels into digital signals in sequence, the analog-to-digital converter being provided in a third chip, thereby providing an effect of facilitating miniaturization of pixels.

[0024] In addition, a second aspect of the present technology is an imaging device including a predetermined number of capacitive elements, a front-stage circuit block that generates a predetermined reset level and a plurality of signal levels corresponding to an exposure amount and holds them in the different capacitive elements, a selection unit that sequentially controls the following: connecting the capacitive element that holds the reset level among the predetermined number of capacitive elements to a predetermined rear-stage node, disconnecting the predetermined number of capacitive elements from the rear-stage node, and connecting the capacitive element that holds any of the plurality of signal levels among the predetermined number of capacitive elements to the rear-stage node, a rear-stage reset transistor that initializes the level of the rear-stage node when the predetermined number of capacitive elements are disconnected from the rear-stage node, a rear-stage circuit that sequentially reads out the reset level and the plurality of signal levels via the rear-stage node, and a signal processing circuit that sequentially converts the reset level and the plurality of signal levels into digital signals and processes them. This brings about an effect of generating image data with reduced kTC noise.

[0025] A third aspect of the present technology is a solid-state imaging device including a first photoelectric conversion element that converts incident light into an electric charge, a second photoelectric conversion element that converts incident light into an electric charge, a front-stage amplification transistor that converts the electric charge into a voltage, a predetermined number of capacitance elements each having one end connected to a front-stage node to which the front-stage amplification transistor is output, a predetermined number of selection transistors inserted in respective paths between the other ends of the predetermined number of capacitance elements and a predetermined rear-stage node, a reset transistor having a source or drain connected to the rear-stage node, and a rear-stage amplification transistor having a gate connected to the rear-stage node and outputting a pixel signal. This provides an effect of reducing kTC noise. [Brief description of the drawings]

[0026] [Figure 1] 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology. [Diagram 2] 1 is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology. [Diagram 3] 1 is a circuit diagram showing a configuration example of a pixel block according to a first embodiment of the present technology. [Figure 4] 2 is a circuit diagram showing a configuration example of a pre-stage circuit and a selection circuit according to the first embodiment of the present technology. FIG. [Diagram 5] 1 is a block diagram showing a configuration example of a column signal processing circuit according to a first embodiment of the present technology. [Figure 6] 4 is a timing chart showing an example of a global shutter operation in the first embodiment of the present technology. [Figure 7] 4 is a timing chart showing an example of a readout operation of a first pixel in a pixel block according to the first embodiment of the present technology. [Figure 8] 11 is a timing chart showing an example of a readout operation of a second pixel in a pixel block according to the first embodiment of the present technology. [Figure 9] FIG. 11 is a circuit diagram showing a configuration example of a pixel in a comparative example. [Figure 10] 4A to 4C are diagrams illustrating an example of a state of a pixel block when a reset level is read out and when a subsequent node is initialized in the first embodiment of the present technology. [Figure 11] 4A to 4C are diagrams illustrating an example of a state of a pixel block when a signal level is read out in the first embodiment of the present technology. [Figure 12] 5 is a flowchart showing an example of an operation of the solid-state imaging element according to the first embodiment of the present technology. [Figure 13] 13 is a timing chart showing an example of a read operation of a reset level and a signal level in a first modified example of the first embodiment of the present technology. [Figure 14] 11 is a diagram showing an example of a layered structure of a solid-state imaging element according to a second modified example of the first embodiment of the present technology. FIG. [Figure 15] 11 is a circuit diagram showing a configuration example of a pixel block in a second modified example of the first embodiment of the present technology. FIG. [Figure 16]13 is a diagram showing an example of a layered structure of a solid-state imaging element according to a third modified example of the first embodiment of the present technology. FIG. [Figure 17] 13 is a plan view showing a configuration example of a pixel array section according to a second embodiment of the present technology. FIG. [Figure 18] 13 is a circuit diagram showing a configuration example of a pixel block according to a second embodiment of the present technology. FIG. [Figure 19] 13 is a circuit diagram showing a configuration example of a pre-stage circuit and a selection circuit according to a second embodiment of the present technology. FIG. [Figure 20] 13 is a timing chart showing an example of a readout operation of first and second pixels in a pixel block according to a second embodiment of the present technology. [Figure 21] 13 is a timing chart showing an example of a readout operation of third and fourth pixels in a pixel block according to the second embodiment of the present technology. [Figure 22] 13 is a timing chart showing an example of a read operation in an addition mode according to a second embodiment of the present technology. [Figure 23] FIG. 13 is a circuit diagram showing a configuration example of a pixel block according to a third embodiment of the present technology. [Figure 24] 13 is a timing chart showing an example of a global shutter operation in the third embodiment of the present technology. [Diagram 25] 13 is a timing chart showing an example of control immediately after the end of exposure in the third embodiment of the present technology. [Figure 26] FIG. 13 is a circuit diagram showing a configuration example of a pixel block according to a fourth embodiment of the present technology. [Figure 27] 13 is a timing chart showing an example of a global shutter operation in the fourth embodiment of the present technology. [Figure 28] 13 is a timing chart showing an example of a read operation of a reset level and a signal level in the fourth embodiment of the present technology. [Figure 29] 1 is a block diagram showing a schematic configuration example of a vehicle control system; [Diagram 30]FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example of holding reset level and signal level in multiple capacitors) 2. Second embodiment (example in which a reset level and a signal level are held in a plurality of capacitors and subsequent nodes are short-circuited) 3. Third embodiment (example in which a reset level and a signal level are held in multiple capacitors and a current source is shared) 4. Fourth embodiment (example in which one capacitor holds a reset level and multiple capacitors hold signal levels) 5. Application examples for mobile objects

[0028] <1. First embodiment> [Example of imaging device configuration] 1 is a block diagram showing an example of a configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device that captures image data, and includes an imaging lens 110, a solid-state imaging element 200, a recording unit 120, and an imaging control unit 130. The imaging device 100 may be a digital camera or an electronic device with an imaging function (such as a smartphone or a personal computer).

[0029] The solid-state imaging element 200 captures image data under the control of the imaging control unit 130. The solid-state imaging element 200 supplies the image data to the recording unit 120 via a signal line 209.

[0030] The imaging lens 110 collects light and guides it to the solid-state imaging element 200. The imaging control unit 130 controls the solid-state imaging element 200 to capture image data. The imaging control unit 130 supplies an imaging control signal including, for example, a vertical synchronization signal VSYNC to the solid-state imaging element 200 via a signal line 139. The recording unit 120 records the image data.

[0031] Here, the vertical synchronization signal VSYNC is a signal that indicates the timing of imaging, and a periodic signal with a constant frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0032] It should be noted that although the imaging device 100 records image data, the image data may be transmitted to the outside of the imaging device 100. In this case, an external interface for transmitting the image data is further provided. Alternatively, the imaging device 100 may further display the image data. In this case, a display unit is further provided.

[0033] [Example of the configuration of a solid-state imaging element] 2 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array section 220, a timing control circuit 212, a DAC (Digital to Analog Converter) 213, a load MOS circuit block 250, and a column signal processing circuit 260. A plurality of pixel blocks 300 are arranged in a two-dimensional lattice in the pixel array section 220. A plurality of pixels (for example, two pixels) are arranged in each of the pixel blocks 300. Moreover, each circuit in the solid-state imaging element 200 is provided on, for example, a single semiconductor chip.

[0034] Hereinafter, a pixel block 300 or a set of pixels arranged in the horizontal direction will be referred to as a "row", and a pixel block 300 or a set of pixels arranged in a direction perpendicular to the rows will be referred to as a "column".

[0035] The timing control circuit 212 controls the operation timing of the vertical scanning circuit 211, the DAC 213, and the column signal processing circuit 260 in synchronization with a vertical synchronization signal VSYNC from the imaging control unit .

[0036] The DAC 213 generates a sawtooth ramp signal by DA (Digital to Analog) conversion. The DAC 213 supplies the generated ramp signal to the column signal processing circuit 260.

[0037] The vertical scanning circuit 211 sequentially selects and drives the rows to output analog pixel signals. The pixels photoelectrically convert incident light to generate analog pixel signals. The pixels supply the pixel signals to the column signal processing circuit 260 via the load MOS circuit block 250.

[0038] In the load MOS circuit block 250, MOS transistors that supply a constant current are provided for each column.

[0039] The column signal processing circuit 260 performs signal processing such as AD conversion processing and CDS (Correlated Double Sampling) processing on pixel signals for each column. The column signal processing circuit 260 supplies image data consisting of the processed signals to the recording unit 120. The column signal processing circuit 260 is an example of a signal processing circuit described in the claims.

[0040] [Pixel block configuration example] 3 is a circuit diagram showing a configuration example of a pixel block 300 according to the first embodiment of the present technology. The pixel block 300 includes a front-stage circuit block 305, capacitance elements 331, 332, 336, and 337, a selection section 340, a rear-stage reset transistor 361, and a rear-stage circuit 370. As the capacitance elements 331, 332, 336, and 337, for example, capacitances having a metal-insulator-metal (MIM) structure are used.

[0041] The capacitive elements 331 and 332 are examples of the first and second capacitive elements set forth in the claims, and the capacitive elements 336 and 337 are examples of the third and fourth capacitive elements set forth in the claims.

[0042] Furthermore, the previous stage circuit block 305 includes previous stage circuits 310 and 320. The selection section 340 includes selection circuits 350 and 355. The subsequent stage circuit 370 includes a subsequent stage amplification transistor 371 and a subsequent stage selection transistor 372.

[0043] The previous stage circuit 310 generates a reset level and a signal level in sequence and holds them in the capacitive elements 331 and 332. The previous stage circuit 320 generates a reset level and a signal level in sequence and holds them in the capacitive elements 336 and 337. Note that the previous stage circuit 310 is an example of a first previous stage circuit as set forth in the claims, and the previous stage circuit 320 is an example of a second previous stage circuit as set forth in the claims.

[0044] The selection circuit 350 connects either the capacitance elements 331 or 332 to a subsequent node 360. The selection circuit 355 connects either the capacitance elements 336 or 337 to a subsequent node 360. The selection circuit 350 is an example of a first selection circuit recited in the claims, and the selection circuit 355 is an example of a second selection circuit recited in the claims.

[0045] FIG. 4 is a circuit diagram showing an example configuration of the pre-stage circuits 310 and 320 and the selection circuits 350 and 355 according to the first embodiment of the present technology.

[0046] The pre-stage circuit 310 includes a photoelectric conversion element 311 , a transfer transistor 312 , an FD (Floating Diffusion) reset transistor 313 , an FD 314 , a pre-stage amplification transistor 315 , and a current source transistor 316 .

[0047] The pre-stage circuit 320 includes a photoelectric conversion element 321 , a transfer transistor 322 , an FD reset transistor 323 , an FD 324 , a pre-stage amplification transistor 325 , and a current source transistor 326 .

[0048] The photoelectric conversion elements 311 and 321 generate electric charges by photoelectric conversion. The transfer transistor 312 transfers electric charges from the photoelectric conversion element 311 to the FD 314 in accordance with a transfer signal trg1 from the vertical scanning circuit 211. The transfer transistor 322 transfers electric charges from the photoelectric conversion element 321 to the FD 324 in accordance with a transfer signal trg2 from the vertical scanning circuit 211.

[0049] The photoelectric conversion elements 311 and 321 are examples of the first and second photoelectric conversion elements set forth in the claims. The transfer transistors 312 and 322 are examples of the first and second transfer transistors set forth in the claims.

[0050] The FD reset transistor 313 extracts charge from the FD 314 to initialize it in accordance with an FD reset signal rst1 from the vertical scanning circuit 211. The FD reset transistor 323 extracts charge from the FD 324 to initialize it in accordance with an FD reset signal rst2 from the vertical scanning circuit 211. The FDs 314 and 324 accumulate charge and generate a voltage according to the amount of charge.

[0051] The FD reset transistors 313 and 323 are examples of the first and second reset transistors set forth in the claims. The FDs 314 and 324 are examples of the first and second floating diffusion layers set forth in the claims.

[0052] The pre-stage amplification transistor 315 amplifies the voltage level of the FD 314 and outputs it to a pre-stage node 330. The pre-stage amplification transistor 325 amplifies the voltage level of the FD 324 and outputs it to a pre-stage node 335. The pre-stage amplification transistors 315 and 325 are examples of the first and second pre-stage amplification transistors set forth in the claims.

[0053] The drains of the FD reset transistors 313 and 323 and the pre-amplification transistors 315 and 325 are connected to a power supply voltage VDD. The current source transistor 316 is connected to the source of the pre-amplification transistor 315. The current source transistor 316 supplies a current id11 under the control of the vertical scanning circuit 211. The current source transistor 326 is connected to the source of the pre-amplification transistor 325. The current source transistor 326 supplies a current id12 under the control of the vertical scanning circuit 211.

[0054] The current source transistors 316 and 326 are an example of the first and second current source transistors set forth in the claims.

[0055] One end of each of the capacitance elements 331 and 332 is commonly connected to the previous-stage node 330, and the other end is connected to the selection circuit 350. One end of each of the capacitance elements 336 and 337 is commonly connected to the previous-stage node 335, and the other end is connected to the selection circuit 355.

[0056] The selection circuit 350 includes selection transistors 351 and 352. The selection transistor 351 opens and closes a path between the capacitive element 331 and a subsequent node 360 ​​in accordance with a selection signal Φr1 from the vertical scanning circuit 211. The selection transistor 352 opens and closes a path between the capacitive element 332 and a subsequent node 360 ​​in accordance with a selection signal Φs1 from the vertical scanning circuit 211.

[0057] The selection circuit 355 includes selection transistors 356 and 357. The selection transistor 356 opens and closes a path between the capacitance element 336 and a subsequent node 360 ​​in accordance with a selection signal Φr2 from the vertical scanning circuit 211. The selection transistor 357 opens and closes a path between the capacitance element 337 and a subsequent node 360 ​​in accordance with a selection signal Φs2 from the vertical scanning circuit 211.

[0058] The latter-stage reset transistor 361 initializes the level of the latter-stage node 360 ​​to a predetermined potential Vreg in accordance with a latter-stage reset signal rstb from the vertical scanning circuit 211. A potential different from the power supply potential VDD (for example, a potential lower than VDD) is set to the potential Vreg.

[0059] In the rear circuit 370, the rear-stage amplifying transistor 371 amplifies the level of the rear-stage node 360. The rear-stage selecting transistor 372 outputs the signal having the level amplified by the rear-stage amplifying transistor 371 to the vertical signal line 309 as a pixel signal in accordance with a rear-stage selecting signal selb from the vertical scanning circuit 211.

[0060] It should be noted that various transistors (such as the transfer transistor 312) in the pixel block 300 are, for example, nMOS (n-channel Metal Oxide Semiconductor) transistors.

[0061] A circuit consisting of the above-mentioned front-stage circuit 310, the capacitance elements 331 and 332, the selection circuit 350, the rear-stage reset transistor 361, and the rear-stage circuit 370 functions as one pixel. Also, a circuit consisting of the front-stage circuit 320, the capacitance elements 336 and 337, the selection circuit 355, the rear-stage reset transistor 361, and the rear-stage circuit 370 functions as one pixel. These two pixels share the rear-stage reset transistor 361 and the rear-stage circuit 370.

[0062] Moreover, the two pixels in the pixel block 300 are arranged, for example, in the column direction. In other words, these two pixels are arranged in an odd-numbered row and an even-numbered row. The positional relationship of the two pixels in the pixel block 300 is not limited to an odd-numbered row and an even-numbered row. For example, the two pixels may be arranged in an odd-numbered column and an even-numbered column. Alternatively, one of the two pixels may be arranged diagonally above the other.

[0063] The vertical scanning circuit 211 supplies a high-level FD reset signal (rst1 or rst2) and a high-level transfer signal (trg1 or trg2) to all rows at the start of exposure. This initializes the photoelectric conversion elements (311 or 321). Hereinafter, this control is referred to as "PD reset."

[0064] Then, just before the end of exposure, the vertical scanning circuit 211 supplies FD reset signals rst1 and rst2 at a high level over a pulse period while setting the subsequent reset signal rstb and the selection signals Φr1 and Φr2 to a high level for all rows. This initializes the FDs 314 and 324, and the levels corresponding to the levels of the FDs 314 and 324 at that time are held in the capacitive elements 331 and 336. This control is hereinafter referred to as "FD reset."

[0065] The levels of the FDs 314 and 324 when the FDs are reset and the levels corresponding to those levels (the levels held by the capacitive elements 331 and 336 and the level of the vertical signal line 309) are hereinafter collectively referred to as the "P phase" or "reset level."

[0066] At the end of exposure, the vertical scanning circuit 211 sets the subsequent reset signal rstb and the selection signals Φs1 and Φs2 to high levels for all rows, and supplies the transfer signals trg1 and trg2 at a high level for the pulse period. This causes a signal charge according to the amount of exposure to be transferred to the FDs 314 and 324, and a level according to the level of the FDs 314 and 324 at that time is held in the capacitance elements 332 and 337.

[0067] The levels of the FDs 314 and 324 when the signal charges are transferred and the levels corresponding to those levels (the levels held by the capacitive elements 332 and 337 and the level of the vertical signal line 309) are hereinafter collectively referred to as the "D phase" or "signal level."

[0068] This exposure control, in which exposure starts and ends simultaneously for all pixels, is called a global shutter method. With this exposure control, the front-stage circuit 310 of all pixels sequentially generates a reset level and a signal level. The reset level is held in the capacitance elements 331 and 336, and the signal level is held in the capacitance elements 332 and 337.

[0069] After the exposure is completed, the vertical scanning circuit 211 sequentially selects rows and sequentially outputs the reset level and signal level of the row. When outputting the reset level, the vertical scanning circuit 211 supplies a high-level selection signal Φr1 or Φr2 for a predetermined period while setting the FD reset signal rst1 or rst2 and the subsequent selection signal selb of the selected row to a high level. This connects the capacitance element 331 or 336 to the subsequent node 360, and the reset level is read out.

[0070] After reading out the reset level, the vertical scanning circuit 211 supplies a high-level subsequent-stage reset signal rstb for a pulse period while keeping the FD reset signal rst1 or rst2 and subsequent-stage selection signal selb of the selected row at high levels. This initializes the level of the subsequent-stage node 360. At this time, the selection transistors 351, 352, 356, and 357 are in an open state, and the capacitive elements 331, 332, 336, and 337 are disconnected from the subsequent-stage node 360.

[0071] After initializing the subsequent node 360, the vertical scanning circuit 211 supplies a high-level selection signal Φs1 or Φs2 for a predetermined period while keeping the FD reset signal (rst1 or rst2) and subsequent selection signal selb of the selected row at high level. This connects the capacitance element 332 or 337 to the subsequent node 360, and the signal level is read out.

[0072] By the above-mentioned read control, the selection circuit 350 of the selected row sequentially performs control to connect the capacitive element 331 to the subsequent node 360, control to disconnect the capacitive elements 331 and 332 from the subsequent node 360, and control to connect the capacitive element 332 to the subsequent node 360.

[0073] Furthermore, the selection circuit 355 of the selected row sequentially performs control to connect the capacitive element 336 to the subsequent node 360, control to disconnect the capacitive elements 336 and 337 from the subsequent node 360, and control to connect the capacitive element 337 to the subsequent node 360.

[0074] Furthermore, when the capacitive elements 331, 332, 336, and 337 are disconnected from the subsequent node 360, the subsequent reset transistor 361 of the selected row initializes the level of the subsequent node 360. Furthermore, the subsequent circuit 370 of the selected row sequentially reads out the reset level and the signal level from the capacitive elements 331 and 332 (or the capacitive elements 336 and 337) via the subsequent node 360, and outputs them to the vertical signal line 309.

[0075] [Example of column signal processing circuit configuration] FIG. 5 is a block diagram showing an example of a configuration of the column signal processing circuit 260 according to the first embodiment of the present technology.

[0076] A vertical signal line 309 is wired to the load MOS circuit block 250 for each column of the pixel block 300. If the number of columns is I (I is an integer), then I vertical signal lines 309 are wired. In addition, a load MOS transistor 251 that supplies a constant current id2 is connected to each vertical signal line 309.

[0077] The column signal processing circuit 260 includes a plurality of ADCs 261 and a digital signal processor 262. The ADCs 261 are arranged for each column. If the number of columns is I, then I ADCs 261 are arranged.

[0078] The ADC 261 converts analog pixel signals from the corresponding columns into digital signals using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signals to a digital signal processor 262. For example, a single-slope ADC including a comparator and a counter is disposed as the ADC 261.

[0079] The digital signal processing unit 262 performs predetermined signal processing such as CDS processing on each of the digital signals for each column. The digital signal processing unit 262 supplies the recording unit 120 with image data made up of the processed digital signals.

[0080] [Example of operation of solid-state imaging device] 6 is a timing chart showing an example of a global shutter operation in the first embodiment of the present technology. The vertical scanning circuit 211 supplies high-level FD reset signals rst1 and rst2 and transfer signals trg1 and trg2 to all rows (in other words, all pixels) from timing T0 immediately before the start of exposure to timing T1 after the pulse period has elapsed. This causes the PD reset of all pixels, and exposure is started simultaneously in all rows.

[0081] Here, rst1_[n], rst2_[n], trg1_[n], and trg2_[n] in the figure indicate signals to the pixel in the nth row out of N rows. N is an integer indicating the total number of rows in which pixel blocks 300 are arranged, and n is an integer from 1 to N. When two pixels in pixel block 300 are pixels in an even row and an odd row, the nth row of pixel block 300 includes two rows, an odd row and an even row.

[0082] At timing T2 immediately before the end of the exposure period, the vertical scanning circuit 211 supplies high-level FD reset signals rst1 and rst2 over the pulse period while setting the subsequent reset signal rstb and the selection signals Φr1 and Φr2 to high levels in all rows. This causes the FD reset of all pixels, and the reset levels are sampled and held. Here, rstb_[n], Φr1_[n], and Φr2_[n] in the figure indicate signals to the pixels in the nth row.

[0083] At timing T3 after timing T2, the vertical scanning circuit 211 returns the selection signals Φr1 and Φr2 to the low level.

[0084] At timing T4 when exposure ends, the vertical scanning circuit 211 supplies high-level transfer signals trg1 and trg2 over the pulse period while setting the subsequent reset signal rstb and the selection signals Φs1 and Φs2 to high levels in all rows. This causes the signal levels to be sampled and held. In addition, Φs1_[n] and Φs2_[n] in the figure indicate signals to the pixels in the nth row.

[0085] At timing T5 after timing T4, the vertical scanning circuit 211 returns the selection signals Φs1 and Φs2 to the low level.

[0086] 7 is a timing chart showing an example of a readout operation of the first pixel in the pixel block 300 in the first embodiment of the present technology. In the readout period of the n-th row after timing T10, the vertical scanning circuit 211 sets the FD reset signals rst1 and rst2 and the subsequent selection signal selb of the n-th row to high level. Also, at timing T10, the subsequent reset signals rstb of all rows are controlled to low level. Here, selb_[n] in the figure indicates a signal to the pixel of the n-th row.

[0087] From timing T11 immediately after timing T10 to timing T12, the vertical scanning circuit 211 supplies a high-level selection signal Φr1 to the n-th row. The potential of the subsequent node 360 ​​becomes a reset level Vrst1. The ADC 261 converts this reset level into an AD signal.

[0088] From timing T13 immediately after timing T12 and over a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb to the n-th row. This makes it possible to erase the history of the previous signal held in the parasitic capacitance when the subsequent node 360 ​​has a parasitic capacitance.

[0089] From timing T14 to timing T15 immediately after the initialization of the subsequent node 360, the vertical scanning circuit 211 supplies a high-level selection signal Φs1 to the nth row. The potential of the subsequent node 360 ​​becomes a signal level Vsig1. This signal level is AD converted by the ADC 261. The difference between the reset level Vrst1 and the signal level Vsig1 corresponds to the net signal level from which the reset noise and offset noise of the FD have been removed.

[0090] FIG. 8 is a timing chart showing an example of a readout operation of the first pixel in the pixel block 300 according to the first embodiment of the present technology.

[0091] From timing T16 immediately after timing T15 and throughout the pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb to the n-th row.

[0092] The vertical scanning circuit 211 supplies a high-level selection signal Φr2 to the n-th row over a period from timing T17 to timing T18 immediately after the initialization of the subsequent node 360. The potential of the subsequent node 360 ​​becomes a reset level Vrst2. The ADC 261 converts this reset level into an AD signal.

[0093] From timing T19 immediately after timing T18 and over a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb to the n-th row.

[0094] The vertical scanning circuit 211 supplies a high-level selection signal Φs2 to the n-th row over a period from timing T20 to timing T21 immediately after the initialization of the subsequent node 360. The potential of the subsequent node 360 ​​becomes a signal level Vsig2. The ADC 261 performs AD conversion on this signal level.

[0095] Furthermore, at timing T21, the vertical scanning circuit 211 returns the FD reset signals rst1 and rst2 and the subsequent stage selection signal selb of the nth row to low level.

[0096] 7 and 8, high-level selection signals Φr1, Φs1, Φr2, and Φs2 are supplied in sequence. In response to these selection signals, the selection unit 340 sequentially connects the capacitance elements 331, 332, 336, and 337 to the subsequent node 360. Then, the reset level Vrst1 and signal level Vsig1 of the first pixel in the pixel block 300 and the reset level Vrst2 and signal level Vsig2 of the second pixel are read out in sequence.

[0097] Although the solid-state imaging device 200 reads out the signal level after the reset level, this order is not limited. The solid-state imaging device 200 can also read out the reset level after the signal level. In this case, the vertical scanning circuit 211 supplies a high-level selection signal Φr after a high-level selection signal Φs. In this case, it is also necessary to reverse the slope of the ramp signal.

[0098] 9 is a circuit diagram showing a configuration example of a pixel in a comparative example. In this comparative example, the selection circuit 350 is not provided, and a transfer transistor is inserted between the previous-stage node 330 and the previous-stage circuit. Furthermore, capacitances C1 and C2 are inserted instead of the capacitance elements 331 and 332. The capacitance C1 is inserted between the previous-stage node 330 and a ground terminal, and the capacitance C2 is inserted between the previous-stage node 330 and a subsequent-stage node 360.

[0099] The exposure control and readout control of the pixel in this comparative example are described, for example, in Figure 5.5.2 of Non-Patent Document 1. In this comparative example, assuming that the capacitance values ​​of the capacitors C1 and C2 are C, the level Vn of kTC noise during exposure and readout is expressed by the following equation. Vn = (3*kT / C) 1 / 2 ...Formula 1 In the above formula, k is the Boltzmann constant, and the unit is, for example, Joule per Kelvin (J / K). T is absolute temperature, and the unit is, for example, Kelvin (K). Furthermore, the unit of Vn is, for example, Volt (V), and the unit of C is, for example, Farad (F).

[0100] 10 is a diagram showing an example of the states of the pixel blocks when the reset level is read and when the subsequent node is initialized in the first embodiment of the present technology. In the figure, a shows the state of the pixel block 300 when the reset level is read, and b shows the state of the pixel block 300 when the subsequent node 360 ​​is initialized. In the figure, the selection transistor 351, the selection transistor 352, and the subsequent reset transistor 361 are represented by switch symbols for convenience of explanation.

[0101] As illustrated in FIG. 13A, the vertical scanning circuit 211 closes the selection transistor 351 and opens the selection transistor 352 and the subsequent reset transistor 361. This causes the reset level of the first pixel to be read out via the subsequent circuit 370.

[0102] After reading out the reset level, as illustrated in b in the figure, the vertical scanning circuit 211 opens the selection transistors 351 and 352 and closes the subsequent reset transistor 361. This disconnects the capacitance elements 331 and 332 from the subsequent node 360, and the level of the subsequent node 360 ​​is initialized.

[0103] In this way, the capacitance value of the parasitic capacitance Cp of the subsequent node 360 ​​in the state where it is separated from the capacitance elements 331 and 332 is much smaller than that of the capacitance elements 331 and 332. For example, if the parasitic capacitance Cp is several femtofarads (fF), the capacitance elements 331 and 332 are on the order of several tens of femtofarads.

[0104] FIG. 11 is a diagram showing an example of a state of the pixel block 300 when a signal level is read out in the first embodiment of the present technology.

[0105] After initializing the subsequent node 360, the vertical scanning circuit 211 closes the selection transistor 352 and opens the selection transistor 351 and subsequent reset transistor 361. This causes the signal level of the first pixel to be read out via the subsequent circuit 370.

[0106] Here, let us consider kTC noise during exposure of a pixel. During exposure, kTC noise occurs at each of the sampling of the reset level and the sampling of the signal level just before the end of exposure. Assuming that the capacitance values ​​of the capacitance elements 331 and 332 are C, the level Vn of the kTC noise during exposure is expressed by the following equation. Vn=(2*kT / C) 1 / 2 ...Formula 2

[0107] 10 and 11, the rear-stage reset transistor 361 is driven during readout, and kTC noise occurs at that time. However, the capacitive elements 331 and 332 are disconnected when the rear-stage reset transistor 361 is driven, and the parasitic capacitance Cp at that time is small. Therefore, the kTC noise during readout can be ignored compared to the kTC noise during exposure. Therefore, the kTC noise during exposure and readout is expressed by Equation 2.

[0108] From formulas 1 and 2, in the pixel block 300 in which the capacitance is separated during readout, the kTC noise is smaller than in the comparative example in which the capacitance cannot be separated during readout. This improves the image quality of the image data.

[0109] In addition, since two pixels in the pixel block 300 share the rear-stage reset transistor 361 and the rear-stage circuit 370, the circuit scale of the pixel array section 220 can be reduced compared to a case where they are not shared. The number of pixels that share is not limited to two pixels. Three or more pixels can also share the rear-stage reset transistor 361 and the rear-stage circuit 370.

[0110] 12 is a flowchart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.

[0111] The vertical scanning circuit 211 exposes all pixels (step S901). Then, the vertical scanning circuit 211 selects a row of the pixel block 300 to be read out (step S902). The column signal processing circuit 260 reads out the reset level of the first pixel in the pixel block 300 of that row (step S903), and then reads out the signal level of that pixel (step S904). Next, the column signal processing circuit 260 reads out the reset level of the second pixel (step S905), and then reads out the signal level of that pixel (step S906).

[0112] The solid-state imaging element 200 judges whether or not the readout of all the rows has been completed (step S907). If the readout of all the rows has not been completed (step S907: No), the solid-state imaging element 200 repeats step S902 and subsequent steps. On the other hand, if the readout of all the rows has been completed (step S907: Yes), the solid-state imaging element 200 executes CDS processing and the like, and ends the operation for imaging. When multiple frames of image data are to be captured continuously, steps S901 to S907 are repeatedly executed in synchronization with a vertical synchronization signal.

[0113] In this way, in the first embodiment of the present technology, when the selection circuit 350 separates the capacitive elements 331 and 332 from the subsequent node 360, the subsequent reset transistor 361 initializes the subsequent node 360. Since the capacitive elements 331 and 332 are separated, the level of the reset noise caused by the driving of the subsequent reset transistor 361 is a level corresponding to the parasitic capacitance smaller than the capacitance of the capacitive elements 331 and 332. By reducing this noise, the image quality of the image data can be improved.

[0114] Furthermore, since the two pixels share the rear-stage reset transistor 361 and the rear-stage circuit 370, the circuit scale of the pixel array section 220 can be reduced compared to a case in which they are not shared.

[0115] [First Modification] In the above-described first embodiment, the solid-state imaging device 200 sequentially reads out pixel signals of two pixels in the pixel block 300, but this configuration may result in an insufficient readout speed. The solid-state imaging device 200 of the first modified example of the first embodiment differs from the first embodiment in that it performs pixel addition.

[0116] 13 is a timing chart showing an example of a read operation of a reset level and a signal level in the first modified example of the first embodiment of the present technology. In the solid-state imaging device 200 of the first embodiment, one of a plurality of modes including a non-addition mode in which pixel addition is not performed and an addition mode in which pixel addition is performed is set. The global shutter operation and read operation of the non-addition mode are the same as those of the first embodiment. The global shutter operation of the addition mode is the same as that of the non-addition mode.

[0117] When reading out in the addition mode, as illustrated in the figure, at timing T10 when reading out of the nth row starts, the vertical scanning circuit 211 supplies high-level FD reset signals rst1 and rst2 over a pulse period. In addition, during the readout period from timing T10 to timing T15, the vertical scanning circuit 211 sets the subsequent stage selection signal selb to a high level.

[0118] From timing T11 immediately after timing T10 to timing T12, the vertical scanning circuit 211 supplies high-level selection signals Φr1 and Φs2 to the n-th row. This causes the potential of the subsequent node 360 ​​to become a reset level Vrst. This reset level Vrst is a value obtained by adding up the reset levels of the two pixels in the pixel block 300.

[0119] From timing T13 immediately after timing T12 and over a pulse period, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb to the n-th row.

[0120] From timing T14 to timing T15 immediately after the initialization of the subsequent node 360, the vertical scanning circuit 211 supplies high-level selection signals Φr2 and Φs2 to the n-th row. This causes the potential of the subsequent node 360 ​​to become a signal level Vsig. This signal level Vsig is the sum of the signal levels of the two pixels in the pixel block 300.

[0121] As illustrated in the figure, high-level selection signals Φr1 and Φs1 are supplied, and the selection unit 340 connects the capacitive elements 331 and 336 to the subsequent node 360 ​​in accordance with these selection signals. In other words, the capacitive elements 331 and 336 are shorted. This causes the reset levels of the two pixels to be added together. Also, high-level selection signals Φr2 and Φs2 are supplied, and the selection unit 340 connects the capacitive elements 332 and 337 to the subsequent node 360 ​​in accordance with these selection signals. In other words, the capacitive elements 332 and 337 are shorted. This causes the signal levels of the two pixels to be added together. This pixel addition can improve sensitivity and readout speed compared to the case where no addition is performed. In addition, the number of rows to be read out is reduced by pixel addition, so power consumption can be reduced.

[0122] Although the solid-state imaging device 200 reads out the signal level after the reset level, the order is not limited to this, and the reset level may be read out after the signal level.

[0123] As described above, according to the first modification of the first embodiment of the present technology, the selection unit 340 connects the capacitive elements 331 and 336 to the subsequent node 360 ​​and connects the capacitive elements 332 and 337 to the subsequent node 360, so that it is possible to add up the pixel signals of the two pixels. This makes it possible to improve sensitivity and readout speed and reduce power consumption, compared to a case where the addition is not performed.

[0124] [Second modified example] In the above-mentioned first embodiment, the circuits in the solid-state imaging element 200 are provided on a single semiconductor chip, but in this configuration, there is a risk that the elements will not fit on the semiconductor chip when the pixels are miniaturized. The solid-state imaging element 200 of the second modification of the first embodiment differs from the first embodiment in that the circuits in the solid-state imaging element 200 are distributed and arranged on two semiconductor chips.

[0125] 14 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 in a second modified example of the first embodiment of the present technology. The solid-state imaging element 200 in the second modified example of the first embodiment includes a lower pixel chip 202 and an upper pixel chip 201 stacked on the lower pixel chip 202. These chips are electrically connected by, for example, Cu-Cu bonding. Note that, other than Cu-Cu bonding, they can also be connected by vias or bumps.

[0126] An upper pixel array unit 221 is arranged on the upper pixel chip 201. A lower pixel array unit 222 and a column signal processing circuit 260 are arranged on the lower pixel chip 202. For each pixel in the pixel array unit 220, a part of it is arranged in the upper pixel array unit 221, and the rest is arranged in the lower pixel array unit 222.

[0127] The lower pixel chip 202 also includes a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250. These circuits are omitted in the figure.

[0128] Moreover, the upper pixel chip 201 is manufactured, for example, by a process dedicated to pixels, and the lower pixel chip 202 is manufactured, for example, by a CMOS (Complementary MOS) process. Note that the upper pixel chip 201 is an example of a first chip recited in the claims, and the lower pixel chip 202 is an example of a second chip recited in the claims.

[0129] 15 is a circuit diagram showing a configuration example of a pixel block 300 in a second modified example of the first embodiment of the present technology. In the pixel block 300, the front-stage circuit block 305 is disposed in the upper pixel chip 201, and other circuits and elements (such as capacitive elements 331 and 332) are disposed in the lower pixel chip 202. It is also possible to further dispose current source transistors 316 and 326 in the lower pixel chip 202. As illustrated in the figure, by distributing the elements in the pixel block 300 among the stacked upper pixel chip 201 and lower pixel chip 202, the area of ​​the pixel can be reduced, making it easier to miniaturize the pixel.

[0130] In this way, according to the second modification of the first embodiment of the present technology, the circuits and elements in the pixel block 300 are distributed and arranged on two semiconductor chips, which facilitates miniaturization of pixels.

[0131] [Third modified example] In the second modified example of the first embodiment described above, a part of the pixel block 300 and the peripheral circuits (such as the column signal processing circuit 260) are provided on the lower pixel chip 202. However, in this configuration, the layout area of ​​the circuits and elements on the lower pixel chip 202 side becomes larger than that of the upper pixel chip 201 by the amount of the peripheral circuits, and there is a risk of wasted space without circuits or elements being generated in the upper pixel chip 201. The solid-state imaging element 200 of the third modified example of the first embodiment differs from the second modified example of the first embodiment in that the circuits in the solid-state imaging element 200 are distributed and arranged on three semiconductor chips.

[0132] 16 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 in a third modified example of the first embodiment of the present technology. The solid-state imaging element 200 in the third modified example of the first embodiment includes an upper pixel chip 201, a lower pixel chip 202, and a circuit chip 203. These chips are stacked and electrically connected by, for example, Cu-Cu bonding. Note that, in addition to Cu-Cu bonding, they can also be connected by vias or bumps.

[0133] An upper pixel array section 221 is arranged on the upper pixel chip 201. A lower pixel array section 222 is arranged on the lower pixel chip 202. For each pixel in the pixel array section 220, a part of it is arranged in the upper pixel array section 221, and the rest is arranged in the lower pixel array section 222.

[0134] Furthermore, the circuit chip 203 is provided with a column signal processing circuit 260, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250. Circuits other than the column signal processing circuit 260 are omitted in the figure.

[0135] The upper pixel chip 201 is an example of a first chip as defined in the claims, the lower pixel chip 202 is an example of a second chip as defined in the claims, and the circuit chip 202 is an example of a third chip as defined in the claims.

[0136] The three-layer structure shown in the figure reduces wasted space and allows pixels to be made finer than a two-layer structure. In addition, the lower pixel chip 204 in the second layer can be manufactured using a process dedicated to capacitors and switches.

[0137] In this way, in the third modified example of the first embodiment of the present technology, the circuits in the solid-state imaging element 200 are distributed across three semiconductor chips, so that the pixels can be made even finer than when they are distributed across two semiconductor chips.

[0138] <2. Second embodiment> In the above-described first embodiment, the solid-state imaging device 200 sequentially reads out pixel signals of two pixels in the pixel block 300, but this configuration may result in an insufficient readout speed. The solid-state imaging device 200 of the first modified example of the first embodiment differs from the first embodiment in that it performs pixel addition.

[0139] 17 is a plan view showing a configuration example of a pixel array section 220 according to the second embodiment of the present technology. In the drawing, a is a plan view showing an example of a pixel array section 220 having a Bayer arrangement. In the drawing, b is a plan view showing an example of a pixel array section 220 having a Quadra Bayer arrangement.

[0140] As shown in FIG. 13A, in the pixel array unit 220 of the second embodiment, R (Red), G (Green), and B (Blue) pixels are arranged in a Bayer array. The solid-state imaging device 200 can add up the pixel signals of an R pixel 301 and its neighboring R pixels 302 to 304 among these pixels. Similarly, for the G pixel and B pixel, the solid-state imaging device 200 can add up the pixel signals of the neighboring four pixels.

[0141] Instead of the Bayer array, the pixels may be arranged in a quadra Bayer array as shown in FIG. 1B. In the quadra Bayer array, four pixels of the same color are arranged adjacent to each other in 2 rows and 2 columns. Focusing on the four R pixels, the four B pixels are arranged to the lower right of them, and the four G pixels are arranged to the right and below them. The solid-state imaging device 200 can add up the pixel signals of the four adjacent pixels of the same color (such as pixels 301 to 304) among these pixels.

[0142] The pixel arrangement is not limited to the Bayer arrangement or the Quadra Bayer arrangement, and may be, for example, an arrangement of R, G, B and W (White) pixels.

[0143] Fig. 18 is a circuit diagram showing a configuration example of a pixel block 300 according to the second embodiment of the present technology. Four pixels to be added when pixel addition is performed are arranged in the pixel block 300 according to the second embodiment. For example, pixels 301 to 304 in Fig. 17 are arranged in the pixel block 300.

[0144] The pixel block 300 of the second embodiment is further provided with capacitance elements 431, 432, 436, and 437, a short-circuit transistor 480, a subsequent reset transistor 461, and a subsequent circuit 470. In the second embodiment, the subsequent circuit block 305 is further provided with subsequent circuits 410 and 420, and the selection unit 340 is further provided with selection circuits 450 and 455. The vertical scanning circuit 211 supplies a subsequent reset signal rstb1 to the subsequent reset transistor 361, and supplies a subsequent reset signal rstb2 to the subsequent reset transistor 461.

[0145] The rear stage circuit 470 includes a rear stage amplification transistor 471 and a rear stage selection transistor 472. For example, nMOS transistors are used as these transistors. The circuit configurations of the rear stage reset transistor 461 and the rear stage circuit 470 are similar to those of the rear stage reset transistor 361 and the rear stage circuit 370. The rear stage circuits 370 and 470 are connected to the same vertical signal line 309. The vertical scanning circuit 211 supplies a rear stage selection signal selb1 to the rear stage selection transistor 372, and supplies a rear stage selection signal selb2 to the rear stage selection transistor 472.

[0146] The previous stage circuit 410 generates a reset level and a signal level in sequence and causes them to be held in the capacitive elements 431 and 432. The previous stage circuit 420 generates a reset level and a signal level in sequence and causes them to be held in the capacitive elements 436 and 437. Note that the capacitive elements 431 and 432 are examples of the fifth and sixth capacitive elements recited in the claims, and the capacitive elements 436 and 437 are examples of the seventh and eighth capacitive elements recited in the claims.

[0147] Moreover, the selection circuit 450 connects either the capacitance elements 431 or 432 to the subsequent node 460, and the selection circuit 455 connects either the capacitance elements 436 or 437 to the subsequent node 460. The selection circuit 450 is an example of a third selection circuit as set forth in the claims, and the selection circuit 455 is an example of a fourth selection circuit as set forth in the claims. The subsequent node 360 ​​is an example of a first subsequent node as set forth in the claims, and the subsequent node 460 is an example of a second subsequent node as set forth in the claims.

[0148] The short-circuit transistor 480 opens and closes the path between the subsequent node 360 ​​and the subsequent node 460 in accordance with a short-circuit signal sht from the vertical scanning circuit 211. As the short-circuit transistor 480, for example, an nMOS transistor is used.

[0149] FIG. 19 is a circuit diagram showing an example configuration of the pre-stage circuits 410 and 420 and the selection circuits 450 and 455 according to the second embodiment of the present technology.

[0150] The pre-stage circuit 410 includes a photoelectric conversion element 411, a transfer transistor 412, an FD reset transistor 413, an FD 414, a pre-stage amplification transistor 415, and a current source transistor 416. The vertical scanning circuit 211 supplies the transfer transistor 412 and the FD reset transistor 413 with a transfer signal trg3 and an FD reset signal rst3.

[0151] The pre-stage circuit 420 includes a photoelectric conversion element 421, a transfer transistor 422, an FD reset transistor 423, an FD 424, a pre-stage amplification transistor 425, and a current source transistor 426. The vertical scanning circuit 211 supplies the transfer transistor 422 and the FD reset transistor 423 with a transfer signal trg4 and an FD reset signal rst4.

[0152] The selection circuit 450 includes selection transistors 451 and 452, and the selection circuit 455 includes selection transistors 456 and 457. The vertical scanning circuit 211 supplies the selection transistors 451 and 452 with selection signals Φr3 and Φs3, and supplies the selection transistors 456 and 457 with selection signals Φr4 and Φs4.

[0153] The circuit configuration of the front-stage circuits 410 and 420 is similar to that of the front-stage circuits 310 and 320. The circuit configuration of the selection circuits 450 and 455 is similar to that of the selection circuits 350 and 355.

[0154] 20 is a timing chart showing an example of a readout operation of the first and second pixels in the pixel block 300 in the second embodiment of the present technology. In the solid-state imaging element 200 of the second embodiment, one of a plurality of modes including a non-addition mode in which pixel addition is not performed and an addition mode in which pixel addition is performed is set. The global shutter operation and readout operation in the non-addition mode are the same as those in the first embodiment. The global shutter operation in the addition mode is the same as that in the non-addition mode.

[0155] In the non-addition mode, the vertical scanning circuit 211 sets the short-circuit signal sht to a low level. Also, at timing T10 when readout of a row of the n-th pixel block 300 starts, the vertical scanning circuit 211 sets the FD reset signals rst1 to rst4 to a high level. Also, during the period from timing T10 to T18, the vertical scanning circuit 211 sets the subsequent stage selection signal selb1 to a high level and sets the subsequent stage selection signal selb2 to a low level.

[0156] In addition, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb1 during a pulse period from timing T10 to T11, and supplies a high-level selection signal Φr1 during a period from timing T11 to T12. During this period, the reset level Vrst1 of the first pixel is read out via the vertical signal line 309.

[0157] The vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb1 during a pulse period from timing T12 to T13, and supplies a high-level selection signal Φs1 during a period from timing T13 to T14. During this period, the signal level Vsig1 of the first pixel is read out via the vertical signal line 309.

[0158] Next, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb1 during a pulse period from timing T14 to T15, and supplies a high-level selection signal Φr2 during a period from timing T15 to T16. During this period, the reset level Vrst2 of the second pixel is read out via the vertical signal line 309.

[0159] The vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb1 during a pulse period from timing T16 to T17, and supplies a high-level selection signal Φs2 during a period from timing T17 to T18. During this period, the signal level Vsig2 of the second pixel is read out via the vertical signal line 309.

[0160] FIG. 21 is a timing chart showing an example of a readout operation of the third and fourth pixels in the pixel block 300 according to the second embodiment of the present technology.

[0161] During the period from timing T18 to T26, the vertical scanning circuit 211 sets the subsequent stage selection signal selb1 to a low level and sets the subsequent stage selection signal selb2 to a high level.

[0162] In addition, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb2 during a pulse period from timing T18 to T19, and supplies a high-level selection signal Φr3 during a period from timing T19 to T20. During this period, the reset level Vrst3 of the third pixel is read out via the vertical signal line 309.

[0163] The vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb2 during a pulse period from timing T20 to T21, and supplies a high-level selection signal Φs3 during a period from timing T21 to T22. During this period, the signal level Vsig3 of the third pixel is read out via the vertical signal line 309.

[0164] Next, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb2 during a pulse period from timing T22 to T23, and supplies a high-level selection signal Φr4 during a period from timing T23 to T24. During this period, the reset level Vrst4 of the fourth pixel is read out via the vertical signal line 309.

[0165] The vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb2 during a pulse period from timing T24 to T25, and supplies a high-level selection signal Φs4 during a period from timing T25 to T26. During this period, the signal level Vsig4 of the fourth pixel is read out via the vertical signal line 309.

[0166] Furthermore, at timing T26 when the readout of the n-th row ends, the vertical scanning circuit 211 sets the FD reset signals rst1 to rst4 to low level.

[0167] As illustrated in FIG. 20 and FIG. 21, in the non-addition mode, the short-circuit transistor 480 is controlled to an open state. Also, the capacitive elements 331 and 332 are sequentially connected to the subsequent node 360, and the reset level and signal level of the first pixel are sequentially read out. The capacitive elements 336 and 337 are sequentially connected to the subsequent node 360, and the reset level and signal level of the second pixel are sequentially read out. Then, the capacitive elements 431 and 432 are sequentially connected to the subsequent node 460, and the reset level and signal level of the third pixel are sequentially read out. The capacitive elements 436 and 437 are sequentially connected to the subsequent node 460, and the reset level and signal level of the fourth pixel are sequentially read out. In this manner, the reset level and signal level of each of the four pixels in the pixel block 300 are sequentially read out.

[0168] 22 is a timing chart showing an example of a readout operation in the addition mode according to the second embodiment of the present technology. In the addition mode, the vertical scanning circuit 211 sets the short-circuit signal sht to a high level. In the readout period of the row of the n-th pixel block 300, from timing T10 to T14, the vertical scanning circuit 211 sets the FD reset signals rst1 to rst4 and the subsequent selection signals selb1 and selb2 to a high level.

[0169] Furthermore, the vertical scanning circuit 211 supplies high-level subsequent reset signals rstb1 and rstb2 during the pulse period from timing T10 to T11, and supplies high-level selection signals Φr1 to Φr4 during the period from timing T11 to T12. During this period, a reset level Vrst is read out via the vertical signal line 309. This reset level Vrst is a value obtained by adding up the reset levels of the four pixels in the pixel block 300.

[0170] Next, the vertical scanning circuit 211 supplies high-level subsequent reset signals rstb1 and rstb2 during the pulse period from timing T12 to T13, and supplies high-level selection signals Φs1 to Φs4 during the period from timing T13 to T14. During this period, a signal level Vsig is read out via the vertical signal line 309. This signal level Vsig is a value obtained by adding up the signal levels of the four pixels in the pixel block 300.

[0171] Here, in the pixel block 300 of the first embodiment, four pixels can be added by increasing the number of pixels sharing the subsequent circuit 370 to four. However, increasing the number of pixels sharing the subsequent circuit 370 causes problems. If the number of pixels sharing the subsequent circuit 370 is increased to four, the wiring of the subsequent node 360 ​​spans four pixels, and the parasitic capacitance of the subsequent node 360 ​​increases. This increase in parasitic capacitance reduces the gain of the signal when pixel addition is not performed. This is because the voltage held in the capacitance elements 331 and 332 is reduced by the parasitic capacitance when connected to the subsequent node 360. This reduction in gain reduces the signal-to-noise (SN) ratio.

[0172] In contrast, in the second embodiment in which the short-circuiting transistor 480 is provided, the number of pixels sharing each of the subsequent circuits 370 and 470 can be reduced to two pixels by opening the short-circuiting transistor 480 in the non-addition mode. This makes it possible to suppress an increase in parasitic capacitance of the subsequent node compared to the case in which four pixels share the subsequent circuit 370. With this configuration, it is possible to suppress a decrease in the S / N ratio in the non-addition mode while realizing addition of more than two pixels.

[0173] In the pixel block 300 illustrated in FIG. 18, one vertical signal line 309 is shared by the rear circuits 370 and 470, but the present invention is not limited to this configuration. The vertical signal lines 309-1 and 309-2 may be wired, the rear circuit 370 may be connected to the vertical signal line 309-1, and the rear circuit 470 may be connected to the vertical signal line 309-2. In this case, the number of rear load MOS transistors 251 and the number of ADCs 261 must be doubled, along with the number of wirings for the vertical signal lines. Instead, in the non-addition mode, one of the two pixels sharing the rear circuit 370 and one of the two pixels sharing the rear circuit 470 can be read out simultaneously, thereby improving the readout speed. In the addition mode, only one of the vertical signal lines 309-1 and 309-2 is used, and the load MOS transistor 251 corresponding to the other is controlled to be in the off state.

[0174] It should be noted that the first to third modified examples of the first embodiment can also be applied to the second embodiment.

[0175] In this way, according to the second embodiment of the present technology, the short-circuit transistor 480 shorts the subsequent node 360 ​​and the subsequent node 460, so that the pixel block 300 can add pixel signals of the four pixels. This makes it possible to improve sensitivity and readout speed and reduce power consumption compared to a case where no addition is performed.

[0176] <3. Third embodiment> In the above-described first embodiment, a current source transistor (316 or 326) is arranged for each pixel, but this configuration may make it difficult to miniaturize the pixels. The solid-state imaging device 200 of the third embodiment differs from the first embodiment in that a current source transistor is shared by multiple pixels.

[0177] 23 is a circuit diagram showing a configuration example of a pixel block 300 according to a third embodiment of the present technology. The pixel block 300 according to the third embodiment differs from the first embodiment in that it further includes pre-stage selection transistors 317 and 327 and does not include a current source transistor 316.

[0178] The previous stage selection transistor 317 outputs the voltage amplified by the previous stage amplification transistor 315 to a previous stage node 338 in accordance with a previous stage selection signal sel1 from the vertical scanning circuit 211. The previous stage selection transistor 327 outputs the voltage amplified by the previous stage amplification transistor 325 to a previous stage node 338 in accordance with a previous stage selection signal sel2 from the vertical scanning circuit 211. In addition, the current source transistor 326 is connected to the previous stage node 338.

[0179] Furthermore, one end of each of the capacitance elements 331, 332, 336, and 337 is commonly connected to a previous-stage node 339, and the other end is connected to the selection circuits 350 and 355. The previous-stage node 339 is connected to a previous-stage node 338.

[0180] Furthermore, the circuits and elements in solid-state imaging device 200 are distributed and arranged in upper pixel chip 201 and lower pixel chip 202. For example, previous stage circuits 310 and 320 are arranged in upper pixel chip 201, and the circuits following these are arranged in circuit chip 202. Previous stage node 338 and previous stage node 339 are connected by Cu-Cu connection or the like.

[0181] In the first embodiment in which a current source transistor is arranged for each pixel, when forming a stacked structure, it is necessary to perform Cu-Cu connection for each pixel as illustrated in FIG. 15. In particular, when a capacitive element 331 having an MIM structure is arranged on the circuit chip 202, the thickness of the chip increases, making it difficult to flatten the surface connecting the upper and lower chips, and restricting the pitch of the Cu-Cu connection. For example, the size of a fine pixel of an image sensor for mobile use is micrometers (μm) or less, whereas the pitch of the Cu-Cu connection is several micrometers (μm). For this reason, miniaturization is difficult in a configuration in which a current source transistor is arranged for each pixel.

[0182] In contrast, in the configuration shown in the figure, in which the current source transistor 326 is shared by two pixels, the number of Cu-Cu connections can be reduced. This makes it easier to miniaturize pixels. Also, the current during global shutter operation can be reduced. Also, the current source transistor 326 is generally configured in a cascade configuration to suppress current fluctuations caused by the channel length modulation effect of the transistor. By sharing the current source transistor 326, which is relatively large in size, the area of ​​the transistor can be reduced.

[0183] Although the current source transistor 326 is shared by two pixels, the number of pixels that share it is not limited to two, and it may be three or more pixels.

[0184] 24 is a timing chart showing an example of a global shutter operation in the third embodiment of the present technology. The vertical scanning circuit 211 supplies high-level FD reset signals rst1 and rst2 and transfer signals trg1 and trg2 to all rows from timing T0 immediately before the start of exposure to timing T1 after the pulse period has elapsed. This causes the PD reset of all pixels, and exposure is started simultaneously in all rows.

[0185] During the period from timing T2 to T5 immediately before the end of exposure, the vertical scanning circuit 211 sets the previous-stage selection signal sel1 of all rows to high level. At timing T3 within that period, the vertical scanning circuit 211 supplies a high-level FD reset signal rst1 over the pulse period while setting the next-stage reset signal rstb and the selection signal Φr1 to high level for all rows. This causes the first pixel in the pixel block 300 to be FD-reset, and the reset level is sampled and held.

[0186] At timing T4, the vertical scanning circuit 211 returns the selection signal Φr1 to a low level. Also, during the period from timing T5 to T8, the vertical scanning circuit 211 sets the previous-stage selection signal sel1 for all rows to a low level and the previous-stage selection signal sel2 to a high level. At timing T6 within that period, the vertical scanning circuit 211 supplies a high-level FD reset signal rst2 over the pulse period while setting the next-stage reset signal rstb and the selection signal Φr2 to a high level for all rows. This causes the second pixel in the pixel block 300 to be FD-reset, and the reset level is sampled and held.

[0187] Then, at timing T7, the vertical scanning circuit 211 returns the selection signal Φr2 for all rows to low level, and at timing T8, sets the previous-stage selection signal sel2 to low level and sets the previous-stage selection signal sel1 to high level.

[0188] Here, sel1_[n] and sel2_[n] in the figure indicate signals to pixels in the nth row.

[0189] As illustrated in the figure, the vertical scanning circuit 211 sequentially closes the previous-stage selection transistors 317 and 327 immediately before the end of exposure. When the previous-stage selection transistor 317 is closed, the FD reset transistor 313 performs an FD reset, and when the previous-stage selection transistor 327 is closed, the FD reset transistor 323 performs an FD reset.

[0190] 25 is a timing chart showing an example of control immediately after the end of exposure in the third embodiment of the present technology. At timing T9 when exposure ends, the vertical scanning circuit 211 supplies the transfer signals trg1 and trg2 at high levels over the pulse period to all rows.

[0191] The vertical scanning circuit 211 then sets the selection signal Φs1 to high level for all rows during the period from timing T10 to T11, whereby the signal level of the first pixel in the pixel block 300 is sampled and held.

[0192] At timing T12, the vertical scanning circuit 211 sets the previous-stage selection signals sel1 of all rows to low level and the previous-stage selection signals sel2 to high level.

[0193] Then, the vertical scanning circuit 211 sets the selection signal Φs2 to high level in all rows during the period from timing T13 to T14, whereby the signal level of the second pixel in the pixel block 300 is sampled and held.

[0194] At timing T15, the vertical scanning circuit 211 returns the previous stage selection signals sel2 of all rows to low level.

[0195] As illustrated in the figure, the vertical scanning circuit 211 sequentially closes the front-stage selection transistors 317 and 327 when exposure is completed. Then, the vertical scanning circuit 211 transfers charges to the transfer transistors 312 and 322 when exposure is completed, and then sequentially closes the front-stage selection transistors 317 and 327.

[0196] It should be noted that the first and third modifications of the first embodiment and the second embodiment can be applied to the third embodiment.

[0197] In this way, according to the third embodiment of the present technology, the current source transistor 326 is shared by two pixels, so that the number of Cu-Cu connections between chips can be reduced, which makes it easier to miniaturize pixels.

[0198] <4. Fourth embodiment> In the first embodiment described above, a pair of capacitors is arranged for each pixel, but this configuration makes it difficult to miniaturize the pixels. The solid-state imaging device 200 of the fourth embodiment differs from the first embodiment in that the number of capacitors is reduced.

[0199] 26 is a circuit diagram showing a configuration example of a pixel block 300 according to a fourth embodiment of the present technology. In the pixel block 300 according to the fourth embodiment, a front-stage circuit block 305, capacitive elements 331, 332, 531, 532, and 533, a selection section 340, a rear-stage reset transistor 361, and a rear-stage circuit 370 are arranged. In the pixel block 300 according to the fourth embodiment, four pixels are arranged. For example, the pixels 301 to 304 in FIG. 17 are arranged in the pixel block 300.

[0200] The front-stage circuit block 305 includes photoelectric conversion elements 311, 511, 512, and 513, and transfer transistors 312, 514, 515, and 516. The front-stage circuit block 305 further includes an FD reset transistor 313, an FD 314, a front-stage amplification transistor 315, and a current source transistor 316. The transfer transistors 312, 514, 515, and 516 are, for example, nMOS transistors.

[0201] The selection unit 340 also includes selection transistors 351, 352, 551, 552, and 553. As the selection transistors 551, 552, and 553, for example, nMOS transistors are used.

[0202] The connection configuration of the photoelectric conversion element 311, the transfer transistor 312, the FD reset transistor 313, the FD 314, the pre-amplification transistor 315, and the current source transistor 316 in the fourth embodiment is the same as that in the first embodiment. However, an FD reset signal rst from the vertical scanning circuit 211 is input to the FD reset transistor 313.

[0203] The photoelectric conversion elements 511 to 513 generate electric charges by photoelectric conversion. The transfer transistor 514 transfers electric charges from the photoelectric conversion element 511 to the FD314 in accordance with a transfer signal trg2 from the vertical scanning circuit 211. The transfer transistor 515 transfers electric charges from the photoelectric conversion element 512 to the FD314 in accordance with a transfer signal trg3 from the vertical scanning circuit 211. The transfer transistor 516 transfers electric charges from the photoelectric conversion element 513 to the FD314 in accordance with a transfer signal trg4 from the vertical scanning circuit 211.

[0204] The connection configuration between the capacitive elements 331 and 332 and the selection transistors 351 and 352 in the fourth embodiment is similar to that in the first embodiment, except that a selection signal Φr from the vertical scanning circuit 211 is input to the selection transistor 351.

[0205] One end of each of the capacitance elements 531 , 532 , and 533 is commonly connected to the previous-stage node 330 , and the other end is connected to the selection section 340 .

[0206] The selection transistor 551 opens and closes the path between the capacitive element 531 and the subsequent node 360 ​​in accordance with a selection signal Φr2 from the vertical scanning circuit 211. The selection transistor 552 opens and closes the path between the capacitive element 532 and the subsequent node 360 ​​in accordance with a selection signal Φr3 from the vertical scanning circuit 211. The selection transistor 553 opens and closes the path between the capacitive element 533 and the subsequent node 360 ​​in accordance with a selection signal Φr4 from the vertical scanning circuit 211.

[0207] The circuit configuration of the rear-stage reset transistor 361 and the rear-stage circuit 370 in the fourth embodiment is similar to that in the first embodiment.

[0208] Furthermore, the circuits and elements within the solid-state imaging device 200 are distributed and disposed on the upper pixel chip 201 and the circuit chip 202. For example, the front-stage circuit block 305 is disposed on the upper pixel chip 201, and the circuits subsequent thereto are disposed on the circuit chip 202.

[0209] As shown in Fig. 26, four pixels share one FD 314, the rear-stage reset transistor 361, and the rear-stage circuit 370. The reset levels of the four pixels are held in the capacitive element 331, and the signal levels of the four pixels are held in the capacitive elements 332, 531, 532, and 533. In the first embodiment, a capacitor for holding the reset level had to be provided for each pixel, but in the fourth embodiment, the capacitor is shared by the four pixels, so that the number of capacitors can be reduced. This makes it easier to miniaturize the pixels compared to a case where the capacitors are not shared.

[0210] Although four pixels share the FD 314, the number of pixels that share the FD 314 is not limited to four. The capacitive elements 331 and 332 are examples of the first and second capacitive elements described in the claims. The capacitive elements 531, 532, and 533 are examples of the third capacitive element described in the claims.

[0211] 27 is a timing chart showing an example of a global shutter operation in the fourth embodiment of the present technology. During the period from timing T0 to T4 at the start of exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst to all rows. At timings T0, T1, T2, and T3 within this period, the vertical scanning circuit 211 supplies transfer signals trg1, trg2, trg3, and trg4 to all rows over the pulse period. This causes the PD reset of all pixels.

[0212] Then, during the period from timing T5 to T15 at the end of exposure, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb to all rows. Also, at timing T5, the vertical scanning circuit 211 supplies an FD reset signal rst to all rows over the pulse period. At timing T6 immediately after timing T5, the vertical scanning circuit 211 supplies a selection signal Φr to all rows over the pulse period. This causes all rows to be FD reset.

[0213] At timing T7, the vertical scanning circuit 211 supplies a transfer signal trg1 to all rows over a pulse period. At timing T8 immediately after timing T7, the vertical scanning circuit 211 supplies a selection signal Φs1 to all rows over a pulse period. This causes the signal level of the first pixel in the pixel block 300 to be sampled and held.

[0214] Also, at timing T9, the vertical scanning circuit 211 supplies a transfer signal trg2 to all rows over a pulse period. At timing T10 immediately after timing T9, the vertical scanning circuit 211 supplies a selection signal Φs2 to all rows over a pulse period. This causes the sum of the signal levels of the first and second pixels in the pixel block 300 to be sampled and held.

[0215] Also, at timing T11, the vertical scanning circuit 211 supplies a transfer signal trg3 to all rows over a pulse period. At timing T12 immediately after timing T11, the vertical scanning circuit 211 supplies a selection signal Φs3 to all rows over a pulse period. As a result, the sum of the signal levels of the first to third pixels in the pixel block 300 is sampled and held.

[0216] Furthermore, at timing T13, the vertical scanning circuit 211 supplies a transfer signal trg4 to all rows over the pulse period. At timing T14 immediately after timing T13, the vertical scanning circuit 211 supplies a selection signal Φs4 to all rows over the pulse period. This causes the sum of the signal levels of the first through fourth pixels in the pixel block 300 to be sampled and held.

[0217] Here, rst_[n] and Φr_[n] indicate signals to pixels in the nth row out of N rows.

[0218] In the fourth embodiment, since the FD 314 is shared by four pixels, the charge transfer of each of the four pixels cannot be performed simultaneously, as shown in the figure. However, since sampling of the four capacitances (capacitive elements 332, 531, 532, and 533) to which the charge is transferred can be realized on the order of several microseconds (μs), the exposure time difference between the pixels is not very large.

[0219] FIG. 28 is a timing chart showing an example of a read operation of a reset level and a signal level in the fourth embodiment of the present technology.

[0220] In the period from timing T20 to timing T26 for reading out the n-th row, the vertical scanning circuit 211 sets the FD reset signal rst to a high level.

[0221] At timing T20, the vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb to the n-th row over a pulse period. Then, at timing T21 immediately after timing T20, the vertical scanning circuit 211 supplies a high-level selection signal Φr to the n-th row over a pulse period. Immediately after this control, a reset level commonly used by the four pixels is read out via the vertical signal line 309.

[0222] Then, at timing T22 after the reset level is read out, the vertical scanning circuit 211 supplies a high-level selection signal Φs1 to the n-th row over a pulse period. Immediately after this control, the signal level Vsig1 of the first pixel is read out via the vertical signal line 309. The column signal processing circuit 260 obtains the difference between the reset level Vrst and the signal level Vsig1 as the net signal level of the first pixel by CDS processing.

[0223] Then, at timing T23 after reading out the signal level Vsig1, the vertical scanning circuit 211 supplies a selection signal Φs2 of high level to the nth row over a pulse period. Immediately after this control, Vsig2 is read out via the vertical signal line 309. This Vsig2 corresponds to the sum of the signal levels of the first and second pixels. The column signal processing circuit 260 obtains the difference between Vsig1 and Vsig2 as the signal level after CDS processing of the second pixel.

[0224] Then, at timing T24 after reading out Vsig2, the vertical scanning circuit 211 supplies a high-level selection signal Φs3 to the nth row over the pulse period. Immediately after this control, Vsig3 is read out via the vertical signal line 309. This Vsig3 corresponds to the sum of the signal levels of the first to third pixels. The column signal processing circuit 260 obtains the difference between Vsig2 and Vsig3 as the signal level after CDS processing of the third pixel.

[0225] Then, at timing T25 after reading out Vsig3, the vertical scanning circuit 211 supplies a high-level selection signal Φs4 to the nth row over the pulse period. Immediately after this control, Vsig4 is read out via the vertical signal line 309. This Vsig4 corresponds to the sum of the signal levels of the first to fourth pixels. The column signal processing circuit 260 obtains the difference between Vsig3 and Vsig4 as the signal level after CDS processing of the fourth pixel.

[0226] It should be noted that the third modified example of the first embodiment can also be applied to the fourth embodiment.

[0227] In this manner, in the fourth embodiment of the present technology, the capacitive element 331 for retaining the reset level is shared by four pixels, which makes it easier to miniaturize the pixels compared to a case in which the capacitive element is not shared.

[0228] <5. Application examples for mobile devices> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0229] FIG. 29 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology according to the present disclosure can be applied.

[0230] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 29, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0231] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0232] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0233] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0234] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0235] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0236] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating a vehicle collision, following a vehicle based on the distance between vehicles, maintaining vehicle speed, warning a vehicle collision, or warning a vehicle from leaving a lane.

[0237] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0238] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0239] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 29, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0240] FIG. 30 is a diagram showing an example of the installation position of the imaging unit 12031.

[0241] In FIG. 30, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0242] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0243] 30 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0244] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0245] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0246] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0247] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0248] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above. Specifically, for example, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to reduce kTC noise and obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0249] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology.

[0250] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0251] The present technology can also be configured as follows. (1) a predetermined number of capacitive elements; a front-stage circuit block that generates a predetermined reset level and a plurality of signal levels corresponding to an amount of exposure and stores the signal levels in different capacitance elements; a selection unit which sequentially performs a control to connect a capacitive element holding the reset level among the predetermined number of capacitive elements to a predetermined subsequent node, a control to disconnect the predetermined number of capacitive elements from the subsequent node, and a control to connect a capacitive element holding any of the plurality of signal levels among the predetermined number of capacitive elements to the subsequent node; a subsequent-stage reset transistor that initializes a level of the subsequent-stage node when the predetermined number of capacitive elements are disconnected from the subsequent-stage node; a rear circuit that sequentially reads out the reset level and each of the plurality of signal levels via the rear node; A solid-state imaging device comprising: (2) the predetermined number of capacitive elements includes first and second capacitive elements and third and fourth capacitive elements; The front-stage circuit block includes: a first pre-stage circuit that sequentially generates a first reset level and a first signal level and causes the first and second capacitive elements to hold the first and second reset levels; a second pre-stage circuit that sequentially generates a second reset level and a second signal level and holds them in the third and fourth capacitance elements; Equipped with The selection unit is a first selection circuit that connects either the first or second capacitive element to the subsequent node; a second selection circuit that connects either the third or fourth capacitance element to the subsequent node. The solid-state imaging device according to (1) above. (3) The first front-stage circuit comprises: A first photoelectric conversion element; a first pre-stage transfer transistor that transfers charges from the first photoelectric conversion element to a first floating diffusion layer; a first reset transistor that initializes the first floating diffusion layer; a first pre-amplification transistor that amplifies a voltage of the first floating diffusion layer; Equipped with The second front-stage circuit includes: A second photoelectric conversion element; a second pre-stage transfer transistor that transfers charges from the second photoelectric conversion element to a second floating diffusion layer; a second reset transistor that initializes the second floating diffusion layer; a second pre-amplification transistor that amplifies the voltage of the second floating diffusion layer; Equipped The solid-state imaging device according to (2) above. (4) the first front-stage circuit further includes a first current source transistor connected to a first front-stage node; the second front stage circuit further includes a second current source transistor connected to a second front stage node; the first pre-stage amplifying transistor amplifies a voltage of the first floating diffusion layer and outputs the amplified voltage to the first pre-stage node; the second front-stage amplifying transistor amplifies a voltage of the second floating diffusion layer and outputs the amplified voltage to the second front-stage node; one end of each of the first and second capacitance elements is commonly connected to the first previous-stage node, and the other end of each of the first and second capacitance elements is connected to the first selection circuit; One end of each of the third and fourth capacitance elements is commonly connected to the second front-stage node, and the other end of each of the third and fourth capacitance elements is connected to the second selection circuit. The solid-state imaging device according to (3) above. (5) at a predetermined exposure start timing, the first and second pre-stage transfer transistors transfer the charges to the first and second floating diffusion layers, and the first and second reset transistors initialize the first and second photoelectric conversion elements together with the first and second floating diffusion layers; At a predetermined exposure end timing, the first and second pre-stage transfer transistors transfer the charges to the first and second floating diffusion layers. The solid-state imaging device according to (3) or (4). (6) The selection unit sequentially performs control to connect one of the first and second capacitive elements to the subsequent node, control to connect the other of the first and second capacitive elements to the subsequent node, control to connect one of the third and fourth capacitive elements to the subsequent node, and control to connect the other of the third and fourth capacitive elements to the subsequent node. The solid-state imaging device according to any one of (3) to (5). (7) In a predetermined addition mode, the selection unit sequentially performs control to connect one of the first and second capacitive elements and one of the third and fourth capacitive elements to the subsequent node, and control to connect the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the subsequent node. The solid-state imaging device according to any one of (3) to (6). (8) the first front-stage circuit further includes a first front-stage selection transistor that outputs the voltage amplified by the first front-stage amplification transistor to a predetermined front-stage node in accordance with a predetermined first selection signal; The second front-stage circuit includes: a second pre-stage selection transistor that outputs a voltage amplified by the second pre-stage amplification transistor to the pre-stage node in accordance with a predetermined second selection signal; a current source transistor connected to the previous node; Further equipped with one end of each of the first and second capacitance elements is commonly connected to the previous-stage node, and the other end of each of the first and second capacitance elements is connected to the first selection circuit; The third and fourth capacitive elements have one end commonly connected to the previous-stage node, and the other end connected to the second selection circuit. The solid-state imaging device according to (3) above. (9) immediately before a predetermined timing for ending exposure and after the timing for ending exposure, the first and second front-stage selection transistors are sequentially switched to a closed state; the first reset transistor initializes the first floating diffusion layer when the first pre-stage selection transistor is in the closed state; the second reset transistor initializes the second floating diffusion layer when the second pre-stage select transistor is in the closed state; Immediately after the timing of the end of the exposure, the first and second front-stage selection transistors are sequentially switched to a closed state, The first and second pre-stage transfer transistors transfer the electric charges at a predetermined timing when exposure ends. The solid-state imaging device according to (8) above. (10) further comprising a short-circuit transistor for opening and closing a path between the first subsequent node and the second subsequent node; the predetermined number of capacitances includes first, second, third, fourth, fifth, sixth, seventh, and eighth capacitive elements; The selection unit is a first selection circuit that connects either the first or second capacitive element to the first subsequent node; a second selection circuit that connects either the third or fourth capacitive element to the first subsequent node; a third selection circuit that connects either the fifth or sixth capacitive element to the second subsequent node; a fourth selection circuit that connects either the seventh or eighth capacitive element to the second subsequent node; The solid-state imaging device according to (1) above, (11) In a predetermined non-adding mode, the shorting transistor is open; In the non-addition mode, the selection unit performs control to sequentially connect each of the first and second capacitive elements to the first subsequent node, control to sequentially connect each of the third and fourth capacitive elements to the first subsequent node, control to sequentially connect each of the fifth and sixth capacitive elements to the second subsequent node, and control to sequentially connect each of the seventh and eighth capacitive elements to the second subsequent node in a predetermined order. The solid-state imaging device according to (10) above. (12) in a predetermined summing mode, the shorting transistor is in a closed state; In the addition mode, the selection section sequentially performs control to connect one of the first and second capacitive elements and one of the third and fourth capacitive elements to the first subsequent node while connecting one of the fifth and sixth capacitive elements and one of the seventh and eighth capacitive elements to the second subsequent node, and control to connect the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the first subsequent node while connecting the other of the fifth and sixth capacitive elements and the other of the seventh and eighth capacitive elements to the second subsequent node. The solid-state imaging device according to (10) or (11) above. (13) The predetermined number of capacitive elements includes first and second capacitive elements and a third capacitance; The front-stage circuit block includes: A first photoelectric conversion element; a first pre-stage transfer transistor that transfers charges from the first photoelectric conversion element to a predetermined floating diffusion layer; A second photoelectric conversion element; a second pre-stage transfer transistor that transfers charges from the second photoelectric conversion element to a predetermined floating diffusion layer; a reset transistor for initializing the floating diffusion layer; a pre-amplifying transistor that amplifies the voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined pre-stage node; Equipped with One end of each of the first and second capacitive elements and the third capacitive element is commonly connected to the previous-stage node, and the other end of each of the first and second capacitive elements is connected to the selection section. The solid-state imaging device according to (1) above. (14) at a predetermined exposure start timing, the first and second pre-stage transfer transistors transfer the charges to the floating diffusion layer, and the reset transistor initializes the first and second photoelectric conversion elements together with the floating diffusion layer; At a predetermined exposure end timing, the first and second pre-stage transfer transistors transfer the charges to the first and second floating diffusion layers in sequence. The solid-state imaging device according to (13) above. (15) The selection unit sequentially performs control to connect one of the first and second capacitive elements to the subsequent node, control to connect the other of the first and second capacitive elements to the subsequent node, and control to connect the third capacitive element to the subsequent node. The solid-state imaging device according to (13) or (14). (16) The front-stage circuit block is provided in a first chip, The predetermined number of capacitive elements, the selection unit, the subsequent stage reset transistor, and the subsequent stage circuit are provided on a second chip. The solid-state imaging device according to any one of (1) to (15). (17) An analog-to-digital converter that converts the output reset level and the plurality of signal levels into digital signals in sequence, The analog-to-digital converter is provided on the second chip. The solid-state imaging device according to (16) above. (18) An analog-to-digital converter that converts the output reset level and the plurality of signal levels into digital signals in sequence, The analog-to-digital converter is provided on a third chip. The solid-state imaging device according to (16) or (17) above. (19) A predetermined number of capacitive elements; a front-stage circuit block that generates a predetermined reset level and a plurality of signal levels corresponding to an amount of exposure and stores the signal levels in different capacitance elements; a selection unit which sequentially performs a control to connect a capacitive element holding the reset level among the predetermined number of capacitive elements to a predetermined subsequent node, a control to disconnect the predetermined number of capacitive elements from the subsequent node, and a control to connect a capacitive element holding any of the plurality of signal levels among the predetermined number of capacitive elements to the subsequent node; a subsequent-stage reset transistor that initializes a level of the subsequent-stage node when the predetermined number of capacitive elements are disconnected from the subsequent-stage node; a rear circuit that sequentially reads out the reset level and each of the plurality of signal levels via the rear node; a signal processing circuit that converts the reset level and the plurality of signal levels into digital signals in sequence and processes them; An imaging device comprising: (20) A first photoelectric conversion element that converts incident light into an electric charge; a second photoelectric conversion element that converts incident light into an electric charge; a pre-amplification transistor that converts the charge into a voltage; a predetermined number of capacitance elements each having one end connected to a previous-stage node to which the previous-stage amplification transistor is output; a predetermined number of selection transistors inserted in respective paths between the other ends of the predetermined number of capacitance elements and a predetermined subsequent node; a reset transistor having a source or a drain connected to the subsequent node; a rear-stage amplifying transistor having a gate connected to the rear-stage node and outputting a pixel signal; A solid-state imaging device comprising: [Explanation of symbols]

[0252] 100 Imaging device 110 Imaging lens 120 Recording Section 130 Imaging control section 200 Solid-state image sensor 201 Upper pixel chip 202 Lower pixel chip 203 Circuit Chip 211 Vertical scanning circuit 212 Timing control circuit 213 DAC 220 Pixel array section 221 Upper pixel array section 222 Lower pixel array section 250 Load MOS circuit block 251 Load MOS transistor 260 Column signal processing circuit 261 ADC 262 Digital Signal Processing Unit 300 pixel block 301~304 pixels 305 Front-end circuit block 310, 320, 410, 420 front stage circuit 311, 321, 411, 421, 511~513 Photoelectric conversion element 312, 322, 412, 422, 514~516 Transfer transistor 313, 323, 413, 423 FD reset transistor 314, 324, 414, 424FD 315, 325, 415, 425 Preamplifier Transistor 316, 326, 416, 426 Current source transistors 317, 327 Front-stage selection transistor 331, 332, 336, 337, 431, 432, 436, 437, 531 to 533 Capacitive elements 340 Selection 350, 355, 450, 455 selection circuit 351, 352, 356, 357, 451, 452, 456, 457, 551 to 553 Select transistor 361, 461 Rear reset transistor 370, 470 rear circuit 371, 471 Post-amplification transistor 372, 472 Rear selection transistor 480 Shorted Transistor 12031 Imaging unit

Claims

1. A predetermined number of capacitive elements; a front-stage circuit block that generates a predetermined reset level and a plurality of signal levels corresponding to an amount of exposure and stores them in different capacitance elements; a selection unit which sequentially performs a control to connect a capacitive element holding the reset level among the predetermined number of capacitive elements to a predetermined subsequent node, a control to disconnect the predetermined number of capacitive elements from the subsequent node, and a control to connect a capacitive element holding any of the plurality of signal levels among the predetermined number of capacitive elements to the subsequent node; a subsequent-stage reset transistor that initializes a level of the subsequent-stage node when the predetermined number of capacitive elements are disconnected from the subsequent-stage node; a rear circuit that sequentially reads out the reset level and each of the plurality of signal levels via the rear node; A solid-state imaging device comprising:

2. the predetermined number of capacitive elements includes first and second capacitive elements and third and fourth capacitive elements; The front-stage circuit block includes: a first pre-stage circuit that sequentially generates a first reset level and a first signal level and causes the first and second capacitive elements to hold the first and second reset levels; a second pre-stage circuit that sequentially generates a second reset level and a second signal level and causes the third and fourth capacitance elements to hold the second reset level and the second signal level; Equipped with The selection unit is a first selection circuit that connects either the first or second capacitive element to the subsequent node; a second selection circuit that connects either the third or fourth capacitance element to the subsequent node.

2. The solid-state imaging device according to claim 1.

3. The first front-stage circuit includes: A first photoelectric conversion element; a first pre-stage transfer transistor that transfers charges from the first photoelectric conversion element to a first floating diffusion layer; a first reset transistor for initializing the first floating diffusion layer; a first pre-amplifying transistor that amplifies a voltage of the first floating diffusion layer; Equipped with The second front-stage circuit includes: A second photoelectric conversion element; a second pre-stage transfer transistor that transfers charges from the second photoelectric conversion element to a second floating diffusion layer; a second reset transistor for initializing the second floating diffusion layer; a second pre-amplifying transistor that amplifies the voltage of the second floating diffusion layer; Equipped 3. The solid-state imaging device according to claim 2.

4. the first front-stage circuit further includes a first current source transistor connected to a first front-stage node; the second front-stage circuit further includes a second current source transistor connected to a second front-stage node; the first pre-stage amplifying transistor amplifies a voltage of the first floating diffusion layer and outputs the amplified voltage to the first pre-stage node; the second front-stage amplifying transistor amplifies a voltage of the second floating diffusion layer and outputs the amplified voltage to the second front-stage node; one end of each of the first and second capacitance elements is commonly connected to the first previous-stage node, and the other end of each of the first and second capacitance elements is connected to the first selection circuit; One end of each of the third and fourth capacitance elements is commonly connected to the second front-stage node, and the other end of each of the third and fourth capacitance elements is connected to the second selection circuit.

4. The solid-state imaging device according to claim 3.

5. at a predetermined exposure start timing, the first and second pre-stage transfer transistors transfer the charges to the first and second floating diffusion layers, and the first and second reset transistors initialize the first and second photoelectric conversion elements together with the first and second floating diffusion layers; At a predetermined exposure end timing, the first and second pre-stage transfer transistors transfer the charges to the first and second floating diffusion layers.

4. The solid-state imaging device according to claim 3.

6. The selection unit sequentially performs control to connect one of the first and second capacitive elements to the subsequent node, control to connect the other of the first and second capacitive elements to the subsequent node, control to connect one of the third and fourth capacitive elements to the subsequent node, and control to connect the other of the third and fourth capacitive elements to the subsequent node.

4. The solid-state imaging device according to claim 3.

7. The selection section sequentially performs control to connect one of the first and second capacitive elements and one of the third and fourth capacitive elements to the subsequent node in a predetermined addition mode, and control to connect the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the subsequent node.

4. The solid-state imaging device according to claim 3.

8. the first front-stage circuit further includes a first front-stage selection transistor that outputs a voltage amplified by the first front-stage amplification transistor to a predetermined front-stage node in accordance with a predetermined first selection signal; The second front-stage circuit includes: a second pre-stage selection transistor that outputs a voltage amplified by the second pre-stage amplification transistor to the pre-stage node in accordance with a predetermined second selection signal; a current source transistor connected to the previous node; Further equipped with one end of each of the first and second capacitance elements is commonly connected to the previous-stage node, and the other end of each of the first and second capacitance elements is connected to the first selection circuit; The third and fourth capacitive elements have one end commonly connected to the previous-stage node, and the other end connected to the second selection circuit.

4. The solid-state imaging device according to claim 3.

9. the first and second front-stage selection transistors are successively switched to a closed state immediately before and after a predetermined timing for ending exposure, the first reset transistor initializes the first floating diffusion layer when the first pre-stage selection transistor is in the closed state; the second reset transistor initializes the second floating diffusion layer when the second pre-stage select transistor is in the closed state; Immediately after the timing of the end of the exposure, the first and second front-stage selection transistors are sequentially switched to a closed state, The first and second pre-stage transfer transistors transfer the electric charges at a predetermined timing when exposure ends.

9. The solid-state imaging device according to claim 8.

10. a short-circuit transistor for opening and closing a path between the first subsequent node and the second subsequent node; the predetermined number of capacitive elements includes first, second, third, fourth, fifth, sixth, seventh, and eighth capacitive elements; The selection unit is a first selection circuit that connects either the first or second capacitive element to the first subsequent node; a second selection circuit that connects either the third or fourth capacitive element to the first subsequent node; a third selection circuit that connects either the fifth or sixth capacitive element to the second subsequent node; a fourth selection circuit that connects either the seventh or eighth capacitive element to the second subsequent node; The solid-state imaging device according to claim 1 .

11. In a predetermined non-summing mode, the shorting transistor is open; In the non-addition mode, the selection section performs control to sequentially connect each of the first and second capacitive elements to the first subsequent node, control to sequentially connect each of the third and fourth capacitive elements to the first subsequent node, control to sequentially connect each of the fifth and sixth capacitive elements to the second subsequent node, and control to sequentially connect each of the seventh and eighth capacitive elements to the second subsequent node in a predetermined order. The solid-state imaging device according to claim 10.

12. In a given summing mode, the shorting transistor is closed; In the addition mode, the selection section sequentially performs control to connect one of the first and second capacitive elements and one of the third and fourth capacitive elements to the first subsequent node while connecting one of the fifth and sixth capacitive elements and one of the seventh and eighth capacitive elements to the second subsequent node, and control to connect the other of the first and second capacitive elements and the other of the third and fourth capacitive elements to the first subsequent node while connecting the other of the fifth and sixth capacitive elements and the other of the seventh and eighth capacitive elements to the second subsequent node. The solid-state imaging device according to claim 10.

13. the predetermined number of capacitive elements includes first and second capacitive elements and a third capacitive element; The front-stage circuit block includes: A first photoelectric conversion element; a first pre-stage transfer transistor that transfers charges from the first photoelectric conversion element to a predetermined floating diffusion layer; A second photoelectric conversion element; a second pre-stage transfer transistor that transfers charges from the second photoelectric conversion element to a predetermined floating diffusion layer; a reset transistor for initializing the floating diffusion layer; a pre-amplifying transistor that amplifies the voltage of the floating diffusion layer and outputs the amplified voltage to a predetermined pre-stage node; Equipped with One end of each of the first and second capacitive elements and the third capacitive element is commonly connected to the previous-stage node, and the other end of each is connected to the selection section.

2. The solid-state imaging device according to claim 1.

14. at a predetermined exposure start timing, the first and second pre-stage transfer transistors transfer the charges to the floating diffusion layer, and the reset transistor initializes the first and second photoelectric conversion elements together with the floating diffusion layer; At a predetermined exposure end timing, the first and second pre-stage transfer transistors transfer the charges to the floating diffusion layer in sequence. The solid-state imaging device according to claim 13.

15. The selection section sequentially performs control to connect one of the first and second capacitive elements to the subsequent node, control to connect the other of the first and second capacitive elements to the subsequent node, and control to connect the third capacitive element to the subsequent node. The solid-state imaging device according to claim 13.

16. the front-stage circuit block is provided in a first chip, The predetermined number of capacitive elements, the selection unit, the subsequent stage reset transistor, and the subsequent stage circuit are provided on a second chip.

2. The solid-state imaging device according to claim 1.

17. an analog-to-digital converter for converting the output reset level and the plurality of signal levels into digital signals in sequence; The analog-to-digital converter is provided on the second chip.

17. The solid-state imaging device according to claim 16.

18. an analog-to-digital converter for converting the output reset level and the plurality of signal levels into digital signals in sequence; The analog-to-digital converter is provided on a third chip.

17. The solid-state imaging device according to claim 16.

19. A predetermined number of capacitive elements; a front-stage circuit block that generates a predetermined reset level and a plurality of signal levels corresponding to an amount of exposure and stores them in different capacitance elements; a selection unit which sequentially performs a control to connect a capacitive element holding the reset level among the predetermined number of capacitive elements to a predetermined subsequent node, a control to disconnect the predetermined number of capacitive elements from the subsequent node, and a control to connect a capacitive element holding any of the plurality of signal levels among the predetermined number of capacitive elements to the subsequent node; a subsequent-stage reset transistor that initializes a level of the subsequent-stage node when the predetermined number of capacitive elements are disconnected from the subsequent-stage node; a subsequent circuit that sequentially reads out the reset level and each of the plurality of signal levels via the subsequent node; a signal processing circuit that converts the reset level and the plurality of signal levels into digital signals in sequence and processes them; An imaging device comprising:

20. a first photoelectric conversion element that converts incident light into an electric charge; a second photoelectric conversion element that converts incident light into an electric charge; a pre-amplification transistor that converts the charge into a voltage; a predetermined number of capacitance elements each having one end connected to a previous-stage node to which the previous-stage amplification transistor is output; a predetermined number of selection transistors inserted in respective paths between the other ends of the predetermined number of capacitance elements and a predetermined subsequent node; a reset transistor having a source or a drain connected to the subsequent node; a rear-stage amplifying transistor whose gate is connected to the rear-stage node and which outputs a pixel signal; A solid-state imaging device comprising:

Images