Semiconductor structure and manufacturing method thereof, memory

Abstract

In an embodiment of the present invention, a semiconductor structure and a manufacturing method thereof, and a memory are provided, the semiconductor structure including a substrate, a plurality of oxide pillars, a plurality of active pillars, a first insulating layer, and a memory structure, the plurality of oxide pillars are located on the substrate and are arranged in an array along a first direction and a second direction, the first direction and the second direction are both parallel to a surface of the substrate, and the first direction and the second direction intersect, the first insulating layer is located in gaps between the plurality of oxide pillars, each of the active pillars is located on an upper surface of a corresponding one of the oxide pillars, and the memory structure covers at least a portion of a sidewall of the active pillars.

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) The present invention claims priority to a Chinese patent application filed with the China Patent Office on June 21, 2022, bearing application number 202210708966.5 and entitled "Semiconductor structure and manufacturing method thereof, memory", the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the field of semiconductor technology, and in particular to semiconductor structures and methods for fabricating the same, and memories. [Background technology]

[0003] The architecture of a DRAM (Dynamic Random Access Memory) memory array is an array of transistors and capacitors that are memory cells (i.e., 1T1C memory cells), where the gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor.

[0004] As DRAM becomes smaller, the size of the capacitors also becomes smaller, and how to ensure the performance of the capacitors mounted on DRAM becomes an urgent issue that needs to be solved. Summary of the Invention [Problem to be solved by the invention]

[0005] In view of this, embodiments of the present invention provide a semiconductor structure and method for fabricating the same, a memory. [Means for solving the problem]

[0006] According to one aspect of the present invention, there is provided a semiconductor structure, the semiconductor structure comprising: a substrate, a plurality of oxide pillars, a plurality of active pillars, a first insulating layer, and a memory structure; the plurality of oxide pillars are located on the substrate and are arranged in an array along a first direction and a second direction, the first direction and the second direction are both parallel to a surface of the substrate, and the first direction and the second direction intersect; the first insulating layer is located in gaps between the oxide pillars; Each of the active pillars is located on the upper surface of a corresponding one of the oxide pillars; The memory structure covers at least a portion of the sidewall of the active pillar.

[0007] In the above technical solution, the material of the oxide pillars is the same as or different from the material of the first insulating layer.

[0008] In the above technical solution, each of the active pillars includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar, and the orthogonal projection of the first sub-active pillar on the substrate is located within the orthogonal projection of the second sub-active pillar on the substrate.

[0009] In the above technical solution, the memory structure comprises: a first conductive layer covering a sidewall of the first sub active pillar; a dielectric layer covering a surface of the first conductive layer and an upper surface of the first insulating layer; and a second conductive layer located within the dielectric layer.

[0010] In the above technical solution, the semiconductor structure further includes a plurality of transistors, a channel structure of each of the transistors is located in the second sub-active pillar, and an extension direction of the channel structure is perpendicular to the surface of the substrate.

[0011] In the above technical solution, the transistor is: a gate structure provided around the second sub active pillar; The second sub active pillar includes a source and a drain provided at two opposite ends thereof, respectively.

[0012] In the above technical solution, the semiconductor structure further includes a plurality of bit lines located on the transistor and electrically contacting the tops of the second sub-active pillars.

[0013] According to another aspect of the invention, there is provided a memory including a semiconductor structure according to any one of the preceding embodiments of the invention.

[0014] According to yet another aspect of the present invention there is provided a method for manufacturing a semiconductor structure, the method comprising the steps of: forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction on a substrate, each of the semiconductor pillars including a first portion and a second portion located on the first portion, a maximum radial width of the first portion being smaller than a minimum radial width of the second portion, the first direction and the second direction both being parallel to a surface of the substrate, and the first direction and the second direction intersecting with each other; forming a support layer on the top of the semiconductor pillar, the support layer covering a sidewall of an upper portion of the second portion; oxidizing the semiconductor pillar such that the first portion is fully oxidized to an oxide pillar and an exposed surface of the second portion is oxidized to an oxide layer; filling gaps between the oxide pillars with a first insulating material to form a first insulating layer on a surface of the substrate; removing the oxide layer to obtain a first sub-active pillar; and forming a memory structure on a sidewall of at least the first sub-active pillar.

[0015] In the above technical solution, forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction on the substrate includes: Providing a semiconductor base; forming a plurality of first trenches arranged at intervals along a first direction in the base and a plurality of second trenches arranged at intervals along a second direction; and expanding a bottom of each of the first trench and / or the second trench to form the plurality of semiconductor pillars.

[0016] In the above technical solution, forming the support layer includes: filling spaces between the semiconductor pillars with the first insulating material, and removing a portion of the first insulating material by etching to expose tops of the semiconductor pillars to obtain second sub-active pillars; depositing a second insulating material, the second insulating material covering a surface of the second sub-active pillar to form a second insulating layer on the top of the semiconductor pillar.

[0017] In the above technical solution, a part of the second insulating layer is removed along the second direction to form a first shallow trench, a bottom surface of the first shallow trench is flush with a bottom surface of the second sub active pillar, and the first shallow trench is filled with the first insulating material; removing a portion of the second insulating layer along the first direction to form a second shallow trench, a bottom surface of the second shallow trench being flush with an upper surface of the second sub active pillar, and filling the second shallow trench with the second insulating material; removing all of the first insulating material filled between the semiconductor pillars and forming a lattice-shaped support layer on top of the semiconductor pillars.

[0018] In the above technical solution, after forming the supporting layer, the semiconductor pillar is oxidized, so that the first portion of the semiconductor pillar is completely oxidized to become an oxide pillar, and the exposed surface of the second portion of the semiconductor pillar is oxidized to become an oxide layer. refilling the spaces between the semiconductor pillars with a first insulating material, and removing a portion of the first insulating material and the oxide layer by etching, so that the remaining first insulating material and the oxide pillars form a first insulating layer located on the surface of the substrate.

[0019] In the above technical solution, forming a memory structure on the sidewall of at least the first sub active pillar includes: forming a first conductive layer covering a sidewall of the first sub active pillar; forming a dielectric layer covering a surface of the first conductive layer and an upper surface of the first insulating layer; and forming a second conductive layer in the dielectric layer.

[0020] In the above technical solution, forming a first conductive layer covering the sidewall of the first sub active pillar includes: forming a first conductive layer covering the sidewalls of the first sub-active pillars by a selective deposition process;

[0021] In the above technical solution, the method comprises: removing the support layer to expose the second sub-active pillars; forming a gate structure covering at least one side of the second sub active pillar; and forming a source and a drain on opposite ends of the second sub-active pillar, respectively.

[0022] In the above technical solution, the maximum radial width of the first portion along the first direction is smaller than the minimum radial width of the second portion along the first direction; and / or The maximum radial width of the first portion along the second direction is smaller than the minimum radial width of the second portion along the second direction. Effect of the Invention

[0023] In an embodiment of the present invention, a plurality of semiconductor pillars are formed on a substrate, and each of the semiconductor pillars includes a first portion and a second portion located on the first portion, so that the maximum diameter width of the first portion is smaller than the minimum diameter width of the second portion. Next, the first portions of the plurality of semiconductor pillars are all oxidized to oxide pillars by an oxidation process, and a first insulating material is filled into the gaps between the plurality of oxide pillars. Finally, a corresponding active pillar is formed on the upper surface of each oxide pillar, thereby isolating the active pillars from the substrate. Furthermore, a memory structure formed on a part of the sidewall of the active pillar is insulated from the substrate, thereby improving the leakage problem of the memory structure and further improving the reliability of the memory. [Brief description of the drawings]

[0024] [Figure 1a]2 is a schematic diagram of circuit connections of DRAM transistors provided by an embodiment of the present invention. [Figure 1b] 1 is a structural schematic diagram of a memory provided by an embodiment of the present invention; [Diagram 2] 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention. [Figure 3a] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3b] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3c] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3d] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3e] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3f] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3g] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3h] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3i] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3j] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3k] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3l] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3m]1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3n] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3o] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3p] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. [Figure 3q] 1A-1D are cross-sectional schematic diagrams of a process for fabricating a semiconductor structure provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] In the accompanying drawings (not necessarily drawn to scale), similar drawing marks may depict similar parts in different views. Similar drawing marks with different letter suffixes may show different examples of similar parts. The accompanying drawings generally illustrate embodiments discussed herein, by way of example and not by way of limitation.

[0026] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be described in more detail below with reference to the drawings and examples. Although exemplary implementation methods of the present invention are illustrated in the accompanying drawings, the present invention can be implemented in various forms and should not be limited by the embodiments illustrated in the present specification. Rather, it should be understood that these examples are provided to allow a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0027] The present invention will be more particularly described in the following paragraphs by way of example with reference to the accompanying drawings. In light of the following description and claims, the advantages and features of the present invention will become more apparent. It should be understood that the accompanying drawings are in very simplified form, not to scale, and are only used to explain the embodiments of the present invention as a convenient, clear and helpful aid.

[0028] The meaning of "on," "above," and "on top of" in this invention is to be interpreted in the broadest possible sense, and "on" does not only mean "on" something and there are no intervening features or layers (i.e., directly on top of something), but also means "on" something and there are intervening features or layers.

[0029] Also, for ease of description, this description uses spatially relative terms such as "on...", "above...", "on top of...", "on", "top" and the like to describe the relationship of elements or features to other elements or features as shown in the drawings. In addition to the orientation shown in the accompanying drawings, the spatially relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees, or at other orientations) and the spatially relative terms used in this description may likewise be interpreted accordingly.

[0030] In embodiments of the present invention, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or left unpatterned. Additionally, the substrate can include various semiconductor materials such as silicon, silicon-germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0031] In the present embodiment, the term "layer" refers to a material portion that includes a region having a thickness. A layer may extend throughout an underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a homogeneous or non-homogeneous region of a continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between a top and bottom surface of a continuous structure, or between any pair of horizontal surfaces at the top and bottom surfaces of a continuous structure. A layer may extend along horizontal, vertical, and / or inclined surfaces. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductors, contact sublayers (forming interconnect lines and / or via contacts), and one or more dielectric sublayers.

[0032] In embodiments of the present invention, the terms "first", "second", etc. are used to distinguish between similar objects and are not necessarily used to describe a particular order or sequence.

[0033] The semiconductor structure in the embodiment of the present invention is used in a subsequent process to form at least a part of a final device structure, where the final device may include a memory, including but not limited to a DRAM, as will be described below as an example.

[0034] However, it should be understood that the description of the DRAM in the following embodiment is only used to explain the present invention, and does not limit the scope of the present invention.

[0035] As DRAM technology evolves, the size of memory cells becomes smaller and smaller, and the array architecture becomes 2 From 6F 2 4F further 2Furthermore, based on the requirements for ion and leakage current of DRAM, the memory architecture changes from Planar Array Transistor to Recess Gate Array Transistor, from Recess Gate Array Transistor to Buried Channel Array Transistor, from Buried Channel Array Transistor to Vertical Channel Array Transistor.

[0036] In some embodiments of the present invention, whether it is a planar array transistor or a vertical channel array transistor, the DRAM is composed of multiple memory cell structures, each of which is mainly composed of one transistor and a memory cell (capacitor) controlled by the one transistor, that is, the DRAM includes one transistor (T) and one capacitor (C) (1T1C). Its main working principle is that the amount of charge stored in the capacitor represents a binary bit, which is either 1 or 0.

[0037] FIG. 1a is a schematic diagram of a control circuit using a 1T1C architecture provided by an embodiment of the present invention, and FIG. 1b is a structural schematic diagram of a DRAM memory array formed with transistors using a 1T1C structure provided by an embodiment of the present invention. As shown in FIG. 1a and FIG. 1b, the drain of the transistor T is electrically connected to a bit line (BL), the source region of the transistor T is electrically connected to one of the electrode plates of the capacitor C, and the other electrode plate of the capacitor C can be connected to a reference voltage, which can be a ground voltage or other voltage. The gate of the transistor T is connected to a word line (WL). The transistor T is controlled to be on or off by applying a voltage through the word line WL, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is in an on state.

[0038] However, in order to achieve miniaturization of memories, the size of DRAM is constantly decreasing, and the size of capacitors is also decreasing, making the process of forming the capacitors more difficult, and as a result, the formed capacitors have leakage problems during use.

[0039] Based on this, in order to solve one or more of the above problems, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, which can increase the height of a capacitor to increase the storage capacity of a memory, and at the same time, reduce the process difficulty. Figure 2 is a flow chart of the method for manufacturing a semiconductor structure provided by an embodiment of the present invention. As shown in Figure 2, the method for manufacturing a semiconductor structure provided by an embodiment of the present invention includes the following steps:

[0040] In S100, a plurality of semiconductor pillars are formed on a substrate in an array along a first direction and a second direction, each of the semiconductor pillars includes a first portion and a second portion located on the first portion, a maximum radial width of the first portion is smaller than a minimum radial width of the second portion, the first direction and the second direction are both parallel to a surface of the substrate, and the first direction and the second direction intersect.

[0041] In S200, a support layer is formed on the top of the semiconductor pillar, the support layer covering a sidewall of an upper portion of the second portion.

[0042] In S300, the semiconductor pillar is oxidized such that the first portion is fully oxidized to an oxide pillar and an exposed surface of the second portion is oxidized to an oxide layer.

[0043] In S400, a first insulating material is filled into gaps between the oxide pillars to form a first insulating layer on the surface of the substrate.

[0044] In S500, the oxide layer is removed to obtain a first sub-active pillar.

[0045] In S600, a memory structure is formed on at least a sidewall of the first sub-active pillar.

[0046] It should be understood that the steps shown in FIG. 2 are not exclusive, and other steps may be performed before, after, or between any steps of the operations shown. The steps shown in FIG. 2 may be reordered according to actual needs. FIG. 3a-3q are cross-sectional schematic diagrams of a manufacturing process of a semiconductor structure provided by an embodiment of the present invention. Hereinafter, the manufacturing method of a semiconductor structure provided by an embodiment of the present invention will be described in detail with reference to FIG. 2 and FIG. 3a-3q.

[0047] In step S100, with reference to Figures 3a, 3b, 3c and 3d, a plurality of semiconductor pillars are formed.

[0048] The semiconductor pillars are located on a substrate and are arranged in an array along a first direction and a second direction.

[0049] In some embodiments, forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction on a substrate includes: Providing a semiconductor base; forming a plurality of first trenches arranged at intervals along a first direction in the base and a plurality of second trenches arranged at intervals along a second direction; and enlarging a bottom of each of the first trench and / or the second trench to form the plurality of semiconductor pillars.

[0050] Here, as shown in FIG. 3a, the material of the semiconductor base 300 can include silicon (Si), germanium (Ge), silicon germanium (SiGe), and so on.

[0051] 3a, a first etch is performed on a surface of the semiconductor base 300 to form a plurality of spaced apart first trenches 301 in the semiconductor base along a first direction, where each of the first trenches 301 extends along a second direction.

[0052] It should be noted that the first trench 301 is located within the semiconductor base, ie, the depth of the first trench 301 along the third direction is less than the thickness of the semiconductor base 300 along the third direction.

[0053] The first direction is parallel to the surface of the semiconductor base 300, and the second direction intersects the first direction and is parallel to the surface of the semiconductor base 300. The third direction is perpendicular to the surface of the semiconductor base 300, and the third direction here may also be understood as the extension direction of the semiconductor base 300.

[0054] That is, the first direction and the second direction intersect, that is, the angle between the first direction and the second direction is an arbitrary angle between 0 and 90 degrees, and both the first direction and the second direction are perpendicular to the third direction.

[0055] In order to clearly explain the present invention, the following embodiments will be described with an example in which the first direction and the second direction are perpendicular to each other. Exemplarily, the first direction is the X-axis direction shown in Fig. 3a, the second direction is the Y-axis direction shown in Fig. 3a, and the third direction is the Z-axis direction shown in Fig. 3a. However, it should be understood that the explanation of the directions in the following embodiments is for explaining the present invention and is not intended to limit the scope of the present invention.

[0056] In some embodiments, the first trench 301 includes, but is not limited to, a Shallow Trench Isolation (STI) structure.

[0057] The first etching process includes, but is not limited to, a dry plasma etching process.

[0058] Referring to FIG. 3b, a first insulating material 302 is formed in the first trench 301, where an upper surface of the first insulating material 302 is substantially flush with an upper surface of the semiconductor base 300, where the first insulating material 302 is used as a support.

[0059] In some embodiments, the first insulating material 302 may be made of, but is not limited to, silicon oxide (SiO2).

[0060] Methods for forming the first insulating material 302 include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and the like.

[0061] 3c, a second etching is performed on the semiconductor base 300 on which the first insulating material 302 is formed to form a plurality of second trenches 303 in the semiconductor base 300. Here, the plurality of second trenches 303 are arranged at intervals along a second direction, and each of the second trenches 303 extends along a first direction. That is, the first trenches 301 and the second trenches 303 intersect with each other.

[0062] Exemplarily, when the first direction is perpendicular to the second direction, the first trench 301 and the second trench 303 are perpendicular to each other.

[0063] Here, the second trench 303 is located in the semiconductor base 300. That is, the depth of the second trench 303 in the third direction is smaller than the thickness of the semiconductor base 300 in the third direction.

[0064] Exemplarily, the second trenches 303 are arranged at intervals along the Y-axis direction, and each of the second trenches 303 extends along the X-axis direction, and the depth of each of the second trenches 303 along the Z-axis direction is smaller than the thickness of the semiconductor layer along the Z-axis direction.

[0065] Here, the second etching process includes, but is not limited to, a dry plasma etching process.

[0066] In some embodiments, the second trench 303 includes, but is not limited to, a shallow trench isolation (STI) structure.

[0067] In some embodiments, the depth of the first trench 301 along the third direction may be the same as or different from the depth of the second trench 303 along the third direction.

[0068] Preferably, the depth of the first trench 301 along the third direction is the same as the depth of the second trench 303 along the third direction. In this way, the adjustment of process parameters in the manufacturing process can be reduced, and the process difficulty can be reduced.

[0069] Here, the first trench 301 and the second trench 303 divide the semiconductor base into a plurality of cubic pillars arranged in an array along a first direction and a second direction, and a substrate 304 is formed below the plurality of cubic pillars.

[0070] In another embodiment, a lattice-shaped mask layer may be formed on the surface of the semiconductor base, and the semiconductor base may be etched using the lattice-shaped mask layer as a mask to form a plurality of cubic pillars arranged in an array along a first direction and a second direction in the semiconductor base.

[0071] 3c, the bottoms of the first trench 301 and / or the second trench 303 are enlarged by etching the bottom of the first trench 301 along a first direction and / or etching the bottom of the second trench 303 along a second direction, so that the diameter of the bottom of the first trench 301 and / or the second trench 303 along the first direction becomes larger than the diameter of the top of the corresponding trench along the first direction; and / or This can be understood as meaning that the radial width of the bottom of the first trench 301 and / or the second trench 303 in the second direction is greater than the radial width of the top of the corresponding trench in the second direction.

[0072] The etching process used here may include a wet etching process, a dry etching process, and the like.

[0073] For example, in the wet etching process, an etchant is passed through the bottom of the first trench 301 and / or the second trench 303, and the anisotropic etching of the etchant increases the diameter width of the bottom of the first trench 301 and / or the second trench 303 in the X-axis direction and / or increases the diameter width of the bottom of the first trench 301 and / or the second trench 303 in the Y-axis direction.

[0074] For example, the dry etching process may be performed by controlling plasma to perform lateral etching, thereby forming a trench structure with an enlarged diameter at the bottom of the first trench 301 and / or the second trench 303.

[0075] In an embodiment of the present invention, referring to FIG. 3c, after enlarging the bottom of each of the first trench 301 and / or the second trench 303, an etching process is performed to etch the bottom regions of a plurality of cubic pillars located on the substrate, thereby reducing the size of the bottom regions of the cubic pillars, thereby forming the semiconductor pillars 305.

[0076] That is, the semiconductor pillar 305 includes a first portion 3051 (see the drawing in the dashed frame in FIG. 3c ) and a second portion 3052 located on the first portion 3051. Here, the first portion 3051 of the semiconductor pillar is located between the second portion 3052 of the semiconductor pillar and the substrate 304.

[0077] In some embodiments, a maximum radial width of the first portion along the first direction is smaller than a minimum radial width of the second portion along the first direction; and / or The maximum radial width of the first portion along the second direction is smaller than the minimum radial width of the second portion along the second direction.

[0078] For example, when only the first trench 301 is enlarged, the maximum diameter of the first portion 3051 of the semiconductor pillar along the X-axis direction is smaller than the minimum diameter of the second portion 3052 of the semiconductor pillar along the X-axis direction.

[0079] For example, when only the second trench 303 is enlarged, the maximum diameter of the first portion 3051 of the semiconductor pillar along the Y-axis direction is smaller than the minimum diameter of the second portion 3052 of the semiconductor pillar along the Y-axis direction.

[0080] For example, when both first trench 301 and second trench 303 are enlarged, the maximum diameter width of first portion 3051 of the semiconductor pillar along the X-axis direction is smaller than the minimum diameter width of second portion 3052 of the semiconductor pillar along the X-axis direction, and the maximum diameter width of first portion 3051 of the semiconductor pillar along the Y-axis direction is smaller than the minimum diameter width of second portion 3052 of the semiconductor pillar along the Y-axis direction.

[0081] Preferably, both the first trench 301 and the second trench 303 are enlarged so that the size of the first portion of the semiconductor pillar is reduced.

[0082] Exemplarily, the maximum radial width of the first portion can be understood as the radial width of the contact location of the first portion 3051 of the semiconductor pillar and the second portion 3052 of the semiconductor pillar in Fig. 3c, and the minimum radial width of the second portion can be understood as the area having the minimum dimension of the second portion 3052 of the semiconductor pillar. Referring to Fig. 3c, the dimensions of the top and bottom of the second portion 3052 of the semiconductor pillar are the same, i.e., the minimum radial width and the maximum radial width of the second portion of the semiconductor pillar are the same.

[0083] 3d, a first insulating material 302 is formed in the second trench 303. The top surface of the first insulating material 302 is substantially flush with the top surface of the semiconductor pillar 305. The first insulating material is used as a support.

[0084] Exemplarily, the material constituting the first insulating material 302 includes, but is not limited to, silicon oxide.

[0085] Here, the method for forming the first insulating material 302 includes, but is not limited to, PVD, CVD, and the like.

[0086] It should be noted that the order of forming the first trench 301 and the second trench 303 and filling the first trench 301 and the second trench 303 with the first insulating material 302 can be selected according to practical circumstances. In another specific embodiment, after forming the first trench 301 and the second trench 303, the first trench 301 and the second trench 303 can be filled with the first insulating material 302, where the first insulating material is substantially flush with the top surfaces of the plurality of semiconductor pillars.

[0087] In step S200, with reference to Figures 3e to 3k, a support layer is formed.

[0088] In some embodiments, forming the support layer includes removing a portion of the first insulating material by etching to expose a top of the semiconductor pillar to obtain a second sub-active pillar; depositing a second insulating material, the second insulating material covering a surface of the second sub-active pillar to form a second insulating layer on the top of the semiconductor pillar.

[0089] 3e, a portion of the first insulating material 302 located in the first trench 301 and the second trench 303 is etched to form a first gap 306, exposing the top of the semiconductor pillar, i.e., the second sub-active pillar 3052b, which is the end of a second portion of the semiconductor pillar away from the first portion 3051.

[0090] 3f, a second insulating material is formed in the first gap by a deposition process, and then the second insulating material is planarized to form a second insulating layer 308 on the top of the semiconductor pillar. The second insulating layer 308 covers the surface of the second sub-active pillar, and the top surface of the second insulating layer 308 is higher than the top surface of the semiconductor pillar.

[0091] Here, the deposition process includes, but is not limited to, PVD, CVD, and the like.

[0092] The planarization process includes, but is not limited to, chemical mechanical polishing (CMP).

[0093] The second insulating layer 308 may be made of, but is not limited to, nitrides, carbides, and the like.

[0094] In some embodiments, referring to FIG. 3g, removing a portion of the second insulating layer 308 along the second direction to form a first shallow trench 309, a bottom surface of the first shallow trench 309 is flush with a bottom surface of the second sub-active pillar, and filling the first shallow trench 309 with the first insulating material 302; removing a portion of the second insulating layer 308 along the first direction to form a second shallow trench 310, a bottom surface of the second shallow trench 310 being flush with an upper surface of the second sub-active pillar, the second shallow trench 310 being located directly above the second sub-active pillar and exposing an upper surface of the second sub-active pillar; filling the second shallow trench 310 with the second insulating material; The first insulating material 302 filled between the semiconductor pillars is entirely removed, and a lattice-shaped support layer 311 is formed on the top of the semiconductor pillars.

[0095] 3g, an etching process is performed to etch the second insulating layer 308 to remove a portion of the second insulating layer 308, to expose a portion of the top of the first insulating material 302, and to form a plurality of first shallow trenches 309 on the top of the semiconductor pillar. The plurality of first shallow trenches 309 are spaced apart along the X-axis direction, and each first shallow trench 309 extends along the Y-axis direction.

[0096] Here, the bottom surface of the first shallow trench 309 is substantially flush with the bottom surface of the second sub active pillar 3052b.

[0097] 3h, first shallow trench 309 is filled with first insulating material 302 such that a top surface of first insulating material 302 located in first shallow trench 309 is higher than a top surface of the semiconductor pillar, where the top surface of first insulating material 302 located in first shallow trench 309 is substantially flush with a top surface of remaining second insulating layer 308.

[0098] 3i, an etching process is performed to etch the second insulating layer 308 and the first insulating material 302 located in the first shallow trench 309, thereby removing a part of the second insulating layer 308 and a part of the first insulating material 302, exposing a part of the upper surface of the semiconductor pillar, and forming a plurality of second shallow trenches 310 on the upper surface of the semiconductor pillar. The plurality of second shallow trenches 310 are arranged at intervals along the Y-axis direction, and each second shallow trench groove 310 extends along the X-axis direction.

[0099] Here, the bottom surface of the second shallow trench 310 is substantially flush with the top surface 3052b of the second sub active pillar, and the second shallow trench 310 is located directly above the second sub active pillar and exposes the top surface of the second sub active pillar.

[0100] "Substantially flush" in relation to the embodiments of the present invention may be understood as being roughly flush. It should be understood that misalignment or non-leveling due to process errors in the memory manufacturing process is also included in the scope of "substantially flush."

[0101] 3j, the second shallow trench 310 is filled with the second insulating material, where a top surface of the second insulating material located in the second shallow trench 310 is substantially flush with a top surface of the second insulating layer 308.

[0102] Referring to FIG. 3k, the first insulating material 302 between the semiconductor pillars is removed, and a lattice-shaped support layer 311 is formed on top of the semiconductor pillars.

[0103] Here, the constituent material of the support layer 311 includes, but is not limited to, nitride and carbon.

[0104] Preferably, the material of the support layer 311 includes silicon nitride.

[0105] In step S300, referring to FIG. 3l and FIG. 3m, the semiconductor pillars 305 are oxidized.

[0106] In some embodiments, referring to FIG. 3l, after forming the support layer 311, the semiconductor pillar is oxidized such that the first portion of the semiconductor pillar is entirely oxidized to an oxide pillar 312 and the exposed surface of the second portion of the semiconductor pillar is oxidized to an oxide layer 313.

[0107] Referring to FIG. 3m, next, a first insulating material 302 is filled between the semiconductor pillars, and a part of the first insulating material 302 and the oxide layer 313 are removed by etching, and the remaining first insulating material 302 and the oxide pillars 312 form a first insulating layer 314 located on the surface of the substrate.

[0108] Exemplarily, referring to FIG. 3l, by oxidizing the semiconductor pillar in an oxidation process, the first portion 3051 of the semiconductor pillar is entirely oxidized to become an oxide pillar 312, the exposed surface of the second portion of the semiconductor pillar is oxidized to become an oxide layer 313, and at the same time, the surface of the substrate 304 is oxidized to form an oxide layer.

[0109] Here, the material of the oxide pillars 312 and the oxide layer 313 is the same.

[0110] Exemplarily, the constituent material of the oxide pillars 312 and the oxide layer 313 includes, but is not limited to, silicon oxide.

[0111] In some embodiments, the material of the oxide pillars 312 is the same as or different from the material of the first insulating layer 314 .

[0112] Illustratively, the material of the first insulating layer 314 includes, but is not limited to, silicon oxide.

[0113] It should be understood that in the above-mentioned embodiment, after the first trench 301 and / or the second trench 303 are enlarged, the size of the first portion of the semiconductor pillar is small and it is easy to be completely oxidized, and further, when the first portion of the semiconductor pillar is completely oxidized, only the surface of the second portion of the semiconductor pillar is oxidized.

[0114] It should also be appreciated that because the second sub-active pillar in the second portion of the semiconductor pillar is surrounded by the support layer 311, when the first and second portions of the semiconductor pillar are oxidized, the support layer 311 can protect the portion covered by the support layer 311 at the top of the semiconductor pillar (i.e., the second sub-active pillar) from being oxidized or damaged.

[0115] 3m and 3n, in step S400, a first insulating layer 314 is formed, and in step S500, a first sub active pillar is obtained.

[0116] Referring to FIG. 3 m, a first insulating material 302 is filled between the semiconductor pillars on which the oxide layer 313 is formed, so that the first insulating material 302 is substantially flush with the upper surface of the support layer 311 .

[0117] Here, the method of filling the first insulating material 302 includes, but is not limited to, processes such as PVD, CVD, etc.

[0118] Referring to FIG. 3n, an etching process is performed to remove a portion of the first insulating material 302 located between the semiconductor pillars and the oxide layer 313 located on the surface of the second portion of the semiconductor pillar to obtain a first sub-active pillar 3052a.

[0119] It should be understood that the first sub-active pillar 3052a and the second sub-active pillar 3052b form a second portion 3052 of the semiconductor pillar, and the second sub-active pillar 3052b is located on the first sub-active pillar 3052a.

[0120] The remaining first insulating material 302 and the oxide pillars 312 form a first insulating layer 314 between the first sub-active pillars 3052a and the substrate 304.

[0121] The etching process includes, but is not limited to, a dry plasma etching process.

[0122] In some embodiments, an orthogonal projection of the first sub-active pillar 3052a on the substrate lies within an orthogonal projection of the second sub-active pillar 3052b on the substrate.

[0123] In step S600, referring to Figures 3o, 3p and 3q, a memory structure 315 is formed.

[0124] Here, the memory structure 315 is used to store data. Exemplarily, the memory structure 315 includes a capacitor.

[0125] In some embodiments, forming a memory structure on the sidewall of at least the first sub-active pillar 3052a includes: forming a first conductive layer 3151 covering a sidewall of the first sub active pillar 3052a; forming a dielectric layer 3152 covering a surface of the first conductive layer and an upper surface of the first insulating layer 314; forming a second conductive layer 3153 in the dielectric layer 3152.

[0126] Here, the first conductive layer is used as a lower electrode of the capacitor, the dielectric layer is used as a dielectric of the capacitor, and the second conductive layer is used as an upper electrode of the capacitor.

[0127] In some specific embodiments, the first conductive layer 3151 may be made of, but is not limited to, ruthenium (Ru), ruthenium oxide (RuO), titanium nitride (TiN), etc.

[0128] In the embodiment of the present invention, the first conductive layer may be formed on the sidewalls of the first sub active pillars by a selective deposition process, or may be formed by another deposition process.

[0129] The selective deposition process means selectively depositing a first conductive layer on the sidewalls of the first sub active pillars, and the other deposition process includes, but is not limited to, PVD, CVD, and ALD (Atomic Layer Deposition).

[0130] In some specific embodiments, forming a first conductive layer covering the sidewall of the first sub active pillar 3052a includes: The method includes forming a first conductive layer covering the sidewalls of the first sub-active pillars 3052a by a selective deposition process.

[0131] 3o, it should be understood that in the embodiment of the present invention, the process of forming the first conductive layer by a selective deposition process can be carried out such that the material forming the first conductive layer is formed only on the sidewalls of the first sub-active pillars 3052a or on other selected materials, without being formed on the top surface of the first insulating layer 314. In this way, on the one hand, it is possible to avoid forming the first conductive layer in the gaps having a higher aspect ratio, thereby reducing the process difficulty and improving the process window, and on the other hand, it is possible to avoid the problem of voids occurring when forming the first conductive layer by other processes, thus improving the reliability of the semiconductor structure.

[0132] Referring to FIG. 3o, a dielectric layer 3152 is formed on the surface of the first conductive layer and the dielectric layer on the top surface of the first insulating layer 314 by a deposition process.

[0133] The dielectric layer may be made of a high-k material, which generally refers to a material having a dielectric constant greater than 3.9, and is usually much higher than this value. In some embodiments, the dielectric layer may be made of, but is not limited to, aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), strontium titanate (SrTiO3), and the like.

[0134] Referring to FIG. 3o, a second conductive layer 3153 is formed on the dielectric layer.

[0135] In some specific embodiments, the material of the second conductive layer includes, but is not limited to, ruthenium, ruthenium oxide, and titanium nitride.

[0136] Here, the method for forming the second conductive layer includes, but is not limited to, processes such as PVD and CVD.

[0137] In the above embodiment, the method of forming the first conductive layer and the second conductive layer can be understood as forming a conductive layer on conductive layer (CoC) by a selective deposition process, which includes, but is not limited to, an ALD process.

[0138] In some embodiments, the method further comprises: removing the support layer 311 to expose the second sub active pillars 3052b; forming a gate structure covering at least one side of the second sub active pillar; The method further includes forming a source and a drain on opposite ends of the second sub active pillar, respectively.

[0139] Exemplarily, referring to FIG. 3p and FIG. 3q, the support layer 311 is removed by an etching process to expose the second sub active pillars 3052b.

[0140] It should be understood that in some other specific embodiments, when the dielectric layer is also formed on the bottom surface of the support layer 311, removing the support layer 311 further includes removing the dielectric layer located on the bottom surface of the support layer 311.

[0141] Here, the bottom of the support layer 311 is parallel to the bottom surface of the second sub active pillar 3052b.

[0142] The etching process includes, but is not limited to, a dry plasma etching process.

[0143] Next, referring to FIG. 3q, a process forms a gate structure (not shown in FIG. 3q) on at least one side of the second sub active pillar.

[0144] Here, the shape of the gate varies depending on the type of transistor. For example, in a pillar-type gate transistor, the gate is formed in a pillar shape on one side of the trench region, in a half-gate transistor, the gate is formed to surround half of the trench region, and in a gate all around (GAA) type gate transistor, the gate is formed to completely surround the trench region.

[0145] The transistor type in the embodiments of the present invention may include, but is not limited to, the various types mentioned above. Preferably, the transistor type is an all-around gate transistor.

[0146] Here, the gate structure includes a gate (G) and a gate oxide layer, where it is understood that the gate oxide layer is located between the gate and the trench region and is used to electrically isolate the trench region from the gate and reduce hot carrier effects in the transistor.

[0147] Here, the gate material may include metal, polysilicon (Poly), etc. The material of the gate oxide layer may include, but is not limited to, silicon oxide.

[0148] In some embodiments, the method of forming the gate includes, but is not limited to, PVD, CVD, ALD, etc. The method of forming the gate oxide layer includes, but is not limited to, in-situ oxidation.

[0149] A source and a drain are formed on opposite ends of the second sub active pillar (not shown in FIG. 3q).

[0150] In some specific embodiments, the method of forming the source and drain includes, but is not limited to, a doping process and a diffusion process.

[0151] It should be understood that the source and drain located at opposite ends of the second sub-active pillar may be interchanged, and in practice, may be selected and set according to actual needs.

[0152] It should be understood that the memory in the above embodiment is a transistor on capacitor (TOC) structure, which further includes a plurality of bit lines located on the transistors and electrically contacting the tops of the second sub-active pillars.

[0153] Thus, in some embodiments, the method further comprises forming a bit line BL over the transistor.

[0154] It should be understood that the bit line BL is used to perform a read or write operation on the transistor when the transistor is on.

[0155] Here, by providing the bit line BL above the transistor and using the bit line BL as a metal bit line (Metal BL), the resistance is reduced, the process difficulty is lowered, and matching with the memory circuit design plan is improved.

[0156] Based on this, in an embodiment of the present invention, a plurality of semiconductor pillars are formed on a substrate, and each of the semiconductor pillars includes a first portion and a second portion located on the first portion, so that the maximum diameter width of the first portion is smaller than the minimum diameter width of the second portion. Next, the first portions of the plurality of semiconductor pillars are all oxidized to oxide pillars by an oxidation process, and a first insulating material is filled into the gaps between the plurality of oxide pillars. Finally, a corresponding active pillar is formed on the upper surface of each oxide pillar, so that the active pillars are insulated from the substrate. Furthermore, a memory structure formed on a part of the sidewall of the active pillar is insulated from the substrate, thereby improving the leakage problem of the memory structure and further improving the reliability of the memory.

[0157] According to another aspect of the present invention, an embodiment of the present invention further provides a semiconductor structure, the semiconductor structure including a substrate, a plurality of oxide pillars, a plurality of active pillars, a first insulating layer, and a memory structure.

[0158] the plurality of oxide pillars are located on the substrate and are arranged in an array along a first direction and a second direction, the first direction and the second direction are both parallel to a surface of the substrate, and the first direction and the second direction intersect; the first insulating layer is located in gaps between the oxide pillars; Each of the active pillars is located on the upper surface of a corresponding one of the oxide pillars, The memory structure covers at least a portion of the sidewall of the active pillar.

[0159] In some embodiments, the material of the oxide pillars is the same as or different from the material of the first insulating layer.

[0160] In some embodiments, each of the active pillars includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar, and an orthogonal projection of the first sub-active pillar on the substrate is located within an orthogonal projection of the second sub-active pillar on the substrate.

[0161] In some embodiments, the memory structure comprises: a first conductive layer covering a sidewall of the first sub active pillar; a dielectric layer covering a surface of the first conductive layer and an upper surface of the first insulating layer; and a second conductive layer located within the dielectric layer.

[0162] In some embodiments, the semiconductor structure further includes a plurality of transistors, a channel structure of each of the transistors being located within the second sub-active pillar, the channel structure extending along a direction perpendicular to the surface of the substrate.

[0163] In some embodiments, the transistor comprises: a gate structure provided around the second sub active pillar; The second sub active pillar includes a source and a drain provided at two opposite ends thereof, respectively.

[0164] In some embodiments, the semiconductor structure further includes a plurality of bit lines located over the transistors and in electrical contact with the tops of the second sub-active pillars.

[0165] According to yet another aspect of the present invention, an embodiment of the present invention further provides a memory, the memory comprising one or more semiconductor structures according to any one of the above embodiments of the present invention.

[0166] Based on this, in an embodiment of the present invention, by providing a corresponding oxide pillar between each active pillar and the substrate, it is possible to isolate a memory structure (e.g., a capacitor) formed on a portion of the sidewall of the active pillar, and further reduce leakage problems during use of the memory structure (e.g., a capacitor).

[0167] The features disclosed in the several method or apparatus embodiments provided by the present invention may be combined in any non-conflicting manner to obtain new method or apparatus embodiments.

[0168] The above content is merely a specific embodiment of the present invention, and the protection scope of the present invention is not limited thereto. Any modifications or replacements that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. [Industrial Applicability]

[0169] In an embodiment of the present invention, a plurality of semiconductor pillars are formed on a substrate, each of the semiconductor pillars including a first portion and a second portion located on the first portion, such that the maximum diameter width of the first portion is smaller than the minimum diameter width of the second portion; then, all of the first portions of the plurality of semiconductor pillars are oxidized to oxide pillars by an oxidation process, and a first insulating material is filled into the gaps between the plurality of oxide pillars; finally, a corresponding active pillar is formed on the upper surface of each oxide pillar, thereby insulating the active pillars from the substrate; and further, a memory structure formed on a part of a sidewall of the active pillar is insulated from the substrate, thereby improving the leakage problem of the memory structure and further improving the reliability of the memory. [Explanation of symbols]

[0170] 300 Semiconductor-based 301 Trench No. 1 302 First insulating material 303 Second Trench 304 Substrate 305 Semiconductor Pillar 3051 First part of semiconductor pillar 3052 Second part of semiconductor pillar 3052a 1st Sub Active Pillar 3052b Second sub-active column 306 First Gap 308 Second insulating layer 309 First Shallow Trench 310 Second Shallow Trench 311 Support layer 312 Oxidation column 313 Oxide layer 314 First insulating layer 315 Memory Structure 3151 First conductive layer 3152 Dielectric layer 3153Second conductive layer.

Claims

1. 1. A semiconductor structure comprising: a substrate, a plurality of oxide pillars, a plurality of active pillars, a first insulating layer, and a memory structure; the plurality of oxide pillars are located on the substrate and are arranged in an array along a first direction and a second direction, the first direction and the second direction are both parallel to a surface of the substrate, and the first direction and the second direction intersect; the first insulating layer is located in gaps between the oxide pillars; Each of the active pillars is located on the upper surface of a corresponding one of the oxide pillars, the memory structure covers at least a portion of a sidewall of the active pillar; Each of the active pillars includes a first sub-active pillar and a second sub-active pillar located on the first sub-active pillar, and an orthogonal projection of the first sub-active pillar on the substrate is located within an orthogonal projection of the second sub-active pillar on the substrate; The memory structure comprises: a first conductive layer covering a sidewall of the first sub active pillar; a dielectric layer covering a surface of the first conductive layer and an upper surface of the first insulating layer; a second conductive layer located within the dielectric layer.

2. The material of the oxide pillars is the same as or different from the material of the first insulating layer. The semiconductor structure of claim 1 .

3. The semiconductor structure further includes a plurality of transistors, each of which has a channel structure located within the second sub-active pillar, and the extension direction of the channel structure is perpendicular to the surface of the substrate. The semiconductor structure of claim 1 .

4. The transistor is a gate structure provided around the second sub active pillar; The second sub active pillar includes a source and a drain provided at two opposite ends of the second sub active pillar. The semiconductor structure of claim 3.

5. The semiconductor structure further includes a plurality of bit lines located over the transistors and electrically contacting the tops of the second sub-active pillars. The semiconductor structure of claim 4.

6. A memory comprising a semiconductor structure according to any one of claims 1 to 5.

7. 1. A method for manufacturing a semiconductor structure, comprising the steps of: forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction on a substrate, each of the semiconductor pillars including a first portion and a second portion located on the first portion, a maximum radial width of the first portion being smaller than a minimum radial width of the second portion, the first direction and the second direction both being parallel to a surface of the substrate, and the first direction and the second direction intersecting with each other; forming a support layer on the top of the semiconductor pillar, the support layer covering a sidewall of an upper portion of the second portion; oxidizing the semiconductor pillar such that the first portion is fully oxidized to an oxide pillar and an exposed surface of the second portion is oxidized to an oxide layer; filling gaps between the oxide pillars with a first insulating material to form a first insulating layer on a surface of the substrate; removing the oxide layer to obtain a first sub-active pillar; and forming a memory structure on a sidewall of at least the first sub-active pillar.

8. Forming a plurality of semiconductor pillars arranged in an array along a first direction and a second direction on the substrate includes: Providing a semiconductor base; forming a plurality of first trenches in the semiconductor base spaced apart along a first direction and a plurality of second trenches in the semiconductor base spaced apart along a second direction; and expanding a bottom of each of the first trench and / or the second trench to form the plurality of semiconductor pillars. A method for manufacturing a semiconductor structure according to claim 7.

9. Forming the support layer comprises: filling spaces between the semiconductor pillars with the first insulating material, and removing a portion of the first insulating material by etching to expose tops of the semiconductor pillars to obtain second sub-active pillars; depositing a second insulating material, the second insulating material covering a surface of the second sub-active pillar to form a second insulating layer on the top of the semiconductor pillar. A method for manufacturing a semiconductor structure according to claim 7.

10. removing a portion of the second insulating layer along the second direction to form a first shallow trench, a bottom surface of the first shallow trench being flush with a bottom surface of the second sub active pillar, and filling the first shallow trench with the first insulating material; removing a portion of the second insulating layer along the first direction to form a second shallow trench, a bottom surface of the second shallow trench being flush with an upper surface of the second sub active pillar, and filling the second shallow trench with the second insulating material; removing all of the first insulating material filled between the semiconductor pillars and forming a lattice-shaped support layer on the tops of the semiconductor pillars. A method for manufacturing a semiconductor structure according to claim 9.

11. oxidizing the semiconductor pillar after forming the support layer, such that the first portion of the semiconductor pillar is completely oxidized to become an oxide pillar and an exposed surface of the second portion of the semiconductor pillar is oxidized to become an oxide layer; filling the spaces between the semiconductor pillars with a first insulating material again, and removing a portion of the first insulating material and the oxide layer by etching, so that the remaining first insulating material and the oxide pillars form a first insulating layer located on the surface of the substrate. The method of claim 10 .

12. forming a memory structure on a sidewall of at least the first sub active pillar; forming a first conductive layer covering a sidewall of the first sub active pillar; forming a dielectric layer covering a surface of the first conductive layer and an upper surface of the first insulating layer; forming a second conductive layer in the dielectric layer. A method for manufacturing a semiconductor structure according to claim 9.

13. forming a first conductive layer covering the sidewalls of the first sub active pillars, forming a first conductive layer covering the sidewalls of the first sub-active pillars by a selective deposition process. The method of claim 12 .

14. The method for manufacturing the semiconductor structure includes: removing the support layer to expose the second sub-active pillars; forming a gate structure covering at least one side of the second sub active pillar; forming a source and a drain on opposite ends of the second sub active pillar, respectively. The method of claim 13 .

15. a maximum radial width of the first portion along the first direction is smaller than a minimum radial width of the second portion along the first direction; and / or The maximum radial width of the first portion along the second direction is smaller than the minimum radial width of the second portion along the second direction. The method of claim 8 .

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