Ferroelectric memory device having a blocking layer - Patents.com

Abstract

To provide an integrated circuit which improves performance of a ferroelectric layer and a memory cell.SOLUTION: A memory cell includes a blocking layer 104 for blocking diffusion of metal from an electrode of the memory cell 102 to a ferroelectric layer 108 of the memory cell. The blocking layer 104 and the ferroelectric layer 108 are located between a top electrode 106 of the memory cell 102 and a bottom electrode 110 of the memory cell, where both the top electrode and the bottom electrode include metal. Further, the blocking layer is located between the ferroelectric layer and an electrode corresponding to one of the top electrode and the bottom electrode. In some embodiments, the metal of the one of the top electrode and the bottom electrode has the lowest electronegativity among the metals of the top electrode and the bottom electrode, and thus is the most reactive among the metals of the top electrode and the bottom electrode and is likely to diffuse.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] Many modern electronic devices are equipped with non-volatile memory, which is electronic memory that can retain data even without power. Promising candidates for the next generation of non-volatile memory include ferroelectric random access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal oxide semiconductor (CMOS) logic manufacturing processes. Summary of the Invention [Problem to be solved by the invention]

[0002] A FeRAM memory cell may include two electrodes and a ferroelectric layer between them. One or both of the two electrodes may include a metal with low electronegativity, which is more likely to diffuse from one or both of the two electrodes into the ferroelectric layer during annealing, and is more reactive and therefore more likely to diffuse during annealing. The metal diffusing from one or both of the two electrodes into the ferroelectric layer adversely affects the performance of the ferroelectric layer and the memory cell.

[0003] The present invention provides an integrated circuit (IC) chip including a memory cell, the memory cell including a first electrode and a second electrode, both including a metal, a ferroelectric layer between the first electrode and the second electrode, and a blocking layer between the ferroelectric layer and the first electrode. The blocking layer is configured to block a first metal of the first electrode from diffusing into the ferroelectric layer. The first metal of the first electrode is less electronegative than a second metal of the second electrode.

[0004] The present invention also provides an IC chip including a memory cell comprising a bottom electrode at a bottom of the memory cell, a top electrode at a top of the memory cell, a ferroelectric layer between the bottom electrode and the top electrode, and a diffusion barrier layer between the ferroelectric layer and a first electrode, the first electrode being one of the bottom electrode and the top electrode and comprising a metal having an electronegativity less than about 1.6.

[0005] The present invention also provides a method including forming a bottom electrode on a substrate, depositing a stacked blocking layer, a ferroelectric layer, and a top electrode layer on the substrate, patterning the top electrode layer to form a top electrode, and patterning the blocking layer and the ferroelectric layer to define individual blocking layer and ferroelectric layer segments in memory cells. After patterning the blocking layer and the ferroelectric layer, the bottom electrode and the top electrode and the blocking layer and ferroelectric layer segments form memory cells. The bottom electrode and the top electrode comprise a metal. The blocking layer is between the ferroelectric layer and the metal that is the least electronegative of the bottom electrode and the top electrode. Effect of the Invention

[0006] The blocking or diffusion barrier layer can minimize metal diffusion into the ferroelectric layer, including during annealing, to increase the ferroelectric phase of the ferroelectric layer. Preventing metal diffusion into the ferroelectric layer can improve the performance of the ferroelectric layer and memory cells. [Brief description of the drawings]

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings, in which it is emphasized that, in accordance with standard industry practice, various features are not drawn to scale, and in fact the dimensions of various features may be arbitrarily increased or decreased for clarity of illustration.

[0008] [Figure 1] 1A-1D illustrate cross-sectional views of several embodiments of a memory cell including a blocking layer. [Diagram 2] 2A-2C illustrate cross-sectional views of several alternative embodiments of the memory cell of FIG. [Diagram 3] 2A-2C illustrate various views of several alternative embodiments of the memory cell of FIG. 1, integrated into an interconnect structure of an integrated circuit (IC) chip. [Figure 4]3A and 3B show various views of several alternative embodiments of the memory cell of FIG. 3A, in which the width of the top electrode is reduced compared to the remainder of the memory cell. [Diagram 5] 4C and 4D show cross-sectional views of several alternative embodiments of the memory cell of FIGS. 4A and 4B. [Figure 6] 3A and 3B, in which components of the memory cell have a U-shaped profile. [Figure 7] 3A and 3B, depicting various views of several alternative embodiments of the memory cell of FIG. 3A and 3B, in which the top electrode surrounds the bottom electrode. [Figure 8] 3C show cross-sectional views of several alternative embodiments of the memory cell of FIGS. 3A and 3B, where a blocking layer is at the bottom electrode. [Figure 9] 9A-9C illustrate cross-sectional views of several alternative embodiments of the memory cell of FIG. 8. [Figure 10] 3A and 3B, depicting cross-sectional views of several alternative embodiments of the memory cell of FIGS. 3A and 3B, the memory cell having a blocking layer on the bottom electrode and a blocking layer on the top electrode. [Figure 11] 11A-11C show cross-sectional views of several alternative embodiments of the memory cell of FIG. [Figure 12] 3A and 3B. FIG. 3C shows cross-sectional views of several embodiments of an IC chip with memory cells integrated into individual one-transistor-one-capacitor (1T1C) cells. [Figure 13] 12C show cross-sectional views of several alternative embodiments of the IC chip of FIGS. 12A and 12B. [Figure 14] 12C show top view layout views of several embodiments of the IC chip of FIGS. 12A and 12B. [Figure 15] 1A-1D show cross-sectional views of several embodiments of IC chips with ferroelectric field effect transistors (FeFETs) including blocking layers. [Figure 16] 16A-16D show cross-sectional views of several alternative embodiments of the FeFET of FIG. [Figure 17]1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 18] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 19] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 20] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 21] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 22] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 23] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 24] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Diagram 25] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 26] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 27] 1A-1C illustrate a series of cross-sectional views of several embodiments of methods for forming an IC chip with memory cells integrated into individual 1T1C cells and including a blocking layer. [Figure 28]17-27 depict block diagrams of some embodiments of the methods of FIG. [Figure 29] 17-27 depict a series of cross-sectional views of several alternative embodiments of the method of FIGS. [Diagram 30] 17-27 depict a series of cross-sectional views of several alternative embodiments of the method of FIGS. [Diagram 31] 17-27 depict a series of cross-sectional views of several alternative embodiments of the method of FIGS. [Diagram 32] 17-27 depict a series of cross-sectional views of several alternative embodiments of the method of FIGS. [Diagram 33] 17-27 depict a series of cross-sectional views of several alternative embodiments of the method of FIGS. [Diagram 34] 17-27 depict a series of cross-sectional views of several alternative embodiments of the method of FIGS. [Diagram 35] 17-27 depict a series of cross-sectional views of several alternative embodiments of the method of FIGS. [Diagram 36] 17-27 depict a series of cross-sectional views of several alternative embodiments of the method of FIGS. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. In order to simplify the present invention, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above / on a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features without the first and second features being in direct contact. Furthermore, the present invention may repeat symbols and / or descriptions in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations described.

[0010] Additionally, spatially relative terms such as "below," "downward," "lower," "upward," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature illustrated in the figures for ease of description. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in another direction (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0011] An integrated circuit (IC) chip may include an interconnect structure and a memory cell within the interconnect structure. The memory cell includes a bottom electrode, a ferroelectric layer overlying and in direct contact with the bottom electrode, and a top electrode overlying and in direct contact with the ferroelectric layer. The interconnect structure includes a bottom electrode wire below the memory cell and a top electrode wire overlying the memory cell. Additionally, the interconnect structure includes vias extending from the bottom electrode wire and the top electrode wire to the bottom electrode and top electrode, respectively.

[0012] A challenge for the memory cell is that the top electrode may include a metal with low electronegativity and / or the bottom electrode may include a metal with low electronegativity. Such low electronegativity may be, for example, less than about 1.6 or some other suitable value. Metals with low electronegativity are more reactive and therefore have a higher tendency to diffuse during annealing. Thus, the metal of the top electrode and / or the metal of the bottom electrode may have a higher tendency to diffuse into the ferroelectric layer during annealing and increase the ferroelectric phase of the ferroelectric layer.

[0013] Metal diffusing from the top and / or bottom electrodes into the ferroelectric layer can adversely affect the performance of the ferroelectric layer and therefore the performance of the memory cell, such as by reducing the ferroelectric phase, reducing the remnant polarization (2Pr), reducing the polarization uniformity, increasing leakage current, reducing capacitance, reducing data retention, reducing breakdown voltage, or any combination of the above.

[0014] Various embodiments of the present invention are directed to a memory cell comprising a blocking layer configured to block diffusion of a metal from an electrode of the memory cell to a ferroelectric layer of the memory cell. More specifically, the blocking layer and the ferroelectric layer are between a top electrode of the memory cell and a bottom electrode of the memory cell, the top electrode and the bottom electrode comprising respective metals. Furthermore, the blocking layer is between the ferroelectric layer and one of the top electrode and the bottom electrode. In some embodiments, the metal of said one of the top electrode and the bottom electrode has the lowest electronegativity of the metals of the top electrode and the bottom electrode, and is therefore the most reactive and likely to diffuse between the metals of the top electrode and the bottom electrode.

[0015] The blocking layer can minimize metal diffusion into the ferroelectric layer, including during annealing, to increase the ferroelectric phase of the ferroelectric layer. Preventing metal diffusion into the ferroelectric layer can improve the performance of the ferroelectric layer, and therefore the performance of the memory cell. For example, the ferroelectric phase can be increased, remnant polarization (2Pr) can be increased, polarization uniformity can be increased, leakage current can be reduced, capacitance can be increased, data retention can be increased, breakdown voltage can be increased, or any combination of the above can result. Additionally, the memory cell is compatible with logic fabrication processes, allowing the memory device cells to be used in embedded memory applications.

[0016] 1, a cross-sectional view 100 of some embodiments of a memory cell 102 is provided in which a blocking layer 104 is configured to block diffusion of metal from a top electrode 106 to a ferroelectric layer 108. In some embodiments, the blocking layer 104 may additionally or alternatively be referred to as an interface layer, a mixed layer, a diffusion barrier layer, or the like, or any combination of the foregoing. The memory cell 102 may be or include, for example, a metal-ferroelectric-metal (MFM) cell, a ferroelectric capacitor, a ferroelectric tunnel junction (FTJ), or the like, or any combination of the foregoing.

[0017] The ferroelectric layer 108 is over the bottom electrode 110, the blocking layer 104 is over the ferroelectric layer 108, and the top electrode 106 is over the blocking layer 104. Additionally, the bottom electrode 110 and the top electrode 106 comprise individual metals, with the bottom electrode 110 and the top electrode 106 having high and low electronegativity, respectively. Note that the low electronegativity is indicated diagrammatically by the diagonal hashing overlaying the top electrode 106. Due to the low electronegativity, the metal of the top electrode 106 is highly reactive and therefore has a high tendency to diffuse into the ferroelectric layer 108. In contrast, due to the high electronegativity, the metal of the bottom electrode 110 is less reactive and therefore has a low tendency to diffuse into the ferroelectric layer 108.

[0018] In some embodiments, high electronegativity and low electronegativity are relative to one another. In some embodiments, high electronegativity is greater than about 1.6, about 2.0, or some other suitable value, and / or is an electronegativity between about 1.6 and 2.4, between about 1.6 and 2.0, between about 2.0 and 2.4, or some other suitable value. In some embodiments, low electronegativity is less than about 1.6, about 1.5, or some other suitable value, and / or is an electronegativity between about 1.1 and 1.6, or some other suitable value.

[0019] Metal diffusing into the ferroelectric layer 108 adversely affects the performance of the ferroelectric layer 108 and therefore the performance of the memory cell 102. Because the bottom electrode 110 has a high electronegativity, metal diffusion from the bottom electrode 110 into the ferroelectric layer 108 can be minimized. In contrast, because the top electrode 106 has a low electronegativity, metal diffusion from the top electrode 106 into the ferroelectric layer 108 can be significant. Therefore, by disposing the blocking layer 104 between the top electrode 106 and the ferroelectric layer 108, metal diffusion into the ferroelectric layer 108 can be significantly reduced. Furthermore, the blocking layer 104 can be more effective in reducing metal diffusion into the ferroelectric layer 108 than between the bottom electrode 110 and the ferroelectric layer 108.

[0020] By reducing the diffusion of metal into the ferroelectric layer 108, the blocking layer 104 improves the performance of the ferroelectric layer 108, which in turn improves the performance of the memory cell 102. For example, the ferroelectric phase may be increased, the remnant polarization (2Pr) may be increased, the polarization uniformity may be increased, the leakage current may be decreased, the capacitance may be increased, the data retention may be increased, the breakdown voltage may be increased, or any combination of the foregoing may result. Additionally, as will be better understood below, the fabrication of the blocking layer 104 is compatible with logic fabrication processes, such that the blocking layer 104 may be used in memory cells for embedded memory applications.

[0021] The ferroelectric phase corresponds to an orthorhombic phase, which is contrasted with a tetragonal phase and a monoclinic phase. A higher ratio of the orthorhombic phase to the other phases leads to a higher remanent polarization (2Pr) and therefore improved data retention. Thus, the blocking layer 104 increases the ratio of the orthorhombic phase to the other phases. The ferroelectric phase can be measured and / or quantified, for example, by X-ray diffraction (XRD), electron backscatter diffraction (EBSD), etc.

[0022] As mentioned above, the bottom electrode 110 includes a metal with high electronegativity and the top electrode 106 includes a metal with low electronegativity. In some embodiments, the low electronegativity metal is or includes titanium (e.g., electronegativity of Ti / 1.54), tantalum (e.g., electronegativity of Ta / 1.51), lanthanum (e.g., electronegativity of La / 1.11), some other suitable metal, or any combination of the foregoing. In some embodiments, the highly electronegative metal is or includes molybdenum (e.g., Mo / 2.16 electronegativity), tungsten (e.g., W / 2.36 electronegativity), ruthenium (e.g., Ru / 2.2 electronegativity), osmium (e.g., Os / 2.18 electronegativity), rhodium (e.g., Rh / 2.28 electronegativity), iridium (e.g., Ir / 2.2 electronegativity), palladium (e.g., Pd / 2.2 electronegativity), platinum (e.g., Pt / 2.28 electronegativity), copper (e.g., Cu / 1.9 electronegativity), silver (e.g., Ag / 1.93 electronegativity), gold (e.g., Au / 2.54 electronegativity), aluminum (e.g., Al / 1.61 electronegativity), some other suitable metal, or any combination of the foregoing.

[0023] In some embodiments, the blocking layer 104 is made of silicon oxide (e.g., SiO x ), silicon nitride (e.g., SiN x), a metal oxide, a high-k dielectric, some other suitable material, or any combination of the foregoing. A high-k dielectric can be, for example, a dielectric having a dielectric constant greater than about 3.9, about 10, or some other suitable value. In some embodiments, blocking layer 104 is a dielectric. For example, blocking layer 104 can be or include a silicon oxide, a silicon nitride, a high-k dielectric, or some other suitable dielectric. In some embodiments, blocking layer 104 is a semiconductor. For example, blocking layer 104 can be or include a semiconducting metal oxide or some other suitable semiconducting material. In some embodiments, blocking layer 104 is conductive. For example, blocking layer 104 can be or include a conductive metal oxide or some other suitable conductive material.

[0024] In some embodiments where the blocking layer 104 is or includes a metal oxide, the metal of the metal oxide has a high electronegativity. In some embodiments, this high electronegativity is higher than the electronegativity of the metal of the top electrode 106. Further, in some embodiments, this high electronegativity is greater than about 1.6, about 2.0, or some other suitable value, and / or is between about 1.6-2.4, between about 1.6-2.0, between about 2.0-2.4, or some other suitable value.

[0025] In some embodiments, the blocking layer 104 includes metal that diffuses from the top electrode 106 toward the ferroelectric layer 108. In some embodiments, the blocking layer 104 has an amorphous structure, which eliminates grain boundaries and increases the complexity of the diffusion paths. Alternatively, in some embodiments, the blocking layer 104 has a nanocrystalline structure, and the grains of the blocking layer 104 are equiaxed rather than columnar, which increases the complexity of the diffusion paths. Increasing the complexity of the diffusion paths reduces the diffusion of the metal through the blocking layer 104.

[0026] In some embodiments, the blocking layer 104 has a thickness T of about 2-50 angstroms, about 2-26 angstroms, about 26-50 angstroms, or some other suitable value. b The thickness T b If the thickness T is too small (e.g., less than 2 angstroms), the blocking layer 104 may not be able to effectively block the diffusion of metal from the top electrode 106 to the ferroelectric layer 108. b If is too large (eg, greater than 50 Angstroms), the resistance of the blocking layer 104 may be too high, resulting in little current flowing through the memory cell 102 .

[0027] In some embodiments, the metal of the top electrode 106 is minimally diffused into the ferroelectric layer 108, even with the blocking layer 104. For example, the atomic percentage of the metal in the ferroelectric layer 108 may be a non-zero value less than about 10%, about 5%, about 1%, or other suitable percentage, and / or may be between about 1% and 10%, about 1% and 5%, about 5% and 10%, or other suitable percentage. In some embodiments, there is little or no minimal diffusion during the anneal to increase the ferroelectric phase of the ferroelectric layer 108. In some such embodiments, the atomic percentage of the metal in the ferroelectric layer 108 is less than 10% at the completion of the anneal when the blocking layer 104 is present, and is greater than 30% at the completion of the anneal when the blocking layer 104 is not present.

[0028] In some embodiments, the ferroelectric layer 108 is or includes a binary oxide, a ternary oxide or nitride, a quaternary oxide, other suitable ferroelectric material, or any combination of the foregoing. A binary oxide may be or include, for example, hafnium oxide (e.g., hafnia or HfO2) and / or some other suitable binary oxide. A ternary oxide or nitride may be, for example, hafnium silicate (e.g., HfSiO x ), hafnium zirconate (e.g., HfZrO x), barium titanate (e.g., BaTiO3), lead titanate (e.g., PbTiO3), strontium titanate (e.g., SrTiO3), calcium manganite (e.g., CaMnO3), bismuth ferrite (e.g., BiFeO3), aluminum scandium nitride (e.g., AlScN), aluminum gallium nitride (e.g., AlGaN), aluminum yttrium nitride (e.g., AlYN), some other suitable ternary oxide and / or nitride, or any combination of the foregoing. Quaternary oxides may be, for example, barium strontium titanate (e.g., BaSrTiO3), lead sulphide (e.g., PbTiO3), ... x ) and / or some other suitable quaternary oxide.

[0029] In some embodiments, the ferroelectric layer 108 comprises a non-metallic element that has an electronegativity greater than the electronegativity of the metal of the top electrode 106. In such embodiments, the difference between the electronegativity of the non-metallic element and the metal of the top electrode is at least 1.7, 1.84, or some other suitable value, and / or about 1.6-2.5, about 1.6-2.05, about 2.05-2.5, about 1.9-2.33, or some other suitable value. Non-metallic elements include, for example, oxygen, etc.

[0030] In some embodiments, the thickness T of the ferroelectric layer 108 f The thickness T may be about 10 to 200 angstroms, about 10 to 105 angstroms, about 105 to 200 angstroms, or some other suitable value. f If the thickness T is too small (e.g., less than 10 Angstroms) or too large (e.g., more than 200 Angstroms), the ferroelectric layer 108 may have no remanent polarization or may have an unusably small remanent polarization. f If is too large (eg, greater than 200 Angstroms), the resistance of the ferroelectric layer 108 may be too high and the current through the memory cell 102 may be low.

[0031] During operation of the memory cell 102, the remnant polarization of the ferroelectric layer 108 is used to represent a bit of data. For example, a positive polarity of the remnant polarization can represent a binary "0" and a negative polarity of the remnant polarization can represent a binary "1," or vice versa.

[0032] A first write voltage is applied across the ferroelectric layer 108 from the top electrode 106 to the bottom electrode 110 to set the remnant polarization to a positive polarity. A second write voltage is applied across the ferroelectric layer 108 from the top electrode 106 to the bottom electrode 110 to set the remnant polarization to a negative polarity. The first write voltage is of opposite polarity to the second write voltage and has a magnitude greater than the coercive voltage. In some embodiments, to read the polarity of the remnant polarization, the remnant polarization is set to positive or negative as described above. If the polarity of the remnant polarization changes, a current pulse is generated. If not, no current pulse is generated. Thus, the current pulse can be used to identify the polarity of the remnant polarization.

[0033] 2A and 2B, cross-sectional views 200A, 200B of several alternative embodiments of the memory cell 102 of FIG. 1 are provided.

[0034] 2A, the blocking layer 104 is between the bottom electrode 110 and the ferroelectric layer 108, rather than between the top electrode 106 and the ferroelectric layer 108. Additionally, the metal of the bottom electrode 110 has low electronegativity, and the metal of the top electrode 106 has high electronegativity. The low electronegativity is indicated generally by the diagonal hashing overlying the bottom electrode 110. Further, non-limiting examples of low and high electronegativity metals are provided above.

[0035] Due to its low electronegativity, the metal of the bottom electrode 110 is highly reactive and therefore has a high tendency to diffuse into the ferroelectric layer 108. In contrast, due to its high electronegativity, the metal of the top electrode 106 is less reactive and therefore has a low tendency to diffuse into the ferroelectric layer 108. Thus, by disposing the blocking layer 104 between the bottom electrode 110 and the ferroelectric layer 108, the diffusion of the metal into the ferroelectric layer 108 can be significantly reduced. This can significantly improve the performance of the ferroelectric layer 108, and therefore the performance of the memory cell 102.

[0036] In some embodiments where the blocking layer 104 is or includes a metal oxide, the metal of the metal oxide has a high electronegativity. In some embodiments, the high electronegativity is higher than the electronegativity of the metal of the bottom electrode 110. Further, in some embodiments, the high electronegativity is greater than about 1.6, about 2.0, or some other suitable value, and / or is between about 1.6-2.4, between about 1.6-2.0, between about 2.0-2.4, or some other suitable value.

[0037] In FIG. 2B, the memory cell 102 has a pair of blocking layers 104, each of which is correspondingly described with respect to FIG. 1. A first blocking layer 104a between the top electrode 106 and the ferroelectric layer 108 blocks the diffusion of metal from the top electrode 106 to the ferroelectric layer 108. A second blocking layer 104b between the bottom electrode 110 and the ferroelectric layer 108 blocks the diffusion of metal from the bottom electrode 110 to the ferroelectric layer 108. By blocking the diffusion of metal into the ferroelectric layer 108, the first blocking layer 104a and the second blocking layer 104b can significantly improve the performance of the ferroelectric layer 108 and, therefore, the performance of the memory cell 102.

[0038] In some embodiments, both the metal of the bottom electrode 110 and the metal of the top electrode 106 have low electronegativity. This low electronegativity is indicated generally by the diagonal hashing overlaying the bottom electrode 110 and the top electrode 106. In some embodiments, this low electronegativity is less than about 1.6, about 1.5, or some other suitable value, and / or is between about 1.1 and 1.6, or some other suitable value. Furthermore, in some embodiments where the first blocking layer 104a and the second blocking layer 104b comprise a metal oxide, this low electronegativity is less than the electronegativity of the metal of the metal oxide. Non-limiting examples of low electronegativity metals are provided above.

[0039] 1 and 2A illustrate the blocking layer 104 as being located on the electrode having the lowest metal electronegativity among the top electrode 106 and the bottom electrode 110, this may not be the case in alternative embodiments. For example, the blocking layer 104 may instead be located on the electrode having the highest metal electronegativity, or the top electrode 106 and the bottom electrode 110 may have the same metal electronegativity, which may be high or low. Additionally, while FIGS. 1 and 2A illustrate one of the top electrode 106 and the bottom electrode 110 as having a low metal electronegativity and the other of the top electrode 106 and the bottom electrode 110 as having a high metal electronegativity, this may be reversed in alternative embodiments, or in alternative embodiments, both the top electrode 106 and the bottom electrode 110 may have low or high metal electronegativity. Although FIG. 2B illustrates the top electrode 106 and the bottom electrode 110 as having low metal electronegativity, the top electrode 106 and the bottom electrode 110 may alternatively have high metal electronegativity.

[0040] Although Figures 1, 2A, and 2B describe the metals of the bottom and top electrodes in terms of electronegativity, the metals can also be described in terms of electropositivity. A metal with low electronegativity has high electropositivity, and a metal with high electronegativity has low electropositivity. Thus, the top and bottom electrodes 106, 110 of Figure 1 can also be considered to have high and low electropositivity, respectively, and the top and bottom electrodes 106, 110 of Figure 2A can also be considered to have low and high electropositivity, respectively. Additionally, the top and bottom electrodes 106, 110 of Figure 2B can also be considered to have high electropositivity.

[0041] Referring to FIG. 3A, a cross-sectional view 300A of some embodiments of the memory cell 102 of FIG. 1 is provided, where the memory cell 102 is integrated into an interconnect structure 302 of an IC chip.

[0042] A top electrode wire 304t is above the memory cell 102, and a top electrode via (TEVA) 306t extends downward from the top electrode wire 304t to the top electrode 106. A bottom electrode wire 304b is below the memory cell 102, and a bottom electrode via (BEVA) 306b extends upward from the bottom electrode wire 304b to the bottom electrode 110. The BEVA 306b comprises a BEVA barrier 308 and a BEVA body 310. The BEVA barrier 308 wraps around the bottom surface of the BEVA body 310, separating the BEVA body 310 from the bottom electrode wire 304b. In an alternative embodiment, the BEVA barrier 308 is omitted, such that the BEVA body 310 directly contacts the bottom electrode wire 304b. The BEVA barrier 308 may be configured, for example, to block or otherwise substantially reduce diffusion of material from the bottom electrode wire 304 b to the bottom electrode 110 .

[0043] In some embodiments, the top electrode wire 304t, TEVA 306t, and bottom electrode wire 304b are or include copper, aluminum, tungsten, or the like, or any combination of the foregoing. In some embodiments, the BEVA body 310 is or includes (1) the same material as the top electrode lead 304t, TEVA 306t, bottom electrode wire 304b, or any combination of the foregoing, (2) the same material as the BEVA barrier 308, (3) the same material as the bottom electrode 110, (4) some other suitable material, or (5) any combination of the above. In some embodiments, the BEVA barrier 308 is or includes titanium nitride, platinum, aluminum copper, gold, titanium, tantalum, tantalum nitride, tungsten, tungsten nitride, or the like, or any combination of the foregoing. In some embodiments, the thickness of the BEVA barrier 308 is about 50-200 Angstroms, or some other suitable value.

[0044] The hard mask 312 overlies the top electrode 106, and the TEVA 306t extends through the hard mask 312 from the top electrode wire 304t to the top electrode 106. In alternative embodiments, the hard mask 312 is omitted. The hard mask 312 may be or include, for example, titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, a metal oxide, some other suitable material, or any combination of the foregoing. The metal oxide may be or include, for example, titanium oxide, aluminum oxide, some other suitable silicon oxide, or any combination of the foregoing. In some embodiments, the thickness of the hard mask 312 is about 50-400 angstroms, or some other suitable value.

[0045] 1, the blocking layer 104 is configured to block the metal of the top electrode 106 from diffusing into the ferroelectric layer 108, which can improve the performance of the ferroelectric layer 108.

[0046] The bottom electrode 110, the ferroelectric layer 108, the blocking layer 104, the top electrode 106, and the hard mask 312 share a common width and form a pair of common sidewalls, one on each side of the memory cell 102. Moreover, the common sidewalls have a flat profile, but may instead have a curved profile or other suitable profile.

[0047] A sidewall spacer structure 314 is on the common sidewall. The sidewall spacer structure 314 may be or include, for example, titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, a metal oxide, some other suitable material, or any combination of the foregoing. The metal oxide may be or include, for example, titanium oxide, aluminum oxide, some other suitable silicon oxide, or any combination of the foregoing. In some embodiments, the sidewall spacer structure 314 is the same material as the hard mask 312.

[0048] A plurality of intermetal dielectric (IMD) layers 316 surround the bottom electrode wire 304b and the top electrode wire 304t, respectively. Further, a first etch stop layer 318, a second etch stop layer 320, and a buffer layer 322 separate the plurality of IMD layers 316. The first etch stop layer 318 surrounds the BEVA 306b vertically between the bottom electrode wire 304b and the memory cell 102. The second etch stop layer 320 and the buffer layer 322 cover and are conformal with the first etch stop layer 318 and the memory cell 102. Further, the second etch stop layer 320 is between the buffer layer 322 and the memory cell 102.

[0049] The IMD layer 316 may be or include, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, some other suitable dielectric, or any combination of the foregoing. The first etch stop layer 318 and / or the second etch stop layer 320 may be or include, for example, a metal nitride, a metal oxide, a metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, some other suitable dielectric, or any combination of the foregoing. In some embodiments, the first etch stop layer 318 and the second etch stop layer 320 are the same material. In some embodiments, the thickness of the first etch stop layer 318 is about 150-350 angstroms or some other suitable value. In some embodiments, the thickness of the second etch stop layer 320 is about 50-300 angstroms or some other suitable value. Buffer layer 322 may be or include, for example, tetraethylorthosilicate (TEOS) oxide and / or some other suitable dielectric, hi some embodiments, the thickness of buffer layer 322 is about 50-300 angstroms or some other suitable value.

[0050] Referring to FIG. 3B, a top view layout view 300B of some embodiments of memory cell 102 of FIG. 3A is provided. Additionally, the top layouts of BEVA 306b and TEVA 306t are shown in phantom lines overlaying memory cell 102. Cross-sectional view 300A of FIG. 3A may be taken, for example, along line A-A'. Memory cell 102 has a square or rectangular top layout, but may alternatively have a circular top layout or some other suitable top layout. BEVA 306b and TEVA 306t have a square or rectangular top layout, but may alternatively have other suitable top layout.

[0051] 4A, a cross-sectional view 400A of some alternative embodiments of the memory cell 102 of FIG. 3A is provided in which the width of the top electrode is reduced relative to the remainder of the memory cell 102.

[0052] The bottom electrode 110, the ferroelectric layer 108, and the blocking layer 104 share a first common width and form a pair of first common sidewalls 402 on either side of the memory cell 102. Furthermore, the top electrode 106 and the hard mask 312 share a second common width and form a pair of second common sidewalls 404 on either side of the memory cell 102. The second common width is smaller than the first common width, and the second common sidewalls 404 are laterally between the first common sidewalls 402. Furthermore, the second common sidewalls 404 are covered by the sidewall spacer structure 314 on the blocking layer 104. The first common sidewalls 402 and the second common sidewalls 404 have flat contours, but may have other suitable contours.

[0053] Referring to FIG. 4B, a top view layout diagram 400B of some embodiments of the memory cell 102 of FIG. 4A is provided. Additionally, the top layouts of BEVA 306b and TEVA 306t are shown in phantom lines overlaying the memory cell 102. The cross-sectional diagram 400A of FIG. 4A may be taken, for example, along line B-B'. The memory cell 102 has a square or rectangular top layout, with the second common sidewall 404 laterally offset from and disposed between the first common sidewall 402. In alternative embodiments, the memory cell 102 may have a circular top layout or some other suitable top layout. The BEVA 306b and TEVA 306t have a square or rectangular top layout, but may instead have other suitable top layouts.

[0054] 5, a cross-sectional view 500 of some alternative embodiments of the memory cell 102 of FIG. 4A is provided in which the BEVA barrier 308 and the BEVA body 310 are omitted. Additionally, the bottom electrode barrier 502 and the bottom electrode 110 form a BEVA 306b. The bottom electrode barrier 502 is between the bottom electrode 110 and the bottom electrode wire 304b, and for example, the BEVA barrier 308 can be as described in FIG. 3A. The bottom electrode barrier 502, the bottom electrode 110, the ferroelectric layer 108, the blocking layer 104, the top electrode 106, and the hard mask 312 are recessed at the BEVA 306b and the TEVA 306t are laterally offset from the center of the memory cell 102.

[0055] 6A, a cross-sectional view 600A of some alternative embodiments of the memory cell 102 of FIG. 3A is provided, omitting the BEVA 306b, the BEVA barrier 308, the BEVA body 310, the sidewall spacer structure 314, the second etch stop layer 320, and the hard mask 312. Thus, the memory cell 102 extends from the bottom electrode wire 304b. Additionally, the bottom electrode barrier 502, the bottom electrode 110, the ferroelectric layer 108, and the blocking layer 104 cover the lower surface of the top electrode 106. For example, the bottom electrode barrier 502, the bottom electrode 110, the ferroelectric layer 108, and the blocking layer 104 may each have a U-shaped profile, or the like. The bottom electrode barrier 502 is between the bottom electrode 110 and the bottom electrode wire 304b, and may be similar to the BEVA barrier 308 described in FIG. 3A, for example.

[0056] Referring to FIG. 6B, a top view layout diagram 600B of some embodiments of the memory cell 102 of FIG. 6A is provided. Additionally, the top layout of the TEVA 306t is shown in phantom lines overlaying the memory cell 102. The cross-sectional diagram 600A of FIG. 6A may be taken, for example, along line C-C'. The bottom electrode barrier 502 extends in a closed path around the bottom electrode 110, which extends in a closed path around the ferroelectric layer 108, which extends in a closed path around the blocking layer 104, which extends in a closed path around the top electrode 106. The memory cell 102 has a square or rectangular top layout, but may alternatively have a circular top layout or some other suitable top layout. The TEVA 306t has a square or rectangular top layout, but may alternatively have another suitable top layout.

[0057] 7A, a cross-sectional view 700A of some alternative embodiments of the memory cell 102 of FIG. 3A is provided, in which the BEVA 306b, the BEVA barrier 308, the BEVA body 310, the sidewall spacer structure 314, the second etch stop layer 320, and the hard mask 312 are omitted. Thus, the memory cell 102 extends from the bottom electrode lead 304b. Additionally, an additional wire 304a is below the TEVA 306t and is at the same level as the bottom electrode wire 304b, with the top electrode 106, the blocking layer 104, and the ferroelectric layer 108 forming the sidewall spacer structure.

[0058] The sidewall spacer structure is over an upper sidewall portion of the bottom electrode 110 and over the first etch stop layer 318. Additionally, the sidewall spacer structure has a pair of spacer segments between which the bottom electrode 110 is disposed. The TEVA 306t extends over a portion of the top electrode 106 in one of these segments and further into the first etch stop layer 318. In at least some embodiments, the spacer segments are continuous with each other outside of the cross-sectional view 800. The blocking layer 104 and the ferroelectric layer 108 have an L-shaped portion in each spacer segment. The L-shaped portion of the ferroelectric layer 108 wraps around a bottom corner of the corresponding L-shaped portion of the blocking layer 104, which in turn wraps around a bottom corner of the corresponding portion of the top electrode 106.

[0059] Referring to FIG. 7B, a top view layout diagram 700B of some embodiments of the memory cell 102 of FIG. 7A is provided. Additionally, the top layout of the TEVA 306t is shown in phantom lines overlaying the memory cell 102. The cross-sectional diagram 700A of FIG. 7A may be taken, for example, along line D-D'. The top electrode 106 extends in a closed path around the blocking layer 104, which extends in a closed path around the ferroelectric layer 108, which extends in a closed path around the bottom electrode 110. The memory cell 102 has a square or rectangular top layout, but may alternatively have a circular top layout or some other suitable top layout. The TEVA 306t has a square or rectangular top layout, but may alternatively have another suitable top layout.

[0060] 8, a cross-sectional view 800 of several alternative embodiments of the memory cell 102 of 3A and 3B is provided in which the blocking layer 104 is located at the bottom electrode 110 as in FIG. 2A. Furthermore, the metal of the bottom electrode 110 has low electronegativity and the metal of the top electrode 106 has high electronegativity.

[0061] 9A-9D, cross-sectional views 900A-900D are provided of several alternative embodiments of the memory cell 102 of FIG. 8, where the memory cell 102 is configured as in FIGS. 4A, 5, 6A, and 7A, respectively.

[0062] 10, a cross-sectional view 1000 of some alternative embodiments of the memory cell 102 of Figures 3A and 3B is provided, where the memory cell 102 has a pair of blocking layers 104 as in Figure 2B. Additionally, the metal of the bottom electrode 110 and the metal of the top electrode 106 have low electronegativity.

[0063] 11A-11D, cross-sectional views 1100A-1100D are provided of several alternative embodiments of the memory cell 102 of FIG. 10, where the memory cell 102 is configured as in FIGS. 4A, 5, 6A, and 7A, respectively.

[0064] 12A, a cross-sectional view 1200A is provided of some embodiments of an IC chip including memory cells 102 integrated into individual one-transistor one-capacitor (1T1C) cells 1202. The cells 102 correspond to those described in FIGS. 3A and 3B, respectively.

[0065] The 1T1C cell 1202 includes individual drain regions 1204 and individual drain side conductive paths 1206. The drain regions 1204 are doped regions of a substrate 1208, each having an opposite doping type as an adjacent region of the substrate 1208. Additionally, the drain regions 1204 are electrically isolated by trench isolation structures 1210 and partially define access transistors 1212 (partially shown) used to individually select the memory cells 102. The trench isolation structures 1210 extend over the top of the substrate 1208 and include silicon oxide and / or some other suitable dielectric material. The substrate 1208 may be, for example, a bulk silicon substrate or some other suitable type of semiconductor substrate.

[0066] The drain side conductive path 1206 electrically couples the drain region 1204 to the memory cell 102 and is formed by an interconnect structure 302 in which the memory cell 102 is disposed. The interconnect structure 302 includes a plurality of wires 304 and a plurality of vias 306. The plurality of wires 304 includes a top electrode wire 304t and a bottom electrode wire 304b. In some embodiments, the top electrode wire 304t corresponds to a bit line BL. The plurality of vias 306 includes a TEVA 306t and a BEVA 306b. The vias 306 in the level closest to the substrate 1208 are located in an inter-layer dielectric (ILD) layer 1214, while the vias 306 and wires 304 in the remaining levels are located in an IMD layer 316. The wires 304 and vias 306, except for the BEVA 306b, may be or include, for example, copper, aluminum, some other suitable metal, or any combination of the foregoing. BEVA 306b may be, for example, its counterpart described with respect to Figures 3A and 3B.

[0067] A peripheral region 1216 on the side of the 1T1C cell 1202 houses peripheral devices 1218 (only one of which is shown). The peripheral devices 1218 may be, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (finFETs), gate-all-around field-effect transistors (GAA FETs), or some other suitable type of semiconductor device. Each of the peripheral devices 1218 comprises a pair of source / drain regions 1220 in the substrate 1208, as well as a gate electrode 1222 and a gate dielectric layer 1224 stacked between the source / drain regions 1220.

[0068] Referring to Figure 12B, a cross-sectional view 1200B of some embodiments of an IC die of Figure 12A is provided taken along an axis perpendicular to the axis along which the cross-sectional view 1200A of Figure 12A is taken. The 1T1C cell 1202 includes an individual memory cell 102, an individual drain side conductive path 1206, an individual access transistor 1212, and an individual source side conductive path 1226. The memory cells 102 each correspond to those described with respect to Figures 3A and 3B.

[0069] The access transistors 1212 are on the substrate 1208 between the substrate 1208 and the interconnect structure 302 and are electrically isolated by the trench isolation structure 1210. The access transistors 1212 include respective drain regions 1204, respective source regions 1228, respective gate dielectric layers 1230, and respective gate dielectric layers 1232. The gate electrodes 1232 are on the respective gate dielectric layers 1230 and, in some embodiments, form word lines. The drain regions 1204 and the source regions 1228 are doped regions of the substrate 1208, each having an opposite doping type as adjacent regions of the substrate 1208. Furthermore, the drain regions 1204 and the source regions 1228 are adjacent to the respective gate electrodes 1232. The access transistors 1212 may be, for example, a MOSFET, a finFET, a GAA FET, or some other suitable type of semiconductor device.

[0070] A drain side conductive pathway 1206 electrically couples the drain region 1204 to the memory cell 102, and a source side conductive pathway 1226 electrically couples the source region 1228 to the source line SL. The drain side conductive pathway 1206 and the source side 1226 are formed by a plurality of wires 304 and a plurality of vias 306.

[0071] Although Figures 12A and 12B are shown with memory cell embodiments like those of Figures 3A and 3B, the memory cell embodiments of Figures 1, 2A, 2B, 4A, 4B, 5, 6A, 6B, 7A, 7B, 8, 9A-9D, 10, and 11A-11D are applicable to other embodiments. For example, as shown in cross-sectional view 1300 of Figure 13, memory cell 102 of Figures 12A and 12B may alternatively be configured as in Figures 7A and 7B.

[0072] Referring to Figure 14, a top view layout view 1400 of some embodiments of the IC chip of Figures 12A and 12B is provided. The cross-sectional views 1200A, 1200B of Figures 12 and 12 may be taken, for example, along lines E and F, respectively. The IC chip includes a plurality of 1T1C cells 1202 in a plurality of rows and a plurality of columns, thereby forming a memory array 1402. Peripheral devices 1218 surround the memory array 1402 in a peripheral region 1216 of the IC chip. The peripheral devices 1218 may implement, for example, read / write circuits and / or other suitable circuits for operating the 1T1C cells 1202.

[0073] 15, a cross-sectional view 1500 of some embodiments of an IC chip including a ferroelectric field effect transistor (FeFET) 1502 is shown, where a blocking layer 104 is configured to block diffusion of metal from a top gate electrode 1504 into the ferroelectric layer 108. A pair of source / drain regions 1506 are in the substrate 1208, with a channel region 1508 of the substrate 1208 separating the source / drain regions 1506. The source / drain regions 1506 may be, for example, doped regions of the substrate 1208.

[0074] The gate dielectric layer 1510, the floating gate electrode 1512, the ferroelectric layer 108, the blocking layer 104, the top gate electrode 1504, and the hard mask 1514 form a gate stack above the channel region 1508 and share a common width. In an alternative embodiment, the floating gate electrode 1512 and / or the gate dielectric layer 1510 are omitted. The floating gate electrode 1512 and the top gate electrode 1504 are similar to the bottom electrode 110 and the top electrode 106, respectively, described in FIG. 1. Thus, the floating gate electrode 1512 has a high electronegativity, whereas the top gate electrode 1504 has a low electronegativity. Additionally, the blocking layer 104 and the ferroelectric layer 108 are as described in any of FIG. 1, whereby the blocking layer 104 is configured to block the metal of the top gate electrode 1504 from diffusing into the ferroelectric layer 108. This improves the performance of the ferroelectric layer 108, and thus the memory cell 102.

[0075] A sidewall spacer structure 1516 is on the opposing sidewall of the gate stack, and the interconnect structure 302 overlies and is electrically coupled to the FeFET 1502. The interconnect structure 302 includes a plurality of wires 304 and a plurality of vias 306 that are stacked to define a conductive path leading from the FeFET 1502. Although only one level of vias 306 and one level of wires 304 are shown, additional levels are applicable. A contact etch stop layer 1518 covers and lines the FeFET 1502, and an ILD layer 1214 and an IMD layer 316 are stacked on top of the contact etch stop layer 1518. The contact etch stop layer 1518 and ILD layer 1214 surround the vias 306, and the IMD layer 316 surrounds the wires 304.

[0076] In some embodiments, the hard mask 1514 is or includes titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, metal oxide, some other suitable material, or any combination of the foregoing. In some embodiments, the sidewall spacer structures 1516 are or include titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, metal oxide, some other suitable material, or any combination of the foregoing. In some embodiments, the contact etch stop layer 1518 is or includes a metal nitride, metal oxide, metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, some other suitable dielectric, or any combination of the foregoing.

[0077] During operation of the FeFET 1502, the remnant polarization of the ferroelectric layer 108 can be used to represent a bit of data. For example, a positive polarity of the remnant polarization can represent a binary "0" and a negative polarity of the remnant polarization can represent a binary "1", or vice versa.

[0078] A first write voltage is applied across the ferroelectric layer 108 from the top gate electrode 1504 to the channel region 1508 (e.g., via the source / drain region 1506) to set the remnant polarization to a positive polarity. A second write voltage is applied across the ferroelectric layer 108 from the top gate electrode 1504 to the channel region 1508 to set the remnant polarization to a negative polarity. The first and second write voltages have opposite polarities and a magnitude greater than the coercive voltage.

[0079] The polarity of the remnant polarization shifts the threshold voltage of the FeFET 1502. Whether the threshold voltage is a first or second threshold depends on whether the remnant polarization is positive or negative. To read the polarity of the remnant polarization, a read voltage less than the coercive voltage and between the first and second threshold voltages is applied from the top gate electrode 1504 to the source of one of the source / drain regions 1506. Depending on whether the channel region 1508 is conducting, the remnant magnetic polarization has a positive or negative polarity.

[0080] Although FIG. 15 illustrates an FeFET 1502 having a blocking layer 104 on the top gate electrode 1504, the FeFET 1502 may alternatively have a blocking layer 104 on the floating gate electrode 1512, as shown in cross-sectional view 1600A of FIG. 16A. In such an alternative embodiment, the floating gate electrode 1512 has a low electronegativity and the top gate electrode 1504 has a high electronegativity. Furthermore, although FIG. 15 illustrates an FeFET 1502 having a single blocking layer 104, the FeFET 1502 may alternatively have a pair of blocking layers 104, as shown in cross-sectional view 1600B of FIG. 16B. In such an alternative embodiment, a first blocking layer 104a is located between the top gate electrode 1504 and the ferroelectric layer 108, and a second blocking layer 104b is located between the floating gate electrode 1512 and the ferroelectric layer 108. In addition, both the floating gate electrode 1512 and the top gate electrode 1504 have low electronegativity.

[0081] 17-27, a series of cross-sectional views 1700-2700 are provided of several embodiments of methods of forming an IC chip including memory cells integrated into individual 1T1C cells and including a blocking layer. Cross-sectional views 1700-2700 may correspond to, for example, the IC die of FIGS. 12A and 12B and / or may be taken along, for example, line E of FIG. 14.

[0082] As shown in cross-sectional view 1700 of Figure 17, the interconnect structure 302 is partially formed above and electrically coupled to a plurality of access transistors 1212 (only partially shown) and peripheral devices 1218. The access transistors 1212 are separate from the plurality of 1T1C cells 1202 being formed, and the peripheral devices 1218 are located in a peripheral region 1216 of the IC chip being formed. The access transistors 1212 and peripheral devices 1218 are located on and partially formed by a substrate 1208 and separated by trench isolation structures 1210 in the substrate 1208. The access transistors 1212 and peripheral devices 1218 may be, for example, those described in Figures 12A and 12B.

[0083] The interconnect structure 302 includes a plurality of wires 304 and a plurality of vias 306 stacked on a dielectric structure. The dielectric structure includes an ILD layer 1214 and a first IMD layer 316a disposed on the ILD layer 1214. The plurality of wires 304 includes a plurality of bottom electrode wires 304b along a top surface of the interconnect structure 302. The bottom electrode wires 304b are individual to the 1T1C cells 1202 being formed. Furthermore, the bottom electrode wires 304b are each electrically coupled to the drain regions 1204 of the access transistors 1212. The first IMD layer 316a may be formed by and / or using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition process, or any combination of the foregoing. Wires 304 and vias 306 may be formed by and / or using, for example, CVD, PVD, ALD, electroless plating, electroplating, some other suitable deposition process, or any combination of the foregoing.

[0084] As shown in cross-sectional view 1800 of Figure 18, a first etch stop layer 318 is deposited or otherwise formed on the interconnect structure 302. Note that for simplicity of drawing, the lower portion of the interconnect structure 302 is omitted in this specification and subsequent figures. The first etch stop layer 318 is a dielectric and may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing.

[0085] 18, BEVA 306b are formed, each extending through first etch stop layer 318 to bottom electrode wire 304b. BEVA 306b comprises an individual BEVA body 310 and an individual BEVA barrier 308 each covering an underside of BEVA body 310. BEVA body 310 and / or BEVA barrier 308 may be formed by and / or using, for example, CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing.

[0086] As shown in cross-sectional view 1900 of FIG. 19, the bottom electrode layer 110l is deposited on the BEVA 306b and the first etch stop layer 318. The bottom electrode layer 110l is conductive and is or includes a metal having high electronegativity. Thus, the metal of the bottom electrode layer 110l is less reactive and therefore less prone to diffusion. The bottom electrode layer 110l may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing.

[0087] In some embodiments, the high electronegativity is related to the electronegativity of a subsequently formed top electrode layer, in some embodiments, the high electronegativity is greater than about 1.6, about 2.0, or some other suitable value, and / or is an electronegativity of about 1.6-2.4, about 1.6-2.0, about 2.0-2.4, or some other suitable value. In some embodiments, the highly electronegative metal may be or include molybdenum (e.g., Mo / 2.16 electronegativity), tungsten (e.g., W / 2.36 electronegativity), ruthenium (e.g., Ru / 2.2 electronegativity), osmium (e.g., Os / 2.18 electronegativity), rhodium (e.g., Rh / 2.28 electronegativity), iridium (e.g., Ir / 2.2 electronegativity), palladium (e.g., Pd / 2.2 electronegativity), platinum (e.g., Pt / 2.28 electronegativity), copper (e.g., Cu / 1.9 electronegativity), silver (e.g., Ag / 1.93 electronegativity), gold (e.g., Au / 2.54 electronegativity), aluminum (e.g., Al / 1.61 electronegativity), some other suitable conductive material, or any combination of the foregoing.

[0088] Also shown in cross-sectional view 1900 of Figure 19 is a ferroelectric layer 108 deposited on the bottom electrode layer 110l. Deposition can be performed by, for example, CVD, PVD, ALD, the like, or any combination of the foregoing.

[0089] 20, the blocking layer 104 is deposited on the ferroelectric layer 108, and the top electrode layer 106l is deposited on the blocking layer 104. The blocking layer 104 may be deposited by, for example, CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing. Similarly, the top electrode layer 106l may be deposited by, for example, CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing.

[0090] The top electrode layer 106l includes a metal with low electronegativity, and the blocking layer 104 is configured to block diffusion of the metal into the ferroelectric layer 108. This low electronegativity is indicated generally by the diagonal hashing overlying the top electrode layer 106l. In some embodiments, this low electronegativity is lower than the electronegativity of the bottom electrode layer 110l. In some embodiments, this low electronegativity is less than about 1.6, about 1.5, or some other suitable value, and / or is an electronegativity between about 1.1 and 1.6, or some other suitable value.

[0091] Due to the low electronegativity, the metal of the top electrode layer 106l is highly reactive and therefore has a high tendency to diffuse into the ferroelectric layer 108. Metal diffusing into the ferroelectric layer 108 adversely affects the performance of the ferroelectric layer 108. Therefore, the blocking layer 104 improves the performance of the ferroelectric layer 108 by blocking metal diffusion from the top electrode layer 106l into the ferroelectric layer 108. For example, the ferroelectric phase can be increased, the remnant polarization (2Pr) can be increased, the polarization uniformity can be increased, the leakage current can be reduced, the capacitance can be increased, the data retention can be increased, the breakdown voltage can be increased, or any combination of the foregoing can result.

[0092] In contrast to the top electrode layer 106l, the metal of the bottom electrode layer 110l has high electronegativity and therefore is less prone to diffuse into the ferroelectric layer 108. Therefore, diffusion of the metal from the bottom electrode layer 110l into the ferroelectric layer 108 does not significantly affect the performance of the ferroelectric layer 108, and a blocking layer in the bottom electrode layer 110l may be omitted.

[0093] In some embodiments, the blocking layer 104 is made of silicon oxide (e.g., SiO x ), silicon nitride (e.g., SiN x), a metal oxide, a high-k dielectric, some other suitable metal, or any combination of the foregoing. A high-k dielectric can be, for example, a dielectric having a dielectric constant greater than about 3.9, about 10, or some other suitable value. In some embodiments, blocking layer 104 is a dielectric. For example, blocking layer 104 can be or include a silicon oxide, a silicon nitride, a high-k dielectric, or some other suitable dielectric. In some embodiments, blocking layer 104 is a semiconductor. For example, blocking layer 104 can be or include a semiconducting metal oxide or some other suitable semiconducting material. In other embodiments, blocking layer 104 is conductive. For example, blocking layer 104 can be or include a conductive metal oxide or some other suitable conductive material.

[0094] In some embodiments, the blocking layer 104 includes a metal that diffuses from the top electrode layer 106l toward the ferroelectric layer 108. In some embodiments, the blocking layer 104 has an amorphous structure, which eliminates grain boundaries and increases the complexity of the diffusion paths. Alternatively, in some embodiments, the blocking layer 104 has a nanocrystalline structure, and the grains of the blocking layer 104 are equiaxed rather than columnar, which increases the complexity of the diffusion paths. Increasing the complexity of the diffusion paths reduces the diffusion of the metal through the blocking layer 104.

[0095] In some embodiments, the blocking layer 104 has a thickness T of about 2-50 angstroms, about 2-26 angstroms, about 26-50 angstroms, or some other suitable value. b The thickness T b If the thickness T is too small (e.g., less than 2 angstroms), the blocking layer 104 may not be able to effectively block the diffusion of metal from the top electrode layer 106l to the ferroelectric layer 108. b If is too large (eg, greater than 50 Angstroms), the resistance of blocking layer 104 may be too high, resulting in little current flowing through the memory cell.

[0096] In some embodiments, the metal of the top electrode layer 106l is minimally diffused into the ferroelectric layer 108, even with the blocking layer 104. For example, the atomic percentage of the metal in the ferroelectric layer 108 may be a non-zero value less than about 10%, about 5%, about 1%, or other suitable percentage, and / or between about 1% and 10%, between about 1% and 5%, between about 5% and 10%, or other suitable percentage. In some embodiments, there is little or no minimal diffusion during the anneal to increase the ferroelectric phase of the ferroelectric layer 108. In some such embodiments, the atomic percentage of the metal in the ferroelectric layer 108 is less than 10% at the completion of the anneal when the blocking layer 104 is present, and is greater than 30% at the completion of the anneal when the blocking layer 104 is not present.

[0097] As shown in cross-sectional view 2100 of FIG. 21, an anneal is performed to increase the ferroelectric phase in the ferroelectric layer 108. Note that the anneal is illustrated diagrammatically by the change in hashing of the ferroelectric layer 108 from FIG. 20 to FIG. 21. The ferroelectric phase corresponds to the orthorhombic phase, as contrasted with the tetragonal and monoclinic phases. The higher the ratio of the orthorhombic phase to other phases in the ferroelectric layer 108, the higher the remanent polarization (2Pr) and therefore the better the data retention. The anneal can be performed at temperatures, for example, about 300-1500° C., about 300-900° C., about 900-1500° C., etc.

[0098] During annealing, the metals of the top electrode layer 106l and the bottom electrode layer 110l are more prone to react and diffuse. However, the metal of the bottom electrode layer 110l still has a low diffusivity during annealing, so it has minimal impact on the ferroelectric layer 108 during annealing. In contrast, the metal of the top electrode layer 106l has a higher diffusivity during annealing. However, despite the higher diffusivity, the metal of the top electrode layer 106l has minimal impact on the ferroelectric layer 108, because the blocking layer 104 blocks the diffusion of the metal into the ferroelectric layer 108. In some embodiments, the atomic percentage of the metal in the ferroelectric layer 108 is less than about 10%, 5%, or 1% at the completion of annealing when the blocking layer 104 is present, and is greater than about 30% at the completion of annealing when the blocking layer 104 is not present.

[0099] Also, as shown in cross-sectional view 2100 of FIG. 21, a hard mask 312 is formed individually for the 1T1C cell 1202 to be formed. As will be seen below, the hard mask 312 has a pattern for the memory cell to be formed. The process for forming the hard mask 312 may include, for example, depositing a hard mask layer on the top electrode layer 106l, followed by patterning the hard mask layer into the hard mask 312. The deposition may be, for example, deposited by CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing. The patterning may be performed, for example, by a photolithography / etch process or some other suitable patterning process.

[0100] As shown in the cross-sectional view 2200 of FIG. 22, with the hard mask 312 in place, an etch is performed on the top electrode layer 106l, the blocking layer 104, the ferroelectric layer 108, and the bottom electrode layer 110l. In some embodiments where the hard mask 312 is formed by a photolithography / etching process, the etch of the photolithography / etching process is the same as the etch on the top electrode layer 106l, etc. The etch stops on the first etch stop layer 318, i.e., the first etch stop layer 318 acts as an etch stop for the etch. Furthermore, the etch transfers the pattern of the hard mask 312 to the top electrode layer 106l, the blocking layer 104, the ferroelectric layer 108, and the bottom electrode layer 110l, thereby forming the memory cells 102 on the BEVA 306b, respectively. Hereinafter, the individual segments of the top electrode layer 106l in the memory cell 102 will be referred to as top electrodes 106, and the individual segments of the bottom electrode layer 110l in the memory cell 102 will be referred to as bottom electrodes 110.

[0101] 23, a sidewall spacer structure 314 is formed on a common sidewall formed by the hard mask 312, the top electrode 106, the blocking layer 104, the ferroelectric layer 108, and the bottom electrode 110. The process for forming the sidewall spacer structure 314 may include, for example, 1) depositing a sidewall spacer layer on the memory cell 102, and 2) etching back the sidewall spacer layer, although other suitable processes may also be applied. The sidewall spacer layer may be deposited by, for example, CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing.

[0102] As shown in the cross-sectional views of FIGS. 24-27, interconnect structure 302 is completed over and around memory cell 102.

[0103] As shown in cross-sectional view 2400 of FIG. 24, the second etch stop layer 320 is formed over the memory cells 102 and laterally offset from the peripheral region 1216. Forming the second etch stop layer 320 includes 1) depositing the second etch stop layer 320 over the memory cells 102 and the peripheral region 1216, and 2) patterning the second etch stop layer 320 to remove it from the peripheral region 1216. However, other suitable processes may also be applied. The second etch stop layer 320 may be deposited, for example, by CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing. The patterning may be performed, for example, by a photolithography / etch process or some other suitable process.

[0104] 25, the buffer layer 322 and the second IMD layer 316b are deposited over the first and second etch stop layers 318, 320, covering the memory cells 102 and the peripheral region 1216. In an alternative embodiment, the buffer layer 322 is omitted. The buffer layer 322 and / or the second IMD layer 316b may be deposited by, for example, CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing.

[0105] 25, the second IMD layer 316b, the buffer layer 322, the first etch stop layer 318, and the second etch stop layer 320 are patterned to form a number of via openings 2502. The via openings 2502 expose the top electrodes 106 of the memory cells 102 and the wires 304 of the peripheral region 1216, respectively. The patterning may be performed, for example, by one or more photolithography / etching steps and / or some other suitable patterning steps. In some embodiments, the first etch stop layer 318 and the second etch stop layer 320 act as etch stops during the etching of the photolithography / etching steps.

[0106] 26, the second IMD layer 316b is further patterned to form a plurality of wire openings 2602 that overlap the via openings 2502. The patterning may be performed, for example, by a photolithography / etch process and / or some other suitable patterning process.

[0107] As shown in cross-sectional view 2700 of FIG. 27, a plurality of additional wires 304 and a plurality of additional vias 306 are formed filling via openings 2502 (see, e.g., FIG. 25) and wire openings 2602 (see, e.g., FIG. 26). The plurality of additional wires 304 each fill the wire openings 2602 and comprise a plurality of top electrode wires 304t that are individually located on the memory cells 102, respectively. The plurality of additional vias 306 each fill the via openings 2502 and comprise a plurality of TEVAs 306t that are individually located on the top electrodes 106, respectively. Further, the TEVAs 306t each extend from the top electrode wires 304t to the top electrodes 106, respectively.

[0108] The steps of forming the additional wires 304 and the additional vias 306 may include, for example, 1) depositing a metal layer filling the via openings 2502 and the wire openings 2602, and 2) performing planarization on the metal layer and the second IMD layer 316b until the top surfaces of the second IMD layer 316b and the metal layer are flush with one another, although other suitable steps may also be applied. The metal layer may be deposited, for example, by CVD, PVD, ALD, electroless plating, electroplating, some other suitable deposition process, or any combination of the foregoing.

[0109] Although Figures 17-27 are described with reference to a method, it should be understood that the structures shown in Figures 17-27 are not limited to the method and may be independent of the method. Although Figures 17-27 are described as a series of operations, it should be understood that in other embodiments, the order of operations may be changed. For example, instead of forming a blocking layer 104 between the ferroelectric layer 108 and the top electrode layer 106, a blocking layer 104 may be formed between the bottom electrode layer 110l and the ferroelectric layer 108. In such an embodiment, the metal of the electrode layer 110l has a low electronegativity and the metal of the top electrode layer 106l has a high electronegativity.

[0110] 17-27 show and describe a particular sequence of operations, other embodiments may omit some of the acts shown and / or described. Other embodiments may include additional operations not shown and / or described. For example, a separate blocking layer may be formed between the bottom electrode layer 110l and the ferroelectric layer 108. In such an embodiment, both the metal of the bottom electrode layer 110l and the metal of the top electrode layer 106l have low electronegativity and therefore high diffusivity.

[0111] Referring to FIG. 28, a block diagram 2800 of some embodiments of the methods of FIGS. 17-27 is provided.

[0112] In 2802, an interconnect structure is partially formed over a substrate, the interconnect structure including bottom electrode wires in a memory region, see, for example, FIG.

[0113] At 2804, an etch stop layer is deposited over the interconnect structure. See, for example, FIG.

[0114] At 2806, bottom electrode vias are formed that extend through the etch stop layer to the bottom electrode wires. See, for example, FIG.

[0115] At 2808, a bottom electrode layer, a ferroelectric layer, a blocking layer, and a top electrode layer are stacked and deposited over the bottom electrode via, with the blocking layer being between the ferroelectric layer and the electrode layer having the lowest metal electronegativity among the bottom and top electrode layers. The blocking layer is configured to block diffusion of metal from the electrode layers into the ferroelectric layer. See, e.g., Figures 19 and 20.

[0116] At 2810, an anneal is performed to increase the ferroelectric phase of the ferroelectric layer, see, for example, FIG.

[0117] At 2812, a hard mask is formed over the top electrode layer. See, for example, FIG.

[0118] At 2814, the top electrode layer, the blocking layer, the ferroelectric layer, and the bottom electrode layer are etched using a hard mask to form memory cells, see, for example, FIG.

[0119] At 2816, sidewall spacer structures are formed on the sidewalls of the memory cells. See, for example, FIG.

[0120] At 2818, interconnect structures are completed over and around the memory cells, see, for example, Figures 24-27.

[0121] Although block diagram 2800 of FIG. 28 is illustrated and described herein as a series of acts or events, it should be understood that the illustrated order of such acts or events is not to be construed in a limiting sense. For example, some acts may occur in different orders and / or concurrently with other acts or events other than those illustrated and / or described herein. Moreover, not all illustrated acts are required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.

[0122] 29-36, a series of cross-sectional views 2900-3600 are provided of several alternative embodiments of the method of Figures 17-27 in which memory cells 102 are formed as shown and described in Figures 8A and 8B. Thus, an IC chip formed by this method may correspond, for example, to the IC chip of Figure 13.

[0123] As shown in cross-sectional view 2900 of Figure 29, a difference from the operation described with respect to Figure 17 is that interconnect structure 302 has a different layout. For example, interconnect structure 302 has additional wires along a top surface of interconnect structure 302.

[0124] As shown in the cross-sectional view 3000 of FIG. 30, the first etch stop layer 318 and the sacrificial layer 3002 are deposited and stacked on the interconnect structure 302 such that the first etch stop layer 318 is disposed between the sacrificial layer 3002 and the first IMD layer 316a. The first etch stop layer 318 may be or include, for example, a metal nitride, a metal oxide, a metal carbide, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, or the like, or any combination of the foregoing. The sacrificial layer 3002 may be or include, for example, tetraethylorthosilicate (TEOS) oxide and / or the like. The first etch stop layer 318 and the sacrificial layer 3002 may be deposited by, for example, CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing.

[0125] As shown in cross-sectional view 3100 of FIG. 31 , the first etch stop layer 318 and the sacrificial layer 3002 are patterned to form cell openings 3102 exposing the bottom electrode wires 304b, respectively. The patterning may be performed, for example, by a photolithography / etching process or some other suitable patterning process. In some embodiments, the photolithography / etching includes: 1) forming a photoresist mask 3104 on the sacrificial layer 3002 by photolithography; 2) performing an etch on the first etch stop layer 318 and the sacrificial layer 3002 using the photoresist mask 3104; and 3) removing the photoresist mask 3104.

[0126] As shown in cross-sectional view 3200 of FIG. 32, a bottom electrode layer 110l is deposited on the sacrificial layer 3002, filling the cell opening 3102 (see, e.g., FIG. 31). In some embodiments, a bottom electrode barrier layer lining the cell opening 3102 is deposited first, and the bottom electrode layer 110l is deposited on the bottom electrode barrier layer. The bottom electrode layer 110l and / or the bottom electrode barrier layer may be deposited by, for example, CVD, PVD, ALD, some other suitable deposition process, or any combination of the foregoing. The bottom electrode layer 110l may be, for example, as described with respect to FIG. 19, and / or the bottom electrode barrier layer may be, for example, the bottom electrode barrier 502 described with respect to FIG. 5.

[0127] As shown in cross-sectional view 3300 of Figure 33, the top surface of bottom electrode layer 110l is recessed to be flush or nearly flush with the top surface of sacrificial layer 3002. This separates bottom electrode layer 110l into individual bottom electrodes 110 for the memory cells being formed. The recessing can be performed, for example, by etch-back, planarization, etc. Planarization can be performed, for example, by chemical mechanical polishing (CMP) and / or some other suitable planarization.

[0128] As shown in cross-sectional view 3400 of Figure 34, the sacrificial layer 3002 (see, e.g., Figure 33) is removed. The removal can be performed, for example, by etching or some other suitable removal process. To the extent the removal is performed by etching, the first etch stop layer 318 can function as an etch stop for the etch.

[0129] Also shown in cross-sectional view 3400 of Figure 34, a ferroelectric layer 108, a blocking layer 104, and a top electrode layer 106l are deposited and stacked on the bottom electrode 110 and the first etch stop layer 318. The blocking layer 104 is on the ferroelectric layer 108, and the top electrode layer 106l is on the blocking layer 104. The ferroelectric layer 108, the blocking layer 104, and the top electrode layer 106l may be deposited, for example, as described with respect to Figures 9 and 20.

[0130] As shown in cross-sectional view 3500 of Figure 35, an anneal is performed to increase the ferroelectric phase in ferroelectric layer 108, as described in Figure 21. Note that the anneal is indicated diagrammatically by the change in hashing of ferroelectric layer 108 from Figure 34 to Figure 35.

[0131] Also, as shown in cross-sectional view 3500 of FIG. 35, an etchback is performed on the ferroelectric layer 108, the blocking layer 104, and the top electrode layer 106l. The etchback can be performed, for example, by vertical and / or anisotropic etching. The etchback removes horizontal segments of the ferroelectric layer 108, the blocking layer 104, and the top electrode layer 106l, thereby disposing the ferroelectric layer 108, the blocking layer 104, and the top electrode layer 106l on the sidewalls (e.g., the sidewalls of the electrode 110). Furthermore, the remaining segments of the top electrode layer 106l on the sidewalls of the bottom electrode 110 are hereinafter referred to as the top electrode 106.

[0132] The operations described in FIGS. 25-27 are performed to complete the interconnect structure 302 over and around the memory cell 102, as shown in cross section 3600 of FIG.

[0133] Although Figures 29-36 are described with reference to a method, it should be understood that the structures shown in Figures 29-36 are not limited to the method and may be independent of the method. Although Figures 29-36 are described as a series of acts, it should be understood that in other embodiments the order of acts may be changed. Although Figures 29-36 are illustrated and described as a particular series of acts, in other embodiments some of the acts illustrated and / or described may be omitted. Other embodiments may include additional acts not illustrated and / or described.

[0134] In some embodiments, the present invention provides an IC chip including a memory cell. The memory cell comprises a first electrode and a second electrode, both comprising a metal, a ferroelectric layer between the first electrode and the second electrode, and a blocking layer between the ferroelectric layer and the first electrode, the blocking layer configured to block a first metal of the first electrode from diffusing into the ferroelectric layer, the first metal of the first electrode having a lower electronegativity than a second metal of the second electrode. In some embodiments, the blocking layer is in direct contact with the ferroelectric layer and the first electrode, and the second electrode is in direct contact with the ferroelectric layer. In some embodiments, the blocking layer is amorphous. In some embodiments, the blocking layer is a semiconductor. In some embodiments, the blocking layer is a conductive metal oxide. In some embodiments, the ferroelectric layer comprises a non-zero atomic percentage of the first metal that is less than about 10%.

[0135] In some embodiments, the present invention provides another IC chip including a memory cell. The memory cell comprises a bottom electrode at a bottom of the memory cell, a top electrode at a top of the memory cell, a ferroelectric layer between the bottom electrode and the top electrode, and a diffusion barrier layer between the ferroelectric layer and a first electrode, the first electrode comprising a metal having an electronegativity less than about 1.6. In some embodiments, the memory cell further comprises a second diffusion barrier layer between the ferroelectric layer and a second electrode, the second electrode being the other of the bottom electrode and the top electrode, the second electrode comprising a metal having an electronegativity less than about 1.6. In some embodiments, the ferroelectric layer is in direct contact with the second electrode, the second electrode being the other of the bottom electrode and the top electrode, the second electrode comprising a metal having an electronegativity greater than about 1.6. In some embodiments, the ferroelectric layer, the diffusion barrier layer, and one or both of the bottom electrode and the top electrode share a common width. In some embodiments, the ferroelectric layer, the diffusion barrier layer, and the bottom electrode have respective U-shaped contours that wrap around the bottom of the top electrode. In some embodiments, the top electrode extends in a closed path around the bottom electrode, and the top electrode has a bottom surface that is raised relative to the bottom surface of the bottom electrode. In some embodiments, the ferroelectric layer and the diffusion barrier layer extend in a closed path around the bottom electrode, and have respective bottom surfaces that are raised relative to the bottom surface of the bottom electrode. In some embodiments, the IC chip further comprises a substrate, a semiconductor device overlying the substrate and partially defined by the substrate, and a plurality of wires and a plurality of vias alternately stacked above the semiconductor device and electrically coupled at the semiconductor device and grouped into a plurality of wire levels and a plurality of via levels, respectively, the plurality of wires including bottom electrode wires and top electrode wires between which memory cells are disposed.

[0136] In some embodiments, the present invention provides a method comprising: forming a bottom electrode over a substrate, depositing a blocking layer, a ferroelectric layer, and a top electrode layer stacked over the substrate, patterning the top electrode layer to form a top electrode, and patterning the blocking layer and the ferroelectric layer to define individual blocking and ferroelectric layer segments into memory cells, where after patterning the ferroelectric layer, the bottom and top electrodes and the blocking and ferroelectric layer segments form memory cells, where the bottom and top electrodes comprise a metal, and the blocking layer is between the ferroelectric layer and the least electronegative metal among the bottom and top electrodes. In some embodiments, the method further comprises depositing a bottom electrode layer on the substrate, where the blocking layer, the ferroelectric layer, and the top electrode layer are deposited on the bottom electrode layer, and etching the bottom electrode layer, the ferroelectric layer, and the blocking layer using a common mask to pattern the bottom electrode layer into the bottom electrode and further pattern the blocking layer and the ferroelectric layer. In some embodiments, the common mask is further used to etch the top electrode layer and pattern the top electrode layer. In some embodiments, the method further comprises performing an anneal to increase the ferroelectric phase of the ferroelectric layer before patterning the top electrode layer and the blocking layer and the ferroelectric layer. In some embodiments, the blocking layer, the ferroelectric layer, and the top electrode layer are deposited on the bottom electrode and on the sidewalls of the bottom electrode. In some embodiments, forming the bottom electrode includes depositing a sacrificial layer over the dielectric layer covering the conductive wires, etching the dielectric layer and the sacrificial layer to form openings exposing the conductive wires, depositing a bottom electrode layer in the openings, planarizing from the bottom electrode layer to a top surface of the sacrificial layer, and removing the sacrificial layer. In some embodiments, patterning the top electrode layer, the blocking layer, and the ferroelectric layer includes etching back the top electrode layer, the blocking layer, and the ferroelectric layer to remove horizontally extending segments of the top electrode layer, the blocking layer, and the ferroelectric layer, and forming a sidewall structure on an upper sidewall portion of the bottom electrode, the sidewall structure including the top electrode and segments of the blocking layer and the ferroelectric layer.

[0137] The above outlines features of some embodiments so that those skilled in the art may better understand the following detailed description. Those skilled in the art should appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures to carry out the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present invention. [Industrial Applicability]

[0138] The IC chips containing the memory cells of the present invention and the methods of the present invention can be applied to many modern electronic devices that contain non-volatile memory. [Explanation of symbols]

[0139] 100, 200A, 200B, 300A, 400A, 500, 600A, 700A, 800, 900A, 900B, 900C, 900D, 1000, 1100A, 1100B, 1100C, 1100D, 1200A, 1200B, 1300, 1500, 1600A, 1600B, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2900, 3000, 3100, 3200, 3300, 3400, 3500, 3600: Cross-section 102: Memory cell 104: Blocking layer 104a: First blocking layer 104b: second blocking layer 106:Top electrode 106l:Top electrode layer 108: Ferroelectric layer 110: Bottom electrode 110l: Bottom electrode layer 300B, 400B, 600B, 700B, 1400: Top layout diagram 302: Interconnect structure 304: Wire 304a: Additional wires 304b: bottom electrode wire 304t: Top electrode wire 306: Beer 306b: Bottom electrode via (BEVA) 306t: Top electrode via (TEVA) 308: BEVA Barrier 310:BEVA body 312: Hard Mask 314: Sidewall spacer structure 316: Intermetal Dielectric (IMD) layer 316a: 1st IMD layer 316b: Second IMD layer 318: First etch stop layer 320: second etch stop layer 322: Buffer layer 402: First common side wall 404: Second common side wall 502: Bottom electrode barrier 1202:1 transistor 1 capacitor (1T1C) cell 1204: Drain region 1206: Drain side conductive path 1208: Circuit board 1210: Trench isolation structure 1212: Access transistor 1214:ILD layer 1216: Surrounding area 1218: Peripheral devices 1220: Source / drain region 1222: Gate electrode 1224: Gate dielectric layer 1226: Source side conductive path 1228: Source area 1230: Gate dielectric layer 1232: Gate electrode 1402: Memory array 1502: Ferroelectric field effect transistor (FeFET) 1504: Upper gate electrode 1506: Source / drain region 1508: Channel area 1510: Gate dielectric layer 1512: Floating gate electrode 1514: Hard Mask 1516: Sidewall spacer structure 1518: Contact etch stop layer 2502: Via opening 2602: Wire opening 2800: Block diagram 2802, 2804, 2806, 2808, 2810, 2812, 2814, 2816, 2818: Operation 3002: Sacrificial Layer 3102: Cell opening 3104: Photoresist mask A-A', B-B', C-C', D-D', E, F: Section line BL: bit line SL: Source line T b , T f :Thickness

Claims

1. 1. An integrated circuit (IC) chip comprising memory cells, The memory cell includes: a first electrode and a second electrode, both of which comprise a metal; a ferroelectric layer between the first electrode and the second electrode; a blocking layer between the ferroelectric layer and the first electrode, the blocking layer being amorphous; and Equipped with the blocking layer is configured to block a first metal of the first electrode from diffusing into the ferroelectric layer, the first metal of the first electrode having a lower electronegativity than a second metal of the second electrode, the electronegativity of the first metal being less than about 1.6; Integrated circuit (IC) chip.

2. The IC chip of claim 1 , wherein the blocking layer is a semiconductor.

3. 10. The IC chip of claim 1, wherein said blocking layer is a conductive metal oxide.

4. 1. An integrated circuit (IC) chip comprising memory cells, The memory cell includes: a bottom electrode at the bottom of the memory cell; a top electrode at the top of the memory cell; a ferroelectric layer between the bottom electrode and the top electrode; Equipped with a diffusion barrier layer between the ferroelectric layer and a first electrode, the diffusion barrier layer being amorphous, the first electrode being one of the bottom electrode and the top electrode, the first electrode comprising a metal having an electronegativity less than about 1.6; Integrated circuit (IC) chip.

5. 5. The IC chip of claim 4, wherein the ferroelectric layer, the diffusion barrier layer, and one or both of the bottom electrode and the top electrode share a common width.

6. 5. The IC chip of claim 4, wherein said ferroelectric layer, said diffusion barrier layer, and said bottom electrode have respective U-shaped contours that wrap around a bottom of said top electrode.

7. 5. The IC chip of claim 4, wherein said top electrode extends in a closed path around said bottom electrode, said top electrode having a bottom surface that is elevated relative to a bottom surface of said bottom electrode.

8. forming a bottom electrode on a substrate; depositing a blocking layer, a ferroelectric layer, and a top electrode layer over the substrate, the blocking layer being amorphous; patterning the top electrode layer to form a top electrode; patterning the blocking layer and the ferroelectric layer to define segments of the blocking layer and the ferroelectric layer that are individual to memory cells; Including, after patterning the blocking layer and the ferroelectric layer, the bottom electrode and the top electrode, and the segments of the blocking layer and the ferroelectric layer form the memory cell; the bottom electrode and the top electrode comprise a metal; the blocking layer is between the ferroelectric layer and the least electronegative metal electrode among the bottom electrode and the top electrode, the electronegativity of the least electronegative metal electrode being less than about 1.6; method.

9. 9. The method of claim 8, further comprising performing an anneal prior to said patterning of said top electrode layer and said patterning of said blocking layer and said ferroelectric layer to increase the ferroelectric phase of said ferroelectric layer.

Images