Highly Regular Logic Design for Efficient 3D Integration Related Applications

Abstract

The integrated circuit includes an array of unit cells, each of which includes a field effect transistor arranged in a stack. A local interconnect structure forms selective conductive paths between select terminals of the field effect transistors that define cell circuitry confined within each unit cell. An array of contacts is disposed on accessible faces of the unit cells, each contact electrically coupled to a corresponding electrical node of the cell circuitry.

Description

[Technical field]

[0001] This application claims priority under 35 U.S.C. §119(e) from U.S. Provisional Patent Application No. 62 / 879,721, filed July 29, 2019, entitled “Ultra-regular Logic Design for Efficient 3D Integration,” and U.S. Patent Application Publication No. 16 / 847,001, filed April 13, 2020, entitled “HIGHLY REGULAR LOGIC DESIGN FOR EFFICIENT 3D INTEGRATION RELATED APPLICATION DATA,” the disclosures of which are incorporated herein by reference in their entireties.

[0002] The present disclosure relates to the fabrication of integrated circuits and microelectronic devices. [Background technology]

[0003] In the manufacture of semiconductor devices (especially on a microscopic scale), various fabrication processes such as thin film formation deposition, etch mask creation, patterning, material etching and removal, and doping processes are performed. These processes are repeated to form the desired semiconductor device elements on the substrate. Historically, in microfabrication, transistors have been created in one plane with wiring / metallization formed above the active device plane, and are therefore characterized as two-dimensional (2D) circuits using 2D fabrication techniques. Although scaling efforts have significantly increased the number of transistors per unit area in 2D circuits, these scaling efforts face greater challenges as scaling enters single nanometer semiconductor device fabrication nodes. Semiconductor device manufacturers have expressed a desire for three-dimensional (3D) semiconductor circuits in which transistors are stacked on top of each other.

[0004] 3D integration (3Di) is seen as a viable option for continued semiconductor scaling efforts, despite the inevitable saturation of critical dimension scaling. Due to manufacturing variations and electrostatic limitations, once the contacted gate pitch reaches its scaling limit, scaling of 2D transistor density will not proceed any further. Even experimental new transistor designs that may one day overcome these contacted gate pitch scaling limits, such as vertical channel gate-all-around transistors, have their own scaling issues due to resistance, capacitance, and reliability concerns, thereby limiting the density at which transistors can be wired into circuits.

[0005] 3Di, or vertical stacking of multiple devices, aims to overcome these scaling limitations by increasing transistor density in volume rather than area. While this concept has been successfully demonstrated and implemented by the flash memory industry (e.g., 3D NAND), mainstream complementary metal-oxide semiconductor (CMOS) very large scale integrated circuit (VLSI) manufacturers of CPU and GPU products remain hesitant to embrace 3D integration as the primary means of advancing their semiconductor roadmaps. The primary reason for this lack of adoption of 3Di for anything other than niche applications (e.g., memory stacked on top of logic for machine learning accelerators used in artificial intelligence chips) is the inherent inefficiency of known proposals.

[0006] One approach to successful semiconductor scaling is to leverage the modest increase in processing complexity and cost across a significantly larger number of transistors. In 2D scaling, this has been achieved primarily by decreasing feature size and increasing transistor density at a fixed wafer manufacturing cost. However, 3D integration approaches that double the transistor density in volume by incurring twice the manufacturing cost do not provide a viable scaling solution. Successful scaling with 3Di lies in a radical reduction in process and design complexity to minimize node-to-node cost increases. Summary of the Invention [Means for solving the problem]

[0007] The integrated circuit includes an array of unit cells, each of which includes a field effect transistor arranged in a stack. A local interconnect structure forms selective conductive paths between select terminals of the field effect transistors that define cell circuitry confined within each unit cell. An array of contacts is disposed on accessible faces of the unit cells, each contact being electrically coupled to a corresponding electrical node of the cell circuitry.

[0008] In additional or alternative aspects of the inventive concepts disclosed herein, an integrated circuit includes a functionalization layer including conductive wiring segments formed between select contacts on each accessible face of one or more unit cells in the array.

[0009] In another additional or alternative aspect of the inventive concepts disclosed herein, the unit cells have a common footprint and are positioned in the array such that the diffusion break surrounding the cell circuitry of each unit cell aligns with the diffusion breaks in adjacent unit cells to form a continuous space extending across all unit cells in a respective column of the array.

[0010] In yet another additional or alternative aspect of the inventive concepts disclosed herein, the integrated circuit includes a power wall disposed in a contiguous space that provides power to at least the unit cells of each column of the array.

[0011] In another additional or alternative aspect of the inventive concepts disclosed herein, an upper surface of each power supply wall is exposed on an accessible face of each unit cell in a column of the array.

[0012] In yet another additional or alternative aspect of the inventive concepts disclosed herein, the cell circuitry is identical across all unit cells of the array.

[0013] In another additional or alternative aspect of the inventive concepts disclosed herein, the cell circuitry is constructed from similar front-end-of-line and mid-end-of-line processes.

[0014] In yet another additional or alternative aspect of the inventive concepts disclosed herein, the front-end of the line process and the mid-end of the line process include a multiplication patterning process.

[0015] In another additional or alternative embodiment of the inventive concepts disclosed herein, the multiplication patterning process includes self-assembled lithography and / or self-aligned multiple exposure patterning.

[0016] In yet another additional or alternative aspect of the inventive concepts disclosed herein, field effect transistors are stacked in complementary pairs.

[0017] In another additional or alternative aspect of the inventive concepts disclosed herein, the gates of a complementary pair of field effect transistors are connected together.

[0018] In yet another additional or alternative embodiment of the inventive concepts disclosed herein, the number of complementary pairs in the stack of field effect transistors is greater than one.

[0019] It should be understood that this Summary section does not identify every embodiment and / or incrementally novel aspect of the present disclosure or claimed invention. Rather, this Summary merely provides a preliminary discussion of different embodiments and corresponding points of novelty over the prior art. The Detailed Description section and corresponding drawings of this disclosure provide additional details and / or possible perspectives of the invention and embodiments. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a top plan view illustration of an example unit cell in which the principles of the present disclosure may be implemented. [Figures 2A-2E] FIG. 2 reveals the internal 3D structure of the example unit cell shown in FIG. 1. [Figure 3A] 1 is an illustration of a 10×10 array of unit cells according to principles described herein to highlight the regularity of the front-end-of-line (FEOL) and mid-end-of-line (MEOL) layouts. [Figure 3B] 1 is an illustration of a unit cell array, showing only the active channel region and source / drain contacts according to principles described herein. [Figure 3C] 1 is an illustration of a unit cell array showing a grid of cut masks according to principles described herein. [Figure 3D] 1 is an illustration of a unit cell array with VDD and VSS power rails shown in accordance with principles described herein. [Figure 4] 1 is an illustration of a top plan view of a unit cell undergoing functionalization to form a two-fingered inverter (INV2) logic cell according to principles described herein. [Diagram 5] 1 is a top plan view illustration of a pair of unit cells enabled into a two-input AND-OR-invert (AOI22) logic cell according to principles described herein. [Figure 6]1 is a top plan view illustration of a pair of unit cells that are enabled into a two-input AND (AND2) logic cell according to principles described herein. [Figure 7] FIG. 1 is a top plan view illustration of a pair of unit cells, each having a single CFET pair within their respective active device stacks opposite two CFET pairs, which are enabled into a two-input NOT-AND (NAND2) logic cell according to the principles described herein. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The inventive concept is best explained through certain embodiments of the invention, which are described in detail herein with reference to the accompanying drawings, in which like reference numerals refer to like features throughout. It should be understood that the term "invention" as used herein is intended to encompass the inventive concept underlying the embodiments described below, and not merely the embodiments themselves. Furthermore, it should be understood that the general inventive concept is not limited to the exemplary embodiments described below, and the following description should be read in this light.

[0022] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment of a structure, process, design, technique, etc., referred to herein as exemplary is not necessarily to be construed as preferred or advantageous over other such embodiments. No particular quality or suitability of an embodiment shown herein as exemplary is intended or should be inferred.

[0023] The techniques herein include methods of integrated circuit and semiconductor device fabrication that use common front-end-of-line and middle-end-of-line structures for all logic cells and then functionalize these generic unit cells in lower level metallization. One embodiment includes an integrated circuit having an array of unit cells. Each unit cell may have the same unit cell height and the same unit cell width. Each unit cell may have at least two vertical levels of transistors, with a first field effect transistor located above a second field effect transistor in a stack. Each field effect transistor may have a gate-all-around channel. Each unit cell may include local interconnect wiring that electrically connects the source / drain and gate structures. One or more wiring levels may be located directly above the array of unit cells, where at least two different types of functional logic cells may be formed from the array of unit cells. Thus, such techniques may provide 3D integration with process simplification and cost reduction.

[0024] The techniques herein include techniques by which integrated circuits are physically constructed or realized as physical objects, including techniques by which integrated circuits are designed and manufactured. Indeed, those skilled in the art and by understanding this disclosure can transfer the principles described herein to suitable electronic / engineering design automation (EDA) and foundry platforms in which the structures described herein can be physically constructed and / or used as components of a broader circuit design. The techniques herein find particular applicability to monolithically integrated 3D CMOS (complementary metal oxide semiconductor) circuits, as described in U.S. Provisional Patent Application No. 62 / 727,097, filed September 5, 2018, entitled "Architecture Design and Processes for Manufacturing Monolithically Integrated 3D CMOS Logic and Memory," which is incorporated herein by reference in its entirety.

[0025] Logic functionality can be performed as a back-end-of-line (BEOL) operation, for example, through metallization on a readily accessible grid of contacts that provide electrical access to the internal circuit components of the three-dimensional unit cell.

[0026] The embodiments herein include setting a common two contacted poly pitch (cpp) footprint to the unit cell width. Although this restriction limits the unit cells to a single transistor track flanked on either side by a single diffusion break, this design enables substantial scaling benefits and promotes significant complexity reduction. For example, designing all unit cells to a fixed width footprint results in alignment of the diffusion breaks across all rows of the corresponding logic block. This arrangement facilitates the formation of local power rails that operate in the unoccupied space of the diffusion breaks, providing unobstructed access to the source regions of the devices without blocking signal tracks. This arrangement also provides a highly uniform local layout environment, thereby eliminating complex layout-dependent device variability that becomes a significant performance crippler at advanced technology nodes. By using unit cells with equal widths and common used equal heights, logic functions that require more transistors than are available in a single transistor track width stack can be configured by optimally abutting unit cells vertically or horizontally, providing critical freedom in simplifying wiring geometries.

[0027] FIG. 1 is an illustration of a top plan view of an example unit cell 100 in which the principles of the present disclosure may be embodied. The cell view of FIG. 1 shows an accessible surface 105 of the unit cell 100 across which a number of cell contacts 130a-130j, collectively referred to herein as cell contacts 130, are disposed. Each cell contact 130 is electrically connected to a node of a cell circuit constructed below the accessible surface 105. For example, the unit cell 100 may include a double stack of complementary field effect transistor (CFET) circuits, i.e., two pairs of common gate n-type and p-type transistor pairs stacked one on top of the other, collectively referred to herein as an active device stack. An example of such an active device stack is shown in FIG. 2. In the example embodiment of FIG. 1, such a device stack may be limited to a four track (4T) high and 2 cpp wide cell, as shown in FIG. 1, indicated by tracks 140a-140d, collectively referred to herein as track 140. In such a double-stack configuration, four active channels may be established in each active region 150 and controlled by voltages applied to and interconnections established across the cell contacts 130. For example, cell contacts 130a and 130c may be connected to the bottom p-diffusion layer, cell contacts 130d and 130e may be connected to the top p-diffusion layer, cell contacts 130f and 130g may be connected to the top n-diffusion layer, cell contacts 130h and 130j may be connected to the bottom n-diffusion layer, and cell contacts 130b and 130i may be connected to the common polysilicon gates of the upper and lower CFET pairs, respectively. These contacts may also be considered as follows:Cell contacts 130a and 130c may serve as source and drain contacts for the p-type transistors of the lower CFET pair, cell contacts 130d and 130e may serve as source and drain contacts for the p-type transistors of the upper CFET pair, cell contacts 130f and 130g may serve as source and drain contacts for the n-type transistors of the upper CFET pair, cell contacts 130h and 130j may serve as source and drain contacts for the n-type transistors of the lower CFET pair, and cell contacts 130b and 130i may serve as a common gate contact for the upper and lower CFET pairs. This contact assignment is not required to implement the inventive concepts described herein. Other contact assignments are possible and may depend on the internal architecture of the unit cells.

[0028] In addition to the cell contacts 130, the accessible face 105 further exposes the top surfaces of the VDD power wall 110 and the VSS power wall 120. In one embodiment, the VDD power wall 110 and the VSS power wall 120 are constructed as walls that extend upward from the substrate surface to the accessible face 105. Thus, the VDD power wall 110 and the VSS power wall 120 are accessible to local interconnects inside the unit cell 100 as well as wiring in the accessible face 105. Thus, such local interconnects may directly connect to the VDD power wall 110 and / or the VSS power wall 120 for transistor biasing, etc., as opposed to making such connections at the accessible face 105. In one embodiment, the VDD power wall 110 and the VSS power wall 120 may each be located within the space of a single diffusion break, and each may cross cell boundaries as available to adjacent cells, as shown in FIG. 1.

[0029] Also shown in FIG. 1 are four active areas 150 in the exemplary unit cell 100. However, it should be understood that each of the four active areas may include multiple channels through which current flows from source to drain (or vice versa). For example, each active area 150 may include multiple current carrying components, such as nanowires or nanosheets, in a gate-all-around (GAA) configuration. Other active areas may also be realized in embodiments of the present invention, typically depending on the technology node at which the unit cell is designed and fabricated.

[0030] Figure 2, which includes Figures 2A-2E, reveals the internal 3D structure of unit cell 100 through multiple cross-sectional views. Different views are shown in Figures 2A-2D and with reference to Figure 2E. Figure 2E shows accessible face 105 and cell contacts 130 shown in and described with reference to Figure 1. It should be understood that Figure 2, including Figures 2A-2E, is a schematic diagram and is not drawn to scale.

[0031] 2A depicts a cross section through a bottom local interconnect 215, which may connect cell contact 130a to the source / drain of the bottom transistor 210a in active device stack 250, a local interconnect 235, which may connect cell contact 130c to the drain / source of the bottom transistor 210a in active device stack 250, and a top gate polysilicon interconnect 230, which may connect cell contact 130b to the common gate of the top CFET pair including transistors 210c and 210d. Note that in one embodiment, VDD power wall 110 and VSS power wall 120 may be connected to buried power rails, representatively shown at buried power rails 112 and 122, respectively, and that the top surfaces of VDD power wall 110 and VSS power wall 120 are exposed on accessible surface 105.

[0032] 2B represents a cross section through local interconnect 215, local interconnect 220, which may connect cell contact 130f to the drain / source of transistor 210c in active device stack 250, local interconnect 225, which may connect cell contact 130h to the source / drain of transistor 210c of active device stack 250, and cell contact 130d, which may be directly connected to the source / drain of the top transistor 210d of active device stack 250. In addition, FIG. 2B represents a cross section through a portion of active device stack 250.

[0033] 2C represents a cross section through a common gate in active device stack 250. Each of the upper and lower CFET pairs may be connected through polysilicon interconnects 230 and 240 to respective cell contacts 130b and 130i.

[0034] FIG. 2D represents a cross section through a local interconnect 225, which may connect cell contact 130a to the source / drain of the bottommost transistor 210a in active device stack 250, an interconnect 245, which may connect cell contact 130j to the drain / source of the topmost transistor 210d in active device stack 250, and a bottom gate polysilicon interconnect 240, which may connect cell contact 130i to the common gate of the bottommost CFET pair including transistors 210a and 210b.

[0035] According to embodiments of the inventive concepts disclosed herein, signal and power connections may be routed on a plane above the active device stack 250, e.g., on the accessible face 105, as functionalized in local conductive wiring above what is referred to herein as a functionalization layer. The local power rail may operate within the space of a single diffusion break. Thus, each unit cell may have uniform dimensions and, optionally, uniform geometry including transistors, gates, and local interconnects.

[0036] FIG. 3A is an illustration of a 10×10 array 300 of unit cells to highlight the regularity of the front-end-of-line (FEOL) and mid-end-of-line (MEOL) layout. For identification purposes, each cell in the array 300 is associated in FIG. 3A with a column identifier and a row identifier. For example, unit cell 3F refers to the unit cell in column 3 and row F of the array 300. It should be appreciated that as far as the FEOL and MEOL layouts are concerned, the array 300 is highly regular, and thus various manufacturing processes may be utilized to simplify the overall manufacturing effort and reduce costs. In one embodiment, the array 300 may be a monolithic integrated circuit, with the unit cells all constructed on a single substrate (not shown).

[0037] 3B is an illustration of a unit cell array 300 in which the active channel region is only representatively shown in active channel region 310 and the source / drain contacts are only representatively shown in source / drain contact 320. FIG. 3B highlights the possible use of low-cost upconversion patterning techniques (e.g., self-assembled lithography) or self-aligned multiple patterning, such as self-aligned double / triple / quadruple patterning, to image these critical features.

[0038] FIG. 3C is an illustration of unit cell array 300 showing a grid of cut masks, representatively shown in cut masks 330a and 330b, which may optionally provide a low-cost high-precision solution to form local interconnects and line ends for poly gates.

[0039] 3D is an illustration of a unit cell array 300 showing a VDD power rail, typically shown at VDD power rail 340, and a VSS power rail, typically shown at VSS power rail 350. It should be understood that these power rails are located within the space left by the diffusion break. Also shown in FIG. 3D is a macro-level power rail, typically shown at macro-level power rail 360, that supplies power to the local power rails.

[0040] FIG. 4 is an illustration of a top plan view of a unit cell 400 that has been functionalized through a back-end-of-line (BEOL) process. The unit cell 400 may have the same internal architecture as the unit cell 100 described above. The cell contacts, typically shown at cell contact 403, may be distributed across the accessible side 401 to connect to the same internal circuit nodes to which the similarly located cell contacts 130 of the unit cell 100 are connected. In the illustrated embodiment, a first metal 415 and a second metal 420 are disposed on the accessible side 401 to connect to the target unique cell contact 403, thereby forming a unique logic cell. The unique logic cell is, in the case of FIG. 4, a two-finger inverter (INV2). In this example embodiment, three levels of highly ordered and unidirectional metal connections are used. First, VDD power taps 430a and 430b and VSS power taps 460a and 460b may connect unique source / drain contacts to local power rails, i.e., VDD power rail 425 and VSS power rail 455. On a separate layer of local wiring, the vertically oriented source / drain and / or gate contacts may be connected by a first metal, representatively shown in first metal connection 415. On yet another layer of local wiring, input / output pins of logic cells, such as top gate contact 405 electrically connected to bottom gate contact 445 serving as logic cell input pin, cell contact 440 serving as n-type output pin, and cell contact 450 serving as p-type output pin, may be constructed through a second metal, representatively shown in second metal connection 420. A circuit router may connect other circuit components to the second metal. In one embodiment, a signal via, representatively shown at 410, may be constructed to connect an input pin attached to a second metal arranged horizontally across the accessible surface 401 to local wiring of a first metal arranged vertically across the accessible surface 401.

[0041] 5 is a top plan view illustration of a pair of unit cells 505a and 505b, each of which may be constructed identically to unit cell 100 of FIGS. 1 and 2, which are enabled to function as a two-input AND-OR-invert (AOI22) logic cell 500. As in FIG. 4, a first metal connection, typically shown at first metal connection 515, is oriented vertically, a second metal connection, typically shown at second metal connection 520, is oriented horizontally, and a power tap, typically shown at power tap 525, is placed as required. The embodiment shown in FIG. 5 demonstrates the efficient use of first metal connection 510 to fix the output of a p-type "A" transistor to the input of a p-type "B" transistor at the vertical cell junction to form an AOI22 logic cell 500.

[0042] 6 is a top plan view illustration of a pair of unit cells 605a and 605b, each of which may be constructed identically to unit cell 100 of FIGS. 1 and 2, with each of the unit cells functioning as a two-input AND (AND2) logic cell 600, essentially a two-input NOT-AND circuit (NAND2 of unit cell 605a) connected to a dual-output inverter circuit (INV2 of unit cell 605b). As in FIG. 4, the first metal connection, representatively shown at first metal connection 615, is oriented vertically, the second metal connection, representatively shown at second metal connection 620, is oriented horizontally, and the power tap, representatively shown at power tap 625, is placed as required. The embodiment shown in FIG. 6 demonstrates the efficient use of second metal connection 610 to pin the output of the NAND2 circuit to the gate of the INV2 circuit at a horizontal junction to form AND2 logic cell 600.

[0043] Figure 7 is an illustration of a top plan view of a pair of unit cells 705a and 705b, each of which has a single CFET pair in its respective active device stack as opposed to the two CFET pairs of the embodiment of Figures 1 and 2. Figure 7 demonstrates how the design methodology described herein can be applied to other 3Di approaches. In the embodiment shown in Figure 7, a two-input NOT-AND (NAND2) logic cell 700 is constructed as a functioning technology similar to that described above.

[0044] Table 1 shows the sample domain scaling achieved using the techniques herein compared to a relatively aggressive 5T 2D design. Note that the scale factors indicate the significant scaling benefits provided by the techniques herein.

[0045] [Table 1]

[0046] An embodiment of the inventive concepts described herein may include an integrated circuit or semiconductor device having an array of uniform unit cells. A fixed footprint (width and height) unit cell contains all front-end-of-line (FEOL, e.g., device, source / drain, gate) and middle-end-of-line (MEOL, e.g., local interconnect) features. An array of uniform and fixed pitch contacts may be provided to route all signal and power connections to accessible planes on the device stack. A set of local power rails running parallel to the polysilicon gate connections may use the space of the diffusion break. Logic synthesis may be achieved by abutting unit cells either horizontally (i.e., forming wide standard logic cells) or vertically (forming tall standard logic cells). A set of regular and unidirectional metal shapes may be used to enable unit cells for standard cell logic or for large block synthesis (e.g., mapping large logic blocks to the local wiring of an array of unit cells).

[0047] In the above description, specific details have been set forth, such as specific geometries and descriptions of various components and processes used to construct such components. However, it should be understood that the technology described herein may be implemented in other embodiments that deviate from these specific details, and such details are for the purposes of explanation and not for the purposes of limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numbers, materials, and configurations have been set forth to provide a thorough understanding. However, the embodiments may be implemented without such specific details. Components having substantially the same functional configurations are indicated by similar reference symbols, and therefore any redundant description may be omitted.

[0048] To aid in understanding various embodiments, various techniques have been described as multiple discrete operations. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0049] It should be understood that the order of consideration of the different steps as described herein is presented for clarity. In general, these steps may be performed in any suitable order. In addition, although each of the different features, techniques, configurations, etc. herein may be discussed in different parts of this disclosure, it is intended that each of those concepts may be performed independently of each other or in combination with each other. Thus, the present invention may be embodied and considered in many different ways.

[0050] As used herein, "substrate" or "target substrate" refers generally to an object to be processed according to the present invention. The substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be a base substrate structure, such as a semiconductor wafer, a reticle, or a layer on or overlying a base substrate structure, such as a thin film. Thus, the substrate is not limited to any particular base structure, underlying or overlying layer, patterned or unpatterned, but rather is intended to include any such layer or base structure, and any combination of layers and / or base structures. Although the description may refer to a particular type of substrate, this is for illustrative purposes only.

[0051] The above description is intended to illustrate possible implementations of the inventive concept, but is not intended to be limiting. Many variations, modifications, and alternatives will become apparent to those skilled in the art upon review of this disclosure. For example, equivalent components to those shown and described can be substituted, separately described elements and methods can be combined, and separately described elements can be distributed across multiple components. Thus, the scope of the present invention should be determined not by reference to the above description, but by reference to the appended claims and their full scope of equivalents.

Claims

1. 1. An integrated circuit comprising: an array of unit cells, each unit cell comprising: Field effect transistors arranged in a stack; a local interconnect structure including select conductive paths between select terminals of said field effect transistors defining cell circuitry confined within said unit cell; an array of contacts disposed on an accessible surface of the unit cell, each contact being electrically coupled to a corresponding electrical node of the cell circuit; Including, the unit cells have a common footprint and are arranged in the array such that a diffusion break surrounding the cell circuitry of each unit cell aligns with the diffusion break in an adjacent unit cell to form a continuous space extending across all unit cells in a respective column of the array; The integrated circuit further comprises a power wall disposed in the continuous space, the power wall supplying power to at least the unit cells of the respective columns of the array; an upper surface of the power supply wall is exposed on the accessible face of each unit cell of the respective column of the array; Integrated circuits.

2. 10. The integrated circuit of claim 1 further comprising a functionalization layer including conductive wiring segments formed between select contacts on accessible faces of each of one or more unit cells in the array.

3. The integrated circuit of claim 1 , wherein a bottom surface of each said power wall is connected to a buried power rail.

4. 2. The integrated circuit of claim 1, wherein said cell circuitry is identical across all unit cells of said array.

5. 5. The integrated circuit of claim 4, wherein the cell circuitry is constructed from front-end-of-line and middle-end-of-line structures that extend across the unit cell.

6. The integrated circuit of claim 1 , wherein the field effect transistors are stacked in complementary pairs.

7. 7. The integrated circuit of claim 6, wherein the gates of each of the complementary pair of field effect transistors are electrically connected to each other.

8. 8. The integrated circuit of claim 7, wherein the number of said complementary pairs in said stack of field effect transistors is greater than one.

9. The integrated circuit of claim 1 , wherein the field effect transistors are stacked in a plane parallel to the accessible surface.

10. The integrated circuit of claim 1 , wherein the integrated circuit is monolithic.

11. 1. An integrated circuit comprising: A plurality of identical unit cells are provided with electrical contacts disposed across an underlying surface, each unit cell comprising: Transistors arranged in a stack; a local interconnect structure including select conductive paths between select terminals of said transistors defining cell circuitry confined within said unit cells; Including, a select node of the cell circuit is connected to the electrical contact disposed on the stack of transistors of each unit cell; The integrated circuit further comprises a power wall disposed in a contiguous space between the groups of unit cells, the power wall providing power to at least the unit cells of the corresponding group of unit cells; an upper surface of the power supply wall is exposed on the surface on which the electrical contacts are disposed, the surface being an accessible surface; Integrated circuits.

12. 12. The integrated circuit of claim 11, further comprising a functionalization layer including conductive trace segments formed between select ones of said electrical contacts.

13. The integrated circuit of claim 11 , wherein a selected local interconnect structure of said local interconnect structure is connected to at least one of said power walls.

14. 12. The integrated circuit of claim 11, wherein field effect transistors are stacked in a plane parallel to the plane in which the electrical contacts are disposed.

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