Solid-state imaging device and image processing method

Abstract

[Problem] To provide a solid-state imaging device and an image processing device that are capable of reducing the amount of time required for generating a reduced image and performing image processing. [Solution] A solid-state imaging device according to the present disclosure includes: a pixel array that performs photoelectric conversion and that contains a plurality of pixels; a plurality of AD conversion units that are provided so as to correspond to the plurality of pixels and that digitally convert pixel signals coming from the pixels; a plurality of first memory units that are provided so as to correspond to the plurality of AD conversion units and that store the pixel signals digitally converted by the AD conversion units; and a plurality of second memory units, each of which is provided for each of N (N is an integer that is equal to or greater than 2) pixels or N AD conversion units.

Description

[Technical field]

[0001] The present disclosure relates to a solid-state imaging device and an image processing method. [Background technology]

[0002] Image processing techniques such as object detection and tracking use reduced images that are hierarchically reduced from the original images. However, to generate a reduced image, it was necessary to transfer the original image to a frame memory (such as a dynamic random access memory (DRAM)) outside the pixel array and generate a reduced image from the original image using the frame memory. In this case, since the reduced image was generated after the original image, which had a large amount of data, was transferred, it took time to generate the reduced image and perform image processing such as object detection. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Patent Publication No. 2018 / 047618 [Patent Document 2] International Patent Publication No. 2016 / 136448 Summary of the Invention [Problem to be solved by the invention]

[0004] A solid-state imaging device and an image processing method are provided that can reduce the time required for generating a reduced image and for processing the image. [Means for solving the problem]

[0005] A solid-state imaging device according to one aspect of the present disclosure comprises a pixel array including a plurality of pixels that perform photoelectric conversion, a plurality of AD conversion units provided corresponding to each of the plurality of pixels and that digitally convert pixel signals from the pixels, a plurality of first memory units provided corresponding to each of the plurality of AD conversion units and that store the pixel signals digitally converted by the AD conversion units, and a plurality of second memory units provided one for each of N pixels (N is an integer greater than or equal to 2) or N AD conversion units.

[0006] The device may further include a signal processing circuit that performs arithmetic processing on a signal from the first or second memory unit, and a selection circuit that receives an output signal from the signal processing circuit and transfers the output signal to either the first or second memory unit.

[0007] The signal processing circuit may generate one first reduced signal from the plurality of pixel signals from the first and second memory units, and the selection circuit may store the first reduced signal in either the first or second memory unit.

[0008] The second memory unit may be provided for every two pixels.

[0009] The signal processing circuit may compress the multiple pixel signals stored in the multiple first memory units by a factor of four to generate multiple first reduced signals, and some of the multiple second memory units may store each of the first reduced signals.

[0010] The signal processing circuit may compress the multiple first reduced signals stored in the multiple second memory units by a factor of four to generate multiple second reduced signals, and while the multiple first memory units hold the multiple pixel signals, other second memory units among the second memory units may store each of the second reduced signals.

[0011] After the plurality of first reduced signals or the plurality of second reduced signals are transferred outside the second memory unit, the pixel signal may be transferred outside the first memory unit.

[0012] The signal processing circuit may further compress the multiple second reduced signals stored in the multiple second memory units by a quarter to generate multiple third reduced signals, and while the multiple first memory units hold the multiple pixel signals and the multiple second memory units hold the second reduced signals, another second memory unit stores each of the third reduced signals, and the signal processing circuit may further compress the multiple nth (n≧3)th reduced signals stored in the multiple second memory units by a quarter to generate multiple n+1th reduced signals, and the yet another second memory unit stores each of the n+1th reduced signals.

[0013] The second memory unit may be provided for every three pixels.

[0014] The signal processing circuit may compress the multiple pixel signals stored in the multiple first memory units by a factor of four to generate multiple first reduced signals, and some of the multiple second memory units may store each of the first reduced signals.

[0015] The signal processing circuit may compress the multiple first reduced signals stored in the multiple second memory units by a factor of four to generate multiple second reduced signals, and while the multiple first memory units hold the multiple pixel signals, other second memory units among the second memory units may store each of the second reduced signals.

[0016] After the plurality of first reduced signals or the plurality of second reduced signals are transferred outside the second memory unit, the pixel signal may be transferred outside the first memory unit.

[0017] The signal processing circuit may further compress the multiple second reduced signals stored in the multiple first memory units by a quarter to generate multiple third reduced signals, and while the multiple first memory units hold the multiple pixel signals and the multiple second memory units store the second reduced signals, another second memory unit may store each of the third reduced signals, and the signal processing circuit may further compress the multiple nth (n≧3)th reduced signals stored in the multiple second memory units by a quarter to generate multiple n+1th reduced signals, and another second memory unit may store each of the n+1th reduced signals.

[0018] The second memory unit may be provided for every four pixels.

[0019] The signal processing circuit may compress the pixel signals stored in the first memory units by a factor of four to generate first reduced signals, and the second memory units may store the first reduced signals.

[0020] The signal processing circuit may compress the multiple first reduced signals stored in the multiple second memory units by a factor of four to generate multiple second reduced signals, and the first memory units may store each of the second reduced signals.

[0021] After the pixel signals stored in the plurality of first memory units are transferred to the outside of the first memory units, the plurality of first memory units may store the respective second reduced signals.

[0022] The signal processing circuit may further compress the multiple second reduced signals stored in the multiple first memory units by a factor of four to generate multiple third reduced signals, and the first or second memory unit may store each of the third reduced signals, and the signal processing circuit may further compress the multiple nth (n≧3)th reduced signals stored in the multiple first or second memory units by a factor of four to generate multiple n+1th reduced signals, and the first or second memory unit may store each of the n+1th reduced signals.

[0023] An image processing method according to one aspect of the present disclosure is an image processing method using a solid-state imaging device having a pixel array including a plurality of pixels that perform photoelectric conversion, a plurality of AD conversion units provided corresponding to each of the plurality of pixels, a plurality of first memory units provided corresponding to each of the plurality of AD conversion units, and a plurality of second memory units provided one for each of N (N is an integer of 2 or more) pixels or N AD conversion units, and includes digitally converting pixel signals from the pixels, storing the pixel signals digitally converted by the AD conversion units in the plurality of first memory units, generating a single first reduced signal from the plurality of pixel signals from the plurality of first memory units, and storing the plurality of first reduced signals in either the first or second memory unit.

[0024] The first reduced signals may be signals generated by compressing the pixel signals by a factor of four. [Brief description of the drawings]

[0025] [Figure 1] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment of the present technology. [Diagram 2] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present technology. [Diagram 3] 2 is a schematic diagram showing a pixel array section and an ADC section of a peripheral circuit section. [Figure 4] FIG. 4 is a schematic diagram showing a configuration example of a portion of an ADC unit. [Diagram 5] FIG. 2 is a diagram showing a further detailed configuration of a portion of the ADC unit. [Figure 6A] 4 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to the first embodiment. FIG. [Figure 6B] 4 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to the first embodiment. FIG. [Figure 6C] 4 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to the first embodiment. FIG. [Figure 6D] 4 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to the first embodiment. FIG. [Figure 6E] 4 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to the first embodiment. FIG. [Figure 7] FIG. 1 is a conceptual diagram showing original pixels and a reduced image. [Figure 8] 11 is a graph showing the transfer times of an original image and a reduced image. [Figure 9A] 13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a second embodiment. FIG. [Figure 9B] 13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a second embodiment. FIG. [Figure 9C]13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a second embodiment. FIG. [Figure 9D] 13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a second embodiment. FIG. [Figure 9E] 13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a second embodiment. FIG. [Figure 10A] 13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a third embodiment. FIG. [Figure 10B] 13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a third embodiment. FIG. [Figure 10C] 13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a third embodiment. FIG. [Figure 10D] 13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a third embodiment. FIG. [Figure 10E] 13 is a conceptual diagram showing pixel signals or reduced signals stored in first and second memory units according to a third embodiment. FIG. [Figure 11] 11 is a graph showing the transfer times of an original image and a reduced image. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings. The drawings are schematic or conceptual, and the ratios of each part are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with respect to the previously mentioned drawings are given the same reference numerals, and detailed descriptions are omitted as appropriate.

[0027] (First embodiment)

[0028] 1 is a perspective view showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. The solid-state imaging device 100 is configured by stacking a semiconductor chip 511 and a semiconductor chip 512. The semiconductor chip 511 includes a pixel array section 240 formed on a semiconductor substrate. The semiconductor chip 512 includes an ADC section 280 and other peripheral circuits formed on another semiconductor substrate. The semiconductor chips 511 and 512 are formed as separate semiconductor chips and then stacked.

[0029] Each pixel of the pixel array section 240 of the semiconductor chip 511 and elements such as the ADC section 280 of the semiconductor chip 512 are electrically connected using a through electrode such as a TSV (Through Silicon Via) provided in a via region around the pixel array section 240 and the ADC section 280. Alternatively, both semiconductor chips may be bonded together so that the wiring of the semiconductor chip 511 and the wiring of the semiconductor chip 511 are in contact with each other (Cu-Cu bonding). Furthermore, the pixel array section 240 and the ADC section 280 may be configured as one semiconductor chip, and the configuration of other peripheral circuits may be configured as other semiconductor chips. Furthermore, the pixel array section 240, the ADC section 280, and other peripheral circuits may all be configured as one semiconductor chip. The number of layers of the semiconductor chip may be three or more.

[0030] 2 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. A plurality of pixel circuits 250 are arranged in a two-dimensional lattice in a pixel array section 240 on a semiconductor chip 511. The pixel circuits 250 have a photoelectric conversion element (not shown), receive power from a voltage source 180, and perform photoelectric conversion of incident light to generate electric charges. In the ADC section 280 on the semiconductor chip 512, a plurality of ADC circuits 290 are arranged in a two-dimensional lattice. The ADC circuits 290 are provided corresponding to the pixel circuits 250, respectively, and convert pixel signals (analog signals) from the pixel circuits 250 into digital signals. In the present technology, the ADC circuits 290 are provided corresponding to the pixel circuits 250, respectively, and therefore pixel signals simultaneously detected by all pixel circuits 250 in the pixel array section 240 can be immediately and simultaneously AD converted. The digital signal converted from analog to digital by the ADC circuit 290 undergoes signal processing such as CDS (Correlated Double Sampling) processing. Thereafter, the digital signal is transferred to the frame memory 115 via the transfer circuit 260, and is detected and processed by a DSP (Digital Signal Processing) circuit 120 provided inside the semiconductor chip 512. Alternatively, the digital signal may be transferred to a DSP circuit (not shown) outside the semiconductor chips 511 and 512 and detected and processed there. In this way, after CDS processing, the digital signal may be detected and processed within the same semiconductor chip or may be detected and processed in a different semiconductor chip.

[0031] 3 is a schematic diagram showing a pixel array section and an ADC (Analogue-to-Digital Converter) section. As described above, the pixel array section 240 includes a plurality of pixel circuits 250 that perform photoelectric conversion. The pixel circuits 250 as pixels are two-dimensionally arranged on a semiconductor substrate.

[0032] The ADC unit 280 includes a plurality of ADC circuits 290 that digitally convert pixel signals from the pixel circuits 250. The ADC circuits 290 as AD conversion units are two-dimensionally arranged on another semiconductor substrate. The ADC circuits 290 are provided corresponding to each of the pixel circuits 250. In FIG. 3, the ADC circuits 290 are provided in the horizontal direction across two adjacent pixel circuits 250. The two ADC circuits 290 are also provided in the vertical direction relative to one pixel circuit 250. Therefore, in the present disclosure, the ADC circuits 290 are provided in one-to-one correspondence with the pixel circuits 250.

[0033] Fig. 4 is a schematic diagram showing a configuration example of a portion of the ADC section. The ADC section 280 includes a plurality of ADC circuits 290 provided corresponding to a plurality of pixel circuits 250, and a second memory section 292. As shown in Fig. 5, the plurality of ADC circuits 290 include a first memory section 291 in addition to a comparison circuit, a selector, etc.

[0034] The first memory units 291 are provided in the ADC circuits 290, and are provided corresponding to each of the ADC circuits 290. The first memory units 291 store pixel signals that have been AD converted by the corresponding ADC circuits 290.

[0035] The second memory section 292 is a memory additionally provided in addition to the first memory section 291 of the ADC circuit 290, and in this embodiment, one is provided for each of the two ADC circuits 290 (i.e., two pixels). The second memory section 292 is provided to store one reduced signal generated using a plurality of pixel signals stored in the plurality of first memory sections 291. For example, the first memory section 291 stores pixel signals constituting a high-resolution original image, respectively. The second memory section 292 stores a signal of a reduced image (reduced signal) generated by compressing the original image, respectively. In this way, the solid-state imaging device 100 according to the present disclosure does not directly output the pixel signal of the original image generated by the ADC circuit 290 to the outside of the semiconductor chips 511 and 512, but compresses it in the ADC circuit 290 provided for each pixel circuit 250 (i.e., for each pixel) to generate a reduced image. This allows the original image to be compressed into a reduced image in a short time. Note that a more detailed explanation of the image processing method will be given later.

[0036] [ADC configuration example] 5 is a diagram showing a further detailed configuration of a portion of the ADC unit 280. The ADC unit 280 includes ADC circuits 290a_1, 290a_2, 290b_1, 290b_2, 290c_1, 290c_2,..., second memory units 292a, 292b, 292c..., signal processing circuits 293a, 293b, 293c..., and demultiplexers 294a, 294b, 294c...

[0037] The ADC circuits 290a_1, 290a_2, 290b_1, 290b_2, 290c_1, 290c_2, ... have the same internal configuration. Therefore, for convenience, the internal configuration of the ADC circuit 290a_1 will be described, and descriptions of the internal configurations of the other ADC circuits will be omitted.

[0038] The ADC circuit 290a_1 includes a comparison circuit 295, a selector 296, and a first memory unit 291a_1. The comparison circuit 295 compares a pixel signal from a corresponding pixel circuit 250 with a reference signal from a DAC 231. The comparison circuit 295 measures the time from when the voltage of the reference signal starts to change until it crosses the voltage level of the pixel signal. As a result, the pixel signal is AD converted and output as a digital value.

[0039] The selector 296 receives the digital value from the comparison circuit 295 and the output signal from the demultiplexer 294a, and selectively transfers either one of them to the first memory portion 291a_1.

[0040] The first memory unit 291a_1 temporarily stores the signal from the demultiplexer 294a. When the comparison circuit 295 first receives a pixel signal of the original image from the corresponding pixel circuit 250, the demultiplexer 294a sends the pixel signal of the original image to the first memory unit 291a_1, and the first memory unit 291a_1 stores the pixel signal.

[0041] At this time, like the first memory unit 291a_1, the other first memory units 291a_2, etc. also store pixel signals of the original image from the corresponding pixel circuits 250. Therefore, the ADC unit 280 stores pixel signals of the original image as a whole. Note that the second memory units 292a, etc. have not yet stored any specific signals.

[0042] The first and second memory sections 291a_1 to 291c_1, 291a_2 to 291c_2, and 292a to 292c may be latch circuits having the same configuration.

[0043] The signal processing circuit 293a receives a plurality of pixel signals from the first memory units 291a_1, 291a_2, 291b_1, 291b_2 and the second memory unit 292a and performs arithmetic processing on the signals. The arithmetic processing may be filtering of the plurality of pixel signals, thinning out a pixel signal from the plurality of pixel signals, calculating an average of the plurality of pixel signals, or multiplying the plurality of pixel signals by a coefficient and adding them. By such arithmetic processing, the pixel signals can be synthesized to generate one signal (for example, a signal of a reduced image). For example, when synthesizing two pixel signals from the first memory units 291a_1 and 291a_2, the signal processing circuit 293a synthesizes the signals by taking into account the pixel signals from the first memory units 291b_1 and 291b_2 adjacent to the pixel signals, and outputs the result as one signal (reduced signal). When pixel signals of the original images are synthesized, the signals of the second memory section 292a and the like are indefinite, so the signal processing circuit 293a does not use the signals of the second memory section 292a.

[0044] The signal processing circuits 293b and 293c function in the same manner as the signal processing circuit 293a. For example, the signal processing circuit 293b receives a plurality of pixel signals from the first memory units 291b_1, 291b_2, 291c_1, 291c_2 and the second memory unit 292b, and performs arithmetic processing on these. The signal processing circuit 293c receives a plurality of pixel signals from the first memory units 291c_1, 291c_2, 291d_1, 291d_2 and the second memory unit 292c, and performs arithmetic processing on these. The signal processing circuits 293a to 293c may be digital logic circuits having the same configuration.

[0045] The demultiplexer 294a receives the output signal from the signal processing circuit 293a and selectively transfers the output signal to either the ADC circuit 290a_1 or the second memory unit 292a. For example, in this embodiment, the demultiplexer 294a transfers the output signal to the second memory unit 292a and stores the output signal (i.e., the reduced signal).

[0046] The demultiplexers 294b and 294c function in the same manner as the demultiplexer 294a. Thus, the demultiplexer 294b receives an output signal from the signal processing circuit 293b and selectively transfers the output signal to either the ADC circuit 290b_1 or the second memory unit 292b. The demultiplexer 294c receives an output signal from the signal processing circuit 293c and selectively transfers the output signal to either the ADC circuit 290c_1 or the second memory unit 292c.

[0047] For example, the second memory units 292a to 292c each store an output signal. In this case, the output signal is a reduced signal obtained by combining a plurality of pixel signals. That is, the second memory units 292a to 292c each store a signal of a reduced image (first reduced signal) obtained by compressing an original image.

[0048] 5, the signal processing circuits 293a to 293c may further combine at least two of the first reduced signals stored in the second memory units 292a to 292c to store signals of reduced images (second reduced signals) obtained by further compressing the reduced images, respectively. At this time, the pixel signals of the original images may be further taken into account.

[0049] In this way, the ADC unit 280 can create and hold a reduced image of the original image before transferring the original image outside the pixel array unit 240 .

[0050] In FIG. 5, the second memory section 292a is provided for each of the two ADC circuits 290a_1 and 290a_2. Similarly, the other second memory sections 292b and 292c are provided for each of the two ADC circuits 290b_1 and 290b_2 and 290c_1 and 290c_2. That is, the second memory section 292 is provided for each of the two pixel circuits 250. The number of memories (latches) provided in the ADC section 280, including the first and second memory sections 291 and 292, is 1.5 times the number of the first memory section 291. This allows the second memory section 292 to hold the reduced signal while the first memory section 291 maintains the pixel signal of the original image. The relationship between the number of the second memory sections 292 and the amount of image data will be described in detail later.

[0051] In this embodiment, the ratio of the number of the first memory units 291 to the number of the second memory units 292 is 2:1, but the numbers are not particularly limited. The numbers of the ADC circuits 290, the second memory units 292, the signal processing circuits 293, and the demultiplexers 294 are also not particularly limited.

[0052] Also, in FIG. 5, the demultiplexers 294a to 294c are provided. However, the demultiplexers 294a to 294c may be omitted, and the signal processing circuits 293a to 293c may transfer the output signals to both the first memory units 291a_1 to 291c_1 and the second memory units 292a to 292c. In this case, although not shown, a write enable signal may be input to the first memory units 291a_1 to 291c_1 and the second memory units 292a to 292c, and the memory for storing the output signal may be selected by the write enable signal. For example, when the write enable signal is a first logic, the first memory units 291a_1 to 291c_1 store the output signals from the signal processing circuits 293a to 293c, respectively. When the write enable signal is a second logic, the second memory units 292a to 292c store the output signals from the signal processing circuits 293a to 293c, respectively. With this configuration, the output signals can be stored in either the first memory units 291a to 291c or the second memory units 292a to 292c. Also, since the demultiplexers 294a to 294c are not necessary, the area of ​​the ADC unit 280 is reduced.

[0053] Figures 6A to 6E are conceptual diagrams showing pixel signals or reduced signals stored in the first and second memory units according to the first embodiment. Figure 7 is a conceptual diagram showing original pixels and reduced images.

[0054] In the ADC section 280, the first memory section 291 and the second memory section 292 in the ADC circuit 290 are arranged. As shown in FIG. 4 and FIG. 6A, the first memory sections 291 are arranged in the X direction, and the second memory sections 292 are also arranged in the X direction. One second memory section 292 is provided for two first memory sections 291. The first memory section 291 is provided for each ADC circuit 290, and the ADC circuit 290 is provided for each pixel circuit 250. Therefore, the first memory section 291 is provided in one-to-one correspondence with the pixel circuit 250, and the second memory section 292 is provided for every two pixels. The rows of the first memory section 291 and the rows of the second memory section 292 are alternately arranged in the Y direction perpendicular to the X direction.

[0055] 6A to 6D are areas where the ADC circuit 290 (first memory section 291) and the second memory section 292 are not provided. The other white areas indicate that the ADC circuit 290 (first memory section 291) or the second memory section 292 is provided, and each of them can store one pixel signal or reduced signal.

[0056] 6A, the first and second memory units 291, 292 are in an initial state and have not yet stored any pixel signals. The plurality of pixel circuits 250 send pixel signals of a captured image to the ADC unit 280.

[0057] 6B, pixel signals S0 of an original image from pixel circuits 250 are AD converted and then stored in first memory units 291 corresponding to each pixel circuit 250. At this time, the pixel signals S0 stored in first memory units 291 have not yet been compressed.

[0058] Next, as shown in FIG. 6C, the pixel signals S0 stored in the first memory unit 291 are combined to generate a first reduced signal S1. The first reduced signal S1 is generated in the signal processing circuit 293 as described with reference to FIG. 5. The signal processing circuit 293 compresses the pixel signal S0 to one-fourth to generate the first reduced signal S1. The first reduced signal S1 is stored in a part of the second memory unit 292. At this time, the first memory unit 291 holds the pixel signal of the original image. The original image made up of the pixel signal S0 in FIG. 7 is compressed to one-fourth to a reduced image made up of the first reduced signal S1. Each point in FIG. 7 indicates one pixel signal or one reduced signal.

[0059] Next, as shown in FIG. 6D, the first reduced signal S1 stored in the second memory section 292 is synthesized to generate a second reduced signal S2. The signal processing circuit 293 compresses the first reduced signal S1 to one-fourth to generate a second reduced signal S2. The second reduced signal S2 is stored in the other second memory section 292 that does not store the first reduced signal S1. At this time, the first memory section 291 holds the pixel signal of the original image. Also, a part of the second memory section 292 holds the first reduced signal S1. The reduced image made up of the first reduced signal S1 in FIG. 7 is further compressed to one-fourth to a reduced image made up of the second reduced signal S2.

[0060] Next, as shown in FIG. 6E, the second reduced signal S2 is combined to generate a third reduced signal S3. The signal processing circuit 293 compresses the second reduced signal S2 to one-fourth to generate a third reduced signal S3. The third reduced signal S3 is stored in yet another second memory section 292 that does not store the first and second reduced signals S1 and S2. At this time, the first memory section 291 holds the pixel signals of the original image. Also, the second memory section 292 holds the first and second reduced signals S1 and S2. The reduced image made up of the second reduced signal S2 in FIG. 7 is further compressed to one-fourth to a reduced image made up of the third reduced signal S3.

[0061] Furthermore, the signal processing circuit 293 may compress the third reduced signal S3 to one-fourth to generate a fourth reduced signal (not shown). In this way, the signal processing circuit 293 generates a reduced image by repeating the compression process of the original image. That is, the signal processing circuit 293 compresses the nth (n≧3) reduced signal to one-fourth to generate the n+1th reduced signal, and the second memory unit 292 further stores the n+1th reduced signal. The number of times the compression process is repeated may be k (k is an integer of 1 or more). That is, the signal processing circuit 293 compresses the k-1th reduced signal to one-fourth to generate the kth reduced signal. Note that k=0 is the pixel signal of the original image. In this embodiment, the data amount of the pixel signal is reduced by one-fourth each time the compression process is repeated. Therefore, if the data amount of the original image is D0, the total data amount of the original image and the 1st to kth reduced signals is D0+(1 / 4)D0+(1 / 4 2 )D0+(1 / 43 )D0+···, up to a maximum of (4 / 3)*D0. In other words, the total data amount of the original image and the 1st to kth reduced signals is 1.333·· times the data amount D0 of the original image. Therefore, if the total number of the first and second memory units 291 and 292 is 1.5 times the number of the first memory units 291 that store the original image (data amount D0), the first and second memory units 291 and 292 can sufficiently store all of the original image and the 1st to kth reduced signals. For this reason, in this embodiment, one second memory unit 292 is provided for each of the two first memory units 291.

[0062] Furthermore, if any of the second to fourth reduced signals S2 to S4 were to be generated directly from the pixel signal S0 of the original image, the computational load on the signal processing circuit 293 would increase. Therefore, in this embodiment, the first reduced signal S1 is generated from the pixel signal S0, the second reduced signal S2 is generated from the first reduced signal S1, and the third reduced signal S3 is generated from the second reduced signal S2. This reduces the load on the signal processing circuit 293.

[0063] 8 is a graph showing the transfer time of the original image and the reduced images. The horizontal axis indicates time t. In this embodiment, the first and second memory units 291 and 292 store the original image and all the reduced images. Therefore, after the image compression process is completed, the images can be transferred in ascending order of the detection process, that is, from the reduced image with the least amount of data, and the original image can be transferred last.

[0064] Typically, in object detection, a reduced low-resolution image is used to detect whether an object to be detected exists or the rough coordinates of the object. This identifies a detection area in which the object is located and which needs to be detected in detail. Next, a detection area is cut out from the high-resolution image, and object detection processing is performed in the detection area in the high-resolution image. In motion detection, a reduced low-resolution image is used to detect the rough movement of the object. This identifies a region in which movement is located and which needs to be detected in detail. Next, a detection area is cut out from the high-resolution image, and motion detection processing is performed in the detection area in the high-resolution image. By performing detection hierarchically from low-resolution images to high-resolution images in this way, it is possible to increase the accuracy and detection speed of motion detection while suppressing the amount of data to be processed.

[0065] Therefore, according to this embodiment, the transfer circuit 260 transfers the reduced image with the smallest data amount to the larger image in order (in the order of detection processing) to the frame memory 115 outside the signal processing circuit 293 in order to detect hierarchically using low-resolution images to high-resolution images. For example, in FIG. 8, it is assumed that the image data amount of the third reduced signal S3 is the smallest. In this case, the transfer circuit 260 transfers the third reduced signal S3 first. Since the data amount D3 of the third reduced signal S3 is the smallest, the transfer time t_t3 is the shortest among t_t0 to t_t3. The detection time t_d3 is the time required for object detection, motion detection, etc. using the third reduced signal S3. During the detection processing using the third reduced signal S3, the transfer processing of the second reduced signal S2 is started.

[0066] The amount of image data of the second reduced signal S2 is the next smallest after the third reduced signal S3, and is detected after the third reduced signal S3, so the transfer circuit 260 transfers the second reduced signal S2 after the third reduced signal S3. The transfer time t_t2 is longer than the transfer time t_t3, but is relatively short. The detection time t_d2 is the time required for object detection, motion detection, etc. using the second reduced signal S2. During the detection process using the second reduced signal S2, the transfer process of the first reduced signal S1 is started.

[0067] The amount of image data of the first reduced signal S1 is the next smallest after the second reduced signal S2, and is detected after the second reduced signal S2, so the transfer circuit 260 transfers the first reduced signal S1 after the second reduced signal S2. The transfer time t_t1 is longer than the transfer time t_t2, but is shorter than the transfer time of the original image. The detection time t_d1 is the time required for object detection, motion detection, etc. using the first reduced signal S1. During the detection process using the first reduced signal S1, the transfer process of the pixel signal S0 of the original image is started.

[0068] The pixel signal S0 of the original image has the largest amount of image data and is detected last, so the transfer circuit 260 transfers the pixel signal S0 last. The transfer time t_t0 is the longest among t_t0 to t_t3. The detection time t_d0 is the time required for object detection, motion detection, and the like using the pixel signal S0. When this compression process and transfer process are generalized, when the kth reduced signal is generated, after the kth reduced signal is generated, the transfer circuit 260 transfers the pixel signal and the 1st to kth reduced signals to the frame memory 115 outside the signal processing circuit 293 in the order of the detection process (here, in order of the least amount of data). That is, after compressing the image, the transfer circuit 260 transfers the kth reduced signal, the k-1st reduced signal, . . . the 3rd reduced signal, the 2nd reduced signal, the 1st reduced signal, and the pixel signal of the original image to the frame memory 115 in this order.

[0069] In this way, the transfer circuit 260 transfers the reduced images in ascending order of the detection process, i.e., from the reduced image with the smallest amount of data, and finally transfers the original image to the frame memory 115 outside the signal processing circuit 293. This allows the DSP circuit 120 to immediately start the detection process from the image with the smallest amount of data without delay. Also, the detection process and the transfer process of the next reduced signal or pixel signal can be executed in parallel.

[0070] If the second memory unit 292 is not provided and only the original image stored in the first memory unit 291 is transferred to the frame memory 115, the pixel signal S0 of the original image is transferred, and then the DSP circuit 120 generates a reduced image using the pixel signal S0. Therefore, the detection process starts after the pixel signal S0 of the original image is transferred and the reduced image is generated. This delays the timing of the start of the detection process. Furthermore, the transfer process and the detection process cannot be executed in parallel.

[0071] On the other hand, according to the present embodiment, in the ADC section 280 of the signal processing circuit 293, the signal processing circuit 293 generates the reduced signals S1 to Sk using the original image in the first memory section 291, and stores them in the second memory section 292. In this way, since the reduced image is generated inside the ADC section 280, the signal processing circuit 293 can perform the compression process of the image without waiting for the long transfer time t_t0 of the original image. Also, the ADC section 280 can transfer the reduced images and the original images in ascending order from the reduced image with the smallest data amount in the order of the detection process, without waiting for the transfer time t_t0 of the original image. The transfer time of the image with a small data amount is relatively short. Therefore, the DSP circuit 120 can immediately start the detection process without delay.

[0072] Furthermore, when the DSP circuit 120 executes the detection process, the image compression process has already been completed. Therefore, while the DSP circuit 120 is executing the detection process, the transfer circuit 260 can transfer the next reduced signal or pixel signal in parallel to the frame memory 115. As a result, the detection process can be completed earlier.

[0073] Second embodiment 9A to 9E are conceptual diagrams showing pixel signals or reduced signals stored in the first and second memory units according to the second embodiment. In the second embodiment, one second memory unit 292 is provided for each of the three first memory units 291. That is, one second memory unit 292 is provided for each of the three pixel circuits 250. In this case, the number of memories (latches) provided in the ADC unit 280, including the first and second memory units 291 and 292, is 4 / 3 (1.3333··) times the number of first memory units 291. This allows the second memory unit 292 to hold the reduced signal while the first memory unit 291 holds the pixel signal of the original image.

[0074] As described above, the total data amount of the original image and the 1st to kth reduced signals is a maximum of (4 / 3)*D0. In other words, it is 1.333·· times the data amount D0 of the original image. Therefore, according to the second embodiment, the capacity of the second memory section 292 is equal to the total data amount of the 1st to kth reduced signals. This allows the first and second memory sections 291, 292 to store the entire original image and the 1st to kth reduced signals, and eliminates any surplus free space in the second memory section 292. In other words, waste of the first and second memory sections 291, 292 can be suppressed.

[0075] 9A, the first and second memory units 291, 292 are in an initial state and have not yet stored any pixel signals. The pixel circuits 250 send pixel signals of a captured image to the ADC unit 280.

[0076] 9B, pixel signals S0 of an original image from pixel circuits 250 are AD converted and then stored in first memory units 291 corresponding to each pixel circuit 250. At this time, the pixel signals S0 stored in first memory units 291 have not yet been compressed.

[0077] Next, as shown in Fig. 9C, the signal processing circuit 293 synthesizes the pixel signals S0 stored in the first memory unit 291 to generate a first reduced signal S1. That is, the signal processing circuit 293 compresses the pixel signals S0 to one-fourth to generate the first reduced signal S1. The first reduced signal S1 is stored in a part of the second memory unit 292. At this time, the first memory unit 291 holds the pixel signals of the original image.

[0078] Since three first reduced signals S1 are generated for twelve pixel signals S0, three second memory units 292 are used for the twelve first memory units 291 (twelve first reduced signals S1). For example, a frame C1 in Fig. 9C includes twelve first memory units 291, and three second memory units 292 within the frame C1 store the first reduced signals S1. The pattern of the frame C1 is repeated in the X and Y directions.

[0079] Next, as shown in FIG. 9D, the first reduced signal S1 stored in the second memory section 292 is synthesized to generate a second reduced signal S2. The signal processing circuit 293 compresses the first reduced signal S1 to one-fourth to generate the second reduced signal S2. The second reduced signal S2 is stored in the other second memory section 292 that does not store the first reduced signal S1. At this time, the first memory section 291 holds the pixel signals of the original image. Also, a part of the second memory section 292 holds the first reduced signal S1.

[0080] Since three second reduced signals S2 are generated for the twelve first reduced signals S1, three more second memory sections 292 are used for the twelve first reduced signals S1. For example, the frame C2 in Fig. 9D includes twelve second memory sections 292 that store the first reduced signals S1, and the other three second memory sections 292 in the frame C1 store the second reduced signals S2. The pattern of the frame C2 is repeated in the X and Y directions.

[0081] Next, as shown in FIG. 9E, the second reduced signal S2 is combined to generate a third reduced signal S3. The signal processing circuit 293 compresses the second reduced signal S2 to one-fourth to generate a third reduced signal S3. The third reduced signal S3 is stored in yet another second memory section 292 that does not store the first and second reduced signals S1 and S2. At this time, the first memory section 291 holds the pixel signals of the original image. Also, the second memory section 292 holds the first and second reduced signals S1 and S2.

[0082] Three third reduced signals S3 are generated for the twelve second reduced signals S2. Three more second memory units 292 are used for the twelve second reduced signals S2. Although not all are shown in FIG. 9E, among the twelve second memory units 292 that store the second reduced signals S2, the other three available second memory units 292 store the third reduced signals S3.

[0083] Furthermore, the signal processing circuit 293 may similarly compress the third reduced signal S3 to one-fourth to generate a fourth reduced signal (not shown). In this manner, the signal processing circuit 293 generates a reduced image by repeating the compression process of the original image. That is, the signal processing circuit 293 compresses the nth (n≧3) reduced signal to one-fourth to generate the n+1th reduced signal, and the second memory unit 292 further stores the n+1th reduced signal.

[0084] Other configurations and operations of the second embodiment may be similar to the corresponding configurations and operations of the first embodiment, and therefore the second embodiment can achieve the same effects as the first embodiment.

[0085] Furthermore, according to the second embodiment, the capacity of the second memory section 292 is equal to the total data amount of the first to kth reduced signals. This allows the first and second memory sections 291, 292 to store the entire original image and the first to kth reduced signals, and there is no surplus free space in the second memory section 292. As a result, it is possible to prevent waste in the first and second memory sections 291, 292, and memory resources can be fully utilized.

[0086] Third embodiment 10A to 10E are conceptual diagrams showing pixel signals or reduced signals stored in the first and second memory units according to the third embodiment. In the third embodiment, one second memory unit 292 is provided for each of the four first memory units 291. That is, one second memory unit 292 is provided for each of the four pixel circuits 250. In this case, the number of memories (latches) provided in the ADC unit 280, including the first and second memory units 291 and 292, is 1.25 times the number of the first memory units 291. Therefore, the capacity of the first and second memory units 291 and 292 is smaller than the total data amount (4 / 3)*D0) of the original image and the 1st to kth reduced signals. Therefore, in the third embodiment, after transferring the original image or the reduced image before compression, the signal processing circuit 293 needs to perform a compression operation.

[0087] According to the third embodiment, the first and second memory units 291, 292 cannot store the entire original image and the 1st to kth reduced signals. However, the image compression process is executed inside the ADC unit 280. Therefore, while executing the compression operation, the transfer circuit 260 can transfer the pixel signals or compressed signals used in the compression operation to the frame memory 115. This allows the compression operation to be executed almost simultaneously in parallel with the transfer process. As a result, the transfer time of the original image and the 1st to kth reduced signals is shortened, and the timing of starting the detection process is advanced.

[0088] 10A, the first and second memory units 291, 292 are in an initial state and have not yet stored any pixel signals. The pixel circuits 250 send pixel signals of a captured image to the ADC unit 280.

[0089] 10B, pixel signals S0 of an original image from pixel circuits 250 are AD converted and then stored in first memory units 291 corresponding to each pixel circuit 250. At this time, the pixel signals S0 stored in first memory units 291 have not yet been compressed.

[0090] 10C, the signal processing circuit 293 combines the pixel signals S0 stored in the first memory unit 291 to generate a first reduced signal S1. That is, the signal processing circuit 293 compresses the pixel signals S0 to one-fourth to generate the first reduced signal S1. The first reduced signal S1 is stored in the second memory unit 292.

[0091] Next, the transfer circuit 260 transfers the pixel signal S0 of the original image in the first memory unit 291 to the frame memory 115. This makes the first memory unit 291 free to store other signals. Note that after the transfer of the pixel signal S0, the data in the first memory unit 291 may be overwritten with the next signal without being erased. Furthermore, while the signal processing circuit 293 performs the compression operation on the pixel signal S0 of the original image, the transfer circuit 260 may transfer the compressed pixel signal S0 to the frame memory 115 in parallel with the compression operation. Alternatively, the transfer circuit 260 may transfer the pixel signal S0 while the first memory unit 291 holds the pixel signal S0, and thereafter the signal processing circuit 293 may perform the compression operation on the pixel signal S0 of the original image.

[0092] 10D, the first reduced signal S1 stored in the second memory unit 292 is synthesized to generate a second reduced signal S2. The signal processing circuit 293 compresses the first reduced signal S1 to one-fourth to generate the second reduced signal S2. The second reduced signal S2 is stored in the first memory unit 291 that does not store the first reduced signal S1.

[0093] Next, the transfer circuit 260 transfers the first reduced signal S1 in the second memory section 292 to the frame memory 115. This makes the second memory section 292 free to store other signals. After the transfer of the first reduced signal S1, the data in the second memory section 292 may be overwritten with the next signal without being erased.

[0094] 10E, the second reduced signal S2 is combined to generate a third reduced signal S3. The signal processing circuit 293 compresses the second reduced signal S2 to one-fourth to generate a third reduced signal S3. The third reduced signal S3 is stored in the second memory section 292 that does not store the first and second reduced signals S1 and S2.

[0095] Next, the transfer circuit 260 transfers the second reduced signal S2 in the first memory unit 291 to the frame memory 115. This makes the first memory unit 291 free to store other signals. After the transfer of the second reduced signal S2, the data in the first memory unit 291 may be overwritten with the next signal without being erased.

[0096] Furthermore, the signal processing circuit 293 may similarly compress the third reduced signal S3 to one-fourth to generate a fourth reduced signal (not shown). In this manner, the signal processing circuit 293 generates a reduced image by repeating the compression process of the original image. That is, the signal processing circuit 293 compresses the nth (n≧3) reduced signal to one-fourth to generate the n+1th reduced signal, and the first or second memory unit 291, 292 stores the n+1th reduced signal.

[0097] Other configurations and operations of the third embodiment may be similar to the corresponding configurations and operations of the first embodiment.

[0098] 11 is a graph showing the transfer time of the original image and the reduced image. The horizontal axis shows time t. In the third embodiment, the transfer circuit 260 performs the compression operation and the transfer process almost simultaneously. After the third reduced signal S3, which has the smallest data amount, is transferred, the DSP circuit 120 starts the detection process from the third reduced signal S3.

[0099] For example, the signal processing circuit 293 compresses the pixel signal S0 of the original image, and the transfer circuit 260 transfers the compressed pixel signal S0 to the frame memory 115 in parallel. Time t_c1 is the compression time of the pixel signal S0 and is also the generation time of the first reduced signal S1. The transfer process of the pixel signal S0 can be performed almost simultaneously and in parallel with the compression operation of the pixel signal S0. Therefore, the compression time t_c1 of the pixel signal S0 can be made to almost overlap with the transfer time t_t0 of the pixel signal S0.

[0100] Next, the signal processing circuit 293 performs a compression operation of the first reduced signal S1, and the transfer circuit 260 transfers the first reduced signal S1 after the compression operation to the frame memory 115 in parallel. Time t_c2 is the compression time of the first reduced signal S1 and is also the generation time of the second reduced signal S2. The transfer process of the first reduced signal S1 can be performed almost simultaneously in parallel with the compression operation of the first reduced signal S1. Therefore, the compression time t_c2 of the first reduced signal S1 can be made to almost overlap with the transfer time t_t1 of the first reduced signal S1.

[0101] Next, the signal processing circuit 293 performs a compression operation of the second reduced signal S2, and the transfer circuit 260 transfers the second reduced signal S2 after the compression operation to the frame memory 115 in parallel. Time t_c3 is the compression time of the second reduced signal S2 and also the generation time of the third reduced signal S3. The transfer process of the second reduced signal S2 can be performed almost simultaneously in parallel with the compression operation of the second reduced signal S2. Therefore, the compression time t_c3 of the second reduced signal S2 can be made to almost overlap with the transfer time t_t2 of the second reduced signal S2.

[0102] Next, the transfer circuit 260 transfers the third reduced signal S3 for which the compression operation has been completed to the frame memory 115. The transfer time of the third reduced signal S3 is t_t3.

[0103] After that, the DSP circuit 120 performs a detection process using the third reduced signal S3. Next, the DSP circuit 120 performs a detection process using the second reduced signal S2, performs a detection process using the first reduced signal S1, and performs a detection process using the pixel signal S0.

[0104] According to the third embodiment, the image compression process is performed inside the ADC unit 280. Therefore, the transfer circuit 260 can transfer pixel signals or compressed signals used in the compression process to the frame memory 115 while performing the compression operation. This allows the compression operation to be performed almost simultaneously in parallel with the transfer process, and the start timing of the detection process can be advanced. As a result, the solid-state imaging device 100 can reduce the time required for generating a reduced image and for image processing.

[0105] The embodiments according to the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology. (1) a pixel array including a plurality of pixels that perform photoelectric conversion; A plurality of AD conversion units provided corresponding to the plurality of pixels, each of which converts a pixel signal from the pixel into a digital signal; a plurality of first memory units provided corresponding to the plurality of AD conversion units, each of which stores the pixel signals digitally converted by the AD conversion units; a plurality of second memory units provided one for each of N pixels (N is an integer of 2 or more) or N AD conversion units; (2) a signal processing circuit for performing arithmetic processing on a signal from the first or second memory unit; The solid-state imaging device according to (1), further comprising a selection circuit that receives an output signal from the signal processing circuit and transfers the output signal to either the first or second memory unit. (3) the signal processing circuit generates a first reduced signal from the plurality of pixel signals from the first and second memory units; The solid-state imaging device according to (2), wherein the selection circuit stores the first reduced signal in either the first or second memory unit. (4) The solid-state imaging device according to any one of (1) to (3), wherein the second memory unit is provided for two pixels. (5) the signal processing circuit compresses the pixel signals stored in the first memory units to one-fourth to generate the first reduced signals; The solid-state imaging device according to (4), wherein some of the plurality of second memory units store the first reduced signals. (6) the signal processing circuit compresses the first reduced signals stored in the second memory units by a factor of four to generate second reduced signals; The solid-state imaging device according to (5), wherein the plurality of first memory sections hold the plurality of pixel signals, and the other of the second memory sections stores second reduced signals. A solid-state imaging device as described in (6), wherein the pixel signals are transferred outside the first memory unit after the multiple first reduced signals or the multiple second reduced signals are transferred outside the second memory unit. (8) the signal processing circuit further compresses the second reduced signals stored in the second memory units by a factor of four to generate third reduced signals; the plurality of first memory units hold the plurality of pixel signals, and the plurality of second memory units hold the second reduced signals, while other second memory units store third reduced signals; the signal processing circuit further compresses the plurality of n-th (n≧3) reduced signals stored in the plurality of second memory units to one-fourth to generate a plurality of n+1-th reduced signals; The solid-state imaging device according to (6) or (7), wherein the other second memory unit stores each of the (n+1)th reduced signals. (9) The solid-state imaging device according to any one of (1) to (3), wherein the second memory unit is provided for every three pixels. (10) the signal processing circuit compresses the pixel signals stored in the first memory units to one-fourth to generate the first reduced signals; The solid-state imaging device according to (9), wherein some of the plurality of second memory units store the first reduced signals. (11) the signal processing circuit compresses the first reduced signals stored in the second memory units by a factor of four to generate second reduced signals; A solid-state imaging device as described in (10), wherein the plurality of first memory units hold the plurality of pixel signals, while other of the second memory units store second reduced signals. (12) A solid-state imaging device as described in (11), wherein the pixel signals are transferred outside the first memory unit after the multiple first reduced signals or the multiple second reduced signals are transferred outside the second memory unit. (13) the signal processing circuit further compresses the second reduced signals stored in the first memory units by a factor of four to generate third reduced signals; the plurality of first memory units hold the plurality of pixel signals, and the plurality of second memory units store the second reduced signals, while other second memory units store the third reduced signals; the signal processing circuit further compresses the plurality of n-th (n≧3) reduced signals stored in the plurality of second memory units to one-fourth to generate a plurality of n+1-th reduced signals; The solid-state imaging device according to (11) or (12), wherein the other second memory unit stores each of the (n+1)th reduced signals. (14) The solid-state imaging device according to any one of (1) to (3), wherein the second memory unit is provided for every four pixels. (15) the signal processing circuit compresses the pixel signals stored in the first memory units to one-fourth to generate the first reduced signals; The solid-state imaging device according to (14), wherein the plurality of second memory units store the respective first reduced signals. (16) the signal processing circuit compresses the first reduced signals stored in the second memory units by a factor of four to generate second reduced signals; The solid-state imaging device according to (15), wherein the first memory unit stores each of the second reduced signals. (17) A solid-state imaging device as described in (16), wherein after the pixel signals stored in the multiple first memory units are transferred outside the first memory units, the multiple first memory units store respective second reduced signals. (18) the signal processing circuit further compresses the second reduced signals stored in the first memory units by a factor of four to generate third reduced signals; the first or second memory unit stores the third reduced signal; the signal processing circuit further compresses the k-th (k≧3) reduced signals stored in the first or second memory units to one-fourth to generate a k+1-th reduced signal; The solid-state imaging device according to (16) or (17), wherein the first or second memory unit stores a k+1-th reduced signal. (19) An image processing method using a solid-state imaging device including a pixel array including a plurality of pixels that perform photoelectric conversion, a plurality of AD conversion units provided corresponding to each of the plurality of pixels, a plurality of first memory units provided corresponding to each of the plurality of AD conversion units, and a plurality of second memory units provided one for each of N pixels (N is an integer of 2 or more) or the N AD conversion units, digitally converting pixel signals from the pixels; storing the pixel signals digitally converted by the AD conversion unit in the plurality of first memory units; generating one first reduced signal from the plurality of pixel signals from the plurality of first memory units; and storing the plurality of first reduced signals in either the first or second memory unit. (20) The method according to (19), wherein the plurality of first reduced signals are signals generated by compressing the plurality of pixel signals by a factor of four.

[0106] The present disclosure is not limited to the above-described embodiment, and various modifications are possible without departing from the scope of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may be obtained. [Explanation of symbols]

[0107] 100 solid-state imaging device, 240 pixel array section, 260 transfer circuit, 115 frame memory, 120 DSP circuit, 250 pixel circuit, 280 ADC section, 290 ADC circuit, 291 first memory section, 292 second memory section, 293 signal processing circuit, 294 demultiplexer, 295 comparison circuit, 296 selector

Claims

1. a pixel array including a plurality of pixels that perform photoelectric conversion; A plurality of AD (Analogue-to-Digital) conversion units provided corresponding to the plurality of pixels, respectively, for digitally converting pixel signals from the pixels; a plurality of first memory units provided corresponding to the plurality of AD conversion units, each of which stores the pixel signals digitally converted by the AD conversion units; A plurality of second memory units provided for N pixels (N is an integer equal to or greater than 2) or N AD conversion units, a signal processing circuit for performing arithmetic processing on a signal from the first or second memory unit; a selection circuit that receives an output signal from the signal processing circuit and transfers the output signal to either the first or second memory unit.

2. the signal processing circuit generates a first reduced signal from the plurality of pixel signals from the first and second memory units; 2. The solid-state imaging device according to claim 1, wherein the selection circuit stores the first reduced signal in either the first or second memory section.

3. 3. The solid-state imaging device according to claim 2, wherein the second memory section is provided for two pixels.

4. the signal processing circuit compresses the pixel signals stored in the first memory units to one-fourth to generate the first reduced signals; The solid-state imaging device according to claim 3 , wherein some of the plurality of second memory sections store the first reduced signals.

5. the signal processing circuit compresses the first reduced signals stored in the second memory units by a factor of four to generate second reduced signals; 5. The solid-state imaging device according to claim 4, wherein the plurality of first memory sections hold the plurality of pixel signals, while other of the second memory sections store second reduced signals.

6. 6. The solid-state imaging device according to claim 5, wherein the pixel signals are transferred to the outside of the first memory unit after the plurality of first reduced signals or the plurality of second reduced signals are transferred to the outside of the second memory unit.

7. the signal processing circuit further compresses the second reduced signals stored in the second memory units by a factor of four to generate third reduced signals; the plurality of first memory sections hold the plurality of pixel signals, and the plurality of second memory sections hold the second reduced signals, while other second memory sections store third reduced signals; the signal processing circuit repeatedly compresses the n-th reduced signals stored in the second memory units by a factor of four while increasing n from 3 by 1 to generate a plurality of n+1-th reduced signals; 6. The solid-state imaging device according to claim 5, wherein further said second memory sections store each of the (n+1)th reduced signals.

8. 3. The solid-state imaging device according to claim 2, wherein the second memory section is provided for every three pixels.

9. the signal processing circuit compresses the pixel signals stored in the first memory units to one-fourth to generate the first reduced signals; The solid-state imaging device according to claim 8 , wherein some of the plurality of second memory sections store the first reduced signals.

10. the signal processing circuit compresses the first reduced signals stored in the second memory units by a factor of four to generate second reduced signals; 10. The solid-state imaging device according to claim 9, wherein the plurality of first memory sections hold the plurality of pixel signals, while other of the second memory sections store second reduced signals.

11. 11. The solid-state imaging device according to claim 10, wherein the pixel signals are transferred to the outside of the first memory unit after the plurality of first reduced signals or the plurality of second reduced signals are transferred to the outside of the second memory unit.

12. the signal processing circuit further compresses the second reduced signals stored in the second memory units by a factor of four to generate third reduced signals; the plurality of first memory sections hold the plurality of pixel signals, and the plurality of second memory sections store the second reduced signals, while other second memory sections store third reduced signals; the signal processing circuit repeatedly compresses the n-th reduced signals stored in the second memory units by a factor of four while increasing n from 3 by 1 to generate a plurality of n+1-th reduced signals; The solid-state imaging device according to claim 10 , wherein further said second memory sections store each of the (n+1)th reduced signals.

13. 3. The solid-state imaging device according to claim 2, wherein the second memory section is provided for every four pixels.

14. the signal processing circuit compresses the pixel signals stored in the first memory units to one-fourth to generate the first reduced signals; The solid-state imaging device according to claim 13 , wherein the second memory units store the first reduced signals.

15. the signal processing circuit compresses the first reduced signals stored in the second memory units by a factor of four to generate second reduced signals; The solid-state imaging device according to claim 14 , wherein the first memory section stores each of the second reduced signals.

16. 16. The solid-state imaging device according to claim 15, wherein the pixel signals stored in the first memory units are transferred to an outside of the first memory units, and then the first memory units store the second reduced signals.

17. the signal processing circuit further compresses the second reduced signals stored in the first memory units by a factor of four to generate third reduced signals; the first or second memory unit stores the third reduced signal; the signal processing circuit repeatedly compresses the n-th reduced signals stored in the first or second memory units by a factor of four while increasing n by one from 3 to generate a plurality of n+1-th reduced signals; The solid-state imaging device according to claim 15 , wherein the first or second memory section stores the (n+1)th reduced signal.

Images