Semiconductor Device

Abstract

Provided is a semiconductor device (100) comprising: a semiconductor substrate (111) having an upper surface and a lower surface and including a first conductivity-type drift region (116); a first main terminal (101) provided over the upper surface; a second main terminal (102) provided under the lower surface; a control terminal (103) for controlling whether a current is to be flown between the first main terminal and the second main terminal; and a buffer region (118) provided between the drift region and the lower surface and having a higher doping concentration than the drift region. In the C-V characteristic indicating the relationship between a power supply voltage (VCE) applied between the first main terminal and the second main terminal, and a terminal-to-terminal capacitance (CGC) between the control terminal and the second main terminal, a terminal-to-terminal capacitance peak (180) is present in a region with the power supply voltage of greater than or equal to 500 V.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Conventionally, semiconductor devices having a buffer region that functions as a field stop layer are known (see, for example, Patent Document 1). Patent Document 1 WO2016 / 203545 General Disclosure

[0003] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface and a first conductive type drift region. Any of the semiconductor devices may include a first main terminal provided above the upper surface. Any of the semiconductor devices may include a second main terminal provided below the lower surface. Any of the semiconductor devices may include a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal. Any of the semiconductor devices may include a buffer region provided between the drift region and the lower surface and having a doping concentration higher than that of the drift region. In a CV characteristic showing the relationship between a power supply voltage applied between the first main terminal and the second main terminal and a terminal-to-terminal capacitance between the control terminal and the second main terminal, the terminal-to-terminal capacitance may have a peak in a region where the power supply voltage is 500V or more.

[0004] In the semiconductor device, the CV characteristics may have a valley where the inter-terminal capacitance exhibits a minimum value in a region where the power supply voltage is less than 500 V. The inter-terminal capacitance when the power supply voltage is 500 V may be larger than the minimum value.

[0005] In any of the above semiconductor devices, the CV characteristics may be characteristics obtained by setting the semiconductor device in an on state, setting the power supply voltage applied between the first main terminal and the second main terminal to an initial voltage, stabilizing the current flowing between the first main terminal and the second main terminal, and then changing the power supply voltage by a displacement voltage smaller than the initial voltage, analyzing the change in the amount of charge at either terminal using a device simulator that simulates transient changes in charge within the semiconductor device, and calculating the inter-terminal capacitance based on the analyzed change in the amount of charge.

[0006] Any of the above semiconductor devices may include a base region of a second conductivity type provided opposite a control terminal, and in which an inversion layer channel is formed in a channel region opposite the control terminal when a control voltage is applied to the control terminal. Any of the above semiconductor devices may include an increasing region in which the doping concentration increases monotonically from the boundary with the drift region toward the lower surface. Any of the above semiconductor devices may include a slope α of the increase in common logarithm of the doping concentration in the increasing region per cm in the depth direction and a total length β of the channel region that satisfy the following formula: β>2×10 3 / α

[0007] In any of the above semiconductor devices, the doping concentration distribution in the depth direction of the buffer region may have one or less doping concentration peaks.

[0008] In any of the above semiconductor devices, the hydrogen chemical concentration distribution in the depth direction of the buffer region may have more hydrogen concentration peaks than doping concentration peaks.

[0009] Any of the above semiconductor devices may include a plurality of trench portions arranged side by side in an arrangement direction on an upper surface of the semiconductor substrate and extending from the upper surface of the semiconductor substrate to the drift region. Any of the above semiconductor devices may include a mesa portion sandwiched between two trench portions. Any of the above semiconductor devices may have a width in the arrangement direction of the mesa portion that is 20% or less of a depth of the trench portion.

[0010] In any of the above semiconductor devices, the mesa portion may have a width of 1.1 μm or less.

[0011] In any of the above semiconductor devices, in the increased region, the doping concentration distribution may be flatter than the hydrogen chemical concentration distribution.

[0012] In a second aspect of the present invention, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface and a drift region of a first conductivity type. Any of the semiconductor devices may include a first main terminal provided above the upper surface. Any of the semiconductor devices may include a second main terminal provided below the lower surface. Any of the semiconductor devices may include a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal. Any of the semiconductor devices may include a buffer region provided between the drift region and the lower surface and having a doping concentration higher than that of the drift region. Any of the semiconductor devices may include a base region of a second conductivity type that is provided opposite the control terminal and in which an inversion layer channel is formed in a channel region opposite the control terminal by applying a control voltage to the control terminal. The buffer region may have an increasing region in which the doping concentration increases monotonically from the boundary with the drift region toward the lower surface. The gradient α of the increase in the common logarithm of the doping concentration in the increasing region per cm in the depth direction and the total length β of the channel region may satisfy the following formula: β>2×10 3 / α

[0013] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0014] [Figure 1A] 1 is a cross-sectional view showing an example of a semiconductor device 100 to be analyzed. [Figure 1B] 1B is a diagram showing an example of a perspective view of a cross section taken along line AA in FIG. 1A. FIG. [Diagram 2] 2 is a diagram illustrating the inter-terminal capacitance of the semiconductor device 100. FIG. [Diagram 3] 2 is a diagram showing an example of CV characteristics of the semiconductor device 100. FIG. [Figure 4] 1A and 1B are diagrams showing an example of a doping concentration distribution and a hydrogen chemical concentration distribution in the depth direction of a part of a drift region 116, a buffer region 118, and a collector region 120. [Diagram 5] FIG. 13 is a diagram illustrating a gradient α of a doping concentration distribution. [Figure 6] FIG. 13 is a diagram showing an example of numerical values ​​of an approximation line 122. [Figure 7] FIG. 4 is a diagram showing an example of a CV characteristic. [Figure 8] FIG. 13 is a diagram showing an example of a doping concentration distribution in the buffer region 118 with a peak. [Figure 9] FIG. 1 illustrates an example of an analysis device 10 according to an embodiment of the present invention. [Figure 10] 1 is a schematic diagram illustrating an example of a circuit 300 of the semiconductor device 100. [Figure 11] 4 is a diagram for explaining an example of the operation of the charge amount analyzing unit 14. FIG. [Figure 12] 4 is a diagram showing an example of a CV characteristic calculated by a capacitance calculation section 16. FIG. [Figure 13] 13 is a diagram illustrating another example of the operation of the charge amount analyzing unit 14. FIG. [Figure 14] FIG. 1 is a diagram showing an example of a general CV characteristic. [Figure 15] FIG. 13 is a diagram for explaining a measurement method according to a reference example. [Figure 16] FIG. 4 is a diagram illustrating an example of a measurement circuit 405. [Figure 17] FIG. 17 is a diagram showing an example of a CV characteristic calculated based on the measurement circuit 405 shown in FIG. 16. [Figure 18] In the reference example, a circuit 420 showing the operation when the semiconductor device 100 is in an on state is shown. [Figure 19] Illustrated are analytical values ​​of the terminal capacitance CGC when the semiconductor device 100 is in an on state and analytical values ​​of the terminal capacitance CGC when the semiconductor device 100 is in an off state. [Figure 20] 14 is a diagram showing an analysis of each current waveform from the charge amount calculated by the analysis method described with reference to FIG. 9 to FIG. 13. [Figure 21] 14 is a flowchart showing an example of an analysis method using the analysis device 10 shown in FIGS. 9 to 13. [Figure 22] 12 illustrates an example configuration of a computer 1200 in which aspects of the present invention may be implemented in whole or in part. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0016] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0017] In this specification, technical matters may be explained using orthogonal coordinate axes of X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components, and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without indicating positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0018] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are the X-axis and the Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and the Y-axis, may be referred to as the horizontal direction. In this specification, the upper surface side of the semiconductor substrate refers to the region from the center to the upper surface in the depth direction of the semiconductor substrate. In this specification, the lower surface side of the semiconductor substrate refers to the region from the center to the lower surface in the depth direction of the semiconductor substrate.

[0019] In this specification, when the term "same" or "equal" is used, it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0020] In this specification, the conductivity type of a doped region doped with impurities is described as P type or N type. In this specification, the impurity may particularly mean either an N type donor or a P type acceptor, and may be described as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N type conductivity type or a semiconductor exhibiting a P type conductivity type.

[0021] In this specification, the doping concentration means the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding up the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any position is N D -N A It becomes.

[0022] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, the VOH defect, which is a combination of vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor, functions as a donor that supplies electrons.

[0023] In this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than that of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when it is described as P++ type or N++ type, it means that the doping concentration is higher than that of P+ type or N+ type.

[0024] In this specification, the chemical concentration refers to the atomic density of an impurity measured regardless of the state of electrical activation. The chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV). The carrier density measured by spreading resistance measurement (SR) may be the net doping concentration. The carrier density measured by CV or SR may be a value in a thermal equilibrium state. In the N-type region, the donor concentration is sufficiently larger than the acceptor concentration, so the carrier density in the region may be the donor concentration. Similarly, in the P-type region, the carrier density in the region may be the acceptor concentration.

[0025] In addition, when the concentration distribution of the donor, acceptor or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor or net doping in the region. In cases where the concentration of the donor, acceptor or net doping is almost uniform, the average value of the concentration of the donor, acceptor or net doping in the region may be taken as the concentration of the donor, acceptor or net doping.

[0026] The carrier density measured by the SR method may be lower than the concentration of the donor or acceptor. In the range where the current flows when measuring the spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The reduction in carrier mobility occurs when the carriers are scattered due to a disorder in the crystal structure caused by lattice defects, etc.

[0027] The donor or acceptor concentration calculated from the carrier density measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which acts as a donor in a silicon semiconductor, or the acceptor concentration of boron, which acts as an acceptor, is about 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is about 0.1% to 10% of the chemical concentration of hydrogen.

[0028] FIG. 1A is a cross-sectional view showing an example of a semiconductor device 100 to be analyzed. The semiconductor device 100 of this example has a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). However, the structure of the semiconductor device 100 is not limited to the structure of FIG. 1A. The semiconductor device 100 includes a semiconductor substrate 111, a first main terminal 101, a second main terminal 102, and an interlayer insulating film 110. The semiconductor substrate 111 also includes a control terminal 103. The control terminal 103 controls whether or not a main current flows between the first main terminal 101 and the second main terminal 102 by an applied voltage. The control terminal 103 is, for example, a gate terminal or a base terminal of a transistor element. The first main terminal 101 and the second main terminal 102 are terminals through which a main current flows. The first main terminal 101 is, for example, an emitter terminal or a source terminal of a transistor element. The second main terminal 102 is, for example, a collector terminal or a drain terminal of a transistor element. In this example, the first main terminal 101 is an emitter electrode, and the second main terminal 102 is a collector electrode. The first main terminal 101 and the second main terminal 102 are made of a metal material such as aluminum.

[0029] The semiconductor substrate 111 is a substrate formed of a semiconductor material such as silicon, or a compound semiconductor material such as silicon carbide or gallium arsenide. The semiconductor substrate 111 may be formed by an MCZ (Magnetic Field Applied CZ) method. The semiconductor substrate 111 may be in the form of a wafer including a plurality of chips, or may be in the form of individual chips. The semiconductor substrate 111 has an upper surface 113 and a lower surface 115. The semiconductor device 100 of this example is a vertical device in which a first main terminal 101 is provided above the upper surface 113, and a second main terminal 102 is provided below the lower surface 115.

[0030] The semiconductor substrate 111 of this example has a gate structure 105, an emitter region 112, a base region 114, a drift region 116, a buffer region 118, and a collector region 120. The drift region 116 is a region of a first conductivity type (N-type in this example). The emitter region 112 is disposed between the drift region 116 and the upper surface 113. The emitter region 112 is an N+ type contact region that contacts the first main terminal 101. The base region 114 is a second conductivity type (P-type in this example) contact region that contacts the first main terminal 101. At least a part of the base region 114 is disposed between the emitter region 112 and the drift region 116. In this example, the first conductivity type is N type and the second conductivity type is P type, but the conductivity types may be reversed.

[0031] The collector region 120 is a P+ type region provided in contact with the lower surface 115. The collector region 120 is electrically connected to the second main terminal 102. The buffer region 118 is an N+ type region provided between the collector region 120 and the drift region 116. The doping concentration of the buffer region 118 is higher than the doping concentration of the drift region 116. The buffer region 118 functions as a field stop layer that prevents the depletion layer 117 spreading from the upper surface 113 side from reaching the collector region 120.

[0032] The gate structure 105 is provided at a position facing the base region 114 between the emitter region 112 and the drift region 116. The gate structure 105 in this example is a trench type provided from the upper surface 113 of the semiconductor substrate 111 through the emitter region 112 and the base region 114 to the drift region 116. The gate structure 105 in this example is an example of a trench portion. The depth from the upper surface 113 to the lower end of the gate structure 105 is Zt (cm). In another example, the gate structure 105 may be a planar type provided above the upper surface 113 of the semiconductor substrate 111.

[0033] The gate structure 105 is insulated from the first main terminal 101 by an interlayer insulating film 110. The gate structure 105 is repeatedly arranged at predetermined intervals in a predetermined arrangement direction (the X-axis direction in the example of FIG. 1A).

[0034] The gate structure 105 has a gate insulating film 104 and a control terminal 103. In this example, the control terminal 103 is a gate electrode. The control terminal 103 may be formed of a conductive material such as polysilicon. The control terminal 103 and the base region 114 are provided so as to at least partially face each other.

[0035] The gate insulating film 104 may be a film formed by thermally oxidizing or thermally nitriding the semiconductor substrate 111. The gate insulating film 104 insulates the control terminal 103 from the semiconductor substrate 111. A region of the base region 114 that is in contact with the gate insulating film 104 and faces the control terminal 103 across the gate insulating film 104 is referred to as a channel region 106. When a predetermined control voltage is applied to the control terminal 103, an inversion layer channel with an inverted conductivity type is formed in the channel region 106 of the base region 114. As a result, the emitter region 112 and the drift region 116 are connected by the inversion layer channel, and a current flows.

[0036] The semiconductor substrate 111 of this example has a mesa portion 160. The mesa portion 160 is a portion of the semiconductor substrate 111 that is sandwiched between two gate structures 105. The position of the upper end of the mesa portion 160 of this example is the same as the position of the upper end of the gate structure 105 (i.e., the upper surface 113), and the position of the lower end of the mesa portion 160 is the same as the position of the lower end of the gate structure 105. The width of the mesa portion 160 in the arrangement direction of the gate structures 105 is Wm (cm). The width Wm of the mesa portion 160 corresponds to the distance between two adjacent gate structures 105 in the X-axis direction. The width Wm of the mesa portion 160 may be measured on the upper surface 113 of the semiconductor substrate 111.

[0037] In this specification, a state in which an inversion layer channel is formed in the channel region 106 of the base region 114 may be referred to as an on state, and a state in which an inversion layer channel is not formed may be referred to as an off state. A direction perpendicular to the direction in which a current flows through the inversion layer channel (Z-axis direction in the example of FIG. 1A) and perpendicular to the direction in which the base region 114 and the control terminal 103 face each other (X-axis direction in the example of FIG. 1A) is referred to as a channel length direction (Y-axis direction in the example of FIG. 1A). The length of the channel region 106 in the channel length direction is referred to as a channel length.

[0038] FIG. 1B is a diagram showing an example of a perspective view of the AA cross section in FIG. 1A taken from the side. The AA cross section is a YZ cross section passing through the channel region 106 of the base region 114. Each member shown in FIG. 1A is arranged to extend in the Y-axis direction. Therefore, the channel region 106 is also arranged to extend in the Y-axis direction. In this example, the part of the base region 114 that is arranged adjacent to the control terminal 103 with the gate insulating film 104 sandwiched therebetween and that is sandwiched between the emitter region 112 and the drift region 116 is defined as the channel region 106. The length of the channel region 106 in the Y-axis direction is defined as the channel length L CH (cm). The channel length L CH The sum of these is referred to as the total length β of the channel region 106.

[0039] 2 is a diagram illustrating the inter-terminal capacitance of the semiconductor device 100. The semiconductor device 100 has an inter-terminal capacitance C CE between the first main terminal 101 and the control terminal 103, GE between the second main terminal 102 and the control terminal 103, GC has.

[0040] 3 is a diagram showing an example of the CV characteristic of the semiconductor device 100. In this example, the power supply voltage applied between the first main terminal 101 and the second main terminal 102 shown in FIG. CE (V). Figure 3 shows the power supply voltage V CE and the terminal capacitance C GC 1A, and characteristic 154 is the CV characteristic of the semiconductor device 100 according to the reference example. Characteristic 151 and characteristic 154 are the CV characteristics when the semiconductor device is in the on state. Power supply voltage V CE When the capacitance C changes, the range in which the depletion layer 117 spreads changes, and the distribution of the space charge density in the semiconductor substrate 111 changes. GC changes.

[0041] Capacitance between terminals C GC In the voltage range where the power supply voltage V CE By placing the peak 180 in the high power supply voltage V CE This can suppress the oscillation of the voltage waveform in a relatively low range.

[0042] Characteristic 151 shows the power supply voltage V CE In the area where the voltage is 500V or more, the terminal capacitance C GC The voltage at the apex of the peak 180 is the voltage at which the peak 180 is located. CE In addition, when the power supply voltage V is less than 500V, the voltage waveform oscillation can be suppressed. CEEven if a surge voltage occurs in the buffer region 118, the oscillation of the voltage waveform can be suppressed. The peak 180 may be located in a region of 550 V or more, 600 V or more, or 700 V or more. The peak 180 may be located in a region of 1000 V or less, or 800 V or less. As will be described later, the position of the peak 180 can be adjusted by at least one of the shape of the doping concentration distribution in the buffer region 118 and the width Wm of the mesa portion 160.

[0043] Characteristic 151 shows the power supply voltage V CE In the area where the terminal capacitance C is less than 500V, GC The valley 181 has a valley portion 181 where the inter-terminal capacitance C GC The width of the valley 181 is greater than the full width at half maximum (FWHM) of the peak 180. The width of the valley 181 is the difference between the power supply voltage V CE In this case, the terminal capacitance C GC Two power supply voltages V CE The width of the valley 181 may be more than twice the full width at half maximum of the peak 180. The valley 181 is CE may be placed in a range of 100V or more, or may be placed in a range of 200V or more. GC The power supply voltage V CE Let be the voltage at which valley 181 is located.

[0044] In addition, the power supply voltage V CE The capacitance between terminals C when is 500V GC is larger than the minimum value of the valley 181. From the minimum value of the valley 181 to the apex of the peak 180, the inter-terminal capacitance C GC may be monotonically increasing. With this arrangement, the supply voltage V CE In the area where the terminal capacitance C is less than 500V, GC It is possible to suppress a sudden decrease in

[0045] The characteristic 154 according to the reference example is a characteristic CEhas a peak in the range from 100V to 500V. Therefore, in this range, the terminal capacitance C GC As a result, the voltage V CE For example, when a semiconductor device is turned off, the power supply voltage V CE increases, the voltage waveform becomes more likely to oscillate.

[0046] 4 is a diagram showing an example of a doping concentration distribution and a hydrogen chemical concentration distribution in the depth direction of a part of the drift region 116, the buffer region 118, and the collector region 120. The collector region 120 is formed by implanting a P-type dopant such as boron. The collector region 120 has a doping concentration peak.

[0047] The buffer region 118 is formed by implanting an N-type dopant such as hydrogen. The PN junction at the boundary between the buffer region 118 and the collector region 120 is defined as the lower end of the buffer region 118.

[0048] The doping concentration of the drift region 116 is denoted as Dd. The doping concentration of the drift region 116 may be approximately constant in the depth direction. Approximately constant may mean that the fluctuation range of the doping concentration in the depth range of the drift region 116 is less than ±20% of the average doping concentration Dd. The semiconductor substrate 111 may have bulk donors distributed approximately uniformly throughout the substrate. The bulk donors are donors that are present from the time of formation of the ingot of the semiconductor substrate. The bulk donors are, for example, phosphorus, but are not limited to this. 。 The doping concentration of the drift region 116 may be the same as the bulk donor concentration.

[0049] In this example, the buffer region 118 is in contact with the drift region 116. The boundary Zb ​​between the drift region 116 and the buffer region 118 may be the first position where the doping concentration becomes 1.2×Dd when observing the doping concentration distribution from the drift region 116 toward the lower surface 115.

[0050] The buffer region 118 of this example has an increasing region 124 in which the doping concentration increases monotonically from the boundary Zb ​​with the drift region 116 toward the lower surface 115. The increasing region 124 may be provided over ½ or more, or ¾ or more, of the buffer region 118 in the depth direction. The increasing region 124 may be provided over 10 μm or more, 20 μm or more, or 30 μm or more.

[0051] The doping concentration increases monotonically refers to a state in which the doping concentration increases or remains constant when the doping concentration distribution is observed toward the lower surface 115. In other words, the increasing region 124 does not have a region in which the doping concentration decreases toward the lower surface 115. However, the increasing region 124 may include a slight decrease in the doping concentration due to measurement noise or other factors. When the doping concentration distribution is observed toward the lower surface 115, if the minimum value of the doping concentration is 80% or more of the previous maximum value, it may be determined that the doping concentration is not decreased in the portion including the minimum value. If the minimum value of the doping concentration is 90% or more of the previous maximum value, it may be determined that the doping concentration is not decreased in the portion including the minimum value.

[0052] Since the doping concentration of the increasing region 124 increases monotonically, the increasing region 124 does not include a doping concentration peak. By providing the increasing region 124 that is substantially free of a doping concentration peak, when the depletion layer 117 reaches the region, the inter-terminal capacitance C GC This can suppress abrupt changes in the

[0053] The buffer region 118 may have one or less doping concentration peaks 121. In other words, the buffer region 118 may have only one doping concentration peak 121, and the doping concentration peak 121 may not exist. The doping concentration peak 121 has an upper base where the doping concentration decreases from the apex toward the upper surface 113, and a lower base where the doping concentration decreases from the apex toward the lower surface 115. The doping concentration peak 121 in this example has an apex at a depth position Z1. The doping concentrations at the upper and lower bases may be at least half or less than the doping concentration Dp at the apex, and may be 0.1 times or less.

[0054] The increasing region 124 does not include the doping concentration peak 121. When observing the gradient of the doping concentration distribution toward the lower surface 115, the position where the gradient starts to increase toward the apex at the depth position Z1 may be the lower end position of the increasing region 124. The position where the second derivative of the doping concentration in the depth direction is a maximum value may be the lower end position of the increasing region 124. In another example, a depth position 5 μm away from the depth position Z1 may be the end position of the doping concentration peak 121. As shown in FIG. 4, when the doping concentration peak 121 is located below the increasing region 124, a position 5 μm away from the depth position Z1 toward the upper surface 113 may be the lower end position of the increasing region 124. As will be described later, when the buffer region 118 includes a plurality of hydrogen concentration peaks 141, the depth position Z2 of the hydrogen concentration peak 141-2 located second closest to the lower surface 115 may be the lower end position of the increasing region 124.

[0055] In this specification, the gradient of the doping concentration in the increasing region 124 is denoted as α. The gradient α is the rate at which the common logarithm value logD of the doping concentration D increases per 1 cm in the depth direction, and is expressed in units of (cm -1 The slope α may be the slope of an approximation line 122 obtained by approximating the doping concentration distribution of the increased region 124 by the least squares method.

[0056] In the semiconductor device 100, the inclination α and the total length β of the above-mentioned channel region 106 satisfy the following formula (1). β>2×10 3 / α...Equation (1) According to formula (1), the lower limit of the slope α is determined according to the reciprocal 1 / β of the total length β. When the total length β of the channel region 106 is small, the channel region 106 on the upper surface 113 of the semiconductor substrate 111 is reduced, and the number of carriers injected into the semiconductor substrate 111 is reduced. In this case, the lower limit of the slope α is large. When the slope α is large, the increasing region 124 is shortened in the depth direction. On the other hand, according to formula (1), the upper limit of the slope α is determined according to the reciprocal 1 / β of the total length β. When the total length β of the channel region 106 is large, the channel region 106 on the upper surface 113 of the semiconductor substrate 111 is increased, and the number of carriers injected into the semiconductor substrate 111 is increased. In this case, the lower limit of the slope α is small. When the slope α is small, the increasing region 124 may be lengthened in the depth direction. As an example, the increased region 124 may be 30% or more, 40% or more, or 50% or more of the length from the bottom surface of the trench portion to the end surface of the collector region 120 on the buffer region 118 side. A case in which the total length β is large is, for example, a case in which the area of ​​the active region of the semiconductor device 100 is large. In other words, when the active region is large or the total length β is large, the slope α of the formula (1) can be made relatively small to reduce the inter-terminal capacitance C GC This shows that it is possible to suppress sudden changes in

[0057] A line obtained by doping concentration of the approximation line 122 multiplied by two is called a line 123-H, and a line obtained by halving the doping concentration is called a line 123-L. The doping concentration in the increase region 124 may be a value between the lines 123-H and 123-L throughout the entire increase region 124. This prevents a sudden increase or decrease in the doping concentration, so that the inter-terminal capacitance C GC This can suppress sudden changes in the

[0058] The hydrogen chemical concentration distribution in the depth direction of the buffer region 118 may have more hydrogen concentration peaks 141 than the doping concentration peaks 121. The multiple hydrogen concentration peaks 141 can be formed by implanting hydrogen ions at multiple depth positions from the lower surface 115. After the hydrogen ions are implanted, the semiconductor substrate 111 is annealed to form VOH defects in which vacancy defects (V), oxygen (O), and hydrogen (H) are combined. The VOH defects function as donors. For this reason, the doping concentration distribution as shown in FIG. 4 can be formed by implanting hydrogen ions at multiple depth positions while decreasing the dose according to the depth distance from the lower surface 115.

[0059] Buffer region 118 in this example has hydrogen concentration peaks 141-1, 141-2, 141-3, and 141-4 at depth positions Z1, Z2, Z3, and Z4. Hydrogen concentration peak 141-1, which is located closest to bottom surface 115, is located at the same depth as doping concentration peak 121. "Two peaks are located at the same depth" means that the apex of one peak is located within the range of the full width at half maximum of the other peak.

[0060] The hydrogen concentration peak 141-1 has a higher hydrogen chemical concentration than the other hydrogen concentration peaks 141. The peak concentration refers to the concentration at the apex of the peak. The hydrogen concentration peak 141-1 may be 5 times or more, 10 times or more, or 100 times or more, the maximum hydrogen chemical concentration of the other hydrogen concentration peaks 141. By lowering the hydrogen concentrations of the hydrogen concentration peaks 141-2, 141-3, and 141-4, the increased region 124 can be formed without providing a peak in the doping concentration distribution. The depth range from the apex of the hydrogen concentration peak 141-4 formed at the deepest position to the apex of the hydrogen concentration peak 141-2 formed at the second shallowest position may be the increased region 124.

[0061] The concentration of each hydrogen concentration peak 141 decreases as the distance from lower surface 115 increases. A straight line 142 is obtained by approximating the apexes of hydrogen concentration peaks 141-2, 141-3, and 141-4 other than hydrogen concentration peak 141-1 using the least squares method. The slope of straight line 142 is approximately equal to slope α of approximation straight line 122. The slope of straight line 142 may be 0.5 to 2 times the slope α.

[0062] In the hydrogen chemical concentration distribution, the doping concentration distribution is flatter than the hydrogen chemical concentration distribution in the increased region 124. In the hydrogen chemical concentration distribution, the hydrogen concentration peak 141-4 is the farthest from the lower surface 115, and the hydrogen concentration peak 141-5 is the second farthest from the lower surface 115. Departed The depth position of the minimum value between the hydrogen concentration peaks 141-3 is designated as Z5. The difference in doping concentration at the depth positions Z4 and Z5 is smaller than the difference in hydrogen chemical concentration at the depth positions Z4 and Z5. The difference in doping concentration may be 0.5 times or less, 0.1 times or less, or 0.05 times or less of the difference in hydrogen chemical concentration.

[0063] 5 is a diagram for explaining the gradient α of the doping concentration distribution. The doping concentration at the depth position Z4 is D4, and the doping concentration at the depth position Z3 is D3. The gradient α ( / cm) is given by the formula (2). α=|log(D3)-log(D4)| / |Z3-Z4| Formula (2)

[0064] The doping concentration distribution in the increase region 124 may have a convex portion 125 that is convex upward and a concave portion 126 that is convex downward. The convex portion 125 is disposed in a range including the depth position Z4. The concave portion 126 is disposed at a position including the depth position Z5.

[0065] The doping concentration distribution in the increasing region 124 may be an upwardly convex portion 125 as a whole. The doping concentration distribution in the increasing region 124 may be a downwardly convex portion 126 as a whole. The doping concentration distribution in the increasing region 124 may be a linear shape.

[0066] 6 is a diagram showing an example of values ​​of the approximation line 122. In this example, the depth positions of both ends of the approximation line are X1 and X2, and the doping concentrations at the depth positions X1 and X2 are N1 and N2. X1=4.3 μm=4.3×10 ―4 cm, N1= 3.5 ×10 15 / cm 3 , log(N1)=15.55, X2=29.9μm=29.9×10 ―4 cm, N2= 2.9 ×10 13 / cm 3 , log(N2) = 13.46.

[0067] From equation (2), the slope α is given by the following equation. α=|15.55-13.46| / |4.3×10 ―4 - 29.9 x 10 ―4 |≒816.5 In this case, the right side of formula (1) is 2.45 cm. Therefore, it is preferable that the total length β of the channel region 106 is greater than 2.45 cm.

[0068] Fig. 7 is a diagram showing an example of CV characteristics. In this example, an example in which the doping concentration distribution of the buffer region 118 has two or more doping concentration peaks is referred to as "peaked", and an example in which there is one or less doping concentration peak as in the example of Fig. 4 is referred to as "peakless". In addition, an example in which the width Wm of the mesa portion 160 is 20% or less of the depth Zt of the gate structure portion 105 is referred to as a "narrow mesa", and an example in which the width Wm is greater than 20% of the depth Zt is referred to as a "wide mesa".

[0069] Characteristic 152 is a characteristic of an example of "no peak" and "narrow mesa". Characteristic 151 is a characteristic of an example of "no peak" and "wide mesa". Characteristic 153 is a characteristic of an example of "peak present" and "narrow mesa". Characteristic 154 is a characteristic of an example of "peak present" and "wide mesa". In this example, Zt is 5.5 μm, the width Wm of the "narrow mesa" is 1.1 μm, and the width Wm of the "wide mesa" is 2.5 μm.

[0070] As shown in Fig. 7, the characteristics 151 and 152 of the "no peak" example both have terminal capacitance C GC Therefore, the peak of the voltage V CE The vibration can be suppressed.

[0071] In addition, by using a narrow mesa, the inter-terminal capacitance C GC The width Wm of the mesa portion 160 may be 1.1 μm or less. By reducing the mesa width Wm, the carrier injection promotion effect (IE effect) increases, and the amount of carriers injected from the upper surface 113 of the semiconductor substrate 111 increases. When the carrier density on the upper surface 113 side of the semiconductor substrate 111 increases, the inter-terminal capacitance C GC It has been experimentally confirmed that does not decrease suddenly.

[0072] On the other hand, in the case of the "peak" example, characteristics 153 and 154, the terminal capacitance C GC Therefore, the peak of the voltage V CE vibrations are more likely to occur.

[0073] 8 is a diagram showing an example of a doping concentration distribution in the buffer region 118 with a peak. The buffer region 118 in this example has multiple doping concentration peaks 127 closer to the top surface 113 than the doping concentration peak 121. In this example, the doping concentration peaks 127 are located relatively close to the top surface 113. When the depletion layer 117 reaches the doping concentration peaks 127, the inter-terminal capacitance C GC Therefore, as shown in Figure 7, the power supply voltage V CE In the region where the capacitance between terminals C GC A peak appears.

[0074] It is preferable that the CV characteristics as shown in Fig. 3 and Fig. 7 can be analyzed with high accuracy. The CV characteristics may be characteristics acquired by an analysis device 10 described later.

[0075] Fig. 9 is a diagram showing an example of the analysis device 10. The analysis device 10 analyzes the characteristics of the semiconductor device 100 described in Fig. 1A to Fig. 8. The analysis device 10 analyzes any terminal capacitance of the semiconductor device 100. The terminal capacitance may be a parasitic capacitance of any terminal. The terminal capacitance may be a parasitic capacitance between any two terminals.

[0076] Analysis device 10 may be an apparatus realized by a computer. The computer may be provided with a program for causing the computer to function as analysis device 10. The computer executes the program to perform the analysis method by analysis device 10.

[0077] The analysis device 10 includes an input unit 12, a charge amount analysis unit 14, a capacitance calculation unit 16, and an output unit 18. Data related to the semiconductor device 100 to be analyzed is input to the input unit 12. The data may be input by a user of the analysis device 10 or the like. The data may include information such as the position, size, shape, impurity concentration, electrical resistance, and capacitance of each part of the semiconductor device 100.

[0078] The charge amount analysis unit 14 analyzes the charge amount in a predetermined region in the semiconductor device 100 under a predetermined analysis condition. The predetermined analysis condition may include a condition that specifies a control voltage applied to the control terminal and a power supply voltage applied between the first main terminal 101 and the second main terminal 102. The charge amount analysis unit 14 analyzes the charge of the semiconductor device 100 by a device simulator that can simulate a transient change in the charge amount in the semiconductor device 100. The transient change is, for example, a time change in the charge amount in the semiconductor device 100. The device simulator analyzes the time change in the charge amount in the semiconductor device 100 when, for example, the power supply voltage is changed. The device simulator may analyze the charge density in a predetermined region in the semiconductor device 100 using, for example, a Poisson equation, and calculate the charge amount in the region by integrating the charge density. The charge amount analysis unit 14 may analyze the charge amount in the semiconductor device 100 using a known simulator.

[0079] The charge amount analysis unit 14 sets the control voltage applied to the control terminal 103 to a predetermined value to turn on the semiconductor device 100, and sets the power supply voltage applied between the first main terminal 101 and the second main terminal 102 to a predetermined initial voltage. CE The change in the amount of charge at any terminal when the displacement voltage is changed by an amount smaller than the initial voltage is analyzed by a device simulator.

[0080] The capacitance calculation section 16 calculates either of the terminal capacitances based on the change in the charge amount analyzed by the charge amount analysis section 14. The capacitance calculation section 16 may calculate the terminal capacitance based on the change in the charge amount relative to the displacement voltage. Since the capacitance C is a value (C=Q / V) obtained by dividing the charge amount Q by the voltage V, the terminal capacitance can be calculated by dividing the change in the charge by the displacement voltage.

[0081] The output unit 18 outputs information about the terminal capacitance calculated by the capacitance calculation unit 16. The output unit 18 may cause the information about the terminal capacitance to be displayed on a display device, may transmit the information to an external device, or may store the information in a storage medium.

[0082] 10 is an example of a circuit 300 that is a schematic diagram of the semiconductor device 100. The analysis device 10 may use the circuit 300 to analyze the operation of the semiconductor device 100. A control voltage V GE The first main terminal 101 is connected to a reference potential such as a ground potential. A power supply voltage V CE The charge amount analysis unit 14 detects the control voltage V GE and the power supply voltage V CE may be set to analyze the amount of charge in the semiconductor device 100.

[0083] The capacitance between the first main terminal 101 and the second main terminal 102 of the semiconductor device 100 is defined as the inter-terminal capacitance C CE Similarly, the capacitance between the first main terminal 101 and the control terminal 103 is defined as the inter-terminal capacitance C GEThe capacitance between the second main terminal 102 and the control terminal 103 is defined as the inter-terminal capacitance C GC The capacitance calculation unit 16 calculates the capacitance between any of the terminals. The capacitance between the terminals C of the semiconductor device 100 GC may have different values ​​when the semiconductor device 100 is in the on state and when the semiconductor device 100 is in the off state. When the semiconductor device 100 is in the on state, if the current density is large, the inter-terminal capacitance C GC In the following example, it is difficult to accurately measure or calculate the inter-terminal capacitance C GC An example of calculating the above will be described.

[0084] 11 is a diagram for explaining an example of the operation of the charge amount analyzing unit 14. The charge amount analyzing unit 14 adjusts the control voltage V GE That is, the charge amount analysis unit 14 sets a control voltage V that is higher than the threshold voltage of the semiconductor device 100. GE In addition, the charge amount analysis unit 14 sets the power supply voltage V CE is set to a predetermined initial value. Then, the charge amount analysis unit 14 calculates the current I between the collector electrode C and the emitter electrode E. CE After the power supply voltage V CE Displacement voltage ΔV CE The change in the amount of charge at the first main terminal 101 when the displacement voltage ΔV is changed by CE is the power supply voltage V CE is sufficiently small compared to the displacement voltage ΔV CE For example, the power supply voltage V CE The current I between the collector electrode C and the emitter electrode E may be 10% or less, 1% or less, or 0.1% or less. CE is constant, for example, when the current I between the collector electrode C and the emitter electrode E is CE However, the control voltage V may be in a state where it does not substantially change over time at a constant current value, or the current flowing through the control terminal 103 may be in a state where it is substantially zero. "Substantially unchanged" may mean, for example, that the fluctuation range is 20% or less of the average value. GE does not change, so the terminal capacitance C GE does not change. Therefore, the power supply voltage V CEA small change in ΔV CE The displacement current due to the terminal capacitance C GC It is only due to the terminal capacitance C GC For example, the change in charge between the electrodes GC, ΔQ GC Calculate the change in the voltage between the electrodes CE, ΔV CE By dividing (ΔQ GC / ΔV CE ) may be calculated.

[0085] The charge quantity analysis unit 14 calculates the displacement voltage ΔV CE The magnitude of the power supply voltage V CE For example, the change in the magnitude of the displacement voltage ΔV CE is the power supply voltage V CE In another example, the displacement voltage ΔV CE is the power supply voltage V CE It may be a constant voltage regardless of the change in

[0086] The charge amount of a terminal may be the charge amount of a contact region in contact with the terminal in semiconductor substrate 111. For example, the charge amount of second main terminal 102 includes collector region 120 in contact with second main terminal 102. The charge amount of first main terminal 101 includes the charge amount of emitter region 112 and base region 114 in contact with first main terminal 101.

[0087] The charge amount analyzing section 14 may calculate the charge amount of the collector region 120 using the Poisson's equation shown below. ∇ 2 φ=-q(p-n+N D -N A ) / ε where ∇ is the differential operator, φ is the electrostatic potential, q is the elementary charge, p is the hole density, n is the electron density, and N D is the donor concentration, N A is the acceptor concentration, and ε is the dielectric constant of the semiconductor substrate 111. The dielectric constant ε of the semiconductor substrate 111 is calculated by multiplying the dielectric constant ε of a vacuum by the relative dielectric constant ε of the semiconductor substrate 111. r p-n+N D -NA The term corresponds to the charge density.

[0088] The electric charge analyzing unit 14 may be provided with a dielectric constant ε as an analysis condition. CE The electrostatic potential φ at each position in the semiconductor region is determined by the above equation. CE The charge density when the power supply voltage is V CE +ΔV CE The charge density at each position of the semiconductor substrate 111 is calculated by the above Poisson's equation. D , acceptor concentration N A may be set in advance as an analysis condition.

[0089] The charge amount analysis unit 14 calculates the sum of the charge densities in the collector region 120. The charge amount analysis unit 14 may integrate the charge density described above. The charge amount can be calculated by multiplying the integral value of the charge density by the elementary charge. The charge amount analysis unit 14 may calculate the change in the charge amount over time when the power supply voltage is changed as shown in FIG. 11 by transient analysis (creating a differential equation based on Kirchhoff's law and deriving a solution). The charge amount analysis unit 14 calculates the charge amount when the change in the charge amount converges when the power supply voltage is V CE +ΔV CE The charge amount analyzing unit 14 may calculate the charge amount when the power supply voltage is V CE The charge amount when the power supply voltage is V CE +ΔV CE The difference ΔQ between the amount of charge at

[0090] The charge amount analyzing section 14 may further calculate the charge density in at least a part of the drift region 116. The charge density in the drift region 116, like the collector region 120, also varies with the power supply voltage V CE and the displacement voltage ΔV CE For example, the charge amount analysis unit 14 can analyze the charge amount of the power supply voltage V CEmay be applied to the drift region 116. The charge amount analyzing unit 14 may calculate the charge amount of the drift region 116 by integrating the charge density of the drift region 116. The charge amount analyzing unit 14 may include the charge amount of the drift region 116 in the charge amount of the second main terminal 102. The inter-terminal capacitance C GC can change, so by considering the charge in the area, the terminal capacitance C GC can be analyzed more accurately.

[0091] The capacitance calculation unit 16 calculates the charge amount difference ΔQ and the displacement voltage ΔV CE Based on this, the terminal capacitance C GC The capacitance calculation unit 16 calculates the inter-terminal capacitance C GC may be calculated. C GC =ΔQ / ΔV CE

[0092] 12 is a diagram showing an example of the CV characteristic calculated by the capacitance calculation unit 16. In this example, the charge amount analysis unit 14 calculates the CV characteristic of the power supply voltage V CE is changed from the initial voltage, and the changed power supply voltage V CE For each power supply voltage V CE Displacement voltage ΔV CE For example, the charge amount analysis unit 14 analyzes the change ΔQ in the amount of charge when the power supply voltage V CE Vary the power supply voltage V from 10V to 50V, 100V, 500V, etc. CE For the displacement voltage ΔV CE Calculate the change in charge ΔQ when the voltage is changed by

[0093] The capacitance calculation unit 16 calculates the power supply voltage V CE Based on the change in charge ΔQ analyzed every time, the power supply voltage V CE Inter-terminal capacitance C GC As a result, the CV characteristic as shown in FIG. 12 is obtained. The capacitance calculation unit 16 calculates the inter-terminal capacitance C GC , the power supply voltage V CEIn other words, the calculated inter-terminal capacitance C GC The power supply voltage before the change, V CE In another example, the capacitance calculation unit 16 may calculate the inter-terminal capacitance C GC , the power supply voltage V CE +ΔV CE In other words, the calculated inter-terminal capacitance C GC , the power supply voltage V CE Displacement voltage ΔV CE The power supply voltage V after changing CE +ΔV CE The capacitance calculation unit 16 may use the calculated inter-terminal capacitance C GC , the power supply voltage V CE +0.5×ΔV CE In other words, the calculated inter-terminal capacitance C GC may be used as the capacitance value for the average power supply voltage before and after the change.

[0094] 13 is a diagram showing another example of the operation of the charge amount analyzing unit 14. The charge amount analyzing unit 14 of this example operates in response to a first power supply voltage V CE1 First displacement voltage ΔV CE1 The first change in charge ΔQ1 when adding the second power supply voltage V CE2 to the second displacement voltage ΔV CE2 The second change in the amount of charge, ΔQ2, when

[0095] First power supply voltage V CE1 and the second power supply voltage V CE2 In other words, each voltage may be set so that the power supply voltage before the change is the same. CE The change in charge ΔQ1 when the voltage is increased from the same power supply voltage V CE The change in the amount of charge ΔQ2 when the voltage is decreased may be calculated from the first displacement voltage ΔV CE1 and the second displacement voltage ΔV CE2 The charge amount analyzing unit 14 calculates the first displacement voltage ΔV CE1 and the second displacement voltage ΔV CE2In this case, the capacitance calculation section 16 may calculate a weighted average of ΔQ1 and ΔQ2 based on the ratio of the average value ΔQ of the change in the amount of charge. GC The power supply voltage V CE In this case, too, the CV characteristics shown in FIG. 12 can be obtained by varying the respective power supply voltages from their initial values.

[0096] In another example, the first power supply voltage V CE1 and the second power supply voltage V CE2 For example, the first power supply voltage V CE1 First displacement voltage ΔV CE1 The voltage V CE1 +ΔV CE1 and the second power supply voltage V CE2 to the second displacement voltage ΔV CE2 The voltage V CE2 +ΔV CE2 In other words, each voltage may be set so that the power supply voltage after the change is the same. CE1 and the second displacement voltage ΔV CE2 The charge amount analyzing unit 14 is configured to analyze the first power supply voltage V CE1 First displacement voltage ΔV CE1 The change in charge ΔQ1 when adding the second power supply voltage V CE2 to the second displacement voltage ΔV CE2 The capacitance calculation section 16 may calculate the inter-terminal capacitance C calculated from the average value of the charge changes ΔQ1 and ΔQ2. GC , the voltage V CE1 +ΔV CE1 (=V CE2 +ΔV CE2 ) may be used as the capacitance. In this case as well, the CV characteristics shown in FIG. 12 can be obtained by varying each power supply voltage from its initial value.

[0097] The device simulator of the charge amount analysis unit 14 may have a convergence determination function for determining whether or not the process of analyzing the change in the charge amount converges.CE Displacement voltage ΔV CE If the charge amount after the change by the displacement voltage ΔV cannot be calculated within the set calculation period or within the set calculation amount, it may be determined that the analysis process has not converged. CE If is made smaller, the analysis process becomes difficult to converge. On the other hand, the displacement voltage ΔV CE The smaller the displacement voltage, the more accurately the CV characteristics can be analyzed. The charge amount analysis section 14 may set the displacement voltage to be as small as possible within a range in which it is determined that the analysis process will converge. The charge amount analysis section 14 may set the smallest displacement voltage within a range in which it is determined that the analysis process will converge. The displacement voltage to be set may have a predetermined margin with respect to the smallest displacement voltage that satisfies the conditions. By setting the displacement voltage as small as possible, the CV characteristics can be analyzed with higher accuracy.

[0098] FIG. 14 is a diagram showing an example of a typical CV characteristic. The horizontal axis in FIG. CE The vertical axis indicates C GC Capacity C GC is the power supply voltage V CE may begin to saturate when the power supply voltage V falls below a certain saturation voltage. CE When the capacitance C GC is the maximum value C max The voltage that is half of the voltage in FIG. 14 is the saturation voltage.

[0099] Capacity C GC is the maximum value C max The region where the depletion layer does not expand when the semiconductor device 100 is in the off state corresponds to a region where the depletion layer does not expand when the semiconductor device 100 is in the off state. Since the analysis device 10 analyzes the CV characteristics of the semiconductor device 100 in the on state, the charge amount analysis unit 14 calculates the power supply voltage V CE A lower limit voltage of the fluctuation range of the input current may be set. The lower limit voltage may be a saturation voltage.

[0100] The charge amount analysis unit 14 calculates the displacement voltage ΔV according to the saturation voltage. CE The charge amount analyzing section 14 may multiply the saturation voltage by a predetermined coefficient to determine the displacement voltage ΔVCE The coefficient may be, for example, 0.2 or less, 0.1 or less, or 0.01 or less. This allows the power supply voltage V CE The displacement voltage ΔV is sufficiently small compared to the lower limit of the fluctuation range of CE The saturation voltage may be set in advance by a user or the like, or may be analyzed by the charge amount analysis unit 14 based on input information. The saturation voltage may be calculated by analyzing the CV characteristics of the semiconductor device 100 in the off state.

[0101] Fig. 15 is a diagram for explaining a measurement method according to a reference example. In the measurement method of this example, a small signal voltage is applied to the semiconductor device 100, and the current flowing through the semiconductor device 100 is measured to calculate the impedance, thereby measuring the CV characteristics. Fig. 15 is an equivalent circuit showing only the capacitance component of the semiconductor device 100. In the reference example, an AC small signal voltage is applied to a capacitance C whose CV characteristics are to be measured, and the flowing current is measured.

[0102] FIG. 16 is a diagram showing an example of a measurement circuit 405 used in the reference example. In this example, the capacitance C GC This is an example of measuring capacitance C, but other capacitances C can be measured in the same way. GC When measuring the capacitance C, the first main terminal 101 shown in FIG. 15 is connected to the ground potential via an AC guard that allows AC signals to pass. GE and capacity C CE Excluding capacity C GC The impedance of the

[0103] In this example, the second main terminal 102 is connected to a small signal source 401 and a power source V CC Connect in parallel. Capacitance C GC For V = V CC +V ac A voltage of is applied. An ammeter 402 is connected to the control terminal 103. Based on the current I measured by the ammeter 402 and the applied voltage V, the capacitance C GC can be calculated as follows: C GC =I / jωV Power supply voltage V CCBy changing the capacitance C GC The CV characteristics can be obtained by measuring the saturation voltage. The information on the saturation voltage described in FIG. 14 may be obtained from the measurement results of the reference example.

[0104] FIG. 17 is a diagram showing an example of a CV characteristic calculated based on the measuring circuit 405 shown in FIG. 16. In FIG. 17, a generally appropriate CV characteristic is obtained. However, as described above, the CV characteristic is a characteristic when the semiconductor device 100 is in an off state. However, the CV characteristic of the semiconductor device 100 may change when the semiconductor device 100 is in an on state and when the semiconductor device 100 is in an off state. The semiconductor device 100 is often used in an on state. For this reason, it is preferable to be able to analyze the CV characteristic of the semiconductor device 100 in an on state.

[0105] 18 shows a circuit 420 that illustrates the operation of the semiconductor device 100 in the reference example when it is in an on state. The small signal source 401 is omitted in the circuit 420. The operation of the DC component is analyzed using the circuit 420.

[0106] As shown in FIG. 18, when the semiconductor device 100 is in an on-state, a current I C contains the main current I. Usually, the main current I is CE This is much larger than the current that flows through each capacitance when the capacitance changes.

[0107] In such a case, the terminal capacitance C GC When we analyze the current I ac In addition to the current flowing through each capacitance, the main current I component is also included in the terminal capacitance C. GC becomes a very large value.

[0108] FIG. 19 shows the terminal capacitance C GC The analytical value of and the terminal capacitance C when in the off state GC As shown in Figure 19, the terminal capacitance C GCThe analytical value of the off-state terminal capacitance C GC As described above, the analytical method of the reference example cannot accurately analyze the capacitance when the semiconductor device 100 is in the on-state.

[0109] FIG. 20 is a diagram in which each current waveform is analyzed from the charge amount calculated by the analysis method described in FIG. 1A to FIG. 14. In FIG. 20, the power supply voltage is V CE From V CE +ΔV CE 20, the period during which the collector current flowing through the second main terminal 102 shown in FIG. c and the terminal capacitance C GC The change in current ΔI Cgc The change ΔI c is the current I when the power supply voltage is changed c The difference between the change ΔI Cgc can be calculated from the integral value of the charge in the collector region 120.

[0110] As shown in Figure 20, when the power supply voltage is increased, the collector current I C On the other hand, the terminal capacitance C GC Current I Cgc fluctuates during the voltage transition period, but is almost zero outside the voltage transition period. As shown in FIG. 20, the charge amount calculated by the analysis method described in FIG. 1A to FIG. 14 includes the collector current I C This does not include the charge that contributes to the collector current I. Therefore, the CV characteristics of the semiconductor device 100 in the on-state can be analyzed with high accuracy. The CV characteristics in the on-state shown in FIG. 12 are only slightly different from the CV characteristics in the off-state shown in FIG. 19, and are generally appropriate values. The charge calculated in this analysis method includes the collector current I C Since the charge contributing to the collector current I C No effect on terminal capacitance C GC can be calculated.

[0111] Fig. 21 is a flow chart showing an example of an analysis method using the analysis device 10 shown in Fig. 1A to Fig. 14. The analysis method may appropriately perform each process described in Fig. 1A to Fig. 14. The analysis method includes an input step S1500, a charge amount analysis step S1502, a capacitance calculation step S1504, and an output step S1506.

[0112] The process in the input step S1500 is similar to that in the input unit 12. The process in the charge amount analysis step S1502 is similar to that in the charge amount analysis unit 14. The process in the capacitance calculation step S1504 is similar to that in the capacitance calculation unit 16. The process in the output step S1506 is similar to that in the output unit 18.

[0113] 22 shows an example of a computer 1200 in which aspects of the present invention may be embodied in whole or in part. A program installed on the computer 1200 may cause the computer 1200 to function as or execute an operation associated with an apparatus according to an embodiment of the present invention or one or more "parts" of the apparatus, and / or to execute a process or steps of the process according to an embodiment of the present invention. Such a program may be executed by the CPU 1212 to cause the computer 1200 to execute specific operations associated with some or all of the blocks of the flowcharts and block diagrams described herein. Also, a process or steps of the process according to an embodiment of the present invention may be executed on a cloud.

[0114] The computer 1200 according to this embodiment includes a CPU 1212, a RAM 1214, a graphic controller 1216, and a display device 1218, which are connected to each other by a host controller 1210. The computer 1200 also includes input / output units such as a communication interface 1222, a hard disk drive 1224, a DVD-ROM drive 1226, and an IC card drive, which are connected to the host controller 1210 via an input / output controller 1220. The computer also includes legacy input / output units such as a ROM 1230 and a keyboard 1242, which are connected to the input / output controller 1220 via an input / output chip 1240.

[0115] The CPU 1212 operates according to a program stored in the ROM 1230 and the RAM 1214, thereby controlling each unit. The graphic controller 1216 acquires image data generated by the CPU 1212 and stores the image data in a frame buffer or the like provided in the RAM 1214 or in the graphic controller 1216 itself. of The image is displayed on the display device 1218.

[0116] The communication interface 1222 communicates with other electronic devices via a network. The hard disk drive 1224 stores programs and data used by the CPU 1212 in the computer 1200. The DVD-ROM drive 1226 reads programs or data from the DVD-ROM 1201 and provides the programs or data to the hard disk drive 1224 via the RAM 1214. The IC card drive reads programs and data from an IC card and / or writes programs and data to an IC card.

[0117] The ROM 1230 stores therein a boot program, etc., which is executed by the computer 1200 upon activation, and / or a program that depends on the hardware of the computer 1200. The input / output chip 1240 may also connect various input / output units to the input / output controller 1220 via a parallel port, a serial port, a keyboard port, a mouse port, etc.

[0118] The programs are provided by a computer-readable storage medium such as a DVD-ROM 1201 or an IC card. The programs are read from the computer-readable storage medium, installed in the hard disk drive 1224, the RAM 1214, or the ROM 1230, which are also examples of computer-readable storage media, and executed by the CPU 1212. Information processing described in these programs is read by the computer 1200, and brings about cooperation between the programs and the various types of hardware resources described above. An apparatus or method may be constructed by implementing operations or processing of information according to the use of the computer 1200.

[0119] For example, when communication is performed between the computer 1200 and an external device, the CPU 1212 may execute a communication program loaded in the RAM 1214 and instruct the communication interface 1222 to perform communication processing based on the processing described in the communication program. Under the control of the CPU 1212, the communication interface 1222 reads transmission data stored in a transmission buffer area provided in the RAM 1214, the hard disk drive 1224, the DVD-ROM 1201, or a recording medium such as an IC card, and transmits the read transmission data to a network, or writes reception data received from the network to a reception buffer area or the like provided on the recording medium.

[0120] Furthermore, the CPU 1212 may cause all or a necessary portion of a file or database stored in an external recording medium such as a hard disk drive 1224, a DVD-ROM drive 1226 (DVD-ROM 1201), an IC card, etc. to be read into the RAM 1214, and may perform various types of processing on the data on the RAM 1214. The CPU 1212 may then write back the processed data to the external recording medium.

[0121] Various types of information, such as various types of programs, data, tables, and databases, may be stored in the recording medium to be processed. The CPU 1212 may perform various types of processing on the data read from the RAM 1214, including various types of operations, information processing, conditional judgment, conditional branching, unconditional branching, information search / replacement, etc., as described throughout this disclosure and specified by the instruction sequence of the program, and writes back the results to the RAM 1214. The CPU 1212 may also search for information in a file, database, etc. in the recording medium. For example, when a plurality of entries each having an attribute value of a first attribute associated with an attribute value of a second attribute are stored in the recording medium, the CPU 1212 may search for an entry whose attribute value of the first attribute matches a specified condition from among the plurality of entries, read the attribute value of the second attribute stored in the entry, and thereby obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0122] The programs or software modules described above may be stored in a computer-readable storage medium on the computer 1200 or in the vicinity of the computer 1200. In addition, a recording medium such as a hard disk or a RAM provided in a server system connected to a dedicated communication network or the Internet can be used as a computer-readable storage medium, thereby providing the programs to the computer 1200 via the network.

[0123] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0124] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically indicated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0125] REFERENCE SIGNS LIST 10 analysis device, 12 input section, 14 charge amount analysis section, 16 capacitance calculation section, 18 output section, 100 semiconductor device, 101 first main terminal, 102 second main terminal, 103 control terminal, 104 gate insulating film, 105 gate structure section, 106 channel region, 110 interlayer insulating film, 111 semiconductor substrate, 112 emitter region , 113···upper surface, 114···base region, 115···lower surface, 116···drift region, 117···depletion layer, 118···buffer region, 120···collector region, 121···doping concentration peak, 122···approximated line, 123···line, 124···increasing region, 125···convex portion, 126···concave portion, 127···doping concentration peak, 134···power supply, 1 35 power supply, 141 hydrogen concentration peak, 142 straight line, 151, 152, 153, 154 characteristics, 160 mesa, 180 peak, 181 valley, 300 circuit, 401 small signal source, 402 ammeter, 405 measurement circuit, 420 circuit, 1200 computer, 1201 DVD-ROM, 1210 host controller controller, 1212, CPU, 1214, RAM, 1216, graphics controller, 1218, display device, 1220, input / output controller, 1222, communications interface, 1224, hard disk drive, 1226, DVD-ROM drive, 1230, ROM, 1240, input / output chip, 1242, keyboard

Claims

1. a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; A first main terminal provided above the upper surface; A second main terminal provided below the lower surface; a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal; a buffer region provided between the drift region and the lower surface and having a doping concentration higher than that of the drift region; a second conductivity type base region provided opposite the control terminal, the second conductivity type base region having an inversion layer channel formed in a channel region opposite the control terminal when a control voltage is applied to the control terminal; Equipped with a C-V characteristic showing a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal has a peak of the inter-terminal capacitance in a region where the power supply voltage is 500 V or more; the buffer region has an increasing region in which a doping concentration monotonically increases from a boundary with the drift region toward the lower surface, The gradient α of the increase in the common logarithm of the doping concentration in the increasing region per 1 cm in the depth direction and the total length β of the channel region satisfy the following formula: β＞２×１０ ３ ／α Semiconductor device.

2. a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; A first main terminal provided above the upper surface; A second main terminal provided below the lower surface; a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal; a buffer region provided between the drift region and the lower surface, the buffer region having a doping concentration higher than that of the drift region; Equipped with a C-V characteristic showing a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal has a peak of the inter-terminal capacitance in a region where the power supply voltage is 500 V or more; the buffer region has an increasing region in which the doping concentration monotonically increases from a boundary with the drift region toward the lower surface, the increasing region being provided over a region that is half or more of the buffer region in a depth direction and that is provided over a region up to a doping concentration peak provided on the lower surface side of a doping concentration distribution of the buffer region, The doping concentration distribution in the depth direction of the buffer region has one doping concentration peak. Semiconductor device.

3. a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; A first main terminal provided above the upper surface; A second main terminal provided below the lower surface; a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal; a buffer region provided between the drift region and the lower surface, the buffer region having a doping concentration higher than that of the drift region; Equipped with a C-V characteristic showing a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal has a peak of the inter-terminal capacitance in a region where the power supply voltage is 500 V or more; the buffer region is provided over a region that is 10 μm or more from the buffer region in a depth direction and extends to a doping concentration peak provided on the lower surface side of a doping concentration distribution of the buffer region, and has an increasing region in which the doping concentration monotonically increases from a boundary with the drift region toward the lower surface, In the increased region, the doping concentration profile is flatter than the hydrogen chemical concentration profile. Semiconductor device.

4. The increased region is provided over 20 μm or more of the buffer region in the depth direction. The semiconductor device according to claim 3 .

5. a second conductivity type base region provided opposite the control terminal, the second conductivity type base region having an inversion layer channel formed in a channel region opposite the control terminal when a control voltage is applied to the control terminal; Equipped with The gradient α of the increase in the common logarithm of the doping concentration in the increasing region per 1 cm in the depth direction and the total length β of the channel region satisfy the following formula: β＞２×１０ ３ ／α 4. The semiconductor device according to claim 2.

6. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate having a drift region of a first conductivity type; A first main terminal provided above the upper surface; A second main terminal provided below the lower surface; a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal; a buffer region provided between the drift region and the lower surface, the buffer region having a doping concentration higher than that of the drift region; Equipped with a C-V characteristic showing a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal has a peak of the inter-terminal capacitance in a region where the power supply voltage is 500 V or more; the buffer region is provided over a region that is 10 μm or more from the buffer region in a depth direction and extends to a doping concentration peak provided on the lower surface side of a doping concentration distribution of the buffer region, and has an increasing region in which the doping concentration monotonically increases from a boundary with the drift region toward the lower surface, the CV characteristic has a valley where the inter-terminal capacitance exhibits a minimum value in a region where the power supply voltage is less than 500 V; The inter-terminal capacitance when the power supply voltage is 500 V is greater than the minimum value. Semiconductor device.

7. A semiconductor device, a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; A first main terminal provided above the upper surface; A second main terminal provided below the lower surface; a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal; a buffer region provided between the drift region and the lower surface, the buffer region having a doping concentration higher than that of the drift region; Equipped with a C-V characteristic showing a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal has a peak of the inter-terminal capacitance in a region where the power supply voltage is 500 V or more; the buffer region is provided over a region that is 10 μm or more from the buffer region in a depth direction and extends to a doping concentration peak provided on the lower surface side of a doping concentration distribution of the buffer region, and has an increasing region in which the doping concentration monotonically increases from a boundary with the drift region toward the lower surface, The C-V characteristics are obtained by setting the semiconductor device in an on-state, stabilizing the current flowing between the first main terminal and the second main terminal with the power supply voltage applied between the first main terminal and the second main terminal set to an initial voltage, and then analyzing the change in the amount of charge at either terminal when the power supply voltage is changed by a displacement voltage smaller than the initial voltage using a device simulator that simulates a transient change in charge within the semiconductor device, and calculating the inter-terminal capacitance based on the analyzed change in the amount of charge. Semiconductor device.

8. The doping concentration distribution in the depth direction of the buffer region has one doping concentration peak. The semiconductor device according to claim 1 .

9. The hydrogen chemical concentration profile in the depth direction of the buffer region has more hydrogen concentration peaks than the doping concentration peaks. The semiconductor device according to claim 8.

10. a plurality of trench portions arranged side by side in an arrangement direction on the upper surface of the semiconductor substrate and provided from the upper surface of the semiconductor substrate to the drift region; A mesa section sandwiched between two trench sections and Further comprising: The width of the mesa portion in the arrangement direction is 20% or less of the depth of the trench portion. The semiconductor device according to claim 1 .

11. The width of the mesa portion is 1.1 μm or less. The semiconductor device according to claim 10.

12. In the increased region, the doping concentration profile is flatter than the hydrogen chemical concentration profile.

3. The semiconductor device according to claim 1 or 2.

13. A semiconductor substrate having an upper surface and a lower surface, the semiconductor substrate having a drift region of a first conductivity type; A first main terminal provided above the upper surface; A second main terminal provided below the lower surface; a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal; a buffer region provided between the drift region and the lower surface, the buffer region having a doping concentration higher than that of the drift region; Equipped with a C-V characteristic showing a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal has a peak of the inter-terminal capacitance in a region where the power supply voltage is 500 V or more; the buffer region has an increasing region in which the doping concentration monotonically increases from a boundary with the drift region toward the lower surface, the increasing region being provided over a region that is half or more of the buffer region in a depth direction and that is provided over a region up to a doping concentration peak provided on the lower surface side of a doping concentration distribution of the buffer region, the CV characteristic has a valley where the inter-terminal capacitance exhibits a minimum value in a region where the power supply voltage is less than 500 V; The inter-terminal capacitance when the power supply voltage is 500 V is greater than the minimum value. Semiconductor device.

14. A semiconductor device comprising: a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; A first main terminal provided above the upper surface; A second main terminal provided below the lower surface; a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal; a buffer region provided between the drift region and the lower surface, the buffer region having a doping concentration higher than that of the drift region; Equipped with a C-V characteristic showing a relationship between a power supply voltage applied between the first main terminal and the second main terminal and an inter-terminal capacitance between the control terminal and the second main terminal has a peak of the inter-terminal capacitance in a region where the power supply voltage is 500 V or more; the buffer region has an increasing region in which the doping concentration monotonically increases from a boundary with the drift region toward the lower surface, the increasing region being provided over a region that is half or more of the buffer region in a depth direction and that is provided over a region up to a doping concentration peak provided on the lower surface side of a doping concentration distribution of the buffer region, The C-V characteristics are obtained by setting the semiconductor device in an on-state, stabilizing the current flowing between the first main terminal and the second main terminal with the power supply voltage applied between the first main terminal and the second main terminal set to an initial voltage, and then analyzing the change in the amount of charge at either terminal when the power supply voltage is changed by a displacement voltage smaller than the initial voltage using a device simulator that simulates a transient change in charge within the semiconductor device, and calculating the inter-terminal capacitance based on the analyzed change in the amount of charge. Semiconductor device.

15. a semiconductor substrate having an upper surface and a lower surface and having a drift region of a first conductivity type; A first main terminal provided above the upper surface; A second main terminal provided below the lower surface; a control terminal that controls whether or not a current flows between the first main terminal and the second main terminal; a buffer region provided between the drift region and the lower surface and having a doping concentration higher than that of the drift region; a second conductivity type base region provided opposite the control terminal, the second conductivity type base region having an inversion layer channel formed in a channel region opposite the control terminal when a control voltage is applied to the control terminal; Equipped with the buffer region has an increasing region in which a doping concentration monotonically increases from a boundary with the drift region toward the lower surface, The gradient α of the increase in the common logarithm of the doping concentration in the increasing region per 1 cm in the depth direction and the total length β of the channel region satisfy the following formula: β＞２×１０ ３ ／α Semiconductor device.

16. The doping concentration distribution in the depth direction of the buffer region has one or less doping concentration peaks. The semiconductor device according to claim 15.

17. The hydrogen chemical concentration profile in the depth direction of the buffer region has more hydrogen concentration peaks than the doping concentration peaks. The semiconductor device according to claim 16.

18. a plurality of trench portions arranged side by side in an arrangement direction on the upper surface of the semiconductor substrate and provided from the upper surface of the semiconductor substrate to the drift region; A mesa section sandwiched between two trench sections and Further comprising: The width of the mesa portion in the arrangement direction is 20% or less of the depth of the trench portion. The semiconductor device according to claim 15.

19. The width of the mesa portion is 1.1 μm or less. The semiconductor device according to claim 18.

20. In the increased region, the doping concentration profile is flatter than the hydrogen chemical concentration profile. The semiconductor device according to claim 15 .

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