Semiconductor Device

Abstract

This semiconductor device, which makes it possible to provide a semiconductor device (10) using a gallium nitride layer, comprises: an amorphous glass substrate (100); an oriented insulating layer (110) that is provided on the amorphous glass substrate and has crystal orientation; a first gallium nitride layer (120) of a first conductivity type that is provided on the oriented insulating layer and that is in contact with the oriented insulating layer; a gate electrode (130) that faces the first gallium nitride layer; and a gate insulating layer (140) that is between the first gallium nitride layer and the gate electrode. The oriented insulating layer may have a plane with 6-fold rotational symmetry.

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device using gallium nitride. [Background technology]

[0002] Gallium nitride (GaN) is a direct transition semiconductor with a large band gap. Taking advantage of the characteristics of gallium nitride, light emitting diodes (LEDs) using gallium nitride have already been put to practical use. Gallium nitride has the characteristics of high electron saturation mobility and high breakdown voltage. In recent years, taking advantage of the characteristics of gallium nitride, the development of transistors (semiconductor devices) has been progressing for applications such as high frequency power devices. In general, a gallium nitride layer used in a light emitting diode or transistor is formed on a sapphire substrate at a high temperature of 800°C to 1000°C using MOCVD (Metal Organic Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy).

[0003] Furthermore, in recent years, so-called micro LED display devices or mini LED display devices, which are equipped with minute light-emitting diode chips in the pixels of a circuit board, have been developed as next-generation display devices. Micro LED display devices or mini LED display devices have high efficiency, high brightness, and high reliability. Such micro LED display devices or mini LED display devices are manufactured by transferring LED chips to a backplane on which transistors made of oxide semiconductors or low-temperature polysilicon are formed (see, for example, Patent Document 1). On the other hand, a method of forming transistors containing gallium nitride and light-emitting diodes on the same substrate has also been considered (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 8,791,474 [Patent Document 2] US Patent Application Publication No. 2020 / 0075664 Summary of the Invention [Problem to be solved by the invention]

[0005] The manufacturing method of the micro LED display device by transferring the LED chip has a high manufacturing cost, and it is difficult to manufacture the micro LED display device at a low cost. If a transistor using gallium nitride can be formed together with a light emitting diode on a large-area substrate such as an amorphous glass substrate, the manufacturing cost can be reduced. However, as mentioned above, since the gallium nitride layer is formed at a high temperature, it is difficult to directly form a transistor containing gallium nitride on an amorphous glass substrate.

[0006] In view of the above problems, one object of one embodiment of the present invention is to provide a semiconductor device using a gallium nitride layer. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention comprises an amorphous glass substrate, an oriented insulating layer having a crystal orientation provided on the amorphous glass substrate, a first gallium nitride layer of a first conductivity type provided on the oriented insulating layer and in contact with the oriented insulating layer, a gate electrode facing the first gallium nitride layer, and a gate insulating layer between the first gallium nitride layer and the gate electrode.

[0008] A semiconductor device according to one embodiment of the present invention includes an amorphous glass substrate, a gate electrode provided on the amorphous glass substrate, a gate insulating layer having a crystal orientation provided on the gate electrode, and a first gallium nitride layer of a first conductivity type provided on the gate insulating layer and in contact with the gate insulating layer. [Brief description of the drawings]

[0009] [Figure 1]1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 2] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 3] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 4] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Diagram 5] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 6] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 7] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 8] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 9] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 10] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 11] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 12] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 13] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 14] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. [Figure 15] 1 is a schematic diagram illustrating a configuration of a display device according to an embodiment of the present invention. [Figure 16] 1 is a circuit diagram (pixel circuit) of a pixel of a display device according to one embodiment of the present invention. [Figure 17] 1 is a cross-sectional view of a pixel of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In the drawings, the width, thickness, shape, etc. of each part may be shown diagrammatically compared to the actual form in order to make the explanation clearer. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals followed by alphabets, and detailed explanations may be omitted as appropriate.

[0011] In each embodiment of the present invention, the direction from the substrate toward the gate electrode is referred to as "up" or "upper". Conversely, the direction from the gate electrode toward the substrate is referred to as "down" or "down". In this way, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the gate electrode may be arranged so that the up-down relationship is reversed from that shown in the figure. In the following explanation, for example, the expression "gate electrode on the substrate" merely describes the up-down relationship between the substrate and the gate electrode as described above, and other members may be arranged between the substrate and the gate electrode. "Up" or "down" means the stacking order in a structure in which multiple layers are stacked, and when it is expressed as a pixel electrode above a transistor, it may be a positional relationship in which the transistor and the pixel electrode do not overlap in a planar view. On the other hand, when it is expressed as a pixel electrode vertically above a transistor, it means a positional relationship in which the transistor and the pixel electrode overlap in a planar view.

[0012] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0014] [1. First embodiment] [1-1. Configuration of semiconductor device 10] A semiconductor device 10 according to a first embodiment of the present invention will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. As shown in Fig. 1, the semiconductor device 10 has a substrate 100, an oriented insulating layer 110, a first gallium nitride layer 120, a gate electrode 130, a gate insulating layer 140, a second gallium nitride layer 150 (151, 153), and electrodes 160 (161, 163).

[0015] The substrate 100 is an amorphous substrate. For example, the substrate 100 is an amorphous glass substrate. However, the substrate 100 may be a resin substrate. As the resin substrate, a substrate having flexibility, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, is used.

[0016] The oriented insulating layer 110 is provided on the substrate 100. The oriented insulating layer 110 has a crystal orientation (e.g., c-axis orientation). Specifically, the surface of the oriented insulating layer 110 is a plane having six-fold rotational symmetry. For example, the oriented insulating layer 110 has a (0001) plane in a hexagonal close-packed structure, or a (111) plane in a face-centered cubic structure. For example, aluminum nitride, gallium oxide, or titanium oxide is used as the oriented insulating layer 110. Since the oriented insulating layer 110 has the above-mentioned characteristics, when a gallium nitride layer is grown on the oriented insulating layer 110, a gallium nitride layer having high crystallinity is obtained. For example, when the oriented insulating layer 110 is c-axis oriented with respect to the substrate 100, a gallium nitride layer having a c-axis orientation grows on the oriented insulating layer 110. The above-mentioned oriented insulating layer 110 is formed by, for example, a sputtering method.

[0017] However, the alignment insulating layer 110 is not limited to the above configuration. For example, the alignment insulating layer 110 may be formed by other physical vapor deposition (PVD) methods. For example, the alignment insulating layer 110 may be formed by vacuum deposition or electron beam deposition. The alignment insulating layer 110 may be formed by chemical vapor deposition (CVD). As the CVD method, a thermal CVD method, a plasma CVD method, a catalytic CVD method (Cat (Catalytic)-CVD method or a hot wire CVD method), etc. may be used. A base insulating layer may be provided between the substrate 100 and the alignment insulating layer 110. As the base insulating layer, a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, an aluminum nitride layer, or a laminate of these layers may be used. For example, a laminate of [silicon nitride layer / silicon oxide layer / silicon nitride layer] may be used as the base insulating layer.

[0018] The first gallium nitride layer 120 contacts the oriented insulating layer 110 from above. The first gallium nitride layer 120 is formed by, for example, a sputtering method. The crystal growth of the first gallium nitride layer 120 is controlled by the oriented insulating layer 110. As a result, the first gallium nitride layer 120 has crystallinity (or orientation) reflecting the crystallinity (or orientation) of the oriented insulating layer 110. As described above, when the oriented insulating layer 110 is c-axis oriented, the first gallium nitride layer 120 having a c-axis orientation is obtained.

[0019] The first gallium nitride layer 120 is, for example, a p-type gallium nitride layer. In this case, the first gallium nitride layer 120 may be, for example, a gallium nitride layer doped with magnesium or selenium.

[0020] The gate electrode 130 is provided on the first gallium nitride layer 120 and faces the first gallium nitride layer 120. A gate insulating layer 140 is provided between the first gallium nitride layer 120 and the gate electrode 130. The gate insulating layer 140 is in contact with each of the first gallium nitride layer 120 and the gate electrode 130. A general metal is used as the gate electrode 130. For example, aluminum, titanium, platinum, nickel, tantalum, and alloys thereof are used as a single layer or a laminated layer as the gate electrode 130. A metal oxide, a metal nitride, or an organic material is used as the gate insulating layer 140. For example, a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, an aluminum nitride layer, a gallium oxide, a titanium oxide, a titanium nitride, or a laminated layer of these is used as the gate insulating layer 140. When the semiconductor device 10 is configured to use a Schottky barrier at the interface between the first gallium nitride layer 120 and the gate electrode 130, the gate insulating layer 140 may be omitted.

[0021] The second gallium nitride layer 150 contacts the first gallium nitride layer 120 from above the first gallium nitride layer 120. The second gallium nitride layer 150 includes a source-side second gallium nitride layer 151 provided on the source side of the semiconductor device 10 and a drain-side second gallium nitride layer 153 provided on the drain side of the semiconductor device 10. The source-side second gallium nitride layer 151 and the drain-side second gallium nitride layer 153 are separated from each other, and a gate electrode 130 is provided between them. The conductivity of the second gallium nitride layer 150 is higher than that of the first gallium nitride layer 120. That is, the electrical resistivity of the second gallium nitride layer 150 is lower than that of the first gallium nitride layer 120.

[0022] The second gallium nitride layer 150 is formed by a sputtering method in the same manner as the first gallium nitride layer 120. The crystal growth of the second gallium nitride layer 150 is controlled by the first gallium nitride layer 120. As a result, the second gallium nitride layer 150 has crystallinity (or orientation) reflecting the crystallinity (or orientation) of the first gallium nitride layer 120. As described above, when the first gallium nitride layer 120 is c-axis oriented, the second gallium nitride layer 150 having a c-axis orientation is obtained.

[0023] The second gallium nitride layer 150 is, for example, an n-type gallium nitride layer. In this case, for example, a gallium nitride layer doped with silicon or germanium is used as the second gallium nitride layer 150. In this embodiment, the first gallium nitride layer 120 has a p-type conductivity type, and the second gallium nitride layer 150 has an n-type conductivity type, but is not limited to this configuration. The first gallium nitride layer 120 may have an n-type conductivity type, and the second gallium nitride layer 150 may have a p-type conductivity type. As an expression including the above two configurations, the first gallium nitride layer 120 may have a first conductivity type, and the second gallium nitride layer 150 may have a second conductivity type.

[0024] Since the first gallium nitride layer 120 and the second gallium nitride layer 150 are formed by a sputtering method, the process gas used in the sputtering process remains in these gallium nitride layers. For example, if argon gas is used in the sputtering process for forming the first gallium nitride layer 120 and the second gallium nitride layer 150, these gallium nitride layers contain argon. The argon can be detected by, for example, an analysis method such as secondary ion mass spectrometry (SIMS) for these gallium nitride layers.

[0025] The electrode 160 contacts the second gallium nitride layer 150 from above the second gallium nitride layer 150. The electrode 160 includes a source side electrode 161 provided on the source side of the semiconductor device 10 and a drain side electrode 163 provided on the drain side of the semiconductor device 10. The source side electrode 161 is connected to the source side second gallium nitride layer 151. The drain side electrode 163 is connected to the drain side second gallium nitride layer 153. A common metal is used as the electrode 160. For example, aluminum, titanium, platinum, nickel, tantalum, and alloys thereof are used as a single layer or a laminated layer as the electrode 160.

[0026] When a predetermined voltage (ON voltage) is supplied to the gate electrode 130, carriers are generated (a channel is formed) in the first gallium nitride layer 120 near the interface between the first gallium nitride layer 120 and the gate insulating layer 140. In this state, a potential difference is applied between the source-side second gallium nitride layer 151 and the drain-side second gallium nitride layer 153, causing a current to flow from the source-side second gallium nitride layer 151 to the drain-side second gallium nitride layer 153 via the channel.

[0027] [1-2. Manufacturing Method of Semiconductor Device 10] An oriented insulating layer 110 is formed on a substrate 100, which is an amorphous glass substrate. As described above, the oriented insulating layer 110 is formed, for example, by a sputtering method. A first gallium nitride layer 120 and a second gallium nitride layer 150 are formed on the oriented insulating layer 110. These gallium nitride layers are formed, for example, by a sputtering method. The oriented insulating layer 110, the first gallium nitride layer 120, and the second gallium nitride layer 150 are preferably formed continuously. For example, these layers may be formed in a sputtering device equipped with a plurality of chambers for forming each layer while being held in a vacuum. By forming the above layers in this manner, contamination at the interface between the oriented insulating layer 110 and the first gallium nitride layer 120 and the interface between the first gallium nitride layer 120 and the second gallium nitride layer 150 can be reduced, and defects in the first gallium nitride layer 120 and the second gallium nitride layer 150 can be reduced. As a result, good crystallinity can be obtained for each of the first gallium nitride layer 120 and the second gallium nitride layer 150.

[0028] Then, as shown in FIG. 1, the second gallium nitride layer 150 formed in the region where the gate electrode 130 and the gate insulating layer 140 will be provided later is removed to expose the first gallium nitride layer 120 in that region.

[0029] Next, a gate insulating layer 140 and a gate electrode 130 are formed. The gate insulating layer 140 and the gate electrode 130 are formed on the first gallium nitride layer 120 and the second gallium nitride layer 150, respectively. Then, the gate insulating layer 140 and the gate electrode 130 are patterned as shown in Fig. 1. Then, an electrode 160 is formed on the entire surface and patterned as shown in Fig. 1.

[0030] As described above, the oriented insulating layer 110, the first gallium nitride layer 120, and the second gallium nitride layer 150 are formed successively, so that good crystallinity can be obtained for each of the first gallium nitride layer 120 and the second gallium nitride layer 150.

[0031] Although the manufacturing method in which the electrode 160 is formed after the patterns of the gate insulating layer 140 and the gate electrode 130 are formed has been exemplified above, the manufacturing method is not limited to this. For example, the electrode 160 may be formed immediately after the second gallium nitride layer 150 is formed, and the patterns of the gate insulating layer 140 and the gate electrode 130 may be formed after the patterning of the electrode 160 and the patterning of the second gallium nitride layer 150 are performed.

[0032] [1-3. Method for forming first gallium nitride layer 120 and second gallium nitride layer 150] The formation of a gallium nitride layer using sputtering will now be described.

[0033] In the vacuum chamber of the sputtering device, a substrate 100 such as an amorphous glass substrate is placed at a position facing the gallium nitride target. The composition ratio of gallium nitride in the gallium nitride target is preferably 0.7 to 2 in terms of the ratio of gallium to nitrogen. Nitrogen gas is supplied to the vacuum chamber in addition to sputtering gas (argon or krypton, etc.). In this case, the composition ratio of gallium nitride in the gallium nitride target is preferably a ratio in which gallium is more abundant than nitrogen. For example, nitrogen may be supplied by a nitrogen radical source. The sputtering power source may be any of a DC power source, an RF power source, and a pulsed DC power source.

[0034] In the vacuum chamber, the substrate 100 may be heated. For example, the substrate 100 may be heated to a temperature of 400° C. or higher and lower than 600° C. This heating temperature allows the heat treatment to be applied to an amorphous glass substrate, which has low heat resistance. This heating temperature is lower than the heating temperature of metalorganic chemical vapor deposition (MOCVD) or hydride vapor phase epitaxy (HVPE).

[0035] After the vacuum chamber in which the substrate 100 is placed is sufficiently evacuated, a sputtering gas is supplied. A voltage is applied between the substrate 100 and a gallium nitride target at a predetermined pressure to generate plasma, thereby depositing a gallium nitride layer.

[0036] The configuration of the sputtering device or the sputtering conditions can be changed as appropriate. If an aluminum gallium nitride target is used instead of a gallium nitride target, an aluminum gallium nitride layer can be formed.

[0037] [2. Second embodiment] A semiconductor device 10A according to a second embodiment of the present invention will be described with reference to FIG. 2. The semiconductor device 10A is similar to the semiconductor device 10 according to the first embodiment. In the following description, the description of the configuration of the semiconductor device 10A that is similar to the semiconductor device 10 of the first embodiment will be omitted, and differences from the semiconductor device 10 will be mainly described. In the following description, when describing the configuration that is similar to the first embodiment, reference will be made to FIG. 1, and the alphabet "A" will be added after the reference numerals shown in FIG. 1.

[0038] [2-1. Configuration of semiconductor device 10A] As shown in FIG. 2, the second gallium nitride layer 150A (151A, 153A) contacts the oriented insulating layer 110A from above. The second gallium nitride layer 150A is separated into a source side second gallium nitride layer 151A and a drain side second gallium nitride layer 153A. The first gallium nitride layer 120A is provided on the second gallium nitride layer 150A and on the oriented insulating layer 110A exposed from the second gallium nitride layer 150A. The first gallium nitride layer 120A contacts the second gallium nitride layer 150A from above the second gallium nitride layer 150A in the first region 121A. The first gallium nitride layer 120A contacts the oriented insulating layer 110A from above the oriented insulating layer 110A in the second region 122A. In other words, the first gallium nitride layer 120A is provided so as to fill an opening provided between the source-side second gallium nitride layer 151A and the drain-side second gallium nitride layer 153A.

[0039] The gate electrode 130A and the gate insulating layer 140A are provided in a region corresponding to the second region 122A. As shown in Fig. 2, in the D1 direction, the width W1 of the gate electrode 130A is larger than the distance W2 between the source side second gallium nitride layer 151A and the drain side second gallium nitride layer 153A. In other words, in the D1 direction, the distance W2 between the source electrode (the source side second gallium nitride layer 151A) and the drain electrode (the drain side second gallium nitride layer 153A) of the semiconductor device 10A is smaller than the width W1 of the gate electrode 130A.

[0040] 2, the top surface of the first gallium nitride layer 120A is flat, but is not limited to this configuration. For example, the top surface of the first gallium nitride layer 120A may be recessed in a region corresponding to the second region 122A.

[0041] [2-2. Manufacturing Method of Semiconductor Device 10A] As shown in FIG. 2, a second gallium nitride layer 150A is formed on the oriented insulating layer 110A, and the second gallium nitride layer 150A in the second region 122A is removed to expose the oriented insulating layer 110A in the second region 122A. A first gallium nitride layer 120A is formed on the exposed oriented insulating layer 110A and on the second gallium nitride layer 150A. Then, a gate insulating layer 140A and a gate electrode 130A are formed on the first gallium nitride layer 120A. Then, the gate insulating layer 140A, the gate electrode 130A, and the first gallium nitride layer 120A are patterned as shown in FIG. 2. Finally, a pattern of an electrode 160A is formed.

[0042] As described above, the first gallium nitride layer 120A, the gate insulating layer 140A, and the gate electrode 130A are formed successively, so that contamination at the interface between the first gallium nitride layer 120A and the gate insulating layer 140A can be reduced, and defects in the upper part of the first gallium nitride layer 120A (region where a channel is formed) can be reduced. As a result, good electrical characteristics can be obtained for the semiconductor device 10A.

[0043] [3. Third embodiment] A semiconductor device 10B according to a third embodiment of the present invention will be described with reference to FIG. 3. The semiconductor device 10B is similar to the semiconductor device 10A according to the second embodiment. In the following description, differences between the configuration of the semiconductor device 10B and the semiconductor device 10A will be mainly described. In the following description, when describing a configuration similar to the above-described embodiment, reference will be made to FIG. 1, and the alphabet "B" will be added after the reference numerals shown in FIG. 1.

[0044] [3-1. Configuration of semiconductor device 10B] 3, in the direction D1, the width W1 of the gate electrode 130B is smaller than the width W2 of the second region 122B. In the second region 122B, a recess is formed in the upper surface of the first gallium nitride layer 120B. The gate insulating layer 140B and the gate electrode 130B are provided in the recess. In the example of FIG. 3, since the film thickness of the first gallium nitride layer 120B is smaller than the film thickness of the second gallium nitride layer 150B, the position of the upper surface of the second gallium nitride layer 150B is located higher than the lower surface of the gate insulating layer 140B in the direction D2.

[0045] The semiconductor device 10B according to the third embodiment can provide the same effects as the semiconductor device 10A according to the second embodiment.

[0046] [4. Fourth embodiment] A semiconductor device 10C according to a fourth embodiment of the present invention will be described with reference to FIG. 4. The semiconductor device 10C is similar to the semiconductor device 10A according to the second embodiment. In the following description, differences between the configuration of the semiconductor device 10C and the semiconductor device 10A will be mainly described. In the following description, when describing a configuration similar to the above-described embodiments, reference will be made to FIG. 1, and the alphabet "C" will be added after the reference numerals shown in FIG. 1.

[0047] [4-1. Configuration of Semiconductor Device 10C] As shown in FIG. 4, a first gallium nitride layer 120C and a gate insulating layer 140C are provided on the oriented insulating layer 110C. The first gallium nitride layer 120C is in contact with the oriented insulating layer 110C. In a region where the first gallium nitride layer 120C is not provided, a second gallium nitride layer 150C is provided on the oriented insulating layer 110C. The second gallium nitride layer 150C is in contact with the oriented insulating layer 110C. The second gallium nitride layer 150C runs on the pattern end of the first gallium nitride layer 120C and the gate insulating layer 140C, and is also provided on the gate insulating layer 140C. That is, a part of the second gallium nitride layer 150C is in contact with the gate insulating layer 140C from above the gate insulating layer 140C. The second gallium nitride layer 150C is in contact with the first gallium nitride layer 120C on the sidewall of the first gallium nitride layer 120C. A gate electrode 130C is provided on the gate insulating layer 140C in a region between the source-side second gallium nitride layer 151C and the drain-side second gallium nitride layer 153C.

[0048] [4-2. Manufacturing Method of Semiconductor Device 10C] The first gallium nitride layer 120C and the gate insulating layer 140C are successively formed on the oriented insulating layer 110C. Then, the first gallium nitride layer 120C and the gate insulating layer 140C are patterned together. Next, the second gallium nitride layer 150C is formed on the oriented insulating layer 110C and the gate insulating layer 140C, and is patterned as shown in FIG. 4. By this patterning, the gate insulating layer 140C between the source side second gallium nitride layer 151C and the drain side second gallium nitride layer 153C is exposed. The gate electrode 130C is formed on the exposed gate insulating layer 140C. Finally, the pattern of the electrode 160C is formed.

[0049] As described above, in the semiconductor device 10C of this embodiment, the alignment insulating layer 110C, the first gallium nitride layer 120C, and the gate insulating layer 140C are formed continuously. As a result, good crystallinity of the first gallium nitride layer 120C can be obtained, contamination at the interface between the first gallium nitride layer 120C and the gate insulating layer 140C can be reduced, and defects in the upper part of the first gallium nitride layer 120C (region where a channel is formed) can be reduced.

[0050] [4-3. Modification of the third embodiment] 5, the sidewall 123C of the first gallium nitride layer 120C may be tapered. The tapered sidewall 123C allows the first gallium nitride layer 120C and the second gallium nitride layer 150C to easily come into contact with each other. As a result, problems such as poor electrical continuity between the first gallium nitride layer 120C and the second gallium nitride layer 150C can be avoided.

[0051] 5, the taper angle of the sidewall 123C of the first gallium nitride layer 120C and the taper angle of the sidewall of the gate insulating layer 140C are the same angle, but the present invention is not limited to this configuration. For example, the taper angle of the sidewall of the gate insulating layer 140C may be smaller or larger than the taper angle of the sidewall 123C. The pattern end of the gate insulating layer 140C may be recessed to expose the upper surface of the first gallium nitride layer 120C.

[0052] [5. Fifth Embodiment] A semiconductor device 10D according to a fifth embodiment of the present invention will be described with reference to FIG. 6. The semiconductor device 10D is similar to the semiconductor device 10A according to the second embodiment. In the following description, differences between the configuration of the semiconductor device 10D and the semiconductor device 10A will be mainly described. In the following description, when describing a configuration similar to the above-described embodiments, reference will be made to FIG. 1, and the alphabet "D" will be added after the reference numerals shown in FIG. 1.

[0053] [5-1. Configuration of Semiconductor Device 10D] As shown in FIG. 6, the gate electrode 130D is provided on the oriented insulating layer 110D. In other words, the oriented insulating layer 110D is provided between the substrate 100D and the gate electrode 130D. The gate insulating layer 140D is provided on the gate electrode 130D. The gate electrode 130D and the gate insulating layer 140D are in contact with the oriented insulating layer 110D. The gate insulating layer 140D is patterned, and a part of the oriented insulating layer 110D is exposed from the gate insulating layer 140D. The second gallium nitride layer 150D is in contact with the oriented insulating layer 110D from above the exposed oriented insulating layer 110D. The first gallium nitride layer 120D is provided on the gate insulating layer 140D and the second gallium nitride layer 150D. The second gallium nitride layer 150D is in contact with the first gallium nitride layer 120D from below the first gallium nitride layer 120D.

[0054] In this embodiment, the gate electrode 130D and the gate insulating layer 140D have a crystal orientation (e.g., c-axis orientation). Specifically, the surfaces of the gate electrode 130D and the gate insulating layer 140D are planes having six-fold rotational symmetry. For example, the gate electrode 130D and the gate insulating layer 140D have a (0001) plane in a hexagonal close-packed structure or a (111) plane in a face-centered cubic structure. For example, titanium or aluminum is used as the gate electrode 130D. For example, aluminum nitride, gallium oxide, or titanium oxide is used as the gate insulating layer 140D.

[0055] In the example of FIG. 6, a configuration in which the height of the gate insulating layer 140D and the height of the second gallium nitride layer 150D are the same in the D2 direction are illustrated, but the present invention is not limited to this configuration. For example, the height of the gate insulating layer 140D may be greater than the height of the second gallium nitride layer 150D in the D2 direction. In this case, a part of the gate insulating layer 140D may be provided on the second gallium nitride layer 150D. Conversely to the above, the height of the gate insulating layer 140D may be smaller than the height of the second gallium nitride layer 150D in the D2 direction. In this case, a part of the second gallium nitride layer 150D may be provided on the gate insulating layer 140D.

[0056] As described above, by providing the second gallium nitride layer 150D on the oriented insulating layer 110D, it is possible to obtain good crystallinity for the second gallium nitride layer 150. Similarly, by providing the gate electrode 130D and the gate insulating layer 140D having crystal orientation on the oriented insulating layer 110D, and providing the first gallium nitride layer 120D on the gate insulating layer 140D, it is possible to obtain good crystallinity for the first gallium nitride layer 120D.

[0057] [5-2. Manufacturing Method of Semiconductor Device 10D] A gate electrode 130D is formed on the alignment insulating layer 110D and patterned as shown in FIG. 6. A gate insulating layer 140D is formed on the patterned gate electrode 130D and patterned as shown in FIG. 6. Then, a second gallium nitride layer 150D is formed and patterned as shown in FIG. 6. A first gallium nitride layer 120D is formed on the gate insulating layer 140D and the second gallium nitride layer 150D and patterned. Finally, a pattern of an electrode 160D is formed.

[0058] In this embodiment, a manufacturing method has been exemplified in which the second gallium nitride layer 150D is formed after the gate electrode 130D and the gate insulating layer 140D are formed, but the manufacturing method may also be such that the gate electrode 130D and the gate insulating layer 140D are formed after the second gallium nitride layer 150D is formed.

[0059] [6. Sixth Embodiment] A semiconductor device 10E according to a sixth embodiment of the present invention will be described with reference to FIG. 7. The semiconductor device 10E is similar to the semiconductor device 10D according to the fifth embodiment. In the following description, differences between the configuration of the semiconductor device 10E and the semiconductor device 10D will be mainly described. In the following description, when describing a configuration similar to the above embodiments, reference will be made to FIG. 1, and the alphabet "E" will be added after the reference numerals shown in FIG. 1.

[0060] [6-1. Configuration of Semiconductor Device 10E] As shown in FIG. 7, in this embodiment, the oriented insulating layer 110E is provided between the substrate 100E and the second gallium nitride layer 150E and is in contact with the second gallium nitride layer 150E. The second gallium nitride layer 150E is in contact with the first gallium nitride layer 120E from below the first gallium nitride layer 120E. The gate electrode 130E has a crystal orientation similar to the gate electrode 130D of the fifth embodiment. On the other hand, unlike the semiconductor device 10D of the fifth embodiment, the oriented insulating layer 110E is not provided in the region where the gate electrode 130E and the gate insulating layer 140E are provided, and the gate electrode 130E is in contact with the substrate 100E. In this embodiment, the gate insulating layer 140E provided on the gate electrode 130E is in contact with the substrate 100E, and the second gallium nitride layer 150E provided on the oriented insulating layer 110E is in contact with the substrate 100E.

[0061] 7, the second gallium nitride layer 150E covers the pattern end of the oriented insulating layer 110E, but the present invention is not limited to this configuration. The pattern end may be located near the boundary between the gate insulating layer 140E and the second gallium nitride layer 150E, or may be covered by the gate insulating layer 140E. Instead of the oriented insulating layer 110E, a conductive layer with oriented crystals formed in the same layer as the gate electrode 130E may be provided.

[0062] [7. Seventh embodiment] A semiconductor device 10F according to a seventh embodiment of the present invention will be described with reference to FIG. 8. The semiconductor device 10F is similar to the semiconductor device 10E according to the seventh embodiment. In the following description, differences between the configuration of the semiconductor device 10F and the semiconductor device 10E will be mainly described. In the following description, when describing a configuration similar to the above-mentioned embodiments, reference will be made to FIG. 1, and the alphabet "F" will be added after the reference numerals shown in FIG. 1.

[0063] [7-1. Configuration of Semiconductor Device 10F] 8, the second gallium nitride layer 150F and the electrode 160F are provided on the first gallium nitride layer 120F. The second gallium nitride layer 150F is in contact with the first gallium nitride layer 120F. The first gallium nitride layer 120F covers the alignment insulating layer 110F and the gate insulating layer 140F. The alignment insulating layer 110F is in contact with the first gallium nitride layer 120F between the first gallium nitride layer 120F and the substrate 100F in a region overlapping with the second gallium nitride layer 150F in a plan view.

[0064] 8 illustrates a configuration in which the width W1 of the gate electrode 130F in the D1 direction is greater than the distance W2 between the source-side second gallium nitride layer 151F and the drain-side second gallium nitride layer 153F, but is not limited to this configuration. The width W1 of the gate electrode 130F may be smaller than the distance W2 between the source-side second gallium nitride layer 151F and the drain-side second gallium nitride layer 153F, and the source-side second gallium nitride layer 151F and the drain-side second gallium nitride layer 153F may be continuously connected.

[0065] [7-2. Manufacturing Method of Semiconductor Device 10F] After the alignment insulating layer 110F, the gate electrode 130F, and the gate insulating layer 140F are patterned, the first gallium nitride layer 120F and the second gallium nitride layer 150F are successively formed. Then, the second gallium nitride layer 150F is patterned. Then, the electrode 160F is formed on the patterned second gallium nitride layer 150F.

[0066] As described above, the second gallium nitride layer 150F is provided on the first gallium nitride layer 120F, so that the contact area between these layers can be increased. As a result, current concentration in the junction region of these layers can be suppressed. Furthermore, the first gallium nitride layer 120F and the second gallium nitride layer 150F are continuously formed on the alignment insulating layer 110F and the gate insulating layer 140F, so that good crystallinity can be obtained for the first gallium nitride layer 120F and the second gallium nitride layer 150F.

[0067] [8. Eighth embodiment] With reference to FIG. 9, a semiconductor device 10G according to an eighth embodiment of the present invention will be described. The semiconductor device 10G is similar to the semiconductor device 10F according to the eighth embodiment. In the following description, differences between the configuration of the semiconductor device 10G and the semiconductor device 10F will be mainly described. In the following description, when describing a configuration similar to the above-described embodiments, reference will be made to FIG. 1, and the alphabet "G" will be added after the reference numerals shown in FIG. 1.

[0068] [8-1. Configuration of semiconductor device 10G] As shown in FIG. 9, the oriented insulating layer 110G covers the gate electrode 130G. The first gallium nitride layer 120G is provided on the oriented insulating layer 110G. That is, in this embodiment, the oriented insulating layer 110G functions as a gate insulating layer. As shown in FIG. 9, in a region overlapping with the second gallium nitride layer 150G in a plan view, the oriented insulating layer 110G having the function of a gate insulating layer and the first gallium nitride layer 120G are in contact with each other. Similarly, in the above region, the first gallium nitride layer 120G and the second gallium nitride layer 150G are in contact with each other.

[0069] [8-2. Manufacturing method of semiconductor device 10G] After the gate electrode 130G is patterned, the alignment insulating layer 110G, the first gallium nitride layer 120G, and the second gallium nitride layer 150G are successively formed. Then, the second gallium nitride layer 150G is patterned. Then, the electrode 160G is formed on the patterned second gallium nitride layer 150G.

[0070] According to the configuration of this embodiment, it is possible to obtain the same effects as those of the seventh embodiment.

[0071] [8-3. Modifications of the semiconductor device 10G] As shown in Fig. 10, the gate electrode 130G may be embedded in the substrate 100G. That is, a recess is formed in the substrate 100G, and the gate electrode 130G is embedded in the recess. In Fig. 10, the upper surface of the substrate 100G and the upper surface of the gate electrode 130G coincide with each other in the D2 direction, but the upper surfaces of the substrate 100G and the gate electrode 130G do not have to coincide with each other in the D2 direction.

[0072] 11, a planarization layer 165G may be provided between the substrate 100G and the alignment / insulation layer 110G. In this case, even if the upper surface of the substrate 100G and the upper surface of the gate electrode 130G are not aligned in the D2 direction, a surface (upper surface of the planarization layer 165G) on which the alignment / insulation layer 110G is formed can be provided. Therefore, good alignment of the alignment / insulation layer 110G can be obtained.

[0073] [9. Ninth Embodiment] A semiconductor device 10H according to a ninth embodiment of the present invention will be described with reference to FIG. 12. The semiconductor device 10H is similar to the semiconductor device 10G according to the ninth embodiment. In the following description, differences between the configuration of the semiconductor device 10H and the semiconductor device 10G will be mainly described. In the following description, when describing a configuration similar to the above-described embodiment, reference will be made to FIG. 1, and the alphabet "H" will be added after the reference numeral shown in FIG. 1.

[0074] [9-1. Configuration of semiconductor device 10H] As shown in FIG. 12, the second gallium nitride layer 150H is adjacent to the first gallium nitride layer 120H in the horizontal direction (D1 direction). In other words, each of the first gallium nitride layer 120H and the second gallium nitride layer 150H is in contact with the oriented insulating layer 110H. The second gallium nitride layer 150H is in contact with the first gallium nitride layer 120H at the sidewall of the first gallium nitride layer 120H. When a predetermined voltage is supplied to the gate electrode 130H, carriers are generated (channels are formed) in the first gallium nitride layer 120H near the interface between the first gallium nitride layer 120H and the oriented insulating layer 110H. That is, the second gallium nitride layer 150H is in contact with the first gallium nitride layer 120H near the region (124H) where carriers are generated in the first gallium nitride layer 120H.

[0075] As described above, second gallium nitride layer 150H contacts first gallium nitride layer 120H in the region where the carriers are formed (region where a channel is formed), thereby reducing the resistance of the current path from electrode 160H to the channel formed in first gallium nitride layer 120H.

[0076] [9-2. Modifications of the semiconductor device 10H] In FIG. 12, the configuration in which the positions of the upper surface of the first gallium nitride layer 120H and the upper surface of the second gallium nitride layer 150H coincide in the D2 direction is illustrated, but the present invention is not limited to this configuration. For example, the second gallium nitride layer 150H is formed and patterned first, and the first gallium nitride layer 120H is formed thereafter, thereby obtaining a configuration as shown in FIG. 13. On the other hand, the first gallium nitride layer 120H is formed and patterned first, and the second gallium nitride layer 150H is formed thereafter, thereby obtaining a configuration as shown in FIG. 14. In either configuration, the resistance of the current path from the electrode 160H to the channel formed in the first gallium nitride layer 120H can be reduced in the same manner as in the configuration of FIG. 12.

[0077] [10. Tenth Embodiment] A display device 20J according to a tenth embodiment of the present invention will be described with reference to Figs. 15 to 17. Fig. 15 is a schematic diagram showing a configuration of a display device according to an embodiment of the present invention. Fig. 16 is a circuit diagram (pixel circuit) of a pixel of the display device according to an embodiment of the present invention. Fig. 17 is a cross-sectional view of a pixel of the display device according to an embodiment of the present invention.

[0078] [10-1. Overview of the configuration of the display device 20J] FIG. 15 is a schematic diagram showing a configuration of a display device 20J according to an embodiment of the present invention. The display device 20J has a display unit 1020J, a driving circuit unit 1030J, and a terminal unit 1040J on a substrate 100J. The driving circuit unit 1030J is provided around the display unit 1020J and controls the display unit 1020J. The driving circuit unit 1030J includes, for example, a scanning driving circuit. The terminal unit 1040J is provided at an end of the substrate 100J and supplies signals and power from the outside to the display device 20J. The terminal unit 1040J includes, for example, a terminal 1041J. The terminal 1041J is connected to a flexible printed circuit board 1050J. A driver IC 1060J is provided on the flexible printed circuit board 1050J.

[0079] The display unit 1020J can display an image or video and includes a plurality of pixels 1021J arranged in a matrix. However, the arrangement of the plurality of pixels 1021J is not limited to a matrix. The plurality of pixels 1021J may be arranged in a staggered pattern, for example.

[0080] [10-2. Configuration of pixel 1021J] 16 is a circuit diagram (pixel circuit) of a pixel 1021J of a display device 20J according to one embodiment of the present invention. The pixel 1021J includes a first transistor 200J-1, a second transistor 200J-2, a light emitting diode 300J, and a capacitive element 400J.

[0081] The first transistor 200J-1 functions as a selection transistor. That is, the conduction state of the first transistor 200J-1 is controlled by the scanning line 1110J. In the first transistor 200J-1, the gate, the source, and the drain are electrically connected to the scanning line 1110J, the signal line 1120J, and the gate of the second transistor 200J-2, respectively.

[0082] The second transistor 200J-2 functions as a driving transistor. That is, the second transistor 200J-2 controls the light emission luminance of the light emitting diode 300J. In the second transistor 200J-2, the gate, the source, and the drain are electrically connected to the drain of the first transistor 200J-1, the driving power line 1140J, and the anode (p-type electrode) of the light emitting diode 300J, respectively.

[0083] One of the capacitance electrodes of the capacitance element 400J is electrically connected to the gate of the second transistor 200J-2 and the drain of the first transistor 200J-1, and the other of the capacitance electrodes of the capacitance element 400J is electrically connected to the driving power supply line 1140J.

[0084] The anode of the light-emitting diode 300J is connected to the drain of the second transistor 200J-2. The cathode (n-type electrode) of the light-emitting diode 300J is connected to the reference power supply line 1160J.

[0085] [10-3. Cross-sectional structure of display device 20J] The layer configuration of the pixel 1021J will be described with reference to Fig. 17. In the description of Fig. 17, the first transistor 200J-1 and the second transistor 200J-2 will not be particularly distinguished from each other, and will be described as the transistor 200J.

[0086] 17 is a cross-sectional view of the pixel 1021J cut along the line A1-A2 shown in FIG. 15. As shown in FIG. 17, the display device 20J includes a substrate 100J, an underlayer 105J, an alignment insulating layer 110J, a transistor 200J, a light-emitting diode 300J, a light-shielding wall 500J, a light-shielding layer 600J, an interlayer film 170J, a conductive layer 180J, and a transparent conductive layer 190J. The underlayer 105J, the alignment insulating layer 110J, the transistor 200J, the light-emitting diode 300J, the light-shielding wall 500J, the interlayer film 170J, the conductive layer 180J, and the transparent conductive layer 190J are provided on the first surface 101J side of the substrate 100J. The light-shielding layer 600J is provided on the second surface 102J side opposite to the first surface 101J of the substrate 100J.

[0087] The substrate 100J is a support substrate for the transistor 200J and the light emitting diode 300J. As the substrate 100J, an amorphous glass substrate or the like can be used as described above.

[0088] The base layer 105J is provided on the substrate 100J. The base layer 105J can prevent diffusion of impurities from the substrate 100J or impurities from the outside (e.g., moisture or sodium). For example, a silicon nitride layer or a stack of a silicon oxide layer and a silicon nitride layer may be used as the base layer 105J.

[0089] The oriented insulating layer 110J is provided on the underlayer 105J. By providing the oriented insulating layer 110J, the crystallinity of the first gallium nitride layer 120J of the transistor 200J formed on the oriented insulating layer 110J can be improved, and the crystallinity of the gallium nitride layer 310J of the light-emitting diode 300J formed on the oriented insulating layer 110J can be improved. The first gallium nitride layer 120J and the gallium nitride layer 310J are formed in the same layer and have similar film thicknesses and physical properties.

[0090] When the alignment / insulation layer 110J contains a nitrogen compound (for example, titanium nitride or aluminum nitride), the underlayer 105J may not be provided. The nitrogen contained in the nitrogen compound has a large electronegativity, so that it can trap impurities contained in the substrate 100J.

[0091] The transistor 200J includes a first gallium nitride layer 120J, a gate electrode 130J, a gate insulating layer 140J, a source electrode 250J, and a drain electrode 260J. The source electrode 250J corresponds to, for example, the source-side second gallium nitride layer 151 and the source-side electrode 161 in Fig. 1. The drain electrode 260J corresponds to, for example, the drain-side second gallium nitride layer 153 and the drain-side electrode 163 in Fig. 1.

[0092] The first gallium nitride layer 120J is provided on the oriented insulating layer 110J. As described above, since the first gallium nitride layer 120J is in contact with the oriented insulating layer 110J, the crystal growth of the first gallium nitride layer 120J is controlled by the oriented insulating layer 110J. As a result, the first gallium nitride layer 120J is c-axis oriented with respect to the substrate 100J.

[0093] The transistor 200J is a so-called MOS transistor, but is a HEMT (High Effect Transistor). The semiconductor device may be a semiconductor laser diode (SLD) or a semiconductor laser diode (SLD).

[0094] The light emitting diode 300J is provided on the alignment insulating layer 110J. The light emitting diode 300J includes a gallium nitride layer 310J, an n-type semiconductor layer 320J, a light emitting layer 330J, a p-type semiconductor layer 340J, an n-type electrode 350J, and a p-type electrode 360J.

[0095] The gallium nitride layer 310J is provided on the oriented insulating layer 110J. For example, a gallium nitride layer is used as the gallium nitride layer 310J. Since the gallium nitride layer 310J is in contact with the oriented insulating layer 110J, the crystal growth of the gallium nitride layer 310J is controlled by the oriented insulating layer 110J. As a result, the gallium nitride layer 310J is c-axis oriented with respect to the substrate 100J.

[0096] The n-type semiconductor layer 320J is provided on the gallium nitride layer 310J. As the n-type semiconductor layer 320J, for example, a gallium nitride layer doped with silicon or the like is used.

[0097] The light emitting layer 330J is provided on the n-type semiconductor layer 320J. As the light emitting layer 330J, for example, a layer in which indium gallium nitride layers and gallium nitride layers are alternately laminated is used.

[0098] The p-type semiconductor layer 340J is provided on the light emitting layer 330J. As the p-type semiconductor layer 340J, for example, a magnesium-doped gallium nitride layer is used.

[0099] The n-type electrode 350J and the p-type electrode 360J are provided on the n-type semiconductor layer 320J and the p-type semiconductor layer 340J, respectively. The n-type electrode 350J is made of a metal such as indium. The p-type electrode 360J is made of a metal such as palladium or gold.

[0100] The light emitting diode 300J may be, but is not limited to, a so-called micro LED or mini LED. A micro LED is an LED with a side length of 100 μm or less. A mini LED is an LED with a side length of more than 100 μm.

[0101] Although not shown, a protective layer may be provided, if necessary, to cover the transistor 200J or the light-emitting diode 300J. As the protective layer, silicon nitride or a stack of a silicon oxide layer and a silicon nitride layer may be used.

[0102] The light-shielding wall 500J is provided between the transistor 200J and the light-emitting diode 300J. The light-shielding wall 500J can block light emitted from the light-emitting diode 300J and prevent the light from being irradiated onto the transistor 200J. For example, an acrylic resin (black resin) to which carbon has been added can be used as the light-shielding wall 500J.

[0103] The light-shielding layer 600J is provided on the second surface 102J of the substrate 100J. The light-shielding layer 600J can block external light and prevent the light from being irradiated onto the transistor 200J. For example, an acrylic resin (black resin) to which carbon has been added may be used as the light-shielding layer 600J.

[0104] The interlayer film 170J is provided so as to cover the transistor 200J, the light emitting diode 300J, and the light shielding wall 500J. The interlayer film 170J can flatten the unevenness formed by the transistor 200J, the light emitting diode 300J, and the light shielding wall 500J. For example, an organic insulating film such as an acrylic resin film or a polyimide resin film is used as the interlayer film 170J. The interlayer film 170J may be a single layer or a multilayer. When the interlayer film 170J is a multilayer, the interlayer film 170J may include not only an organic insulating layer but also an inorganic insulating layer such as a silicon oxide layer or a silicon nitride layer.

[0105] The conductive layer 180J and the transparent conductive layer 190J are provided on the interlayer film 170J. The conductive layer 180J is electrically connected to the gate electrode 130J through an opening provided in the interlayer film 170J. The transparent conductive layer 190J electrically connects the drain electrode 260J and the p-type electrode 360J through an opening provided in the interlayer film 170J. Light emitted from the light emitting layer 330J of the light emitting diode 300J passes through the transparent conductive layer 190J and is emitted to the outside. For example, a laminate of aluminum and titanium (for example, Ti / Al / Ti) can be used as the conductive layer 180J. For example, a transparent conductive layer such as an indium tin oxide (ITO) film or an indium zinc oxide (IZO) film can be used as the transparent conductive layer 190J.

[0106] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0107] Even if there are other effects and advantages different from those brought about by the respective embodiments described above, those which are clear from the description in this specification or which can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0108] 10: semiconductor device, 20J: display device, 100: substrate, 101J: first surface, 102J: second surface, 105J: underlayer, 110: alignment insulating layer, 120: first gallium nitride layer, 121A: first region, 122A: second region, 123C: sidewall, 130: gate electrode, 140: gate insulating layer, 150: second gallium nitride layer, 151: source side second gallium nitride layer, 153: drain side second gallium nitride layer, 160: electrode, 161: source side electrode, 163: drain side electrode, 165G: planarization layer, 170J: interlayer film, 180J: conductive layer, 190J: transparent conductive layer, 200J: transistor, 250J: source electrode, 260J: drain electrode, 300J: light emitting diode, 310J: gallium nitride layer, 320J: n-type semiconductor layer, 330J: light emitting layer, 340J: p-type semiconductor layer, 350J: n-type electrode, 360J: p-type electrode, 400J: capacitance element, 500J: light shielding wall, 600J: light shielding layer, 1020J: display section, 1021J: pixel, 1030J: driving circuit section, 1040J: terminal section, 1041J: terminal, 1050J: flexible printed circuit board; 1110J: scanning line; 1120J: signal line; 1140J: driving power line; 1160J: reference power line

Claims

1. an amorphous glass substrate; an orientation insulating layer having a crystal orientation provided on the amorphous glass substrate; a first gallium nitride layer of a first conductivity type provided on the alignment / insulation layer and in contact with the alignment / insulation layer; a gate electrode facing the first gallium nitride layer; a gate insulating layer between the first gallium nitride layer and the gate electrode; a source electrode electrically connected to the first gallium nitride layer; a drain electrode electrically connected to the first gallium nitride layer on the opposite side of the gate electrode from the source electrode; A semiconductor device having the above structure.

2. The semiconductor device according to claim 1 , wherein the oriented insulating layer has a surface with six-fold rotational symmetry.

3. 3. The semiconductor device according to claim 2, wherein the oriented insulating layer has a (0001) plane in a hexagonal close-packed structure or a (111) plane in a face-centered cubic structure.

4. The semiconductor device according to claim 1 , wherein the oriented insulating layer comprises aluminum nitride, gallium oxide, titanium nitride, or titanium oxide.

5. The semiconductor device according to claim 1 , wherein the gate electrode is provided on the first gallium nitride layer.

6. a second gallium nitride layer of a second conductivity type having a higher conductivity than the first gallium nitride layer; 6. The semiconductor device according to claim 1, wherein the second gallium nitride layer is in contact with the first gallium nitride layer from above the first gallium nitride layer.

7. a second gallium nitride layer of a second conductivity type having a higher conductivity than the first gallium nitride layer; In a first region, the first gallium nitride layer is in contact with the second gallium nitride layer from above the second gallium nitride layer, The semiconductor device according to claim 1 , wherein in a second region different from the first region, the first gallium nitride layer is in contact with the oriented insulating layer exposed from the second gallium nitride layer.

8. the second gallium nitride layer includes a source-side second gallium nitride layer connected to the source electrode and a drain-side second gallium nitride layer connected to the drain electrode, 8. The semiconductor device according to claim 7, wherein a width of the gate electrode in a first direction on the main surface of the amorphous glass substrate is larger than a distance between the source-side second gallium nitride layer and the drain-side second gallium nitride layer.

9. a second gallium nitride layer of a second conductivity type having a higher conductivity than the first gallium nitride layer; the gate insulating layer is in contact with the first gallium nitride layer from above the first gallium nitride layer, a top surface of the gate insulating layer is exposed from the gate electrode; 6. The semiconductor device according to claim 1, wherein a portion of said second gallium nitride layer is in contact with an upper surface of said portion of said gate insulating layer from above said gate insulating layer.

10. an amorphous glass substrate; a gate electrode provided on the amorphous glass substrate; a gate insulating layer having a crystal orientation and provided on the gate electrode; a first gallium nitride layer of a first conductivity type provided on the gate insulating layer and in contact with the gate insulating layer; a source electrode electrically connected to the first gallium nitride layer; a drain electrode electrically connected to the first gallium nitride layer on the opposite side of the gate electrode from the source electrode; A semiconductor device having the above structure.

11. The semiconductor device according to claim 10 , wherein the gate insulating layer has a surface with six-fold rotational symmetry.

12. The semiconductor device according to claim 11 , wherein the gate insulating layer has a (0001) plane in a hexagonal close-packed structure or a (111) plane in a face-centered cubic structure.

13. The semiconductor device according to claim 10 , wherein the gate insulating layer contains aluminum nitride, gallium oxide, titanium nitride, or titanium oxide.

14. The semiconductor device further includes an orientation insulating layer having a crystal orientation, the orientation insulating layer being provided between the amorphous glass substrate and the gate electrode and in contact with the gate electrode; 14. The semiconductor device according to claim 10, wherein the gate electrode and the gate insulating layer have the same crystal orientation as the oriented insulating layer.

15. a second gallium nitride layer of a second conductivity type having a higher conductivity than the first gallium nitride layer; The semiconductor device according to claim 14 , wherein the second gallium nitride layer is in contact with the orientation / insulation layer from above the orientation / insulation layer, and in contact with the first gallium nitride layer from below the first gallium nitride layer.

16. a second gallium nitride layer of a second conductivity type having a higher conductivity than the first gallium nitride layer; An orientation insulating layer is provided between the amorphous glass substrate and the second gallium nitride layer, is in contact with the second gallium nitride layer, and has a crystal orientation; the gate electrode has a crystal orientation and is in contact with the gate insulating layer; 14. The semiconductor device according to claim 10, wherein the second gallium nitride layer is in contact with the first gallium nitride layer from below the first gallium nitride layer.

17. a second gallium nitride layer of a second conductivity type having a higher conductivity than the first gallium nitride layer; an orientation insulating layer having a crystal orientation, the orientation insulating layer being in contact with the first gallium nitride layer between the amorphous glass substrate and the first gallium nitride layer in a region overlapping with the second gallium nitride layer in a plan view; 14. The semiconductor device according to claim 10, wherein the second gallium nitride layer is in contact with the first gallium nitride layer from above the first gallium nitride layer.

18. a second gallium nitride layer of a second conductivity type having a higher conductivity than the first gallium nitride layer; 14. The semiconductor device according to claim 10, wherein in a region overlapping with the second gallium nitride layer in a plan view, the gate insulating layer and the first gallium nitride layer are in contact with each other, and the first gallium nitride layer and the second gallium nitride layer are in contact with each other.

19. a second gallium nitride layer of a second conductivity type having a higher conductivity than the first gallium nitride layer; 14. The semiconductor device according to claim 10, wherein the second gallium nitride layer is in contact with the gate insulating layer at a position adjacent to the first gallium nitride layer in a first direction on the main surface of the amorphous glass substrate.

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